Class / Patent application number | Description | Number of patent applications / Date published |
326102000 | Field-effect transistor | 75 |
20080309374 | Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same - A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same. | 12-18-2008 |
20090243658 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance. At this point in time, a resistance value as desired is attained through combination of decoupling capacitors having threshold voltages Vth differing from each other. | 10-01-2009 |
20100001763 | Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same - A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same. | 01-07-2010 |
20100085081 | INVERTER MANUFACTURING METHOD AND INVERTER - To provide an enhancement-depletion (E/D) inverter which can be easily manufactured, in the present invention, a method of manufacturing an inverter which is composed of an oxide semiconductor in which a channel layer includes at least one element selected from In, Ga and Zn formed on a same substrate, the inverter being the E/D inverter having plural thin film transistors, is characterized by comprising the steps of: forming a first transistor and a second transistor, the thicknesses of the channel layers of the first and second transistors being mutually different; and executing heat treatment to at least one of the channel layers of the first and second transistors. | 04-08-2010 |
20100148823 | SEMICONDUCTOR DEVICE - An RESURF region is formed so as to surround a high-potential logic region with an isolation region interposed therebetween, in which a sense resistance and a first logic circuit which are applied with a high potential are formed in high-potential logic region. On the outside of RESURF region, a second logic circuit region is formed, which is applied with the driving voltage level required for driving a second logic circuit with respect to the ground potential. In RESURF region, a drain electrode of a field-effect transistor is formed along the inner periphery, and a source electrode is formed along the outer periphery. Furthermore, a polysilicon resistance connected to sense resistance is formed in the shape of a spiral from the inner peripheral side toward the outer peripheral side. | 06-17-2010 |
20110062992 | LOGIC CIRCUIT, LIGHT EMITTING DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - An object is to obtain a desired threshold voltage of a thin film transistor using an oxide semiconductor. Another object is to suppress a change of the threshold voltage over time. Specifically, an object is to apply the thin film transistor to a logic circuit formed using a transistor having a desired threshold voltage. In order to achieve the above object, thin film transistors including oxide semiconductor layers with different thicknesses may be formed over the same substrate, and the thin film transistors whose threshold voltages are controlled by the thicknesses of the oxide semiconductor layers may be used to form a logic circuit. In addition, by using an oxide semiconductor film in contact with an oxide insulating film formed after dehydration or dehydrogenation treatment, a change in threshold voltage over time is suppressed and the reliability of a logic circuit can be improved. | 03-17-2011 |
20110084731 | LOGIC CIRCUIT AND DISPLAY DEVICE HAVING THE SAME - It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided. | 04-14-2011 |
20110089975 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×10 | 04-21-2011 |
20110102019 | SEMICONDUCTOR DEVICE FORMED ON A SOI SUBSTRATE - Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate. | 05-05-2011 |
20110181319 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. | 07-28-2011 |
20120194218 | 3D Semiconductor Device - A semiconductor device includes a first transistor layer and a second transistor layer overlaying the first transistor layer, wherein said first transistor layer comprises a plurality of flip-flops each having a selectively coupleable additional input generated by said second transistor layer. | 08-02-2012 |
20120256657 | FIELD EFFECT TRANSISTOR, AND ELECTRIC CIRCUIT - The invention relates to a field effect transistor comprising at least one source electrode layer and at least one drain electrode layer arranged in the same plane, a semiconductor layer, an insulator layer and a gate electrode layer, wherein the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the at least one drain electrode layer, only partly covers a channel arranged between the at least one source electrode layer and the at least one drain electrode layer. | 10-11-2012 |
20120274357 | Reducing Narrow Gate Width Effects in an Integrated Circuit Design - A method for reducing narrow gate width effects in an integrated circuit includes finding the smallest transistor channel widths that are larger than the minimum width for the technology for library cells that produce logic blocks that meet timing constraints while using the least amount of power and have the smallest possible area. The method may include characterizing a device library while varying process, voltage and temperature parameters, and synthesizing an HDL representation of a functional logic block including cells from the device library. The method may also include determining whether timing, area, and power values of the functional logic block are within a predetermined range. In response to the timing, area, and power values not being within the predetermined range, iteratively increasing the channel width of at least a portion of the transistors of at least one of the cells in the device library. | 11-01-2012 |
20120280715 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - The logic circuit includes an input terminal, an output terminal, a main logic circuit portion that is electrically connected to the input terminal and the output terminal, and a switching element electrically connected to the input terminal and the main logic circuit portion. Further, a first terminal of the switching element is electrically connected to the input terminal, a second terminal of the switching element is electrically connected to a gate of at least one transistor included in the main logic circuit portion, and the switching element is a transistor in which a leakage current in an off state per micrometer of channel width is lower than or equal to 1×10 | 11-08-2012 |
20120293207 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit in which data is held even after power is turned off is provided. Further, a novel logic circuit whose power consumption can be reduced is provided. In the logic circuit, a comparator comparing two output nodes, a charge holding portion, and an output-node-potential determining portion are electrically connected to each other. Such a structure enables data to be held in the logic circuit even after power is turned off. Further, the total number of transistors in the logic circuit can be reduced. Furthermore, the area of the logic circuit can be reduced by stacking a transistor including an oxide semiconductor and a transistor including silicon. | 11-22-2012 |
20120293208 | Semiconductor Device - As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a plurality of capacitors. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region. | 11-22-2012 |
20130009668 | 4-TERMINAL PIEZOELECTRONIC TRANSISTOR (PET) - A 4-terminal piezoelectronic transistor (PET) which includes a piezoelectric (PE) material disposed between first and second electrodes; an insulator material disposed on the second electrode; a third electrode disposed on the insulator material and a piezoresistive (PR) material disposed between the third electrode and a fourth electrode. An applied voltage across the first and second electrodes causing a pressure from the PE material to be applied to the PR material through the insulator material, the electrical resistance of the PR material being dependent upon the pressure applied by the PE material. The first and second electrodes are electrically isolated from the third and fourth electrodes. Also disclosed are logic devices fabricated from 4-terminal PETs and a method of fabricating a 4-terminal PET. | 01-10-2013 |
20130027083 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W | 01-31-2013 |
20130088261 | LOW LEAKAGE SPARE GATES FOR INTEGRATED CIRCUITS - Devices, systems, methods, and other embodiments associated with spare gates are described. In one embodiment, a spare gate in an integrated circuit has a disconnected discharge path to minimize or eliminate current leakage. | 04-11-2013 |
20130127497 | MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped. | 05-23-2013 |
20130147519 | LOGIC CIRCUIT - An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor | 06-13-2013 |
20130249597 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD THEREOF, MASK FOR SEMICONDUCTOR MANUFACTURE, AND OPTICAL PROXIMITY CORRECTION METHOD - An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area ( | 09-26-2013 |
20130293266 | METHOD OF DRIVING SEMICONDUCTOR DEVICE - A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power supply is provided. In the programming element, a node where a drain electrode of the first transistor, a gate electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other is formed. A potential can be supplied to each of a source electrode of the first transistor and the other of the electrodes of the capacitor. The power supply and the logic circuit are electrically connected to each other through a source electrode and a drain electrode of the second transistor. A connection state between the power supply and the logic circuit is controlled in accordance with the state of the second transistor. | 11-07-2013 |
20130300456 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - Provided is a semiconductor chip for a programmable logic device which can hold configuration data even when supply of a power supply potential is interrupted and can operate with low power. Further, a semiconductor device using the semiconductor chip is provided. The semiconductor chip can hold configuration data even when supply of a power supply potential is interrupted and can operate with low power. The semiconductor chip includes a transistor and a pad connected to the transistor. The transistor is formed using a material which allows a sufficient reduction in off-state current of the transistor; for example, an oxide semiconductor material that is a wide bandgap semiconductor. | 11-14-2013 |
20140002137 | EMITTER-COUPLED SPIN-TRANSISTOR LOGIC | 01-02-2014 |
20140167819 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH INDEPENDENT POWER DOMAINS - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 06-19-2014 |
20140266304 | SHIFT REGISTER CIRCUIT - A shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal by changing only the potential of a back gate without changing the potential of a gate is provided. In a shift register circuit including a logic circuit with a first transistor and a second transistor having the same conductivity type, a first gate electrode of the first transistor is connected to a source electrode or a drain electrode of the first transistor, an input signal is supplied to a second gate electrode of the first transistor, a clock signal is supplied to a gate electrode of the second transistor, and the first gate electrode and the gate electrode are formed from the same layer. | 09-18-2014 |
20150015306 | SYSTEMS AND METHODS FOR REDUCING POWER CONSUMPTION IN SEMICONDUCTOR DEVICES - A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor. | 01-15-2015 |
20160020768 | Digital Circuits Having Improved Transistors, and Methods Therefor - Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed. | 01-21-2016 |
20160094224 | LOGIC CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor. | 03-31-2016 |
20160105174 | LOGIC CIRCUIT, PROCESSING UNIT, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor. | 04-14-2016 |
20160204107 | SEMICONDUCTOR INTERGRATED CIRCUIT AND LOGIC CIRCUIT | 07-14-2016 |
20160380631 | LOGIC CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor. | 12-29-2016 |
326103000 | Complementary FET`s | 21 |
20090146693 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential. | 06-11-2009 |
20100060322 | ADIABATIC CMOS DESIGN - An integrated circuit comprising a plurality of CMOS modules ( | 03-11-2010 |
20100090722 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 04-15-2010 |
20100134149 | ULTRA-LOW-POWER CIRCUIT - An ultra-low-power transconductance device is provided, (FIG. | 06-03-2010 |
20100164547 | BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION - A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates. | 07-01-2010 |
20100171525 | HYBRID RESISTOR/FET-LOGIC DEMULTIPLEXER ARCHITECTURE DESIGN FOR HYBRID CMOS/NANODEVICE CIRCUITS - A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux. | 07-08-2010 |
20100182047 | Dynamic Logic Circuit Including Dynamic Standard Cell Library - A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors. | 07-22-2010 |
20110057685 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE LAYOUT METHOD - There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed. | 03-10-2011 |
20110148466 | LOGIC-CELL-COMPATIBLE DECOUPLING CAPACITOR - An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. | 06-23-2011 |
20110156755 | FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION - Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes. | 06-30-2011 |
20120001655 | BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO) - A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell. | 01-05-2012 |
20120074985 | SEMICONDUCTOR DEVICE - In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly. | 03-29-2012 |
20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 05-24-2012 |
20120194219 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal. The high-voltage terminal and the low-voltage terminal are connected respectively to the bulk connection of the p-type transistor and the bulk connection of the n-type transistor. | 08-02-2012 |
20120235706 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 09-20-2012 |
20120293209 | LOGIC CIRCUIT - A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile. | 11-22-2012 |
20120293210 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced. | 11-22-2012 |
20130043906 | CMOS LOGIC CIRCUIT - A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal. | 02-21-2013 |
20140132306 | CMOS LOGIC CIRCUIT USING PASSIVE INTERNAL BODY TIE BIAS - This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor. | 05-15-2014 |
20140375356 | Delay Circuit Independent of Supply Voltage - A delay circuit in which the delay is independent of variations in the power supply which powers the logic gates of the delay circuit is disclosed. By separating the CMOS transistors that form each logic gate by additional CMOS bias transistors which are biased at a controlled voltage, variations in the gate delay of the inverter transistors due to variations in the power supply voltage for the inverter transistors may be minimized. In one embodiment, the constant bias voltage may be provided by a constant current source comprising a series of amplifiers each having a gain significantly less than one connected to a triple cascode. | 12-25-2014 |
20160149573 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING LOGIC CIRCUIT - A logic circuit that can retain a state even without power supply is provided. The logic circuit includes a first circuit, a pair of retention circuits, and a second circuit. The pair of retention circuits includes two switches electrically connected to each other in series and a capacitor electrically connected to a connection portion of the two switches. Each of the two switches is formed using an oxide semiconductor transistor. The first circuit has a function of generating complementary data from a piece of input data. The pair of retention circuits retains the complementary data. The second circuit has a function of amplifying the complementary data retained in the pair of retention circuits. | 05-26-2016 |
20090146693 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential. | 06-11-2009 |
20100060322 | ADIABATIC CMOS DESIGN - An integrated circuit comprising a plurality of CMOS modules ( | 03-11-2010 |
20100090722 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 04-15-2010 |
20100134149 | ULTRA-LOW-POWER CIRCUIT - An ultra-low-power transconductance device is provided, (FIG. | 06-03-2010 |
20100164547 | BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION - A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates. | 07-01-2010 |
20100171525 | HYBRID RESISTOR/FET-LOGIC DEMULTIPLEXER ARCHITECTURE DESIGN FOR HYBRID CMOS/NANODEVICE CIRCUITS - A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux. | 07-08-2010 |
20100182047 | Dynamic Logic Circuit Including Dynamic Standard Cell Library - A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors. | 07-22-2010 |
20110057685 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE LAYOUT METHOD - There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed. | 03-10-2011 |
20110148466 | LOGIC-CELL-COMPATIBLE DECOUPLING CAPACITOR - An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. | 06-23-2011 |
20110156755 | FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION - Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes. | 06-30-2011 |
20120001655 | BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO) - A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell. | 01-05-2012 |
20120074985 | SEMICONDUCTOR DEVICE - In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly. | 03-29-2012 |
20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 05-24-2012 |
20120194219 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal. The high-voltage terminal and the low-voltage terminal are connected respectively to the bulk connection of the p-type transistor and the bulk connection of the n-type transistor. | 08-02-2012 |
20120235706 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 09-20-2012 |
20120293209 | LOGIC CIRCUIT - A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile. | 11-22-2012 |
20120293210 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced. | 11-22-2012 |
20130043906 | CMOS LOGIC CIRCUIT - A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal. | 02-21-2013 |
20140132306 | CMOS LOGIC CIRCUIT USING PASSIVE INTERNAL BODY TIE BIAS - This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor. | 05-15-2014 |
20140375356 | Delay Circuit Independent of Supply Voltage - A delay circuit in which the delay is independent of variations in the power supply which powers the logic gates of the delay circuit is disclosed. By separating the CMOS transistors that form each logic gate by additional CMOS bias transistors which are biased at a controlled voltage, variations in the gate delay of the inverter transistors due to variations in the power supply voltage for the inverter transistors may be minimized. In one embodiment, the constant bias voltage may be provided by a constant current source comprising a series of amplifiers each having a gain significantly less than one connected to a triple cascode. | 12-25-2014 |
20160149573 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING LOGIC CIRCUIT - A logic circuit that can retain a state even without power supply is provided. The logic circuit includes a first circuit, a pair of retention circuits, and a second circuit. The pair of retention circuits includes two switches electrically connected to each other in series and a capacitor electrically connected to a connection portion of the two switches. Each of the two switches is formed using an oxide semiconductor transistor. The first circuit has a function of generating complementary data from a piece of input data. The pair of retention circuits retains the complementary data. The second circuit has a function of amplifying the complementary data retained in the pair of retention circuits. | 05-26-2016 |
326103000 | Complementary FET's | 21 |
20090146693 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential. | 06-11-2009 |
20100060322 | ADIABATIC CMOS DESIGN - An integrated circuit comprising a plurality of CMOS modules ( | 03-11-2010 |
20100090722 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 04-15-2010 |
20100134149 | ULTRA-LOW-POWER CIRCUIT - An ultra-low-power transconductance device is provided, (FIG. | 06-03-2010 |
20100164547 | BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION - A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates. | 07-01-2010 |
20100171525 | HYBRID RESISTOR/FET-LOGIC DEMULTIPLEXER ARCHITECTURE DESIGN FOR HYBRID CMOS/NANODEVICE CIRCUITS - A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux. | 07-08-2010 |
20100182047 | Dynamic Logic Circuit Including Dynamic Standard Cell Library - A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors. | 07-22-2010 |
20110057685 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE LAYOUT METHOD - There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed. | 03-10-2011 |
20110148466 | LOGIC-CELL-COMPATIBLE DECOUPLING CAPACITOR - An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. | 06-23-2011 |
20110156755 | FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION - Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes. | 06-30-2011 |
20120001655 | BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO) - A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell. | 01-05-2012 |
20120074985 | SEMICONDUCTOR DEVICE - In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly. | 03-29-2012 |
20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 05-24-2012 |
20120194219 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal. The high-voltage terminal and the low-voltage terminal are connected respectively to the bulk connection of the p-type transistor and the bulk connection of the n-type transistor. | 08-02-2012 |
20120235706 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 09-20-2012 |
20120293209 | LOGIC CIRCUIT - A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile. | 11-22-2012 |
20120293210 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced. | 11-22-2012 |
20130043906 | CMOS LOGIC CIRCUIT - A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal. | 02-21-2013 |
20140132306 | CMOS LOGIC CIRCUIT USING PASSIVE INTERNAL BODY TIE BIAS - This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor. | 05-15-2014 |
20140375356 | Delay Circuit Independent of Supply Voltage - A delay circuit in which the delay is independent of variations in the power supply which powers the logic gates of the delay circuit is disclosed. By separating the CMOS transistors that form each logic gate by additional CMOS bias transistors which are biased at a controlled voltage, variations in the gate delay of the inverter transistors due to variations in the power supply voltage for the inverter transistors may be minimized. In one embodiment, the constant bias voltage may be provided by a constant current source comprising a series of amplifiers each having a gain significantly less than one connected to a triple cascode. | 12-25-2014 |
20160149573 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING LOGIC CIRCUIT - A logic circuit that can retain a state even without power supply is provided. The logic circuit includes a first circuit, a pair of retention circuits, and a second circuit. The pair of retention circuits includes two switches electrically connected to each other in series and a capacitor electrically connected to a connection portion of the two switches. Each of the two switches is formed using an oxide semiconductor transistor. The first circuit has a function of generating complementary data from a piece of input data. The pair of retention circuits retains the complementary data. The second circuit has a function of amplifying the complementary data retained in the pair of retention circuits. | 05-26-2016 |
20090146693 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential. | 06-11-2009 |
20100060322 | ADIABATIC CMOS DESIGN - An integrated circuit comprising a plurality of CMOS modules ( | 03-11-2010 |
20100090722 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 04-15-2010 |
20100134149 | ULTRA-LOW-POWER CIRCUIT - An ultra-low-power transconductance device is provided, (FIG. | 06-03-2010 |
20100164547 | BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION - A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates. | 07-01-2010 |
20100171525 | HYBRID RESISTOR/FET-LOGIC DEMULTIPLEXER ARCHITECTURE DESIGN FOR HYBRID CMOS/NANODEVICE CIRCUITS - A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux. | 07-08-2010 |
20100182047 | Dynamic Logic Circuit Including Dynamic Standard Cell Library - A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors. | 07-22-2010 |
20110057685 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE LAYOUT METHOD - There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed. | 03-10-2011 |
20110148466 | LOGIC-CELL-COMPATIBLE DECOUPLING CAPACITOR - An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. | 06-23-2011 |
20110156755 | FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION - Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes. | 06-30-2011 |
20120001655 | BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO) - A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell. | 01-05-2012 |
20120074985 | SEMICONDUCTOR DEVICE - In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly. | 03-29-2012 |
20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 05-24-2012 |
20120194219 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal. The high-voltage terminal and the low-voltage terminal are connected respectively to the bulk connection of the p-type transistor and the bulk connection of the n-type transistor. | 08-02-2012 |
20120235706 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 09-20-2012 |
20120293209 | LOGIC CIRCUIT - A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile. | 11-22-2012 |
20120293210 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced. | 11-22-2012 |
20130043906 | CMOS LOGIC CIRCUIT - A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal. | 02-21-2013 |
20140132306 | CMOS LOGIC CIRCUIT USING PASSIVE INTERNAL BODY TIE BIAS - This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor. | 05-15-2014 |
20140375356 | Delay Circuit Independent of Supply Voltage - A delay circuit in which the delay is independent of variations in the power supply which powers the logic gates of the delay circuit is disclosed. By separating the CMOS transistors that form each logic gate by additional CMOS bias transistors which are biased at a controlled voltage, variations in the gate delay of the inverter transistors due to variations in the power supply voltage for the inverter transistors may be minimized. In one embodiment, the constant bias voltage may be provided by a constant current source comprising a series of amplifiers each having a gain significantly less than one connected to a triple cascode. | 12-25-2014 |
20160149573 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING LOGIC CIRCUIT - A logic circuit that can retain a state even without power supply is provided. The logic circuit includes a first circuit, a pair of retention circuits, and a second circuit. The pair of retention circuits includes two switches electrically connected to each other in series and a capacitor electrically connected to a connection portion of the two switches. Each of the two switches is formed using an oxide semiconductor transistor. The first circuit has a function of generating complementary data from a piece of input data. The pair of retention circuits retains the complementary data. The second circuit has a function of amplifying the complementary data retained in the pair of retention circuits. | 05-26-2016 |