| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326101000 | SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS | 83 |
| 20100148822 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING DEDICATED MEMORY STACKS IN A VERTICAL LAYER FORMAT - A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips. | 06-17-2010 |
| 20100066411 | LOGIC CIRCUIT USING METAL-INSULATOR TRANSITION (MIT) DEVICE - Provided is a logic circuit comprising a metal-insulator transition (MIT) device, including: an MIT device unit including an MIT thin film, an electrode thin film contacting the MIT thin film, and at least one MIT device undergoing a discontinuous MIT at a transition voltage V | 03-18-2010 |
| 20100073031 | NANOTUBE-BASED SWITCHING ELEMENTS WITH MULTIPLE CONTROLS AND LOGIC CIRCUITS HAVING SAID ELEMENTS - Boolean logic circuits comprising nanotube-based switching elements with multiple controls. The Boolean logic circuits include input and output terminals and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. Each switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel along the nanotube channel element. At least one nanotube switching element non-volatilely retains an informational state and at least one nanotube switching elements volatilely retains an informational state. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. Dual rail cascode logic circuits may also be constructed from the nanotube switching elements. | 03-25-2010 |
| 20090091351 | CHIP IDENTIFICATION SYSTEM AND METHOD - Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key. | 04-09-2009 |
| 20100264955 | METAL PROGRAMMABLE LOGIC AND MULTIPLE FUNCTION PIN INTERFACE - Some of the embodiments of the present invention provide an integrated circuit device including a first metal interconnect, an end of which is coupled to a core of the integrated circuit device, a second metal interconnect, an end of which is coupled to a first input/output (I/O) pin, and a third metal interconnect configured to be coupled to the first metal interconnect and to the second metal interconnect. Other embodiments are also described and claimed. | 10-21-2010 |
| 20090184733 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (≦90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 07-23-2009 |
| 20090033368 | LOGIC BLOCK, A MULTI-TRACK STANDARD CELL LIBRARY, A METHOD OF DESIGNING A LOGIC BLOCK AND AN ASIC EMPLOYING THE LOGIC BLOCK - A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standard cells having a first track height and (2) a second row of standard cells adjacent to the first row and having a second track height that differs from the first track height. | 02-05-2009 |
| 20100123481 | Semiconductor integrated circuit - A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other. | 05-20-2010 |
| 20100127732 | CMOS-Process-Compatible Programmable Via Device - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided comprising a substrate; a dielectric layer on the substrate; a heater on at least a portion of a side of the dielectric layer opposite the substrate; a first oxide layer over the side of the dielectric layer opposite the substrate and surrounding at least a portion of the heater; a first capping layer over a side of the first oxide layer opposite the dielectric layer; at least one programmable via extending through the first capping layer and the first oxide layer and in contact with the heater, the programmable via comprising at least one phase change material; a second capping layer over the programmable via; a second oxide layer over a side of the first capping layer opposite the first oxide layer; a pair of first conductive vias, each extending through the first and second oxide layers and the first capping layer, and in contact with the heater; and a second conductive via, located between the pair of first conductive vias, extending through the second oxide layer and in contact with the second capping layer. | 05-27-2010 |
| 20090278569 | Semiconductor Device and its Manufacturing Method, Semiconductor Manufacturing Mask, and Optical Proximity Processing Method - An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area ( | 11-12-2009 |
| 20080238486 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS - A semiconductor integrated circuit design method includes a step (L) of providing layout information for laying out elements making up a logical circuit on a semiconductor substrate; a step (P) of providing logical circuit information; a step (a) of classifying logical circuits in response to the logical circuit propagation route of a signal based on the logical circuit information and a step (b) of isolating the logical circuits forming the route obtained in the classifying step (a) for each number of stages; a step (c) of classifying the elements making up the logical circuit according to substrate voltage for each number of stages of the logical circuit; and a layout correction step (d) of correcting the layout information so that each element with the larger stage number of the logical circuit is placed at a point closer to a substrate contact. | 10-02-2008 |
| 20100201400 | METHOD FOR IMPLEMENTING FUNCTIONAL CHANGES INTO A DESIGN LAYOUT OF AN INTEGRATED DEVICE, IN PARTICULAR A SYSTEM-ON-CHIP, BY MEANS OF MASK PROGRAMMABLE FILLING CELLS - A System-on-Chip (SoC) may include logic blocks connected to each other and to external connections, and a hardware debug infrastructure logic connected to the logic blocks and for performing functional changes to a design layout of the SoC. The hardware debug infrastructure logic may include software re-configurable modules based upon the logic blocks obtained from substituting a mask programmable ECO base cell configured as a functional logic cell for a logic cell in the design layout. | 08-12-2010 |
| 20120293206 | PROGRAMMABLE LOGIC DEVICE - An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device. | 11-22-2012 |
| 20090212819 | METHOD AND SYSTEM FOR CHANGING CIRCUITS IN AN INTEGRATED CIRCUIT - A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first threshold voltage; and replacing at least one of the plurality of circuit books with at least one gate array book having a second threshold voltage that is lower than the first threshold voltage. | 08-27-2009 |
| 20120194217 | INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR - One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides. | 08-02-2012 |
| 20090322377 | METHOD AND SYSTEM FOR SIZING FLOW CONTROL BUFFERS - A system that includes a first buffer and a second buffer, wherein the first buffer and the second buffer are connected to the same input, wherein a size of the first buffer is defined by a distance of the first buffer from the input and a transfer rate of data, wherein a size of the second buffer is defined by a distance of the second buffer from the input and the transfer rate of data, and wherein the distance between the first buffer and the input is different from the distance between the second buffer and the input. | 12-31-2009 |
| 20120032704 | INTEGRATION OF OPEN SPACE/DUMMY METAL AT CAD FOR PHYSICAL DEBUG OF NEW SILICON - An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is between a top metallization level and a base level on which the functional block is formed in the IC device. The access pad at the metallization level provides a contact to access an underlying circuit of the functional block so that the functional integrity of the functional block of the IC device can be verified during probing. | 02-09-2012 |
| 20100301901 | UNIVERSAL TWO-INPUT LOGIC GATE THAT IS CONFIGURABLE AND CONNECTABLE IN AN INTEGRATED CIRCUIT BY A SINGLE MASK LAYER ADJUSTMENT - A spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs, and whose output is utilized as a logic gate output. Each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function. By modifying a single photolithographic mask, the spare logic gate can be: configured to perform the desired logic function; connected into a target logic circuit; or both configured and connected into a target logic circuit. | 12-02-2010 |
| 20110025378 | SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD THEREOF - A layout method for a semiconductor integrated circuit includes, generating logic cell layout data by arranging logic cells and signal lines connected to said logic cells, by using an automatic place and root tool, generating variable capacitor cell layout data by arranging variable capacitor cells and control lines for controlling capacitance value of the variable capacitor cells, by using the automatic place and root tool, and generating layout data of the semiconductor integrated circuit, based on the logic cell layout data and the variable capacitor cell layout data. The generating variable capacitor cell layout data includes, arranging the control lines so as to be same as said signal lines in a resistance of a unit length in one wiring layer. | 02-03-2011 |
| 20100052729 | DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT - An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word. | 03-04-2010 |
| 20120119785 | INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR - One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides. | 05-17-2012 |
| 20100283508 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A semiconductor chip includes a plurality of pads, input circuits or output circuits that are electrically connected to the pads, a main control unit that outputs a read access signal, the read access signal controlling reading of signals from an external circuit or an internal circuit, and activation control units that control activation of the input circuits or the output circuits that are electrically connected to the pads based on the read access signal, the pads receiving the signals from the external circuit or the internal circuit. | 11-11-2010 |
| 20120249182 | Power Routing in Standard Cell Designs - A cell-based architecture for an integrated circuit. A row of cell instances borders a first adjacent row of cell instances along a first boundary and a second adjacent row of cell instances along a second boundary. A first power rail (e.g., carrying an auxiliary voltage) extends along the first boundary. A second power rail (e.g., VSS) extends along the second boundary. The second power rail is wider than the first power rail. Additionally, a third power rail (e.g., VDD) extends across the interior of the second row of cells. | 10-04-2012 |
| 20120161814 | STACKED DEVICE IDENTIFICATION ASSIGNMENT - Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die. | 06-28-2012 |
| 20100271071 | Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks - A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack. | 10-28-2010 |
| 20100225354 | LOOKUP TABLE, SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR MAKING LOOKUP TABLE AND METHOD FOR MAKING SEMICONDUCTOR INTEGRATED CIRCUIT - A lookup table includes a single via layer having 2 | 09-09-2010 |
| 20120081150 | Method of adapting standard cells - A method of adapting a layout of a standard cell of an integrated circuit is provided. A current collection path in the standard cell is selected which connects components within the standard cell to an output connection, wherein the current collection path is arranged to collect current from the components at a plurality of current collection points arranged along its length. A maximum current location on the current collection path is determined at which a maximum possible current flow in the current collection path will occur if the output connection is connected there, the maximum possible current flow being a sum of current contributions from the current collection points. A maximum width of the current collection path at the maximum current location is determined such that the maximum width satisfies a minimum path width requirement with respect to the maximum possible current flow. Then a local width of the current collection path at a selected distance from the maximum current location is determined, the local width being less than or equal to the maximum width, such that the local width satisfies the minimum path width requirement with respect to a maximum local current that will occur at the selected distance, the maximum local current being a sum of the current contributions from those current collection points which contribute to the local current. | 04-05-2012 |
| 20100231261 | Apparatus and Method for Mixed Single-Rail and Dual-Rail Combinational Logic with Completion Detection - A computer readable storage medium includes executable instructions to receive a specification of a combinational logic circuit. The specification of the combinational logic circuit is converted to a Single-Rail un-encoded circuit and a Dual-Rail encoded circuit, which periodically encodes a null value, a first valid state and a second valid state on two wires. A logic operation of the Single-Rail un-encoded circuit transpires during processing of a null value by the Dual-Rail encoded circuit. | 09-16-2010 |
| 326102000 | Field-effect transistor | 55 |
| 20130027083 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W | 01-31-2013 |
| 20130088261 | LOW LEAKAGE SPARE GATES FOR INTEGRATED CIRCUITS - Devices, systems, methods, and other embodiments associated with spare gates are described. In one embodiment, a spare gate in an integrated circuit has a disconnected discharge path to minimize or eliminate current leakage. | 04-11-2013 |
| 20100001763 | Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same - A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same. | 01-07-2010 |
| 20100085081 | INVERTER MANUFACTURING METHOD AND INVERTER - To provide an enhancement-depletion (E/D) inverter which can be easily manufactured, in the present invention, a method of manufacturing an inverter which is composed of an oxide semiconductor in which a channel layer includes at least one element selected from In, Ga and Zn formed on a same substrate, the inverter being the E/D inverter having plural thin film transistors, is characterized by comprising the steps of: forming a first transistor and a second transistor, the thicknesses of the channel layers of the first and second transistors being mutually different; and executing heat treatment to at least one of the channel layers of the first and second transistors. | 04-08-2010 |
| 20120293208 | Semiconductor Device - As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a plurality of capacitors. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region. | 11-22-2012 |
| 20080309374 | Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same - A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same. | 12-18-2008 |
| 20120293207 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit in which data is held even after power is turned off is provided. Further, a novel logic circuit whose power consumption can be reduced is provided. In the logic circuit, a comparator comparing two output nodes, a charge holding portion, and an output-node-potential determining portion are electrically connected to each other. Such a structure enables data to be held in the logic circuit even after power is turned off. Further, the total number of transistors in the logic circuit can be reduced. Furthermore, the area of the logic circuit can be reduced by stacking a transistor including an oxide semiconductor and a transistor including silicon. | 11-22-2012 |
| 20090243658 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance. At this point in time, a resistance value as desired is attained through combination of decoupling capacitors having threshold voltages Vth differing from each other. | 10-01-2009 |
| 20100148823 | SEMICONDUCTOR DEVICE - An RESURF region is formed so as to surround a high-potential logic region with an isolation region interposed therebetween, in which a sense resistance and a first logic circuit which are applied with a high potential are formed in high-potential logic region. On the outside of RESURF region, a second logic circuit region is formed, which is applied with the driving voltage level required for driving a second logic circuit with respect to the ground potential. In RESURF region, a drain electrode of a field-effect transistor is formed along the inner periphery, and a source electrode is formed along the outer periphery. Furthermore, a polysilicon resistance connected to sense resistance is formed in the shape of a spiral from the inner peripheral side toward the outer peripheral side. | 06-17-2010 |
| 20120194218 | 3D Semiconductor Device - A semiconductor device includes a first transistor layer and a second transistor layer overlaying the first transistor layer, wherein said first transistor layer comprises a plurality of flip-flops each having a selectively coupleable additional input generated by said second transistor layer. | 08-02-2012 |
| 20110062992 | LOGIC CIRCUIT, LIGHT EMITTING DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - An object is to obtain a desired threshold voltage of a thin film transistor using an oxide semiconductor. Another object is to suppress a change of the threshold voltage over time. Specifically, an object is to apply the thin film transistor to a logic circuit formed using a transistor having a desired threshold voltage. In order to achieve the above object, thin film transistors including oxide semiconductor layers with different thicknesses may be formed over the same substrate, and the thin film transistors whose threshold voltages are controlled by the thicknesses of the oxide semiconductor layers may be used to form a logic circuit. In addition, by using an oxide semiconductor film in contact with an oxide insulating film formed after dehydration or dehydrogenation treatment, a change in threshold voltage over time is suppressed and the reliability of a logic circuit can be improved. | 03-17-2011 |
| 20110102019 | SEMICONDUCTOR DEVICE FORMED ON A SOI SUBSTRATE - Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate. | 05-05-2011 |
| 20110084731 | LOGIC CIRCUIT AND DISPLAY DEVICE HAVING THE SAME - It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided. | 04-14-2011 |
| 20110089975 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×10 | 04-21-2011 |
| 20110181319 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. | 07-28-2011 |
| 20120256657 | FIELD EFFECT TRANSISTOR, AND ELECTRIC CIRCUIT - The invention relates to a field effect transistor comprising at least one source electrode layer and at least one drain electrode layer arranged in the same plane, a semiconductor layer, an insulator layer and a gate electrode layer, wherein the gate electrode layer, as seen perpendicular to the plane of the at least one source electrode layer and the at least one drain electrode layer, only partly covers a channel arranged between the at least one source electrode layer and the at least one drain electrode layer. | 10-11-2012 |
| 20120274357 | Reducing Narrow Gate Width Effects in an Integrated Circuit Design - A method for reducing narrow gate width effects in an integrated circuit includes finding the smallest transistor channel widths that are larger than the minimum width for the technology for library cells that produce logic blocks that meet timing constraints while using the least amount of power and have the smallest possible area. The method may include characterizing a device library while varying process, voltage and temperature parameters, and synthesizing an HDL representation of a functional logic block including cells from the device library. The method may also include determining whether timing, area, and power values of the functional logic block are within a predetermined range. In response to the timing, area, and power values not being within the predetermined range, iteratively increasing the channel width of at least a portion of the transistors of at least one of the cells in the device library. | 11-01-2012 |
| 20120280715 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - The logic circuit includes an input terminal, an output terminal, a main logic circuit portion that is electrically connected to the input terminal and the output terminal, and a switching element electrically connected to the input terminal and the main logic circuit portion. Further, a first terminal of the switching element is electrically connected to the input terminal, a second terminal of the switching element is electrically connected to a gate of at least one transistor included in the main logic circuit portion, and the switching element is a transistor in which a leakage current in an off state per micrometer of channel width is lower than or equal to 1×10 | 11-08-2012 |
| 20130009668 | 4-TERMINAL PIEZOELECTRONIC TRANSISTOR (PET) - A 4-terminal piezoelectronic transistor (PET) which includes a piezoelectric (PE) material disposed between first and second electrodes; an insulator material disposed on the second electrode; a third electrode disposed on the insulator material and a piezoresistive (PR) material disposed between the third electrode and a fourth electrode. An applied voltage across the first and second electrodes causing a pressure from the PE material to be applied to the PR material through the insulator material, the electrical resistance of the PR material being dependent upon the pressure applied by the PE material. The first and second electrodes are electrically isolated from the third and fourth electrodes. Also disclosed are logic devices fabricated from 4-terminal PETs and a method of fabricating a 4-terminal PET. | 01-10-2013 |
| 326103000 | Complementary FET`s | 18 |
| 20130043906 | CMOS LOGIC CIRCUIT - A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal. | 02-21-2013 |
| 20090146693 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential. | 06-11-2009 |
| 20100090722 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 04-15-2010 |
| 20120293209 | LOGIC CIRCUIT - A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile. | 11-22-2012 |
| 20120293210 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced. | 11-22-2012 |
| 20120194219 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal. The high-voltage terminal and the low-voltage terminal are connected respectively to the bulk connection of the p-type transistor and the bulk connection of the n-type transistor. | 08-02-2012 |
| 20100182047 | Dynamic Logic Circuit Including Dynamic Standard Cell Library - A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors. | 07-22-2010 |
| 20110057685 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE LAYOUT METHOD - There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed. | 03-10-2011 |
| 20100164547 | BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION - A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates. | 07-01-2010 |
| 20100060322 | ADIABATIC CMOS DESIGN - An integrated circuit comprising a plurality of CMOS modules ( | 03-11-2010 |
| 20110148466 | LOGIC-CELL-COMPATIBLE DECOUPLING CAPACITOR - An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. | 06-23-2011 |
| 20110156755 | FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION - Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes. | 06-30-2011 |
| 20120001655 | BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO) - A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell. | 01-05-2012 |
| 20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 05-24-2012 |
| 20120074985 | SEMICONDUCTOR DEVICE - In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly. | 03-29-2012 |
| 20100134149 | ULTRA-LOW-POWER CIRCUIT - An ultra-low-power transconductance device is provided, (FIG. | 06-03-2010 |
| 20120235706 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 09-20-2012 |
| 20100171525 | HYBRID RESISTOR/FET-LOGIC DEMULTIPLEXER ARCHITECTURE DESIGN FOR HYBRID CMOS/NANODEVICE CIRCUITS - A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux. | 07-08-2010 |
| 20130043906 | CMOS LOGIC CIRCUIT - A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal. | 02-21-2013 |
| 20090146693 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential. | 06-11-2009 |
| 20100090722 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 04-15-2010 |
| 20120293209 | LOGIC CIRCUIT - A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile. | 11-22-2012 |
| 20120293210 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced. | 11-22-2012 |
| 20120194219 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal. The high-voltage terminal and the low-voltage terminal are connected respectively to the bulk connection of the p-type transistor and the bulk connection of the n-type transistor. | 08-02-2012 |
| 20100182047 | Dynamic Logic Circuit Including Dynamic Standard Cell Library - A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors. | 07-22-2010 |
| 20110057685 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE LAYOUT METHOD - There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed. | 03-10-2011 |
| 20100164547 | BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION - A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates. | 07-01-2010 |
| 20100060322 | ADIABATIC CMOS DESIGN - An integrated circuit comprising a plurality of CMOS modules ( | 03-11-2010 |
| 20110148466 | LOGIC-CELL-COMPATIBLE DECOUPLING CAPACITOR - An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. | 06-23-2011 |
| 20110156755 | FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION - Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes. | 06-30-2011 |
| 20120001655 | BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO) - A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell. | 01-05-2012 |
| 20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 05-24-2012 |
| 20120074985 | SEMICONDUCTOR DEVICE - In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly. | 03-29-2012 |
| 20100134149 | ULTRA-LOW-POWER CIRCUIT - An ultra-low-power transconductance device is provided, (FIG. | 06-03-2010 |
| 20120235706 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 09-20-2012 |
| 20100171525 | HYBRID RESISTOR/FET-LOGIC DEMULTIPLEXER ARCHITECTURE DESIGN FOR HYBRID CMOS/NANODEVICE CIRCUITS - A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux. | 07-08-2010 |
| 326103000 | Complementary FET's | 18 |
| 20130043906 | CMOS LOGIC CIRCUIT - A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal. | 02-21-2013 |
| 20090146693 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential. | 06-11-2009 |
| 20100090722 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 04-15-2010 |
| 20120293209 | LOGIC CIRCUIT - A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile. | 11-22-2012 |
| 20120293210 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced. | 11-22-2012 |
| 20120194219 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal. The high-voltage terminal and the low-voltage terminal are connected respectively to the bulk connection of the p-type transistor and the bulk connection of the n-type transistor. | 08-02-2012 |
| 20100182047 | Dynamic Logic Circuit Including Dynamic Standard Cell Library - A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors. | 07-22-2010 |
| 20110057685 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE LAYOUT METHOD - There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed. | 03-10-2011 |
| 20100164547 | BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION - A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates. | 07-01-2010 |
| 20100060322 | ADIABATIC CMOS DESIGN - An integrated circuit comprising a plurality of CMOS modules ( | 03-11-2010 |
| 20110148466 | LOGIC-CELL-COMPATIBLE DECOUPLING CAPACITOR - An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. | 06-23-2011 |
| 20110156755 | FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION - Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes. | 06-30-2011 |
| 20120001655 | BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO) - A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell. | 01-05-2012 |
| 20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 05-24-2012 |
| 20120074985 | SEMICONDUCTOR DEVICE - In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly. | 03-29-2012 |
| 20100134149 | ULTRA-LOW-POWER CIRCUIT - An ultra-low-power transconductance device is provided, (FIG. | 06-03-2010 |
| 20120235706 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 09-20-2012 |
| 20100171525 | HYBRID RESISTOR/FET-LOGIC DEMULTIPLEXER ARCHITECTURE DESIGN FOR HYBRID CMOS/NANODEVICE CIRCUITS - A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux. | 07-08-2010 |
| 20130043906 | CMOS LOGIC CIRCUIT - A CMOS logic circuit includes a resistive element that is connected to a first voltage line at a first end thereof. The CMOS logic circuit includes a first inverter circuit having a first MOS transistor and a second MOS transistor. The CMOS logic circuit includes a second inverter circuit having a third MOS transistor and a fourth MOS transistor. The CMOS logic circuit includes a fifth MOS transistor that is connected in parallel with the resistive element between the first voltage line and the first end of the first MOS transistor and the gate of which is connected to the second end of the third MOS transistor. The CMOS logic circuit includes a sixth MOS transistor that is connected between the first voltage line and the first output terminal. | 02-21-2013 |
| 20090146693 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential. | 06-11-2009 |
| 20100090722 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 04-15-2010 |
| 20120293209 | LOGIC CIRCUIT - A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile. | 11-22-2012 |
| 20120293210 | SEMICONDUCTOR INTEGRATED CIRCUIT - A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced. | 11-22-2012 |
| 20120194219 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit contains first and second logic inputs, first and second dedicated logic terminals, a high-voltage terminal configured for connection to a high constant voltage, a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor and an n-type transistor. The p-type transistor and n-type transistor each have a respective outer diffusion connection, gate connection, inner diffusion connection, and bulk connection. The first and second dedicated logic terminals are connected respectively to the outer diffusion connection of the p-type transistor and the outer diffusion connection of the n-type transistor. The inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor are connected together to form a common diffusion logic terminal. The high-voltage terminal and the low-voltage terminal are connected respectively to the bulk connection of the p-type transistor and the bulk connection of the n-type transistor. | 08-02-2012 |
| 20100182047 | Dynamic Logic Circuit Including Dynamic Standard Cell Library - A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors. | 07-22-2010 |
| 20110057685 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE LAYOUT METHOD - There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed. | 03-10-2011 |
| 20100164547 | BASE CELL FOR ENGINEERING CHANGE ORDER (ECO) IMPLEMENTATION - A base cell for an Engineering Change Order (ECO) implementation having at least a first pair of CMOS transistors and a second pair of CMOS transistors, characterized in that said at least first pair of CMOS transistors have a common gate and said at least second pair of CMOS transistors have separate gates. | 07-01-2010 |
| 20100060322 | ADIABATIC CMOS DESIGN - An integrated circuit comprising a plurality of CMOS modules ( | 03-11-2010 |
| 20110148466 | LOGIC-CELL-COMPATIBLE DECOUPLING CAPACITOR - An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. | 06-23-2011 |
| 20110156755 | FLEXIBLE CMOS LIBRARY ARCHITECTURE FOR LEAKAGE POWER AND VARIABILITY REDUCTION - Various exemplary embodiments relate to improved fabrication of CMOS transistor arrays for integrated circuits. Increased regularity in standard-cells using gate-isolation architecture may permit further reduction in feature size. MOSFETs may be spaced at roughly equal pitch and have increased channel lengths for leakage current reduction. Logic gates may be designed to have nominal channel lengths for speed and increased channel lengths for leakage current reduction. Further leakage current reduction may involve specialized channel lengths for isolation MOSFETs. Thus, the combination of the gate-isolation technique with MOSFETs having lengthened channels that are evenly spaced at substantially the same pitch may produce a flexible library architecture for improved standard-cell designs in advanced CMOS technology nodes. | 06-30-2011 |
| 20120001655 | BASE CELL FOR IMPLEMENTING AN ENGINEERING CHANGE ORDER (ECO) - A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell. | 01-05-2012 |
| 20120126853 | LOGIC CIRCUIT AND METHOD OF LOGIC CIRCUIT DESIGN - A complementary logic circuit, comprising: a first and second logic input; a first and second dedicated logic terminal; a p-type transistor network comprising multiple p-type transistors, for implementing a predetermined logic function, and having an outer diffusion connection connected to the first dedicated logic terminal, a first network gate connection connected to the first logic input, and an inner diffusion connection; and an n-type transistor network comprising multiple n-type transistors, for implementing a logic function complementary to the predetermined logic function, and having an outer diffusion connection connected to the second dedicated logic terminal, a first network gate connection connected to the second logic input, and an inner diffusion connection; the inner diffusion connections of the p-type transistor network and of the n-type transistor network being connected to form a common diffusion logic terminal. | 05-24-2012 |
| 20120074985 | SEMICONDUCTOR DEVICE - In the case where data is rewritten in a delay period of a signal in a flip flop and a shift register which use an inverted clock signal, current inhibiting charging may flow, whereby data cannot written quickly, so that charging is not completed, which makes operation unstable. In view of the above, a flip flop and a shift register without using an inverted clock signal, which have high stability are provided. Current inhibiting charging of a node where that current inhibiting charging flows is cut off at the time of rewriting data so that data is rewritten quickly. | 03-29-2012 |
| 20100134149 | ULTRA-LOW-POWER CIRCUIT - An ultra-low-power transconductance device is provided, (FIG. | 06-03-2010 |
| 20120235706 | High speed integrated circuit - A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs. | 09-20-2012 |
| 20100171525 | HYBRID RESISTOR/FET-LOGIC DEMULTIPLEXER ARCHITECTURE DESIGN FOR HYBRID CMOS/NANODEVICE CIRCUITS - A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux. | 07-08-2010 |
