Class / Patent application number | Description | Number of patent applications / Date published |
326081000 | CMOS | 58 |
20080204078 | LEVEL SHIFTER FOR PREVENTING STATIC CURRENT AND PERFORMING HIGH-SPEED LEVEL SHIFTING - A level shifter amplifies a voltage of a digital signal to a predetermined voltage and outputs the amplified signal. The level shifter is capable of preventing generation of static current, and performing high-speed level shifting by increasing the speed of charging electric charges into or discharging electric charges from an output terminal of a differential amplification circuit included in the level shifter. | 08-28-2008 |
20080204079 | Level shifting circuits for generating output signals having similar duty cycle ratios - A level shifting circuit includes a level shifting unit and an output buffer unit. The level shifting unit generates first and second output signals responsive to first and second input signals. The first and second input signals range between first and second voltage levels, and the first and second input signals are a first differential pair. The first and second output signals range between the first voltage level and a third voltage level greater than the second voltage level, and the first and second output signals are a second differential pair. The output buffer unit inverts the first and second output signals to provide third and fourth output signals, respectively. Duty ratios of the first and second output signals are determined based on delay times of the first and second input signals. | 08-28-2008 |
20080218213 | BIDIRECTIONAL LEVEL SHIFT CIRCUIT AND BIDIRECTIONAL BUS SYSTEM - A plurality of transistors are connected between an I | 09-11-2008 |
20080265941 | Driving circuits - A driving circuit comprising an input voltage source set, a reference voltage source, a voltage level shift unit, a logic unit, a safety unit, and an output voltage terminal. The input voltage source set provides an input voltage set. The reference voltage source provides a reference voltage. The voltage level shift unit raises one of levels of the input voltage set to a level of the reference voltage. The logic unit receives the reference voltage and the input voltage set and outputs a control voltage. The safety unit conducts the control voltage to a ground. The output voltage terminal receives the control voltage and outputs an output voltage. | 10-30-2008 |
20080303551 | Semiconductor device - A semiconductor device according to an embodiment of the present invention includes an output stage circuit including a first conductive type first transistor and a second conductive type second transistor, the first conductive type first transistor being connected between a first power supply terminal and an output terminal, the second conductive type second transistor being connected between a second power supply terminal and the output terminal and having a leak current larger than that of the first transistor, and an input stage circuit outputting a logic value setting the first transistor to a non-conductive state and setting the second transistor to a conductive state in accordance with a logic circuit disable signal input when the output stage circuit is in a disable state. | 12-11-2008 |
20090015293 | SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT CONTROL METHOD, AND SIGNAL TRANSMISSION CIRCUIT - A semiconductor integrated circuit, a semiconductor integrated circuit control method, and a signal transmission circuit realizing optimization of the performance of a semiconductor integrated circuit and reduction of the power consumption. In the semiconductor integrated circuit, the semiconductor integrated circuit control method, and the signal transmission circuit, functional circuit blocks ( | 01-15-2009 |
20090045844 | LEVEL SHIFTER AND SEMICONDUCTOR DEVICE HAVING OFF-CHIP DRIVER - Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate. | 02-19-2009 |
20090085606 | ELECTRONIC DEVICE AND INTEGRATED CIRCUIT - An electronic device with a CMOS circuit (CC) comprises a first driver circuit ( | 04-02-2009 |
20090128191 | ULTRA-LOW-POWER LEVEL SHIFTER, VOLTAGE TRANSFORM CIRCUIT AND RFID TAG INCLUDING THE SAME - A level shifter increase a voltage level of an output signal with relatively lower power consumption by adopting current-starved configuration. The level shifter includes an input unit and a driving unit. The input unit includes a current-starved inverter configured to generate a control signal in response to an input signal and a bias voltage. The input unit is powered by a first power supply voltage. The driving unit generates an output signal in response to the control signal. The output signal has a voltage level higher than the input signal, and the driving unit is powered by a second power supply voltage higher than the first power supply voltage. | 05-21-2009 |
20090140770 | INPUT/OUTPUT CIRCUIT - An input/output circuit, operable in an input mode and an output mode, for receiving data and an enable signal, the input/output circuit including an input/output terminal; a pull-up output transistor including a gate; a first logic circuit including an output node coupled to the gate of the pull-up output transistor; a pull-down output transistor including a gate; a second logic circuit coupled to the gate of the pull-down output transistor, and the second logic circuit inactivating the pull-down output transistor in the input mode; and a gate signal generation unit configured to generate a gate signal for inactivating the pull-up output transistor in accordance with the enable signal and an input signal provided from an external device to the input/output terminal in the input mode. | 06-04-2009 |
20090153191 | PRE-DRIVER LOGIC - At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal. | 06-18-2009 |
20090174434 | DESIGN METHOD AND ARCHITECTURE FOR POWER GATE SWITCH PLACEMENT - A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells. In one embodiment, fine-grained power gating is achieved by selectively providing non-power-gated logic cells among power-gated logic cells. | 07-09-2009 |
20090189640 | Semiconductor Device - According to an aspect of the present invention, there is provided a semiconductor device including: a first circuit portion including: a first circuit that is connected between a first high-side power line and a low-side power line and that outputs a second signal based on a first signal input thereto; and a second circuit portion including: a first transistor that is connected between a second high-side power line and a node and that has a normally-on characteristic; a second circuit that is connected between the node and the low-side power line and that outputs a third signal based on the second signal input thereto. | 07-30-2009 |
20090195269 | INPUT STAGE FOR MIXED-VOLTAGE-TOLERANT BUFFER WITH REDUCED LEAKAGE - A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node. | 08-06-2009 |
20090251173 | SINGLE-SUPPLY, SINGLE-ENDED LEVEL CONVERSION CIRCUIT FOR AN INTEGRATED CIRCUIT HAVING MULTIPLE POWER SUPPLY DOMAINS - A circuit comprises first, second, third, and fourth transistors. The first transistor has a first current electrode, a control electrode for receiving an input signal, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor for providing an output signal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to a first power supply voltage terminal. The third transistor has a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode coupled to the first current electrode of the first transistor. The fourth transistor has a first current electrode coupled to the control electrode of the third transistor, a control electrode coupled to the control electrodes of the first and second transistors, and a second current electrode coupled to the control electrode of the first transistor. | 10-08-2009 |
20100007380 | LEVEL SHIFTER AND LEVEL SHIFTING METHOD THEREOF - A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage. | 01-14-2010 |
20100013518 | CONFIGURATION BACKUP DEVICE FOR THE TERMINALS OF AN INTEGRATED CIRCUIT AND METHOD OF ENABLING THE DEVICE - The integrated circuit device ( | 01-21-2010 |
20100045342 | LEVEL TRANSLATOR CIRCUIT - A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating from an integrated circuit. | 02-25-2010 |
20100073028 | Level-converting flip-flop and pulse generator for clustered voltage scaling - Provided is a level converting flip-flop for clustered voltage scaling and a level-converting pulse generator for use in the flip-flop. The flip-flop may include a pulse generator that receives an input clock signal with a high level equal to a first level and generates a pulse signal with a high level that may be converted into a second level higher than the first level. The flip-flop may further include a latch that latches input data with a high level equal to a third level lower than the second level and outputs output data with a high level that may be converted into the second level in response to the pulse signal. The third level may be equal to the first level. A supply voltage of the second level may be used as a supply voltage to the latch. Both the pulse generator and the flip-flop may have a level converting function without additional circuits, and therefore, the operating speeds of the pulse generator and the flip-flop may be increased without increasing the area and power consumption of the system. | 03-25-2010 |
20100085080 | ELECTRONIC DEVICE WITH A HIGH VOLTAGE TOLERANT UNIT - An electronic device is provided with a high-voltage tolerant circuit. The high-voltage tolerant circuit comprises an input terminal for receiving an input signal (V | 04-08-2010 |
20100102851 | P-Type Source Bias Virtual Ground Restoration Apparatus - A virtual ground restoration circuit is used to substantially eliminate excessive current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Excessive current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground or common power source voltage, V | 04-29-2010 |
20100134146 | VOLTAGE LEVEL TRANSLATOR AND METHOD - A level translator includes an NMOS input transistor and a PMOS input transistor having respective gates receiving an input voltage. The input transistors compare the input voltage to respective first and second supply voltages. The input voltage is also applied to an inverter that is powered by the first and second supply voltages. An output terminal is coupled to a third supply voltage through a PMOS output transistor and to a fourth supply voltage through an NMOS output transistor. The third and fourth supply voltages are outside of a range bounded by the first and second supply voltages. The respective drains of the input transistors and the output of the inverter are coupled to the gates of the output transistors in a manner that either turns the PMOS output transistor ON and the NMOS output transistor OFF or turns the NMOS output transistor ON and the PMOS output transistor OFF. | 06-03-2010 |
20100156463 | PRE-DRIVER LOGIC - At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal. | 06-24-2010 |
20100213980 | ARCHITECTURE FOR EFFICIENT USAGE OF IO - An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level. | 08-26-2010 |
20100231259 | Logic circuit capable of level shifting - A logic circuit includes a logic gate unit, an inverter, and a switching circuit. The logic gate unit receives a power supply voltage and an input signal to output a first signal. The inverter receives the first signal to output a second signal. The switching circuit provides one of first and second power supply voltages as the power supply voltage of the logic gate unit in response to the first and second signals. The first power supply voltage and the second power supply voltage have different voltage levels, thus enabling stable level shifting. | 09-16-2010 |
20100231260 | Receiver Circuitry for Receiving Reduced Swing Signals From a Channel - A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly is less than the power supply of the transmitter. The receiver comprises a level shifter for offsetting the reduced swing signal, and an amplifier which receives both the reduced swing signal and its offset to produce a full swing signal output referenced to the power supply of the receiver. The full swing signal can thereafter be buffered, and eventually can be captured by a clock. Optionally, the disclosed reduced swing receiver also contains calibration circuitry for improving the integrity of the full swing signal output, and in particular for countering the effects of process, and in some embodiments temperature, variations, which alter the characteristics of the transistors which make up the receiver circuitry. More particularly, the calibration circuitry compensates for the unbalanced way in which process and temperature variations impact transistors of differing polarities (e.g., n-type and p-type). | 09-16-2010 |
20100301900 | Pre-Charged High-Speed Level Shifters - An integrated circuit structure includes a latch having a first output node and a second output node complementary to each other. A first pre-charge transistor has a source-drain path coupled between a positive power supply node and the first output node. A second pre-charge transistor has a source-drain path coupled between the positive power supply node and the second output node. The integrated circuit structure further includes a delay-inverter coupled between a signal input node and inputs of a first NMOS transistor and a second NMOS transistor in the latch. The delay-inverter is configured to allow one of the first pre-charge transistor and the second pre-charge transistor to pre-charge a respective one of the first output node and the second output node before an input signal at the signal input node arrives at a gate of a respective one of the first NMOS transistor and the second NMOS transistor. | 12-02-2010 |
20100315124 | LOW POWER RECEIVER CIRCUIT - Subject matter disclosed herein relates to circuit design, and more particularly relates to low power circuit techniques for receiver circuits. | 12-16-2010 |
20110001513 | CMOS INPUT BUFFER CIRCUIT - Provided is a complementary metal oxide semiconductor (CMOS) input buffer circuit that is capable of lower voltage operation with lower current consumption. The CMOS input buffer circuit includes: a depletion type NMOS transistor including a drain connected to a power supply terminal (VDD), and a gate connected to an output terminal; a PMOS transistor including a source connected to a source of the depletion type NMOS transistor, a drain connected to the output terminal, and a gate connected to an input terminal; and an NMOS transistor including a source connected to a reference terminal (GND), a gate connected to the input terminal, and a drain connected to the output terminal. | 01-06-2011 |
20110006810 | LOW-SWING CMOS INPUT CIRCUIT - The invention relates to a CMOS input circuit for receiving low-swing input signals, which is an alternative to the CMOS input circuits as known from the prior art. The CMOS input circuit according to the invention comprises a leveling circuit (LC) that is constructed for arranging, under control of a voltage associated with an output voltage of a CMOS input stage (Inv | 01-13-2011 |
20110043249 | High Voltage Tolerant Input/Output Interface Circuit - An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an emitter adapted for connection to a voltage return of the interface circuit, a base adapted to receive a first control signal, and a collector connected directly to the signal pad in an open collector configuration. The interface circuit further includes a MOS control circuit coupled to the parasitic bipolar transistor and being operative to generate the first control signal. The IO interface circuit may further include an active pull-up circuit connected between a voltage supply of the interface circuit and the signal pad. | 02-24-2011 |
20110204921 | LEVEL CONVERSION CIRCUIT - Circuit blocks and respectively convert high-voltage logic signals in which two logical values are expressed by a first signal potential and a second signal potential into low-voltage logic signals in which the two logical values are expressed by a third signal potential at least as large as the first signal potential and a fourth signal potential that is the third signal potential to which a positive voltage has been added and which is no greater than the second signal potential, and outputs the converted logic signals. The transistors in the circuit block are of the form of replacing the respective transistors of the circuit block with elements of opposite polarity, so that when the third signal potential is changed and operation of one of the circuit blocks and becomes difficult, the other operates normally. Consequently, stable level conversion can be accomplished. | 08-25-2011 |
20120013362 | LEVEL CONVERTER CIRCUIT FOR USE IN CMOS CIRCUIT DEVICE PROVIDED FOR CONVERTING SIGNAL LEVEL OF DIGITAL SIGNAL TO HIGHER LEVEL - A level converter circuit is provided for converting an input signal of a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. An amplifier circuit amplifies the input signal and outputs an amplified output signal, and a current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit upon change of the signal level of the input signal. A current detector circuit detects the generated control current, and controls the operating current of the amplifier circuit to correspond to the detected control current. The current generator circuit includes series-connected first and second nMOS transistors as inserted between the current detector circuit and the ground. The first nMOS transistor operates responsive to the input signal, and the second nMOS transistor operates responsive to an inverted signal of the input signal. | 01-19-2012 |
20120032702 | HARDENED PROGRAMMABLE DEVICES - Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data. | 02-09-2012 |
20120081149 | LEVEL SHIFT CIRCUIT - A level shift circuit is disclosed. The circuit includes a series circuit of a resistor and a switching device connected between a high voltage side power supply voltage in a secondary side voltage system and a low voltage side power supply voltage in a primary side voltage system, a series circuit of a resistor and a switching device connected between the high voltage side power supply voltage in the secondary side voltage system and the low voltage side power supply voltage in the primary side voltage system, and a latch malfunction protecting circuit operated in the secondary side voltage system to have voltages at a connection point of the resistor and the switching device and at a connection point of the resistor and the switching device inputted. | 04-05-2012 |
20120112790 | Level Shifter - A level shifter having first and second P-type transistors cross coupled at an output port thereof, wherein there are first and second voltage rising circuits coupled at gates of the first and second P-type transistors, respectively. A voltage level at the gate of the first P-type transistor is associated with an output signal of the level shifter. When an input signal, operated by a first power, of the level shifter rises, the first voltage rising circuit couples a second power to the gate of the first P-type transistor to speed up the rising of the output signal. The voltage level at the gate of the second P-type transistor is associated with an inverted output signal. When the input signal falls, the second voltage rising circuit couples the second power to the gate of the second P-type transistor to speed up the rising of the inverted output signal. | 05-10-2012 |
20120229164 | OUTPUT CIRCUIT AND OUTPUT CONTROL SYSTEM - An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor. | 09-13-2012 |
20120306537 | ULTRA-LOW VOLTAGE LEVEL SHIFTING CIRCUIT - A voltage level shifter having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) includes a first PMOS transistor and a second PMOS transistor each with a source connected to the VCCH, a gate of the first PMOS transistor being coupled to a drain of the second PMOS transistor, and a gate of the second PMOS transistor being coupled to a drain of the first PMOS transistor. The voltage level shifter further includes a first NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, such that the voltage level shifter can operate at a lower VCCL. | 12-06-2012 |
20130015883 | CMOS LOGIC INTEGRATED CIRCUITAANM HORI; ChikahiroAACI Kanagawa-kenAACO JPAAGP HORI; Chikahiro Kanagawa-ken JPAANM Takiba; AkiraAACI Kanagawa-kenAACO JPAAGP Takiba; Akira Kanagawa-ken JP - A CMOS logic integrated circuit includes a level shifter and a CMOS logic circuit. The level shifter converts a signal of a first logic level to a signal of a second logic level. The signal of the first logic level changes between a first low potential and a first high potential higher than the first low potential. The signal of the second logic level changes between the first low potential and a second high potential higher than the first high potential. The CMOS logic circuit includes a first N-channel type MOSFET and a second N-channel type MOSFET. The second N-channel type MOSFET is connected in series with the first N-channel type MOSFET. A first signal of the first logic level is input into a gate of the first N-channel type MOSFET. A second signal of the second logic level has an inversion relationship with the first signal. | 01-17-2013 |
20130033289 | INPUT AND OUTPUT BUFFER INCLUDING A DYNAMIC DRIVER REFERENCE GENERATOR - A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad. | 02-07-2013 |
20130321027 | Circuit Arrangements and Methods of Operating the Same - In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load. | 12-05-2013 |
20140002134 | STATE DEFINITION AND RETENTION CIRCUIT | 01-02-2014 |
20140176189 | DYNAMIC VOLTAGE SCALING SYSTEM HAVING TIME BORROWING AND LOCAL BOOSTING CAPABILITY - A dynamic voltage scaling system having time borrowing and local boosting capability, including: a time borrowing circuit and a local boost circuit. The time borrowing circuit connected electrically between a primary stage logic circuit and a secondary stage logic circuit is activated by an all-domain clock signal, and then generates an output data to the secondary stage logic circuit based on input data to the primary stage logic circuit. The local boost circuit is connected to a low working voltage line, when input data of the time borrowing circuit lags behind a positive level of said all-domain clock signal, the time borrowing circuit delays fetching data by a flip flop and changes state to produce a warning signal, so that the local boost circuit disconnects its connection with said low working voltage line, and is connected electrically to a high working voltage line. | 06-26-2014 |
20140218070 | VOLTAGE TRANSLATOR - A voltage translator translates an input voltage signal in a low voltage domain into a output voltage signal in a high voltage domain using a latch that includes a pair of cross-coupled inverters. The bottom rail voltages for the cross-coupled inverters are varied dynamically to speed switching time for the voltage translator. | 08-07-2014 |
20140300386 | VOLTAGE LEVEL SHIFTER CIRCUIT, SYSTEM, AND METHOD FOR HIGH SPEED APPLICATIONS - A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain. The second inverter includes a pair of transistors of opposite conductivity type, and further includes at least one additional transistor driven by a voltage in the first voltage domain. The additional transistors are operable to approximately equalize the fall times of output signals generated by the first and second inverters. | 10-09-2014 |
20150123709 | REFERENCE-VOLTAGE-LESS PSEUDO-DIFFERENTIAL INPUT CIRCUITRY - System, methods and apparatus are described that facilitate data communications using a single-ended communication link. A method for data communications includes decoupling a direct current component from an alternating current component of a single-ended input signal, biasing the alternating current component with a predetermined bias voltage to obtain a realigned signal, and providing a digital output representative of the input signal by comparing the realigned signal with the predetermined bias voltage. The realigned signal can be compared with the predetermined bias voltage using hysteresis comparison to provide an output signal that switches between logic states compatible with a logic circuit. | 05-07-2015 |
20150303920 | SUB-RATE LOW-SWING DATA RECEIVER - A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier. | 10-22-2015 |
20150372680 | Level-Shifting Device - A voltage level shifting device for driving a capacitive load has an input terminal for receiving a first input signal switchable between a first logic state corresponding to a first reference voltage and a second logic state corresponding to a second reference voltage, and an output terminal for supplying an output signal switchable between a first logic state corresponding to a third reference voltage and a second logic state corresponding to a fourth reference voltage. The device also has a first electronic circuit that is activated following a commutation of the first input signal from the first reference voltage to the second reference voltage for fixing the output terminal to the fourth reference voltage. The device further has a second electronic circuit that is activated following a commutation of the first input signal from the second reference voltage to the first reference voltage. | 12-24-2015 |
20160036445 | Receiver Circuitry and Method for Converting an Input Signal From a Source Voltage Domain Into an Output Signal for a Destination Voltage Domain - The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range. Signal evaluation circuitry establishes a logic high voltage threshold and a logic low voltage threshold dependent on the supply voltage, and employs the first and second internal signals in order to detect based on the logic high voltage threshold and logic low voltage threshold when the input signal transitions between a logic low level and a logic high level (in either direction). Output generation circuitry then generates the output signal in dependence on the detection performed by the signal evaluation circuitry. The first voltage range and the second voltage range are such that the first internal signal and second internal signal will not exceed the stressing threshold of components in the signal evaluation circuitry. The receiver circuitry is able to reliably detect transitions in the input signal in situations where the supply voltage of the source voltage domain exceeds the stressing threshold of the receiver's components, but without overstress of the receiver's components. | 02-04-2016 |
20160049936 | SEMICONDUCTOR DEVICE HAVING LOW POWER CONSUMPTION - A semiconductor device includes a first power supply node and a second power supply node having a voltage value higher than the first power supply node. A first switch interrupts a power supplied from the first power supply node to a first circuit node. A second switch interrupts a power supplied from the second power supply node to a second circuit node. A driver drives the second switch by a third switch being driven. The third switch is connected between the second power supply node and the first circuit node. A controller outputs a control signal to drive the first and third switches. | 02-18-2016 |
20160079980 | BUFFER CIRCUIT - A first logic inversion unit generates an input inversion signal and a buffer unit generates a signal having a same logic as that of the input inversion signal. The first logic inversion unit includes first and second MOS transistors. The first and second MOS transistors have conductivity types different from each other. The buffer unit includes third to sixth MOS transistors. The third and fourth MOS transistors are connected in cascade between a third reference potential and an output node of the buffer unit and have conductivity types different from each other. The fifth and sixth MOS transistors are connected in cascade between the output node of the buffer unit and a fourth reference potential and have conductivity types different from each other. | 03-17-2016 |
20160105180 | RECEIVING AN I/O SIGNAL IN MULTIPLE VOLTAGE DOMAINS - Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device. | 04-14-2016 |
20160149579 | VOLTAGE LEVEL SHIFTER CIRCUIT - Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed. | 05-26-2016 |
20160182052 | LEVEL-SHIFTING LATCH | 06-23-2016 |
20160182053 | LEVEL-SHIFTING LATCH | 06-23-2016 |
20160191059 | CROSS-COUPLED LEVEL SHIFTER WITH TRANSITION TRACKING CIRCUITS - A transition tracking circuit may be configured to receive a first input signal and a second input signal from a level shifter. The transition tracking circuit may be configured to track earlier falling transitions of the first and second signals to generate an output signal. | 06-30-2016 |
20170237438 | LEVEL SHIFTER | 08-17-2017 |
20180026639 | A SEMICONDUCTOR LOGIC ELEMENT AND A LOGIC CIRCUITRY | 01-25-2018 |