Class / Patent application number | Description | Number of patent applications / Date published |
326052000 | EXCLUSIVE FUNCTION (E.G., EXCLUSIVE OR, ETC.) | 36 |
20090015291 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF GENERATING CHIP ENABLE SIGNAL THEREOF - Provided are a semiconductor memory device and a method of generating a chip enable signal thereof. The device includes a plurality of memory chips and an interface chip that are stacked. Each of the memory chips includes a control signal setting unit, which sets input signals applied to first and second input nodes as less significant 2-bit control signals of n-bit control signals, performs a logic AND operation on the less significant 2-bit control signals to generate AND operated signals, performs a logic XOR operation on each of the AND operated signals and each bit signal of more significant n−2-bit input signals applied to third to n-th input nodes to set the n−2-bit control signals, outputs the signal applied to the second input node through a first output node, inverts the signal applied to the first input node to output the inverted signal through a second output node, and outputs the more significant n−2-bit input signals through third through n-th output nodes, respectively. The first through n-th output nodes of one of two adjacent memory chips are respectively connected to the first through n-th input nodes of the other of the two adjacent memory chips. | 01-15-2009 |
20090033362 | Method for Forming a Structure on a Substrate and Device - In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions. | 02-05-2009 |
20100033209 | METHOD AND DEVICE FOR GENERATING PSEUDO-RANDOM BINARY DATA - A device for generating k-bit parallel pseudo-random data includes “n” registers, from the first through the n-th registers (“n” is an integer not less than 3), and “k” exclusive-OR gates, from the first through the k-th exclusive-OR gates (“k” is an integer not less than 2). An output of the m-th register is input to the (m+k)th register (“m” is an integer between 1 and (n−k)). Outputs of the first through the (k−1)th exclusive-OR gates are respectively input to the second through the k-th exclusive-OR gates. An output of the first register is input to the first exclusive-OR gate. The outputs of the first through the k-th exclusive-OR gates are respectively input to the k-th through the first registers. Outputs of “k” registers, from the (n−k+1)th through the n-th registers are respectively input to the k-th through the first exclusive-OR gates, and also extracted as the k-bit parallel pseudo-random data. | 02-11-2010 |
20100201398 | APPARATUS FOR PROVIDING A COMBINED DIGITAL SIGNAL - An apparatus for providing a combined digital signal comprises a bit adder and a combiner. The combined digital signal contains information of a first digital input signal and a second digital input signal, wherein a block length of the first digital input signal is shorter than a block length of the second digital input signal. The bit adder is configured to add at least one filling bit to a block of the first digital input signal to obtain an adapted first digital input signal, so that the block length of the adapted first digital input signal is equal to a block length of the second digital input signal. The combiner is configured to combine the adapted first digital input signal and the second digital input signal to obtain and provide the combined digital signal. | 08-12-2010 |
20100301899 | CIRCUITS FOR SOFT LOGICAL FUNCTIONS - A circuit implementing a soft logical processing network includes an interconnection of analog processing elements, which can include soft logic gates, the soft logic gates including one or more soft logic gates. In some examples, each of the soft logic gates include multiple circuit parts, with each part including an input configured to accept a voltage signal representation of a soft logical quantity, and a conversion section configured to use the accepted voltage representation to form a corresponding current signal. The current signals are combined to form a signal representation of the output of the gate. | 12-02-2010 |
20100315123 | NON-MAJORITY MQCA MAGNETIC LOGIC GATES AND ARRAYS BASED ON MISALIGNED MAGNETIC ISLANDS - A non-majority magnetic logic gate device for use in constructing compact and power efficient logical magnetic arrays is presented. The non-majority magnetic logic gate device includes a substrate, symmetrically aligned magnetic islands (SAMIs), at least one misaligned magnetic island (MAMI), magnetic field inputs (MFIs), and at least one magnetic field output (MFO). The SAMIs and MAMI are electrically isolated from each other but are magnetically coupled to one another through their respective magnetic fringe fields. The MAMI is geometrically and/or angularly configured to exhibit a magnetization ground state bias which is dependent upon which direction the applied magnetic clock field is swept. Non-majority logic gates can be made from layouts containing the SAMIs and the MAMI which contain a smaller number of components as comparable majority logic gate layouts. | 12-16-2010 |
20100321063 | INTEGRATED CIRCUIT AND STANDARD CELL FOR AN INTEGRATED CIRCUIT - An integrated circuit and a standard cell of an integrated circuit, having a master-slave flip-flop, having a comparator logic at whose inputs the input signal of the master-slave flip-flop, the inverted input signal of the master-slave flip-flop, the output signal of the master-slave flip-flop, and the inverted output signal of the master-slave flip-flops are present, wherein the master-slave flip-flop has a master flip-flop and a slave flip-flop, wherein the slave flip-flop has a first inverting element and a second inverting element. Whereby for feedback, an output of the first inverting element is connected to an input of the second inverting element and an output of the second inverting element to an input of the first inverting element. Wherein, to output the output signal and the inverted output signal of the master-slave flip-flop, it is possible to connect the output and the input of the second inverting element to the inputs of the comparator logic so that the second inverting element and the comparator logic and an inverter form an exclusive-OR operation of the standard cell. | 12-23-2010 |
20110156752 | METHOD AND APPARATUS FOR GATING A CLOCK SIGNAL - A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic. The polarity comparison logic and the selector logic being further arranged such that, upon the enable signal transitioning from an active state to an inactive state, the selected clock signal provided to the clock freezing logic comprises a polarity substantially equivalent to that of the gated clock signal. | 06-30-2011 |
20110254590 | MAPPING ADDRESS BITS TO IMPROVE SPREAD OF BANKS - A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perform a logic operation on a high order bit and a low order bit of the first address to form a second address, identify one of the memory banks based on the second address, and send the request to the identified memory bank. | 10-20-2011 |
20110316585 | Interlock Circuit And Interlock System Including The Same - An interlock circuit includes an input delay unit and an output suppressing unit. The input delay unit delays a plurality of input signals, provides a plurality of delayed input signals, and provides a plurality of exclusive input signals by performing a logical operation on the plurality of delayed input signals. The output suppressing unit provides a plurality of output signals, which are not simultaneously enabled, based on the plurality of exclusive input signals and the plurality of input signals. | 12-29-2011 |
20120038388 | RC Delay Detectors with High Sensitivity for Through Substrate Vias - A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units. | 02-16-2012 |
20120200316 | DIGITAL FILTER CIRCUIT - According to one embodiment, a digital filter circuit includes an EXOR circuit, a clock gating circuit, a reset control circuit, a counter, a filter time setting circuit, a comparator, and a decoder. The clock gating circuit outputs a clock gating signal. The reset control circuit generates a first signal. The counter generates a count signal. The filter time setting circuit latches the count signal when the first signal is in the enable state, and outputs a latched count value as a second signal. The comparator receives the count signal and the second signal, and outputs a third signal of the enable state when the value of the count signal and the value of the second signal match each other. | 08-09-2012 |
20120306536 | Nonvolatile Full Adder Circuit - A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source. | 12-06-2012 |
20120326750 | DUTY CYCLE BASED PHASE INTERPOLATORS AND METHODS FOR USE - Duty cycle based phase interpolators, and methods for implementing duty cycle based phase interpolators are disclosed. One such phase interpolator includes a first pulse width modulator configured to generate a first duty cycle signal, and a second pulse width modulator configured to generate a second duty cycle signal. The phase interpolator further includes a logic unit configured to merge the first duty cycle signal and the second duty cycle signal to produce a periodic digital signal with a controllable phase depending on the first and second duty cycle signals. | 12-27-2012 |
20130002297 | BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS - A Bias Temperature Instability- (BTI-) resistance circuit is arranged to propagate a received clock signal through a clock tree. The state of the clock signal is inverted at a midpoint of the clock tree that is about the halfway point of the path of the propagated clock signal through the clock tree. The inversion of the clock signal at the midpoint mitigates BTI-aging effects of the BTI-resistant circuit when the clock signal is blocked by a clock gating signal, for example. The clock tree can be used to latch a data signal at an input latch of a logic block using the received clock signal, and to latch a data signal at an output latch of a logic block using a propagated clock signal that is output from the endpoint of the clock tree. | 01-03-2013 |
20130015881 | INTERLOCK CIRCUIT AND INTERLOCK SYSTEM INCLUDING THE SAME - An interlock circuit includes an input delay unit and an output suppressing unit. The input delay unit delays a plurality of input signals, provides a plurality of delayed input signals, and provides a plurality of exclusive input signals by performing a logical operation on the plurality of delayed input signals. The output suppressing unit provides a plurality of output signals, which are not simultaneously enabled, based on the plurality of exclusive input signals and the plurality of input signals. | 01-17-2013 |
20140132304 | DEVICE AND METHOD FOR DIRECT MIXING OF PULSE DENSITY MODULATION (PDM) SIGNALS - A device for mixing multiple (N) pulse density modulated (PDM) bit streams of a bit rate, the device comprises an input logic, an error accumulation circuit, an error correction circuit and an adder of more than N bits; wherein the device is arranged to output an output PDM bit stream that represents a mixture of the multiple input PDM bit streams; wherein the output PDM bit stream comprises a plurality of output PDM bits, wherein a certain output PDM bit of a plurality of output PDM bits that form the output PDM bit stream is generated during a certain clock cycle; wherein the input logic is arranged to select, during each fraction of the certain clock cycle, a current bit of a selected PDM bit stream, wherein different PDM bit streams are selected during different fragments of the certain clock cycle; wherein the error accumulation circuit is arranged to store intermediate values during a first fraction till a penultimate fraction of the certain clock signal and to store a last value during a last fraction of the certain clock signal; | 05-15-2014 |
20140145759 | SYSTEMS AND METHODS FOR PREVENTING SATURATION OF ANALOG INTEGRATOR OUTPUT - Systems and methods for preventing saturation of analog integrator outputs are provided. Applications of the systems and methods in hybrid analog-digital integrators are also provided. Exemplary systems include two switches, one operational amplifier, one capacitor C, four gain blocks, three comparators, one XOR gate, one OR gate, one T flip-flop, and one digital counter. | 05-29-2014 |
20140361809 | PULSE SYNTHESIZING CIRCUIT - A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated. | 12-11-2014 |
326053000 | Half-adder or quarter-adder | 2 |
20100164543 | LOW-COMPLEXITY ELECTRONIC ADDER CIRCUITS AND METHODS OF FORMING THE SAME - In various embodiments, an adder circuit includes a plurality of transistors, all of the transistors being of a single type selected from the group consisting of NMOS transistors and PMOS transistors, and dissipates no more power than an equivalent CMOS circuit. | 07-01-2010 |
20100271068 | LOGIC MODULE INCLUDING VERSATILE ADDER FOR FPGA - A logic module for an FPGA includes a LUT formed from an N-level tree of 2:1 multiplexers. Each of the N inputs to the LUT is connected to the select inputs of the multiplexers in one level of the tree. Each of the data inputs at the leaves of the tree is driven by a configuration memory cell that produces either a logic 0 or a logic 1. The output of the single multiplexer at the last level of the tree forms a Y output and is coupled to one input of an XOR gate and to the select input of a two-input carry multiplexer. The 0 input of the carry multiplexer is coupled to a G input. A CI input is coupled to the other input of the XOR gate and to the 1 input of the carry multiplexer. | 10-28-2010 |
326054000 | Exclusive NOR | 11 |
20080297197 | Efficient XOR Calculation - In one embodiment, an exclusive-OR (XOR) calculation circuit configured to XOR a plurality of N input signals ranging from a first signal to an Nth signal is provided. The calculation circuit includes: a plurality of logic circuits arranged from a first logic circuit to a last logic circuit, wherein each logic circuit is configured to receive two logical input signals and the complement of the two logical input signals and to provide an XOR output signal and an XNOR output signal, wherein the XOR output signal represents the XOR of its two input signals and the XNOR output signal represents an exclusive-NOT-OR (XNOR) of its two input signals, and wherein the first logic circuit receives two of the N input signals as its logical input signals, a second logic circuit receives another one of the N input signals and an XOR output signal from the first logic circuit as its logical input signals, and so on such that the last logic circuit receives a remaining one of the N input signals and an XOR output signal from a next-to-last logic circuit as its logical input signals. | 12-04-2008 |
20100277202 | Circuitry and Layouts for XOR and XNOR Logic - An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high. | 11-04-2010 |
20110121857 | ASYNCHRONOUS DIGITAL CIRCUITS INCLUDING ARBITRATION AND ROUTING PRIMITIVES FOR ASYNCHRONOUS AND MIXED-TIMING NETWORKS - Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data. | 05-26-2011 |
20110291701 | HIGH SPEED FLIP-FLOP CIRCUIT AND CONFIGURATION METHOD THEREOF - A high speed flip-flop circuit and a configuration method thereof are provided. A small number of transistors may be used to configure a flip-flop circuit, so that the flip-flop circuit may be operated at a high-speed. Additionally, an area occupied by the flip-flop circuit may be reduced, and power consumption may be reduced. Accordingly, the flip-flop circuit may be integrated together with a microwave frequency integrated circuit using a Gallium Arsenide (GaAs) compound semiconductor process. | 12-01-2011 |
20120126852 | HIGH-SPEED STATIC XOR CIRCUIT - A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal. | 05-24-2012 |
20120182047 | SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER-SUPPLY VOLTAGE ADAPTIVE CONTROL SYSTEM - A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops. | 07-19-2012 |
20130021061 | TUNNEL FIELD-EFFECT TRANSISTOR - A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region. | 01-24-2013 |
20130069692 | STATE TRANSITIONING CLOCK GATING - In some embodiments, new clock gating approaches, referred hereafter as State Transition Gating (STG) methods and circuits are provided. In areas of circuit designs including sequential elements, the use of STG may be used to reduce dynamic power consumption. | 03-21-2013 |
20130113519 | ASYNCHRONOUS DIGITAL CIRCUITS INCLUDING ARBITRATION AND ROUTING PRIMATIVES FOR ASYNCHRONOUS AND MIXED-TIMING NETWORKS - Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous routing primitive has one data input and two data outputs. The incoming data is routed to one of the two outputs based on a routing bit accompanying the data. The primitives use handshaking with request and acknowledge signals to ensure that data is passed when neighboring circuits are ready to receive or send data. | 05-09-2013 |
20130162293 | Soft Error Hard Electronics Layout Arrangement and Logic Cells - A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell. The method further includes connecting the combined logic integrated circuit cells, where the outputs of the combined integrated circuit cells provide the inputs for other combined circuit cells such that, when the output of the original logic integrated circuit from a first combined logic integrated circuit cell is connected as input to a second combined logic integrated circuit cell, then the output of the second circuit in the first combined logic integrated circuit cell is always also connected to the second combined logic integrated circuit cell serving as the inverse of the input signals that come from the original logic integrated circuit cell. | 06-27-2013 |
20140159772 | Circuitry and Layouts for XOR and XNOR Logic - An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high. | 06-12-2014 |
326055000 | With field-effect transistor | 4 |
20100141299 | XOR LOGIC CIRCUIT - An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals. | 06-10-2010 |
20130082735 | LOGIC CIRCUIT PERFORMING EXCLUSIVE OR OPERATION AND DATA PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a logic circuit that includes a transistor T | 04-04-2013 |
20130265082 | EXCLUSIVE OR CIRCUIT - An exclusive OR circuit includes, inter alia: a low pass unit configured to apply a second data to an output node when a first data is at a low level and to apply the first data to the output node when the second data is at a low level, and a discharge unit configured to discharge a voltage level of the output node when the first and second data are at a high level. | 10-10-2013 |
20150054548 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit that supplies a signal to the gate electrode (e.g., word line driver) is provided with a selection circuit formed of an OR gate, an XOR gate, or the like, whereby potentials of word lines can be simultaneously set higher than potentials of bit lines. | 02-26-2015 |