Class / Patent application number | Description | Number of patent applications / Date published |
326047000 | Significant integrated structure, layout, or layout interconnections | 17 |
20080211540 | PROGRAMMABLE ANTI-FUSE BASED ON, E.G., ZNCDS MEMORY DEVICES FOR FPGA AND OTHER APPLICATIONS - According to some embodiments, an “excess-current programming method” on ZnCdS memory devices for FPGA applications is disclosed. an “excess-current programming method” can also be employed within a variety of other applications, including other memory devices having low On-resistance, such as, e.g., metal-oxide memory like Ti-oxide, Ni-oxide, W-oxide, Cu-oxide and so on. Embodiments of ZnCdS based devices (e.g., memory devices), FPGA elements incorporating the same and methods thereof for reconfigurable circuits can reduce area overhead, power overhead and/or latency (e.g., of FPGA), address a disturbance problem during logic operation, decrease an ON-resistance characteristic and/or obtain increased data retention. | 09-04-2008 |
20090072858 | HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT - A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system. | 03-19-2009 |
20090102512 | Edit structure that allows the input of a logic gate to be changed by modifying any one of the metal or via masks used to form the metal interconnect structure - An edit structure is disclosed that allows the input of a logic gate to be changed by modifying any one of the metal and via masks that are used to form the metal interconnect structure. As a result, a first permanent logic state provided by a tie-in circuit can be changed to a second permanent logic state by modifying any one of the metal and via masks that are used to form the metal interconnect structure. | 04-23-2009 |
20090167354 | Non-Sequentially Configurable IC - Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit. | 07-02-2009 |
20090256591 | STRUCTURE FOR SYSTEMS AND METHODS OF MANAGING A SET OF PROGRAMMABLE FUSES ON AN INTEGRATED CIRCUIT - Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit. | 10-15-2009 |
20110068825 | NON-VOLATILE PROGRAMMABLE LOGIC GATES AND ADDERS - Spin torque magnetic logic device having at least one input element and an output element. Current is applied through the input element(s), and the resulting resistance or voltage across the output element is measured. The input element(s) include a free layer and the output element includes a free layer that is electrically connected to the free layer of the input element. The free layers of the input element and the output element may be electrically connected via magnetostatic coupling, or may be physically coupled. In some embodiments, the output element may have more than one free layer. | 03-24-2011 |
20110148463 | NON-VOLATILE LATCH CIRCUIT AND LOGIC CIRCUIT, AND SEMICONDUCTOR DEVICE USING THE SAME - A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed. | 06-23-2011 |
20120098569 | HARDENED PROGRAMMABLE DEVICES - Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data. | 04-26-2012 |
20120119782 | Logic for Metal Configurable Integrated Circuits - A metal programmable logic unit of a semiconductor device is disclosed. The programmable logic unit comprises: an interconnect structure comprising: a plurality of fixed interconnects including metal and via geometries; and a plurality of selectable interconnect geometries, each selectable geometry coupling a said first fixed interconnect to a said second fixed interconnect; and a programmable logic block comprising a plurality of multiplexers, each multiplexer having a plurality of regular inputs, wherein each said regular input is selectively coupled to one of a zero state, a one state, a first input state, and the compliment of the first input state; and a programmable multiplexer having a plurality of regular inputs, wherein each said regular inputs is selectively coupled to one of a zero state, a one state, and one or more input signals; wherein, selecting a subset of the selectable interconnect geometries program the logic block and the multiplexer regular inputs to implement a logic function. | 05-17-2012 |
20120194216 | 3D Semiconductor Device - A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer. | 08-02-2012 |
20130057315 | Non-Volatile Latch Circuit And Logic Circuit, And Semiconductor Device Using The Same - A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed. | 03-07-2013 |
20130285700 | NON-VOLATILE LOGIC OPERATION DEVICE - A non-volatile logic operation device includes an operation unit that is connected to a first input terminal, a second input terminal, and an output terminal, includes an operation layer, a first non-magnetic layer, and a reference layer, and outputs from the output terminal a result of a logic operation on signals applied at the first input terminal and the second input terminal, and a control unit that is connected to a third input terminal, and includes a control layer. The control unit is arranged in the vicinity of the operation unit. | 10-31-2013 |
20140218068 | HARDENED PROGRAMMABLE DEVICES - Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data. | 08-07-2014 |
20140340117 | SIGNAL PROCESSING DEVICE - A signal processing device is produced. The signal processing device including a first transistor with high off-state resistance, a second transistor which controls conduction between two different nodes, a capacitor which holds electric charge, and a current control element such as a transistor or a resistor. The first node to which a gate of the second transistor and a second electrode of the current control element are connected, and the second node to which one of a source and a drain of the first transistor, a first electrode of the capacitor, and a first electrode of the current control element are connected. The capacitance (including a parasitic capacitance) of the second node is greater than ten times the capacitance (including a parasitic capacitance) of the first node. The capacitance does not affect the first node; thus, a boosting effect is large and charge retention characteristics are favorable. | 11-20-2014 |
20150341035 | PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE - A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor. | 11-26-2015 |
20160133827 | NON-VOLATILE LOGIC DEVICE - A non-volatile logic device, comprising: a first input element magnetizable along a first direction to impart or change a chirality of a domain wall traversing the first input element a second input element configured to transport the domain wall, a magnetization of the second input element along a second direction representing a second logical input; a bifurcated output section comprising a pair of output elements for receiving the domain wall from the second input element, a magnetization of at least part of the output elements being changeable by propagation of the domain wall along the output elements; and a non-magnetic conductive element; wherein the magnetization in an output element after propagation of the domain wall represents a value of a logical function selectable by passing an electrical current through the non-magnetic conductive element to induce a magnetic field of a desired magnitude and direction in the second input element. | 05-12-2016 |
20160380630 | PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE - A programmable logic device includes a plurality of programmable logic elements (PLE) whose electrical connection is controlled by first configuration data. Each of The PLEs includes an LUT in which a relationship between a logic level of an input signal and a logic level of an output signal is determined by second configuration data, an FF to which the output signal of the LUT is input, and an MUX. The MUX includes at least two switches each including first and second transistor. A signal including third configuration data is input to a gate of the second transistor through the first transistor. The output signal of the LUT or an output signal of the FF is input to one of a source and a drain of the second transistor. | 12-29-2016 |