Class / Patent application number | Description | Number of patent applications / Date published |
326040000 | With flip-flop or sequential device | 39 |
20080218207 | SYNCHRONOUS FIRST-IN/FIRST-OUT BLOCK MEMORY FOR A FIELD PROGRAMMABLE GATE ARRAY - The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks. | 09-11-2008 |
20080224732 | Logic Modules for Semiconductor Integrated Circuits - A logic module ( | 09-18-2008 |
20080231316 | Distributed memory in field-programmable gate array integrated circuit devices - Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA. | 09-25-2008 |
20080238476 | Configurable time borrowing flip-flops - Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch. | 10-02-2008 |
20090167347 | USING PROGRAMMABLE LATCH TO IMPLEMENT LOGIC - A logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. The circuit includes a logic block comprising a plurality of logic inputs and at least one logic output, the logic output generating a logic function of the plurality of logic inputs; a first latch input to provide a data state to store in the latch is coupled to said at least one output of logic block; a global latch input to change the stored data state of the latch couple by a programmable method to a local input; and a latch output, wherein when the local input is coupled to the global latch input, the latch output generates logic function of the logic output and the local input. | 07-02-2009 |
20090167348 | PROGRAMMABLE LATCH BASED MULTIPLIER - A programmable logic circuit is disclosed that includes a latch for enhancing the circuit logic capacity. In a multiplier configuration, the circuit comprises a logic block; and a latch having a latch output coupled to a logic block input, wherein the latch output computes an AND function of a first and second latch input. | 07-02-2009 |
20090167349 | PROGRAMMABLE LOGIC BASED LATCHES AND SHIFT REGISTERS - A latch is described, comprising: a first programmable logic element (LE); and a second programmable logic element (LE); and an output of the first LE adapted to directly couple to a first input of the second LE; and an output of the second LE coupled to a first input of the first LE; and a first common input coupled to a second input of the first and second LE; and a second common input coupled to a third input of the first and second LE. | 07-02-2009 |
20090167350 | PROGRAMMABLE LOGIC BASED LATCHES AND SHIFT REGISTERS - Disclosed is a programmable logic device adapted to implement a shift register, the device comprising: a logic block comprised of: a latch having an input; and a logic element having an output capable of coupling to an adjacent logic block and the latch input, wherein the output is coupled to the adjacent logic block and decoupled from the latch input; and an interconnect coupled to the latch and adapted to transmit the latch output to an input of the logic element. In the device, the logic element is configured as a route through for the latch output to couple to the adjacent logic block. | 07-02-2009 |
20090174429 | Programmable logic device structure using third dimensional memory - A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate. | 07-09-2009 |
20090278566 | CONFIGURABLE TIME BORROWING FLIP-FLOPS - Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch. | 11-12-2009 |
20100156460 | (N+1) INPUT FLIP-FLOP PACKING WITH LOGIC IN FPGA ARCHITECTURES - A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources. | 06-24-2010 |
20100194431 | Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Devices - Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions. | 08-05-2010 |
20100213977 | USERS REGISTERS IMPLEMENTED WITH ROUTING CIRCUITS IN A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used. | 08-26-2010 |
20100219860 | Integrated Circuit with Improved Logic Cells - The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through;wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed. | 09-02-2010 |
20100219861 | Integrated Circuit with Improved Logic Cells - The present invention provides integrated circuits with improved logic cells. In one embodiment, an integrated circuit having a plurality of logic cells (LC) is provided, each LC comprising: a lookup table having a LUT output terminal; and, a first multiplexer; wherein, a first multiplexer input terminal is connected to of a first input terminal of the LC, a second multiplexer input terminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal of the LC, and a multiplexer select terminal is connected to a second input terminal of the LC so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one LC to the first output terminal of another LC, a WLUT chain is formed. | 09-02-2010 |
20100308862 | Element Controller for a Resilient Integrated Circuit Architecture - The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation. | 12-09-2010 |
20100327906 | INVERTING FLIP-FLOP FOR USE IN FIELD PROGRAMMABLE GATE ARRAYS - A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal. | 12-30-2010 |
20110025376 | System for the flexible configuration of functional modules - A system for the flexible configuration of function modules. The system includes the following components a plurality of logic cells in a fixedly wired FPGA/standard ASIC structure, wherein the logic cells are so configurable by means of configuration registers, that they execute basic logic functions; a switch matrix having a plurality of memory cells, via which different logical connections of the logic cells in defined complex connections are configurable by means of the configuration registers; and a control unit, which partially dynamically so configures the logic cells and the switch matrix via an internal bus and via the configuration registers by means of a configuration bit stream, that the fixedly wired FPGA/ASIC structure behaves functionally as a partially dynamically reconfigurable logic chip. | 02-03-2011 |
20110062988 | POWER REGULATOR CIRCUITRY FOR PROGRAMMABLE LOGIC DEVICE MEMORY ELEMENTS - Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors. | 03-17-2011 |
20110181318 | Electrically and/or Thermally Actuated Device - An electrically, thermally, or electrically and thermally actuated device is disclosed herein. The device includes a substrate, a first electrode established on the substrate, an active region established on the electrode, and a second electrode established on the active region. A pattern is defined in at least one of the substrate, the first electrode, the second electrode, or the active region. At least one of grain boundaries are formed within, or surface asperities are formed on, at least one of the electrodes or the active region. The pattern controls the at least one of the grain boundaries or surface asperities. | 07-28-2011 |
20110187409 | RECONFIGURABLE SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a plurality of the functional blocks; a plurality of configuration data memories in which a plurality of configuration data are stored; and a plurality of programmable switches configured to control connection between said plurality of functional blocks based on one of the plurality of configuration data which is stored in a common one of said plurality of configuration data memories. | 08-04-2011 |
20110199118 | Power control of an integrated circuit including an array of interconnected configurable logic elements - An integrated circuit ( | 08-18-2011 |
20110254588 | POWER SAVING CIRCUIT USING A CLOCK BUFFER AND MULTIPLE FLIP-FLOPS - A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal. | 10-20-2011 |
20120081148 | PROGRAMMABLE LOGIC DEVICE - A programmable logic device includes a plurality of repeating units, each of which includes interconnecting lines, a logic block comprising logic circuits, and a configuration memory block including a plurality of configuration memory circuits. One of the plurality of repeating units includes: a selection device coupled to output data of the plurality of configuration memory circuits and a shift chain segment input; and a flip flop receiving output of the selection device to output a shift chain segment output. | 04-05-2012 |
20120139580 | USER REGISTERS IMPLEMENTED WITH ROUTING CIRCUITS IN A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used. | 06-07-2012 |
20120153989 | Element Controller for a Resilient Integrated Circuit Architecture - The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation. | 06-21-2012 |
20120268164 | PROGRAMMABLE LSI - A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off. | 10-25-2012 |
20120274353 | SYSTEMS AND METHODS FOR PREVENTING DATA REMANENCE IN MEMORY SYSTEMS - Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory. | 11-01-2012 |
20120274354 | LOGIC CIRCUIT DESIGN METHOD, LOGIC DESIGN PROGRAM, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A computer device which performs logic synthesis using hardware description and a component in a cell library and generates a net list of a logic circuit including a series path of a clock synchronous sequential circuit and a combinational circuit performs optimization processing for decreasing the number of gate stages in a critical path between sequential circuits in the data path by using a third sequential circuit having a negative-logic input terminal and a negative-logic non-inverted output terminal and a fourth sequential circuit having a negative-logic input terminal and a negative-logic inverted output terminal in addition to a first sequential circuit having a positive-logic input terminal and a positive-logic non-inverted output terminal and a second sequential circuit having a positive-logic input terminal and a positive-logic inverted output terminal. | 11-01-2012 |
20120319729 | FIELD PROGRAMMABLE GATE ARRAY - A field programmable gate array is disclosed, which comprises at least one logic element having at least one switching element. The switching element comprises a static support element and a movable connecting element for providing a non-volatile electrical connection. | 12-20-2012 |
20130076391 | PROGRAMMABLE GATE ARRAY AS DRIVERS FOR DATA PORTS OF SPARE LATCHES - Aspects of the invention provide for improving a success rate of an engineering design change (ECO) for an integrated circuit. In one embodiment, aspects of the invention include a method for improving a success rate of an engineering design change (ECO) for an integrated circuit, including: identifying a plurality of spare latches within the integrated circuit; determining an input driver for each of the spare latches; and replacing each input driver with a programmable gate array, such that the programmable gate array is programmed to a functionality of the input driver. | 03-28-2013 |
20130127494 | MEMORY ELEMENTS WITH RELAY DEVICES - Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity. | 05-23-2013 |
20130154686 | Method and Apparatus for Facilitating Communication Between Programmable Logic Circuit and Application Specific Integrated Circuit with Clock Adjustment - A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain. | 06-20-2013 |
20140145756 | MEMORY INTERFACE CIRCUITRY WITH IMPROVED TIMING MARGINS - Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe signal in response to activation of the latched data strobe enable signal. The integrated circuit may include counter circuitry that monitors the gated data strobe signal. The counter circuitry may monitor the gated data strobe signal by counting pulses in the gated data strobe signal to produce a counter value. When the counter value reaches a target value, the logic circuitry may block the data strobe signal from passing to the memory controller. | 05-29-2014 |
20150303926 | Robust Flexible Logic Unit - A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit that is part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that loaded data is properly locked, to prevent overwrites. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration. The invention also provides for splitting the single FLU into multiple independent reconfigurable FLU sections, with independent user clock and reset, for implementing a plurality of independent functions or for establishing redundancy for critical functions. | 10-22-2015 |
20150326227 | USER REGISTERS IMPLEMENTED WITH ROUTING CIRCUITS IN A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used. | 11-12-2015 |
20160028383 | SHARED LOGIC FOR MULTIPLE REGISTERS WITH ASYNCHRONOUS INITIALIZATION - A control circuit is provided that enables a register to provide a synchronous initialization capability as well as an asynchronous capability despite the register having no asynchronous input. | 01-28-2016 |
20160126954 | METHODS AND APPARATUSES FOR SUB-THREHOLD CLOCK TREE DESIGN FOR OPTIMAL POWER - A method and flow for implementing a “clock tree” inside an ASIC using Sub-threshold or Near-threshold technology with optimal power. The invention may also implement concurrently use of two voltage domains inside a single place and route block. One voltage domain for the “clock tree” buffers and one voltage domain for the other cells at the block. The voltage domain for the “clock tree” buffers that is used is slightly higher than the voltage domain which is used for the other cells. The higher voltage ensures a large reduction of the total number of buffers inside the “clock tree” and the dynamic and static power are reduced dramatically despite the use of slightly higher operating voltage. | 05-05-2016 |
20180026643 | NOISE-IMMUNIE REFERENCE (NREF) INTERGARED IN A PROGRAMMABLE LOGIC DEVICE | 01-25-2018 |