Entries |
Document | Title | Date |
20080197877 | Per byte lane dynamic on-die termination - Embodiments of the invention are generally directed to systems, methods, and apparatuses for per byte lane dynamic on-die termination. In some embodiments, an integrated circuit includes logic to independently program at least one on-die termination (ODT) value for each of a plurality of integrated circuits coupled together through an interconnect. Other embodiments are described and claimed. | 08-21-2008 |
20080204072 | Programmable Logic Device - The invention relates to a connector ( | 08-28-2008 |
20080204073 | REDUNDANT CONFIGURATION MEMORY SYSTEMS AND METHODS - Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of configuration memory cells; and at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell. | 08-28-2008 |
20080211538 | FLEXIBLE WRAPPER ARCHITECTURE FOR TILED NETWORKS ON A CHIP - A wrapper organization and architecture for networks on a chip employing an optimized switch arrangement with virtual output queuing and a backpressure mechanism for congestion control. | 09-04-2008 |
20080218202 | Reconfigurable array to compute digital algorithms - An integrated circuit comprising a reconfigurable arrangement to compute digital algorithms by operating on digital data is described. | 09-11-2008 |
20080218203 | Programmable logic integrated circuit for digital algorithmic functions - A programmable integrated circuit for calculating a digital algorithm is disclosed. The integrated circuit is programmable to operate on input data in accordance with one or more predetermined digital algorithms. | 09-11-2008 |
20080218204 | METHOD OF CONFIGURING EMBEDDED APPLICATION-SPECIFIC FUNCTIONAL BLOCKS - A method of configuring application-specific functional blocks embedded in a user programmable fabric, the user programmable fabric comprising configuration data control means having an input and an output and the application-specific functional blocks comprising configuration memory means having an input and an output. The method comprises the steps of sending configuration data to configure the application-specific functional block to the configuration control means of the user programmable fabric, routing the output of the configuration data control means of the user programmable fabric to the input of the configuration memory means of the application-specific functional blocks, transferring the configuration data to the configuration memory means of the application-specific functional blocks and configuring, using the configuration data, the application-specific functional blocks. | 09-11-2008 |
20080218205 | Timing Exact Design Conversions from FPGA to ASIC - A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts. | 09-11-2008 |
20080224730 | CONFIGURATION NETWORK FOR A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile. | 09-18-2008 |
20080231315 | Configurable IC Having A Routing Fabric With Storage Elements - Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC. | 09-25-2008 |
20080238475 | Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions. | 10-02-2008 |
20080252334 | ADDING OR SUBTRACTING INPUTS USING A CARRY SIGNAL WITH A FIXED VALUE OF LOGIC 0 - A configurable logic device configured to add or subtract inputs using a carry signal with a fixed value of 0 is described. In embodiment(s), inputs are received by a device. The device is configured to add or subtract the inputs using a carry signal that has a fixed value of logic 0. The device is further configured to provide an output that has a value of the sum or the difference of the received inputs. | 10-16-2008 |
20080258757 | INTEGRATED CIRCUIT FEATURE DEFINITION USING ONE-TIME-PROGRAMMABLE (OTP) MEMORY - In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser. | 10-23-2008 |
20080258758 | EMBEDDED SYSTEM AND CONTROL METHOD THEREFOR - An embedded system having a programmable logic circuit, a plurality of storage devices each storing configuration data defining circuit information of the logic circuit, a setting information storage storing setting information including information of a storage device storing the configuration data and a controller selecting one of the plurality of storage devices based on the setting information and incorporating circuit information defined by configuration data stored in the selected storage device into the logic circuit. | 10-23-2008 |
20080258759 | UNIVERSAL DIGITAL BLOCK INTERCONNECTION AND CHANNEL ROUTING - A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O. | 10-23-2008 |
20080258760 | SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING - Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers. | 10-23-2008 |
20080258761 | RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network. | 10-23-2008 |
20080258762 | ASICs HAVING PROGRAMMABLE BYPASS OF DESIGN FAULTS - A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times when the fault-infected ASIC block is about to perform a fault-infected operation (bug-infected operation). The substitution or bypass does not have to be a permanent one that is in effect at all times for the entirety of the fault-infected ASIC block. Instead affected outputs of the faulty ASIC block can be disabled from working just at the time they would otherwise initiate or propagate an error. Such fault-infected operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed pro-Logic at the appropriate times. Thus, a fault-infected ASIC block that is 99% good (for example) and operates improperly just 1% of the time can continue to be gainfully used for that 99% of the time when its operations are fault free and can be blocked from having its erroneous output(s) used only in the 1% time periods (example) when its behavior is faulty. During those faulty times, a relatively small amount of the pro-Logic can be used as a fault-correcting or fault-bypassing substitute for the fault-infected ASIC block. This substitution or bypassing can be activated after initial design of the mostly-ASIC circuitry and/or after pilot production and/or mass production thereby providing for cost saving and faster time to market and/or for repair or maintenance even years after installation and use of the mostly-ASIC device. | 10-23-2008 |
20080272801 | RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network. | 11-06-2008 |
20080272802 | Random access of user design states in a configurable IC - Some embodiments of the invention is a configurable integrated circuit (IC) that includes (1) several configurable logic circuits, (2) a first routing network for connecting the configurable logic circuits, (3) several user design state (UDS) circuits, and (4) a second network communicatively coupled to the UDS circuits. In least one period during the operation of the IC, the second network receives addresses for a several UDS circuits in a random access manner. In some embodiments, the second network is a debug network for reading randomly state values stored by the addressed UDS circuits during the user-design operation of the IC. | 11-06-2008 |
20080272803 | SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT INCLUDING DUAL-FUNCTION ANALOG AND DIGITAL INPUTS - An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture programmably coupling selected ones of the plurality of inputs, the plurality of outputs, the programmable logic block, the analog circuit block, and the analog-to-digital converter. At least one of the inputs may be programmably configured as one of a digital input programmably coupleable to elements in the programmable logic block or as an analog input to an analog circuit in the analog circuit block. | 11-06-2008 |
20080272804 | NON-VOLATILE MEMORY CONFIGURATION SCHEME FOR VOLATILE-MEMORY-BASED PROGRAMMABLE CIRCUITS IN AN FPGA - A non-volatile memory configuration scheme is disclosed for volatile-memory-based programmable circuits in a programmable integrated circuit that includes an FPGA fabric, a plurality of first configurable circuit elements external to the FPGA fabric, and a plurality of second configurable circuit elements external to the FPGA fabric. A plurality of distributed configuration non-volatile memory cells is disposed in the FPGA, each one of the distributed configuration non-volatile memory cells coupled to a different one of the plurality of first configurable circuit elements. A non-volatile memory array stores configuration information for the second configurable circuit elements. A plurality of register cells is disposed with the second configurable circuit elements and is coupleable to the non-volatile memory array, each one of the register cells coupled to a different one of the plurality of second configurable circuit elements. | 11-06-2008 |
20080278195 | STRUCTURE FOR EXECUTING SOFTWARE WITHIN REAL-TIME HARDWARE CONSTRAINTS USING FUNCTIONALLY PROGRAMMABLE BRANCH TABLE - A computer system is disclosed which includes a design structure including a CPU or microprocessor to drive tightly constrained hardware events. The system comprises a processor having a set of system inputs to drive a functionally programmable event, and a fast branch in the CPU including a state handler to execute instructions from the CPU to process the event. A queue in the CPU stores the events such that the non-pre-empted events are serviced in the order they are received. | 11-13-2008 |
20080278196 | LOGIC CIRCUITS HAVING DYNAMICALLY CONFIGURABLE LOGIC GATE ARRAYS - A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates. | 11-13-2008 |
20080278197 | PROGRAMMABLE LOGIC DEVICE WITH EMBEDDED SWITCH FABRIC - The invention in the simplest form is a programmable logic device consisting of gate arrays, external I/O endpoints, and an embedded switch fabric configurable for connecting gates to gates, endpoints to endpoints and gates to endpoints. The architecture may employ a fabric interface of non-blocking crossbar switches for making complex bus connections of multiple devices to facilitate high speed processing. | 11-13-2008 |
20080290895 | SYSTEM AND METHOD FOR LOCAL GENERATION OF PROGRAMMING DATA IN A PROGRAMABLE DEVICE - An apparatus for and method of programming a programmable logic device, the programmable logic device comprising a plurality of serially connected programmable logic regions. The method comprises the steps of receiving initial programming data for programming the plurality of serially connected programmable logic regions and receiving transformation data related to the presence and location of at least one faulty serially connected programmable logic region. The method also comprises the steps of generating bypass programming data which, in use, renders a serially connected programmable logic region logically invisible and generating effective programming data by incorporating, using information found in the transformation data, the bypass programming data into the initial programming data. Finally, the method comprises the step of programming the programmable logic device using the effective programming data such that the at least one faulty serially connected programmable logic region is programmed with the bypass programming data. | 11-27-2008 |
20080290896 | System and Method for Dynamically Executing a Function in a Programmable Logic Array - A reconfigurable logic array (RLA) system that includes an RLA and a programmer for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks. The programmer contains software that partitions the RLA into a function region FR located between two storage regions SR | 11-27-2008 |
20080297195 | PROGRAMMABLE ROM - A programmable ROM includes first and second field effect transistors serially connected between first and second power source terminals, a third field effect transistor having a gate connected to a word line and used for data transfer between a first bit line and the drains of the first and second field effect transistors, fourth and fifth field effect transistors serially connected between the first and second power source terminals, and a sixth field effect transistor having a gate connected to the word line and used for data transfer between a second bit line and the drains of the fourth and fifth field effect transistors. The threshold voltages of the first and fourth field effect transistors are different from each other and the magnitude relation thereof is determined according to ROM data. | 12-04-2008 |
20080297196 | Element Controller for a Resilient Integrated Circuit Architecture - The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation. | 12-04-2008 |
20080303547 | PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL - A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with temperature measuring and control circuitry performs temperature measurement and control functions and can be used to create an on-chip temperature log. | 12-11-2008 |
20080309370 | Reprogrammable Integrated Circuit - A reprogrammable integrated circuit, including one or more logic dies including circuit components; and one or more reprogrammable interconnect dies including reprogrammable interconnect components electrically connected to the circuit components to define signal routing paths between the circuit components to allow a user to develop an integrated circuit. | 12-18-2008 |
20090002022 | CONFIGURABLE IC WITH DESKEWING CIRCUITS - Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs. | 01-01-2009 |
20090002023 | Modular ASIC With Crosspoint Switch - Provided is a digital signal processing device, specifically a modular application specific integrated circuit (“ASIC”), having a programmable crosspoint switch for facilitating data transfer and processing within the circuit. A programmable matrix element is operable to perform advanced matrix operations (arithmetic operations) according to user provided commands. The crosspoint switch interconnects the programmable matrix element with various other processing or conditioning modules (i.e. down conversion, filter, pulse processing and demodulation modules) to ensure parallel processing at System Clock rates. The ASIC, which is reconfigurable at a top-level according to user requirements, facilitates design changes and bench testing. | 01-01-2009 |
20090027079 | Method and Apparatus for Implementing Complex Logic Within a Memory Array - A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function. | 01-29-2009 |
20090027080 | Low leakage and data retention circuitry - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 01-29-2009 |
20090033358 | PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL - Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap. | 02-05-2009 |
20090039915 | Integrated Circuit, Chip Stack and Data Processing System - An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated. | 02-12-2009 |
20090039916 | Systems and Apparatus for Providing a Multi-Mode Memory Interface - An integrated circuit for a memory input/output (I/O) pin has five different modes of operation. The memory chip is enabled to operate with unbuffered (or registered) dual inline memory modules (DIMMs) as well as fully buffered DIMMs. A T-coil circuit equalizes the capacitive loading of the high-speed functions. An exemplary embodiment provides a memory chip containing a multi-functional physical I/O circuit that can act as power or ground; as a DDR2 or DDR3 interface; as a high-speed differential receiver; or as a high-speed differential transmitter. | 02-12-2009 |
20090039917 | Programmable Interconnect Structures - A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes. | 02-12-2009 |
20090045836 | ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE - A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process. | 02-19-2009 |
20090045837 | APPARATUS FOR DYNAMIC DEPLOYMENT OF PIN FUNCTIONS ON A CHIP - An apparatus for dynamic deployment of pin functions on a chip is disclosed in the present invention. The apparatus comprises: an input pin receiving unit, capable of integrating a plurality of pins and selecting pin functions according to a program; an output pin control unit, capable of issuing a control signal to the plurality of pins; and a signal control unit, controlled by the program and coupled to the input pin receiving unit and the output pin control unit so as to communicate therebetween; wherein the pin functions are designated by the user to select an output signal for each of the plurality of pins according to the program. | 02-19-2009 |
20090045838 | INTEGRATED CIRCUIT APPARATUS - An integrated circuit apparatus includes a reconfigurable arithmetic operation device and a control device that generates mapping data defining a circuit configuration of the reconfigurable arithmetic operation device whose circuit configuration is changed while a given application is running and another application is newly implemented and run. The control device generates mapping data defining an intermediate configuration to shift from a circuit configuration defined by first mapping data to a configuration defined by final mapping data through the intermediate configuration. | 02-19-2009 |
20090058460 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 03-05-2009 |
20090058461 | Configurable Circuits, IC's, and Systems - Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data. | 03-05-2009 |
20090058462 | FIELD PROGRAMMABLE GATE ARRAY INCLUDING A NONVOLATILE USER MEMORY AND METHOD FOR PROGRAMMING - An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to store device data such as a serial number, product identification number, date code, or security data. Portions of the non-volatile memory may be made unavailable to the user once programmed, while other portions of the non-volatile may remain available for user access. | 03-05-2009 |
20090066364 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 03-12-2009 |
20090072856 | MEMORY CONTROLLER FOR HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUITS - A system including a configurable memory controller, a memory interface, and a configurable high speed communications fabric comprising a plurality of interconnect stations arranged in an array and operable to implement a plurality of pipelined buses, where the configurable memory controller is operably coupled to the configurable high speed communications fabric using a first interconnect station of the plurality of interconnect stations, where the memory interface is operably coupled to the configurable high speed communications fabric using a second interconnect station of the plurality of interconnect stations, where the plurality of interconnect stations are configured to satisfy a timing requirement of the memory interface, and where the configurable memory controller, the memory interface, and the configurable high speed communications fabric are associated with a configurable integrated circuit. | 03-19-2009 |
20090072857 | Integrated circuits with adjustable body bias and power supply circuitry - An integrated circuit is provided with adjustable transistor body bias circuitry and adjustable power supply circuitry. The adjustable circuitry may be used to selectively apply body bias voltages and power supply voltages to blocks of programmable logic, memory blocks, and other circuit blocks on the integrated circuit. The body bias voltages and power supply voltages may be identified by computer aided design tools. The body bias voltages may be used to reduce leakage currents and power consumption when high speed circuit block operation is not required. Reduced power supply voltages may also be used to reduce power consumption when high speed circuit block operation is not required. To ensure optimum switching speeds, circuit blocks for which high-speed performance is critical can be provided with minimal body bias voltage or no body bias and can be provided with maximum power supply levels. | 03-19-2009 |
20090079467 | METHOD AND APPARATUS FOR UPGRADING FPGA/CPLD FLASH DEVICES - A method for programming a non-volatile memory associated with a programmable logic device (PLD). The method for programming a non-volatile memory includes a reading a data file, wherein the data file includes information to be programmed into the non-volatile memory. The data file is then translated into a plurality of commands based on the information contained therein. The plurality of command is forwarded to a microcontroller. The microcontroller then executes the plurality of commands, wherein said executing causes the non-volatile memory to be programmed. | 03-26-2009 |
20090079468 | Debug Network for a Configurable IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile. | 03-26-2009 |
20090079469 | Semiconductor integrated circuit - A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells. | 03-26-2009 |
20090096481 | SCHEDULER DESIGN TO OPTIMIZE SYSTEM PERFORMANCE USING CONFIGURABLE ACCELERATION ENGINES - A reusable hardware control structure is provided for a hardware acceleration engine that can be configured for implementation within an electronic integrated circuit design according to any one of a plurality of configuration alternatives. The reusable hardware control structure comprises a digital logic circuit design developed to receive configuration data from the hardware acceleration engine describing a selected configuration alternative. The selected configuration alternative is any one of the plurality of configuration alternatives. The digital logic circuit design is developed to process the configuration data to provide an evaluation of an input-to-output latency and an input blocking pattern of the hardware acceleration engine configured according to the selected configuration alternative. The evaluation is capable of being leveraged by control logic within the electronic integrated circuit design to increase utilization of the hardware acceleration engine. | 04-16-2009 |
20090096482 | INTEGRATED CIRCUIT HAVING A CONFIGURABLE LOGIC GATE - In one general aspect, a system may include a circuit board, a first integrated circuit attached to the circuit board, and a second integrated circuit attached to the circuit board being separate from the first integrated circuit and configured to operate in multiple power domains that include at least a core power domain and an I/O power domain and that is configured with a logic gate to receive and process external requests from the first integrated circuit and internal requests from the second integrated circuit for a common external resource. | 04-16-2009 |
20090108868 | METHOD AND CIRCUIT FOR MATCHING SEMICONDUCTOR DEVICE BEHAVIOR - A design structure and method. The design structure comprises a selection circuit comprising a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential. | 04-30-2009 |
20090108869 | Design Structure for a Flexible Multimode Logic Element For Use In A Configurable Mixed-Logic Signal Distribution Path - A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit. | 04-30-2009 |
20090115451 | CONFIGURABLE AND REUSABLE NAND SYSTEM - A configurable and reusable hardware-software NAND system adaptive to various NAND devices independent of the NAND device manufacturer and NAND device characteristics. A device identification signature is decoded from a NAND device in a NAND system; the device identification signature signal is analyzed to obtain a control phase sequence value descriptive of a characteristic of the NAND device; the control phase register is populated with the control phase sequence value; and control phase register provides the control phase sequence values to the command sequencer. The control phase register can be programmed by a low level driver for devices which NAND system cannot decode the device identification signature. | 05-07-2009 |
20090115452 | LOGIC BLOCK CONTROL SYSTEM AND LOGIC BLOCK CONTROL METHOD - The number of blocks that can be stopped when performing target processing in a programmable logic unit is obtained, and a stop rate of each of a plurality of logic blocks included in the programmable logic unit is calculated. The same number of logic blocks as the blocks that can be stopped are selected from among the plurality of logic blocks in ascending order of a stop rate, the selected logic blocks are determined as logic blocks whose operations are to be stopped, and the operations are stopped. As a technique of stopping an operation of a logic block, a gated clock technique, a power-off technique, or the like is used. | 05-07-2009 |
20090115453 | IC OUTPUT SIGNAL PATH WITH SWITCH, BUS HOLDER, AND BUFFER - An electronic integrated circuit includes a signal path connected between the functional logic ( | 05-07-2009 |
20090128186 | PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL - A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads. | 05-21-2009 |
20090134909 | PROGRAMMABLE STRUCTURED ARRAYS - A programmable semiconductor device includes a user programmable switch comprising a configurable element is positioned above a transistor material layer deposited on a substrate layer. | 05-28-2009 |
20090140767 | Universal circuit for secure function evaluation - An exemplary method enables implementation of a universal circuit capable of emulating each gate of a circuit designed to calculate a function. A first selection module receives inputs associated with the function. It generates outputs that are an ordered series of the inputs. A universal module receives these outputs and generates another set of outputs. A second selection module receives the outputs from the universal module and generates final function outputs that are an ordered series inputs received from the universal module. The selection modules and universal module themselves are also aspects of the present invention. | 06-04-2009 |
20090146686 | Configuration Context Switcher with a Latch - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 06-11-2009 |
20090146687 | INTEGRATED CIRCUIT FEATURE DEFINITION USING ONE-TIME-PROGRAMMABLE (OTP) MEMORY - In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing a value, and (c) a feature control module for each feature block, each feature control module connected between the corresponding OTP memory cell and the corresponding feature block, and adapted to enable or disable the corresponding feature block based on the value stored in the corresponding OTP memory cell. The OTP memory cells are programmed by a vendor to select the particular feature set for the IC which is to be available to a purchaser. | 06-11-2009 |
20090153187 | Monolithically integrated interface circuit - The invention relates to integrated circuits comprising a monolithically integrated logic IC and a monolithically integrated interface circuit that is conductively connected to the logic IC. The electrical properties of said interface circuit are programmable. The interface circuit also has a lower integration density than the logic IC, and comprises monitoring modules for monitoring the logic ICs. | 06-18-2009 |
20090153188 | PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE) - In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory. | 06-18-2009 |
20090160481 | Configurable Circuits, IC's and Systems - Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection schemes for communicatively coupling the input terminal set to the output terminal set. During the operation of the IC, the second connection circuit supplies sets of configuration data to the first interconnect circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the first interconnect circuit to use two different connection schemes that differently couple the input and output terminal sets. | 06-25-2009 |
20090167345 | Reading configuration data from internal storage node of configuration storage circuit - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 07-02-2009 |
20090167346 | RECONFIGURABLE CIRCUIT, CONFIGURATION METHOD AND PROGRAM - The present invention is intended to provide a reconfigurable circuit, a configuration method and a program capable of significantly shortening the configuration time without increasing the area of the chip of the circuit. The reconfigurable circuit equipped with a configuration chain having multiple serial connection registers, comprises first connecting means for connecting the registers inside a first serial connection register and the registers inside a second serial connection register in series, and second connecting means for connecting the registers inside the first serial connection register and the registers inside the second serial connection register in parallel, wherein duplication is made possible by using the second connecting means as bypasses. | 07-02-2009 |
20090174428 | PROGRAMMABLE ELEMENT, AND MEMORY DEVICE OR LOGIC CIRCUIT - A multi-terminal programmable element. The programmable element includes a source electrode and a drain electrode on a base. The programmable element includes reference voltage contact that is not in contact with the source or drain electrode. The base includes a transition-metal oxide with oxygen vacancies for drifting under an applied electric field. Further, materials of the source electrode and the base are selected such that an interface of a source and/or drain electrode material and the transition metal oxide base material forms an energy barrier for electron injection from the electrode into the base material. The energy barrier has a height that depends on an oxygen vacancy concentration of the base material. Four non-volatile states are programmable into the programmable element. | 07-09-2009 |
20090189637 | Machine for programming on-board chipsets - The present invention discloses a machine for programming on-board chipsets, wherein the on-board chipsets means that some chipsets are mounted on a circuit board, and the circuit board has a plurality of input pads electrically connected to each chipset individually. The machine comprises a platform, a number of programming modules and an IC programming burner in which the platform faces a surface of the circuit board having the input pads, the programming modules disposed movably on the platform separately extends a number of output pins outwardly so that for connecting electrically an input pad as contacting the input pad, and the IC programming burner electrically connected to each of the programming modules separately distributes a set of programming codes into each programming module when the output pins electrically connect to the input pads. | 07-30-2009 |
20090206874 | SEMICONDUCTOR DEVICE - A first operation unit stores first code information having a bit length shorter than a first set bit, receives dictionary information expressing each set bit corresponding to each code information, reads the set bit corresponding to the first code information from the dictionary information to obtain the first set bit, and further, changes setting according to the first set bit to execute any of a plurality of operations so as to obtain an operation result. A second operation unit stores second code information having a bit length shorter than a second set bit, receives the dictionary information from the first operation unit, reads the set bit corresponding to the second code information from the dictionary information to obtain the second set bit, and further, changes setting according to the second set bit so as to execute any of the operations with respect to the operation result. | 08-20-2009 |
20090206875 | PROGRAMMABLE IO ARCHITECTURE - A buffer device coupled to at least one input/output port of an integrated circuit has a plurality of control inputs configured to receive configuration programming information. The at least one input/output circuit is capable of: (a) being configured in a directional sense of communication by the configuration programming information, (b) being configured as an input circuit which can be further configured to provide input logic switching level thresholds according to the configuration programming information, and (c) being configured as at least one output circuit which can be further configured to provide an output drive strength according to the configuration programming information. | 08-20-2009 |
20090212817 | Configuration information writing apparatus, configuration information writing method and computer program product - A configuration information writing apparatus for writing configuration information defining a logical configuration of a logic circuit device into the logic circuit device to change the logical configuration thereof, the apparatus comprising: a difference extracting unit that acquires plural pieces of configuration information and extracts differences between each of the acquired plural pieces of configuration information; a differential relation generating unit that generates a differential relation indicating a relation of the differences between each of the plural pieces of configuration information based on the differences extracted by the difference extracting unit; and an order information generating unit that generates order information specifying an order of writing the configuration information from the relation of the differences indicated by the differential relation generated by the differential relation generating unit. | 08-27-2009 |
20090219051 | HYBRID NANOTUBE/CMOS DYNAMICALLY RECONFIGURABLE ARCHITECTURE AND AN INTEGRATED DESIGN OPTIMIZATION METHOD AND SYSTEM THEREFOR - A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant logic density improvement and flexibility in performing area-delay tradeoffs are possible. NanoMap incorporates temporal logic folding during the logic mapping, temporal clustering and placement steps. NanoMap provides for automatic selection of a best folding level, and uses force-direct scheduling to balance resources across folding stages. Mapping can thereby target various optimization objectives and user constraints. A high-density, high-speed carbon nanotube RAM can be implemented as the universal memory, allowing on-chip multi-context configuration storage, enabling fine-grain temporal logic folding, and providing a significant increase in relative logic density. | 09-03-2009 |
20090237110 | PROGRAMMABLE ON-CHIP LOGIC ANALYZER APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed. | 09-24-2009 |
20090237111 | Integrated Circuits with Hybrid Planer Hierarchical Architecture and Methods for Interconnecting Their Resources - The present invention relates to methods for interconnecting base, switching and interconnect resources for configurable integrated circuits that include the following steps: interconnecting base and switching resources with interconnect resources to form a hierarchical interconnect structure; physically placing the hierarchical interconnect structure in a two dimensional format; and directly interconnecting selected neighboring base and switching resources. The integrated circuits generated include base resources, interconnect resources; and switching resources that are interconnected to form a hierarchical interconnect structure, and, additional interconnect resources that directly interconnect neighboring switching or base resources. Integrated circuits of this invention and integrated circuits with resources interconnected with methods of this invention have improved performance and exhibit the advantages of both integrated circuits with hierarchical interconnect routing architecture and integrated circuits with mesh interconnect routing architecture. | 09-24-2009 |
20090237112 | DATA TRANSFER CABLE FOR PROGRAMMABLE LOGIC DEVICES - A programmable logic device (PLD) data transfer cable includes a parallel interface, a programming interface, and a logic control circuit. The parallel interface is used for connecting to PLDs. The logic control circuit includes a first group of transmission channels, a second group of transmission channels, a first group of switches, and a second group of switches. The first and second group of switches control the working status of the first and second group of transmission channels respectively. The electrical connections between pins of the parallel interface and the programming interface when first group of transmission channels are activated are different with those when second group of transmission channels are activated. | 09-24-2009 |
20090243650 | PROGRAMMABLE LOGIC DEVICES COMPRISING TIME MULTIPLEXED PROGRAMMABLE INTERCONNECT - A time multiplexed programmable switch of a semiconductor device comprising: a first node; and a plurality of second nodes, each of the second nodes having a path to couple to the first node, the path comprising: a first configurable device configured to select or deselect the path; and a second configurable device in series with the first configurable device configured to select or deselect the path by a digital signal; wherein, the plurality of digital signals are time multiplexed to have no more than one second device in the select state within a time interval. | 10-01-2009 |
20090243651 | Method and Apparatus for Decomposing Functions in a Configurable IC - Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function. | 10-01-2009 |
20090243652 | INCREMENTER BASED ON CARRY CHAIN COMPRESSION - A computational unit is disclosed to increment or decrement n-bits of data. The unit has n/3 logic blocks to process the n-bits of data, each logic block including: first and second multiplexers to propagate a carry chain; and first, second and third exclusive—OR (XOR) circuits coupled to the carry chain of the multiplexers to generate a 3-bit incremented output. | 10-01-2009 |
20090256588 | PROGRAMMABLE ARRAY LOGIC CIRCUIT EMPLOYING NON-VOLATILE FERROMAGNETIC MEMORY CELLS - A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line. Additionally, the integrated circuit may further include a logical AND array and a logical OR array. | 10-15-2009 |
20090256589 | PROGRAMMABLE DEVICE, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING PROGRAMMABLE DEVICE - A programmable device connected to a storage unit which stores logic circuit configuration information to form a logic circuit and control circuit configuration information to form a control circuit includes a first programmable logic device and a second programmable logic device, and a configuration unit which forms the control circuit in the first programmable logic device, by providing the control circuit configuration information in the storage unit to the first programmable logic device. The control circuit formed in the first programmable logic device forms the logic circuit in the second programmable logic device, by providing the logic circuit configuration information in the storage unit to the second programmable logic device. | 10-15-2009 |
20090261857 | Universal non-volatile support device for supporting reconfigurable processing systems - A universal support device for supporting a reconfigurable electronics device is disclosed. The universal support device includes an application specific integrated circuit (ASIC) module coupled to multiple non-volatile memory devices. The ASIC module is capable of interfacing with an external reconfigurable electronics device via a set of load/read-back interface lines and sense mitigation lines. The load/read-back interface lines are capable of being programmed to provide a parallel or a serial load and/or store protocols. The sense mitigation line can sense conditions that indicate a signal-event functional interrupt or a radiation-induced event occurred within the reconfigurable electronics device. | 10-22-2009 |
20090261858 | PROGRAMMABLE INTERCONNECT NETWORK FOR LOGIC ARRAY - A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structure are connected to logic cells; said interconnect network also has peripheral switch boxes, of which at least one is connected to an external logic. Also, an integrated circuit comprising an FP array of logic cells connected by the said programmable interconnect network and a mask programmable (MP) logic array. | 10-22-2009 |
20090267643 | FLEXIBLE ADDER CIRCUITS WITH FAST CARRY CHAIN CIRCUITRY - Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a redundancy control signal. During manufacturing, the integrated circuitry may be tested. If a defect is identified on the integrated circuit, the redundancy control signal may be used in switching redundant circuitry into place bypassing the defect. The integrated circuit may contain an array of logic regions. Each logic region may contain adders and multiplexer circuitry for selectively combining the multiplexers to form larger adders. The multiplexer circuitry in each logic region may be controlled by propagate signals from the adders and by static redundancy control signals. | 10-29-2009 |
20090267644 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a voltage supply terminal; a first input terminal fed with a first input signal; an output terminal that outputs an output signal; a second input terminal fed with a second input signal; a first MOS transistor having one end connected to the voltage supply terminal and a gate electrode connected to the first input terminal; a second MOS transistor having one end connected to a first potential, an other end connected to the output terminal, and a gate electrode connected to the second input terminal; and a program element acting as a MOS transistor having one end connected to the other end of the second MOS transistor and an other end connected to a second potential higher than the first potential. | 10-29-2009 |
20090273366 | SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT CONTROL METHOD, AND TERMINAL SYSTEM - A semiconductor integrated circuit | 11-05-2009 |
20090273367 | IC HAVING PROGRAMMABLE DIGITAL LOGIC CELLS - An integrated circuit (IC) includes at least one programmable digital logic cell that includes first dedicated digital logic cell having a plurality of transistors including at least one PMOS transistor and at least one NMOS transistor configured to perform at least one digital logical function. The first dedicated digital logic cell includes a plurality of nodes including at least one input node and at least one output node that reflects performance of a digital logical function. Programmable tuning circuitry includes at least one tuning input and at least one tuning circuit output. Circuitry for coupling or decoupling the tuning input or tuning circuit output to at least one of the plurality of nodes of the first dedicated digital logical cell is provided, wherein the coupling or decoupling is operable to change the processing speed for the first reprogrammable digital logic cell. | 11-05-2009 |
20090295427 | Programmable switch circuit and method, method of manufacture, and devices and systems including the same - A switching circuit can include a logic circuit having a logic circuit input and a logic circuit output and at least three input transistors coupled to provide three separate paths between three input/output (I/O) nodes and the logic circuit input. The switching circuit can further include at least three output transistors coupled to provide three separate paths between the three I/O nodes and the logic circuit output. Methods of fabricating such switch circuits and devices and/or systems including such switching circuits are also disclosed. | 12-03-2009 |
20090302887 | APPARATUS FOR POWER CONSUMPTION REDUCTION IN PROGRAMMABLE LOGIC DEVICES AND ASSOCIATED METHODS - A programmable logic device (PLD) includes a driver circuit, a configuration memory, and a control circuit. The configuration memory stores driver strength information for the driver circuit. The control circuit uses the driver strength information stored in the configuration circuit to control the driver strength of the driver. | 12-10-2009 |
20090315586 | Setting Operating Mode of an Interface Using Multiple Protocols - This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention includes a plurality of operational units each having at least one data input/output for data transfer and an enable input. The operational unit have a normal mode and a stall mode controlled by an enable input. The operational units can exchange data via the data input/output in normal mode and are not capable of exchanging data in the stall mode. A selection logic selectively enables an operation unit and connects the data input/output of the enabled operation unit to the at least one data pin. The selection logic is responsive to external signals on at least one data pin to selectively enable operation units. | 12-24-2009 |
20090315587 | Key Based Pin Sharing Selection - This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention plural operational units each having a normal mode and a stall mode controlled by an enable input. Selection logic selectively enables an operation unit and connects the data input/output of the enabled operation unit to the data pin. The operational units are responsive to a preceding or following key to enter the normal mode. Each operational unit switches between stall mode and the normal mode upon receiving a corresponding predetermined selection number of pulses at while the clock input receives a non-cycling signal. Greater number of pulses deselect all operational units, switch operational units to the normal mode if the correct key is received and switch all operational units to the stall mode. | 12-24-2009 |
20090315588 | VARIABLE SIZED SOFT MEMORY MACROS IN STRUCTURED CELL ARRAYS, AND RELATED METHODS - The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may have different requirements (e.g., in terms of size) for such memory blocks. For example, pre-designed macros of memory blocks may be provided and then combined as needed to provide memory blocks of various sizes. Placement constraints may be observed for certain portions of the memory circuitry (e.g., the memory core), while other portions (e.g., address predecoder circuitry, write and read data registers, etc.) may be located relatively freely. | 12-24-2009 |
20100001759 | CONFIGURABLE IC HAVING A ROUTING FABRIC WITH STORAGE ELEMENTS - Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC. | 01-07-2010 |
20100001760 | PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL - A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads. | 01-07-2010 |
20100007376 | STORAGE ELEMENTS FOR A CONFIGURABLE IC AND METHOD AND APPARATUS FOR ACCESSING DATA STORED IN THE STORAGE ELEMENTS - Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits. | 01-14-2010 |
20100007377 | METHOD AND SYSTEM FOR A SERIAL PERIPHERAL INTERFACE - An integrated circuit device includes a serial peripheral interface adapted for receiving a first command supporting an address of a first configuration, wherein the serial peripheral interface supports an address of a second configuration upon receipt of a second command, the second configuration being different from the first configuration. In a specific embodiment, the first and the second configurations are different in address length. In another embodiment, a second address cooperated with the second command has a first part and a second part, the second part comprising a plurality of byte addresses, each of the byte addresses being associated with a corresponding byte of data. In another embodiment, integrated circuit device also includes a mode logic circuit for controlling operations of the first command and the second command. Various other embodiments are also described. | 01-14-2010 |
20100013517 | RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS - In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics (302, 304) for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics. | 01-21-2010 |
20100039136 | Gate Level Reconfigurable Magnetic Logic - A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation switch in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal based on the programmed states of the memory circuits. A sensor is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power. | 02-18-2010 |
20100039137 | DOWNLOAD SEQUENCING TECHNIQUES FOR CIRCUIT CONFIGURATION DATA - Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different programmable circuit elements may use configuration data, but have different ramp-up times before stable operation. With early download sequence positioning of configuration data, and corresponding immediacy in initiation of operation, certain clock elements are able to commence initiation of operation while remaining clock elements are provided with configuration data from a latter portion of the download sequence. | 02-18-2010 |
20100039138 | NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME - Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate. | 02-18-2010 |
20100039139 | RECONFIGURABLE SEQUENCER STRUCTURE - A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means. | 02-18-2010 |
20100066407 | Operational Time Extension - Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit. The method then maintains a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint. | 03-18-2010 |
20100066408 | CONFIGURATION DATA FEEDING DEVICE - A configuration data feeding device for feeding configuration data to a plurality of FPGAs includes a memory for storing configuration data that are fed to the plurality of FPGAs, a plurality of interface units for outputting the configuration data read out from the memory, according to their specific configuration layouts, an interface selection unit for selecting, out of the plurality of interface units, an interface unit that is to be used for configuring each of the plurality of FPGAs, and a circuit-switching unit for switching the circuits that connect the FPGAs to the interface units depending upon the selection by the interface selection unit. | 03-18-2010 |
20100073024 | ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS - An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers. | 03-25-2010 |
20100079165 | NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME - Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate. | 04-01-2010 |
20100085076 | CIRCUIT COMPRISING A MATRIX OF PROGRAMMABLE LOGIC CELLS - An integrated circuit comprises a matrix ( | 04-08-2010 |
20100097098 | CONFIGURABLE LOGIC DEVICE - The configurable logic device comprises a plurality of configurable logic cells ( | 04-22-2010 |
20100102848 | Asynchronous Logic Automata - A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation. | 04-29-2010 |
20100102849 | ELECTRONIC DEVICE, METHOD FOR CONFIGURING REPROGRAMMABLE LOGIC ELEMENT, COMPUTER-READABLE MEDIUM, COMPUTER DATA SIGNAL AND IMAGE FORMING APPARATUS - An electronic device includes a reprogrammable logic element, a configuration data storage, a reading section, a dummy data creating section, a skip determination section, a writing section and a control section. The configuration data storage stores configuration data for the reprogrammable logic element. The reading section successively reads the configuration data from the configuration data storage. The dummy data creating section creates dummy data. The skip determination section determines as to whether or not the configuration data is to be skipped. The writing section writes the configuration data or the dummy data into the reprogrammable logic element. If the skip determination section determines that the configuration data is to be skipped, the control section controls the dummy data, which is created by the dummy data creating section, to be sent to the writing section. | 04-29-2010 |
20100117680 | Semiconductor device, and programming method and programming system therefor - In a method of programming a differential programming semiconductor device, first identification data corresponding to first program data is outputted from an ID register of a program circuit in the device to a host. The first program data is programmed in a plurality of interconnections. The first program data is read from a storage unit based on the first identification data. Write data is generated based on the first program data and a second program data, which is to be newly programmed in the plurality of interconnections. The write data is transferred from the host to the device. The write data is written in the plurality of interconnections by the program circuit so as to program the second program data in the plurality of interconnections. | 05-13-2010 |
20100117681 | METHOD AND APPARATUS FOR SAFE POWER UP OF PROGRAMMABLE INTERCONNECT - A method and apparatus for connecting a load track ( | 05-13-2010 |
20100134140 | PROGRAM CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, VOLTAGE APPLICATION METHOD, CURRENT APPLICATION METHOD, AND COMPARISON METHOD - In a program circuit that can reduce exhaustion of a switching element that uses oxidation-reduction reactions of an electrolyte material, a voltage source ( | 06-03-2010 |
20100141297 | Configuration of Reconfigurable Interconnect Portions - Configuring reconfigurable interconnect resources employing a switch matrix and configuration bit look-up table are disclosed. Reconfigurable interconnect resources include multiplexors to decrease the number of bits needed to load a configuration. Distributed processing resources configure a selected reconfigurable interconnect resource, interconnecting each input of the reconfigurable interconnect resource with a particular output of the reconfigurable interconnect resource using configuration bits scalably extracted from a row of configuration bits of a look-up table. Use of a configuration bit look-up table allows for compression of the bits needed to load the configuration for a reconfigurable interconnect resource. | 06-10-2010 |
20100156456 | Integrated Circuit with Delay Selecting Input Selection Circuitry - Some embodiments provide an integrated circuit (IC) with a delay select input selection circuit. The delay select input selection circuit comprises a first input selection circuit, a first storage element, a second storage element, and a first input line branching into multiple input lines. The multiple input lines include at least a second, third, and fourth input line. The second input line is communicably connected to a first input of the first input selection circuit. The third input line enters the first storage element. The fourth input line enters the second storage element. An output from the first storage element is communicably connected to a second input of the first input selection circuit. An output from the second storage element is communicably connected to a third input of the first input selection circuit. | 06-24-2010 |
20100164542 | SYSTEM LSI - A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells. | 07-01-2010 |
20100171522 | IC OUTPUT SIGNAL PATH WITH SWITCH, BUS HOLDER, AND BUFFER - An electronic integrated circuit includes a signal path connected between the functional logic ( | 07-08-2010 |
20100171523 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device | 07-08-2010 |
20100182040 | PROGRAMMABLE THROUGH SILICON VIA - Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack. | 07-22-2010 |
20100182041 | 3D CHIP-STACK WITH FUSE-TYPE THROUGH SILICON VIA - Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack. | 07-22-2010 |
20100182042 | Circuits and Methods for Programmable Transistor Array - A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Methods for producing integrated circuits are disclosed forming programmable transistor arrays and implementing customer specified system designs upon the programmable transistor arrays. | 07-22-2010 |
20100182043 | RECONFIGURABLE CIRCUIT DEVICE AND RECEIVING APPARATUS - A reconfigurable device includes a first control unit ( | 07-22-2010 |
20100188117 | Defining a Default Configuration for Configurable Circuitry in an Integrated Circuit - An integrated circuit with a configurable portion, such as an input/output port, that can be placed in a default configuration prior to actual configuration of the integrated circuit. An external terminal that serves as an output during normal operation is coupled, after power-on of the integrated circuit, to a comparator that senses the voltage level at that external terminal. If the external terminal is at a particular level, a multiplexer is controlled to ignore the state of the normal configuration memory, and to place the configurable input/output port into a default protocol. | 07-29-2010 |
20100194429 | RECONFIGURABLE IC THAT HAS SECTIONS RUNNING AT DIFFERENT RECONFIGURATION RATES - Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of at least two different sections change configuration data sets at two different reconfiguration rates. | 08-05-2010 |
20100194430 | RECONFIGURABLE LOGIC CELL MADE UP OF DOUBLE-GATE MOSFET TRANSISTORS - Reconfigurable logic cells based on dual gate MOSFET transistors (DG MOSFETs) including n inputs (A,B), n being greater than or equal to 2 and capable of performing at least four logic functions with which logical signals provided on the n inputs (A,B) may be processed. The cell contains, between the ground and the output (F) of the cell, at least one first branch including n dual gate N-type MOSFET transistors (M | 08-05-2010 |
20100213974 | Method and apparatus for camouflaging a printed circuit board - A method, apparatus, article of manufacture, and a memory structure for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells. In one embodiment, the method comprises the steps of identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein, placing one filler cell or combination of filler cells into the identified gap and defining a routing of the placed filler cells. | 08-26-2010 |
20100213975 | COMBINED PROCESSING AND NON-VOLATILE MEMORY UNIT ARRAY - A reconfigurable logic device comprises an array of tiles interconnected through a routing network, each tile comprises both a processing unit including volatile configuration memory and a Random Access Memory unit. | 08-26-2010 |
20100219859 | Non-Sequentially Configurable IC - Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit. | 09-02-2010 |
20100225350 | RECONFIGURABLE MAGNETIC LOGIC-CIRCUIT ARRAY AND METHODS FOR PRODUCING AND OPERATING SUCH LOGIC DEVICES - The invention relates to a reconfigurable magnetic logic-circuit array having at least two magnetoresistive elements, each composed of at least two magnetic layers, which are separated from one another by an intermediate layer, in each instance, whereby one of the magnetic layers, as a reference layer, does not substantially change its magnetization under the influence of external magnetic fields, and the other magnetic layer, as a free layer, changes its magnetization perceptibly under the influence of external magnetic fields, and having at least one conductor for signal ports, with which conductor, when current is flowing, a first magnetic field can be generated that flips the magnetization of the free layers, and having a device for on-demand generation of a second variable magnetic field, which also influences the magnetoresistive elements. For this purpose, two such magnetoresistive elements are disposed adjacent to one another, whereby the magnetization of the two reference layers is oriented in opposite directions by means of preadjusted unidirectional anisotropy, and the magnetoresistive elements are interconnected with one another in such a manner that, as a result of the action of the first and second magnetic fields on the magnetoresistive elements, the switching behavior of all basic logic functions, especially the AND, OR, NAND, NOR, XOR or XNOR functions, can be induced on the basis of the resulting changes in the orientation of the magnetization of the free layers, and thus of the resistance of the magnetoresistive elements in the logic-circuit array. | 09-09-2010 |
20100244893 | VARIABLE SIZED SOFT MEMORY MACROS IN STRUCTURED CELL ARRAYS, AND RELATED METHODS - The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may have different requirements (e.g., in terms of size) for such memory blocks. For example, pre-designed macros of memory blocks may be provided and then combined as needed to provide memory blocks of various sizes. Placement constraints may be observed for certain portions of the memory circuitry (e.g., the memory core), while other portions (e.g., address predecoder circuitry, write and read data registers, etc.) may be located relatively freely. | 09-30-2010 |
20100259296 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A configurable integrated circuit (IC) system comprising: a first die comprising input/output cells; and a configurable logic second die connected by a first plurality of through-silicon-vias (TSVs) to the first die. | 10-14-2010 |
20100277201 | EMBEDDED DIGITAL IP STRIP CHIP - An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment, the standard logic cells are assembled or interconnected to accommodate known protocols. The base cells include configurable logic to adapt to modifications to emerging communication protocols, which are supported by the base cells. The second region can be embedded in the first region in one embodiment. In another embodiment, the second region is defined around a perimeter of the first region. The configurable logic may be composed of hybrid logic elements that have metal mask programmable interconnections so that as emerging communication protocols evolve and are modified, the IC can be modified to accommodate to the changes in the protocol. In another embodiment, a generic device can be customized by replacing the original function with a completely new function targeting a specific application space, e.g., replacing the original function such as a PCI Express, used for computing based applications, with 40 G/100 G Ethernet and Interlaken, used in wireline applications. A method of designing an integrated circuit is also provided. | 11-04-2010 |
20100289524 | Method for Fabrication of a Semiconductor Element and Structure Thereof - Re-programmable antifuses and structures utilizing re-programmable antifuses are presented herein. Such structures include a configurable interconnect circuit having at least one re-programmable antifuse, wherein the at least one re-programmable antifuse is configured to be programmed to conduct by applying a first voltage across it and is configured to be re-programmed not to conduct by applying second voltage across it, wherein the second voltage is higher than the first voltage. Additionally, the re-programmable antifuses may be configured to a permanently conductive state by applying an even higher voltage across it. | 11-18-2010 |
20100295574 | Runtime Loading of Configuration Data in a Configurable IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network. | 11-25-2010 |
20100301897 | Apparatus and Method for Forming a Mixed Signal Circuit with Fully Customizable Analog Cells and Programmable Interconnect - A mixed signal integrated circuit includes a digital logic array and an analog cell array. Each cell of the analog cell array shares a common architecture and is fully programmable. An analog cell includes mirror NFETs, cascode NFETs, differential pair NFETs, differential pair PFETs, cascode PFETs and mirror PFETs. An analog cell may also include special purpose components, such as low value resistors, high value resistors and PFETs. | 12-02-2010 |
20100327905 | Method and Apparatus for Providing a Non-Volatile Programmable Transistor - A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function. | 12-30-2010 |
20110006805 | RECONFIGURABLE SEQUENCER STRUCTURE - A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means. | 01-13-2011 |
20110006806 | SEMICONDUCTOR DEVICE - An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function. | 01-13-2011 |
20110018581 | MULTI-FUNCTIONAL LOGIC GATE DEVICE AND PROGRAMMABLE INTEGRATED CIRCUIT DEVICE USING THE SAME - Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal. The multi-function logic gate includes a pull-down switching unit having input switches of a second group being respectively connected to multiple input terminals and selection switches of the second group connected to either the selection terminal or the inverted selection terminal, the pull-down switching unit electrically connecting the input switches of the second group in parallel or in series between the output terminal and a ground terminal according to the logic levels of the selection terminal and the inverted selection terminal. The connection of the input switches of the second group is complementarily opposite to the connection of the input switches of the first group. | 01-27-2011 |
20110018582 | CONFIGURATION CONTEXT SWITCHER WITH A CLOCKED STORAGE ELEMENT - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for retiming the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 01-27-2011 |
20110031998 | CONFIGURABLE IC'S WITH LARGE CARRY CHAINS - Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two. | 02-10-2011 |
20110031999 | PROGRAMMABLE LOGIC FABRIC - A programmable logic circuit comprising a plurality of programmable logic elements and a plurality of programmable interconnect means, and memory means for storing the configuration of the logic elements and interconnect means, wherein said memory means is formed and arranged to store a multiplicity of different configurations for each said logic element. | 02-10-2011 |
20110037497 | Method for Fabrication of a Semiconductor Device and Structure - A novel method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the antifuse. | 02-17-2011 |
20110043247 | IC OUTPUT SIGNAL PATH WITH SWITCH, BUS HOLDER, AND BUFFER - An electronic integrated circuit includes a signal path connected between the functional logic ( | 02-24-2011 |
20110050281 | METHOD AND SYSTEM FOR GROUPING LOGIC IN AN INTEGRATED CIRCUIT DESIGN TO MINIMIZE NUMBER OF TRANSISTORS AND NUMBER OF UNIQUE GEOMETRY PATTERNS - A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit. | 03-03-2011 |
20110062986 | LOGIC BASED ON THE EVOLUTION OF NONLINEAR DYNAMICAL SYSTEMS - A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value. | 03-17-2011 |
20110084726 | ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS - A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value. | 04-14-2011 |
20110089970 | CONFIGURATION CONTEXT SWITCHER - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 04-21-2011 |
20110089971 | DOWNLOAD SEQUENCING TECHNIQUES FOR CIRCUIT CONFIGURATION DATA - Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different programmable circuit elements may use configuration data, but have different ramp-up times before stable operation. With early download sequence positioning of configuration data, and corresponding immediacy in initiation of operation, certain clock elements are able to commence initiation of operation while remaining clock elements are provided with configuration data from a latter portion of the download sequence. | 04-21-2011 |
20110102016 | Four-Terminal Reconfigurable Devices - Reconfigurable devices and methods for the fabrication thereof are provided. In one aspect, a reconfigurable device is provided. The reconfigurable device comprises a substrate; a first dielectric layer on the substrate; a conductive layer recessed into at least a portion of a side of the first dielectric layer opposite the substrate; at least one second dielectric layer over the side of the first dielectric layer opposite the substrate, so as to cover the conductive layer; a heater within the second dielectric layer; at least one programmable via extending through the second dielectric layer, extending through and surrounded by the heater and in contact with the conductive layer, the programmable via comprising at least one phase change material; a capping layer over the programmable via; a first conductive via and a second conductive via, each extending through the second dielectric layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive layer. | 05-05-2011 |
20110115523 | STORAGE ELEMENTS FOR A CONFIGURABLE IC AND METHOD AND APPARATUS FOR ACCESSING DATA STORED IN THE STORAGE ELEMENTS - Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits. | 05-19-2011 |
20110133776 | ARRAYS OF TRANSISTORS WITH BACK CONTROL GATES BURIED BENEATH THE INSULATING FILM OF A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures. | 06-09-2011 |
20110133777 | Configurable Circuits, IC's, and Systems - Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data. | 06-09-2011 |
20110140735 | CONFIGURABLE LOGIC DEVICE - The configurable logic device comprises a plurality of configurable logic cells ( | 06-16-2011 |
20110148459 | DYNAMIC PHASE ALIGNMENT - Embodiments of the present disclosure provide methods and integrate circuits with dynamic phase alignment between an input data signal and a clock signal. In some embodiments, a sampling window of the input data signal may be determined and timing of the input data signal may be adjusted to enable the input data signal to be sampled within the sampling window. Other embodiments may be disclosed and claimed. | 06-23-2011 |
20110148460 | RECONFIGURABLE SEQUENCER STRUCTURE - A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means. | 06-23-2011 |
20110156751 | IMAGE PROCESSING APPARATUS, CONTROL METHOD, AND STORAGE MEDIUM - An image processing apparatus including a processing unit having a rewritable circuit arrangement, comprises a supply unit which supplies a voltage to the processing unit, a measurement unit which measures a magnitude of the voltage supplied from the supply unit to the processing unit, a control unit which rewrites the circuit arrangement of the processing unit in accordance with the magnitude of the voltage that is measured by the measurement unit. | 06-30-2011 |
20110169524 | RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS - In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics. | 07-14-2011 |
20110181317 | OPERATIONAL TIME EXTENSION - Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit. The method then maintains a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint. | 07-28-2011 |
20110199116 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A Configurable device comprising, a logic die connected by at least one through silicon-via (TSV), to an input/output (I/O) die. | 08-18-2011 |
20110199117 | TRIGGER CIRCUITS AND EVENT COUNTERS FOR AN IC - Some embodiments provide an integrated circuit (‘IC’). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred. | 08-18-2011 |
20110204917 | CONFIGURABLE MEMORY SHEET AND PACKAGE ASSEMBLY - A configurable memory sheet includes a plurality of segmentable memory banks arranged on a repeating grid such that the plurality of segmentable memory banks can be configured for applications with a variety of circuit elements, where the plurality of segmentable memory banks are configured into memories by their connections to the variety of circuit elements. | 08-25-2011 |
20110221470 | MAGNETIC DEVICE FOR PERFORMING A "LOGIC FUNCTION" - A device for performing a “logic function” including a magnetic structure including at least one first magnetoresistive stack including a first ferromagnetic layer and a second ferromagnetic layer separated by a non-ferromagnetic interlayer, the ferromagnetic hard layer being pinned in a fixed magnetic state which serves as a reference and at least one first and one second current line belonging to a first and a second level of metallization respectively, each of the two lines generating a magnetic field in the vicinity of the first stack when a current flows therethrough. The first and second lines are disposed at various distances of the second ferromagnetic layer, the various distances being determined by the “logic function”. | 09-15-2011 |
20110227605 | Configuration method and FPGA circuit - A configuration method performs a configuration of a FPGA circuit by setting configuration data from a configuration circuit to the FPGA circuit. The method counts, within the FPGA circuit, a number of times a configuration of the FPGA circuit fails. The method adjusts, within the FPGA circuit, the configuration data at a time when the configuration failed if the counted number exceeds an upper limit value, and re-executes the configuration based on the adjusted configuration data. The method sets the configuration data in which the configuration is succeeded from the FPGA circuit to the configuration circuit when the configuration is successful. | 09-22-2011 |
20110241728 | CONTROLLABLE STORAGE ELEMENTS FOR AN IC - An integrated circuit (‘IC’) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or a distribute signals throughout the IC. | 10-06-2011 |
20110254586 | CONFIGURATION CONTEXT SWITCHER WITH A LATCH - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 10-20-2011 |
20110260751 | MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE - The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks. | 10-27-2011 |
20110273205 | RECONFIGURABLE INTEGRATED CIRCUIT - A reconfigurable integrated circuit has non-volatile storage cells which form a plurality of programmable routing switches between basic tiles. The circuit includes a plurality of non-volatile storage cells providing a multiplexer-type programmable routing switch including a plurality of input terminals and an output terminal. The non-volatile storage cells are structured as a field effect transistor with a switch function and are placed in a propagation path of signal voltage from the input terminals to the output terminal, and the non-volatile storage cells configure the multiplexer-type programmable routing switch to selectively propagate the signal voltage from the input terminals, to provide a control circuit which directly writes conducted or non-conducted status for the non-volatile storage cells, erases the connection information, and reads to verify the conducted or non-conducted status of the non-volatile storage cells. . | 11-10-2011 |
20110309858 | NON-VOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output electrode in a plan view. The first input electrode is next to the second input electrode along the a direction orthogonal to the direction between the electric current source electrode and the output electrode. A method of operating the non-volatile logic circuit includes a step of writing one state selected from four states by applying voltages to the first input electrode and the second input electrode, respectively, and a step of measuring current generated by applying the voltage between the electric current power electrode and the output electrode to determine on the basis of the current, which of the high or low resistant state the non-volatile logic circuit has. | 12-22-2011 |
20110309859 | METHOD FOR OPERATING A NON-VOLATILE LOGIC CIRCUIT - In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output electrode in a plan view. The semiconductor layer is disposed on a ferroelectric layer. A method of operating the non-volatile logic circuit includes a step of writing one state selected from four states by applying voltages to the first and second input electrode, respectively, a step of measuring current generated by applying the voltage between the electric current source electrode and the output electrode to determine, on the basis of the measured current, which of the high or low resistant state the non-volatile logic circuit has. | 12-22-2011 |
20110309860 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME AS AN EXCLUSIVE-OR (XOR) CIRCUIT - A non-volatile logic circuit includes a control electrode, a ferroelectric layer disposed on the control electrode, a semiconductor layer disposed on the ferroelectric layer, a power electrode and an output electrode disposed on the semiconductor layer, and first to fourth input electrodes disposed on the semiconductor layer. The first and second input electrodes receive first and second inputs, respectively. The third and fourth input electrodes receive inversion signals of the second and first input signal, respectively. A resistance value of the semiconductor layer between the power electrode and the output electrode varies according to the first input signal and the second input signal so that an exclusive-OR signal of the first and second input signals is output from the output electrode. | 12-22-2011 |
20110316583 | APPARATUS AND METHOD FOR OVERRIDE ACCESS TO A SECURED PROGRAMMABLE FUSE ARRAY - An apparatus in an integrated circuit for re-enabling the use of precluded extended JTAG operations. The apparatus includes a JTAG control chain, a feature fuse, a machine specific register, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The machine specific register is configured to store a value therein. The access controller is coupled to the feature fuse, the machine specific register, and the JTAG control chain, and is configured to determine that the feature fuse is blown, and is configured to direct the JTAG control chain to enable the precluded extended JTAG operations if the value matches an override value within the access controller during a period that the value is stored within the machine specific register. | 12-29-2011 |
20110316584 | FINGERPRINTED CIRCUITS AND METHODS OF MAKING AND IDENTIFYING THE SAME - A circuit having a fingerprint for identification of a particular instantiation of the circuit is disclosed. The circuit may include a plurality of digital circuits or gates. Each of the digital circuits or gates is responsive to a configuration voltage applied to its analog input for controlling whether or not the digital circuit or gate performs its intended digital function and each of the digital circuits or gates transitioning between its functional state and its at least one other state when the configuration voltage equals a boundary voltage. The boundary voltage varies between different instantiations of the circuit for a majority of the digital circuits or gates and these differing boundary voltages serving to identify (or fingerprint) different instantiations of the same circuit. | 12-29-2011 |
20120001653 | Dense Nanoscale Logic Circuitry - One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints. | 01-05-2012 |
20120007633 | RECONFIGURABLE LOGICAL CIRCUIT - Provided is a reconfigurable logic circuit that can effectively use a preposition logic that composes a logic block. The reconfigurable logic block according to the present invention includes a plurality of logic blocks ( | 01-12-2012 |
20120019283 | SPIN MOSFET AND RECONFIGURABLE LOGIC CIRCUIT - A spin MOSFET includes: a first ferromagnetic layer provided on a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower and upper faces; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on the second ferromagnetic layer; a third ferromagnetic layer provided on the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween. | 01-26-2012 |
20120025868 | Asynchronous Logic Automata - A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation. | 02-02-2012 |
20120062277 | Reconfigurable Logic Automata - A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level. A reconfigurable asynchronous logic cell comprises a set of one-bit buffers for communication with at least one neighboring cell, each buffer capable of having several states and configured for receiving input state tokens from neighboring cells and for transferring output state tokens to neighboring cells, and a one-bit processor configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, wherein the logic operation and the functional configuration of the buffers are reconfigurably programmable. A reconfigurable logic circuit comprises a plurality of reconfigurable logic cells that compute by locally passing state tokens and are reconfigured by the directed shifting of programming instructions through neighboring logic cells. | 03-15-2012 |
20120068732 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes. | 03-22-2012 |
20120086471 | PSOC ARCHITECTURE - A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip. | 04-12-2012 |
20120098566 | Interconnection Architectures for Multilayer Crossbar Circuits - An interconnection architecture for multilayer circuits includes metal-insulator transition channels interposed between address leads and each bar in the multilayer circuit. An extrinsic variable transducer selectively transitions the metal-insulator channels between insulating and conducting states to selectively connect and disconnect the bars and the address leads. A method for accessing a programmable crosspoint device within a multilayer crossbar circuit is also provided. | 04-26-2012 |
20120098567 | RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. | 04-26-2012 |
20120098568 | METHOD AND APPARATUS FOR PERFORMING AN OPERATION WITH A PLURALITY OF SUB-OPERATIONS IN A CONFIGURABLE IC - Some embodiments provide a method of performing a mathematical operation on a set of operands. The mathematical operation includes several sub-operations. The method examines several bits of at least one operand at a time and depending on the value of these bits, reconfigures a single logic circuit to perform one of the sub-operations to generate a partial result of the mathematical operation. In some embodiments, the logic circuit is reconfigured by receiving a first set of configuration data that cause the logic circuit to reconfigure to perform a first sub-operation operation and a second set of configuration data that cause the logic circuit to reconfigure to perform a second sub-operation. In some embodiments, the logic circuit receives different inputs based on the value of the bits being examined. In some embodiments, the mathematical operation is multiplication and the sub-operations are addition and subtraction. | 04-26-2012 |
20120105101 | MAGNETIC LOGIC GATE - This disclosure is directed to a magnetic logic gate for implementing a combinational logic function. The magnetic logic gate may include a write circuit configured to apply a spin-polarized current to the magnetoresistive device such that a resulting programmed magnetization state of the magnetoresistive device corresponds to a logic input value of a combinational logic function implemented by the magnetic logic device. The magnetic logic gate may further include a read circuit configured to generate a logic output value for the combinational logic function based on the programmed magnetization state in response to the write circuit applying the spin-polarized current to the magnetoresistive device. | 05-03-2012 |
20120105102 | MAGNETIC LOGIC GATE - This disclosure is directed to a magnetic logic device for implementing a combinational logic function. The magnetic logic device may include a chain of at least two magnetoresistive devices electrically coupled in series comprising a first terminal located at a first end of the chain and a second terminal located at a second end of the chain. The magnetic logic device may further include a voltage source configured to apply a voltage between the first terminal and the second terminal of the chain of at least two magnetoresistive devices electrically coupled in series. The magnetic logic device may further include a logic output generator configured to generate a logic output value for a logic function based on a magnitude of a current produced at the second terminal of the chain in response to the applied voltage. | 05-03-2012 |
20120105103 | MAGNETIC LOGIC GATE - This disclosure is directed to a magnetic logic device for implementing a combinational logic function. The magnetic logic device may include a network of at least two magnetoresistive devices electrically coupled in parallel. The magnetic logic device may further include a voltage source configured to apply a voltage between a first terminal and a second terminal of the network of at least two magnetoresistive devices electrically coupled in parallel. The magnetic logic device may further include a logic output generator configured to generate a logic output value for a logic function based on a magnitude of a current produced at the second terminal of the network in response to the applied voltages. | 05-03-2012 |
20120112787 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes. | 05-10-2012 |
20120119781 | RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS - In accordance with the present invention there are provided herein asynchronous reconfigurable logic fabrics for integrated circuits and methods for designing asynchronous circuits to be implemented in the asynchronous reconfigurable logic fabrics. | 05-17-2012 |
20120126850 | Hierarchically-Scalable Reconfigurable Integrated Circuit Architecture With Unit Delay Modules - The exemplary embodiments provide a reconfigurable integrated circuit architecture having a predetermined, unit timing increment (or delay) for both data operations and data word transfers within every zone and between zones, which are independent of application placement and routing. An exemplary IC comprises a plurality of circuit zones, with each zone comprising: a plurality of composite circuit elements, a plurality of cluster queues, and a full interconnect bus. Each composite circuit element comprises: a configurable circuit element circuit and an element interface and control circuit, with the element interface and control circuit comprising an input queue and an output queue. Each cluster queue comprises an element interface and control having an input queue and an output queue. The full interconnect bus couples every output queue within the zone to every input queue within the zone. Any data operation performed by a composite circuit element, any data word transfer through a cluster queue, and any data word transfer over the first full interconnect bus, is completed within a predetermined unit time delay which is independent of application placement and application data routing on the reconfigurable IC. | 05-24-2012 |
20120126851 | Data-Driven Integrated Circuit Architecture - The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data. | 05-24-2012 |
20120139579 | CONFIGURABLE IC HAVING A ROUTING FABRIC WITH STORAGE ELEMENTS - Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC. | 06-07-2012 |
20120176155 | RESCALING - A novel method for designing an integrated circuit (“IC”) by resealing an original set of circuits in a design of the IC is disclosed. The original set of circuits to be resealed includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a resealed set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the resealed set of circuits. | 07-12-2012 |
20120182045 | Method for the creation of an electronic signal box replacing an existing signal box - According to one aspect of the invention, the circuit logic of an existing relay interlocking system is mapped onto a functionally equivalent circuit of electronic components. Semiconductor components that are functionally identical to the components of the relay circuit are thus preferably used. The circuit logic is created, for example, by transforming an interlocking table or track diagram into a logic circuit by means of an automatic compiler according to predefined rules. | 07-19-2012 |
20120187979 | CONFIGURATION CONTEXT SWITCHER WITH A CLOCKED STORAGE ELEMENT - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 07-26-2012 |
20120200314 | IC WITH DESKEWING CIRCUITS - Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs. | 08-09-2012 |
20120212255 | Logic Circuit, Integrated Circuit Including The Logic Circuit, And Method Of Operating The Integrated Circuit - The logic circuit includes at least one variable resistance device configured such that a resistance value of the at least one variable resistance device varies according to at least one selected value. The selected value is selected from among a voltage and a current of an input signal, and the at least one variable resistance device is configured to memorize the resistance value. The logic circuit is configured to store multi-level data by setting the memorized resistance value. | 08-23-2012 |
20120217994 | Self-reconfigurable memristor-based analog resonant computer - An apparatus which provides a self-reconfigurable analog resonant computer employing a fixed electronic circuit schematic which performs computing logic operations (for example OR, AND, NOR, and XOR Boolean logic) without physical re-wiring and whose components only include passive circuit elements such as resistors, capacitors, inductors, and memristor devices. The computational logic self-reconfiguration process in the circuit takes place as training input signals, which are input causing the impedance state of the memristor device to change. Once the training process is completed, the circuit is probed to determine whether the desired logic operation has been programmed. | 08-30-2012 |
20120217995 | Reconfigurable memristro-based computing logic - An apparatus for reconfigurable computing logic implemented by an innovative memristor based computing architecture. The invention employs a decoder to select memristor devices whose ON/OFF impedance state will determine the reconfigurable logic output. Thus, the resulting circuit design can be electronically configured and re-configured to implement any multi-input/output Boolean logic computing functionality. Moreover, the invention retains its configured logic state without the application of a current or voltage source. | 08-30-2012 |
20120217996 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes. | 08-30-2012 |
20120217997 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes. | 08-30-2012 |
20120229163 | Dynamic Pad Hardware Control - Some embodiments of the present disclosure relate to dynamic hardware pad control that is triggered by an intelligent hardware module that monitors an operational state of an IC pin. This hardware module then provides a control signal, which is based on the operational state of the IC pin, to a multiplexer control block that selects one of several different configurations for the IC pin. Because the control signal is provided by the hardware module, the techniques disclosed herein allow precise switching between a number of different IC pin configurations in a fast and efficient manner. | 09-13-2012 |
20120242369 | Local Result Processor - A system includes a register, a first logical function portion, the first logical function portion operative to receive a first numerical value from the register, perform a first logical function with the first numerical value, and output a second numerical value, a second logical function portion, the second logical function portion operative to receive the first numerical value from the register, perform a second logical function with the first numerical value, and output a third numerical value, and a control logic portion, the control logic portion operative to receive the first numerical value from the register, determine whether the first numerical value includes a code associated with either the first logical function or the second logical function, and responsive to determining that the code is associated with the first logical function, and direct the output of the second numerical value to an input of the register. | 09-27-2012 |
20120280710 | REUSE OF CONSTANTS BETWEEN ARITHMETIC LOGIC UNITS AND LOOK-UP-TABLES - A combinatorial processing element used in a reconfigurable logic device having a plurality of processing elements interconnected by way of a routing network. The combinatorial processing element includes an arithmetic logic unit, having at least one input, a multiplexer tree, having a data input and a memory device. The processing element is arranged such that the memory can be connected to the data input of the multiplexer tree and/or the at least one input of the arithmetic logic unit. | 11-08-2012 |
20120286821 | SYSTEMS AND METHODS FOR CONFIGURING AN SOPC WITHOUT A NEED TO USE AN EXTERNAL MEMORY - Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space. | 11-15-2012 |
20120293199 | Programmable Priority Encoder - In one embodiment, a programmable priority encoder is configured to receive inputs, including an ordered list of a plurality of input request values each representing either a request or a non-request, and a starting position within the ordered list of the plurality of input request values. The programmable priority encoder is configured to generate an identification of a result position of a first input indicating said request in order from a position identified from the starting position within the ordered list. In one embodiment, the programmable priority encoder includes a hierarchal structure of logic blocks including a plurality of columns of logic blocks; wherein a first-stage column of the plurality of columns of logic blocks is configured to operate on at most N input values; and wherein the ordered list of the plurality of input request values consists of N input request values. | 11-22-2012 |
20120293200 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE - A semiconductor device using a programming unit with is provided. A highly reliable semiconductor device using the programming unit is provided. A highly integrated semiconductor device using the programming unit is provided. In a semiconductor circuit having a function of changing a structure of connections between logic cells such as PLDs, connection and disconnection between the logic cells or power supply to the logic cells is controlled by a programming unit using an insulated gate field-effect transistor with a small amount of off-state current or leakage current. A transfer gate circuit may be provided in the programming unit. To lower driving voltage, a capacitor may be provided in the programming unit and the potential of the capacitor may be changed during configuration and during operation. | 11-22-2012 |
20120293201 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element. | 11-22-2012 |
20120306532 | INTEGRATED CIRCUIT AND METHOD OF USING THE SAME - An integrated circuit wherein all elements such as a chip area, a cost, a function to change a logic, an operating frequency, flexibility, a throughput and electric power consumption can be improved; and a reconfigurable processor wherein a function of an instruction can be changed, are provided. A high-density logic reconfigurable leaf cell is defined. The integrated circuit is characterized in that: a logic reconfigurable leaf cell module, which is integrated with high density by arranging a plurality of leaf cells regularly to minimize the connection channel area for a signal between the leaf cells, and the reconfigurable processor, which can change the function of an instruction set by inserting the logic reconfigurable leaf cell module into a data path of an instruction execution process circuit, are integrated. | 12-06-2012 |
20120319727 | CONFIGURABLE REFERENCE CIRCUIT FOR LOGIC GATES - This disclosure is directed to techniques for generating a reference current based on a combinational logic function that is to be performed by a magnetic logic device. A comparator circuit may compare an amplitude of a read current that flows through the magnetic logic device and the reference current to generate a logic output value that corresponds to the logic output value when combinational logic function is applied to the input values. By selecting appropriate amplitudes for the reference current the magnetic logic device may be caused to implement different combinational logic functions. | 12-20-2012 |
20120319728 | PROGRAMMABLE STRUCTURED ARRAYS - A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer. | 12-20-2012 |
20120326747 | RECONFIGURABLE LOGIC DEVICE - A logic device that includes a plurality of non-volatile memory cells configured to store possible output results related to the input signal. The logic device generating an output signal by selecting and accessing one of the plurality of non-volatile memory cells based on the input signal. | 12-27-2012 |
20120326748 | LOGIC DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - According to example embodiments, a logic device includes a first functional block configured to perform a first operation according to first operation information and a second operation according to second operation information, and a second functional block configured to perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first functional block is configured to receive configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the first or second operation based on the selected first or second operation information. The second functional block is configured to receive the configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the third or fourth operation based on the selected first or second operation information. | 12-27-2012 |
20130002293 | RECONFIGURABLE DYNAMIC LOGIC GATE WITH LINEAR CORE - A dynamically reconfigurable linear core logic gate is a device that allows logical outputs dependent upon configurable parameters set within device. The device is comprised of three blocks: The first block receives at least one input signal and determines whether the signal o signals are low or high in comparison with a threshold reference signal. The second block sums the logic signals of the first block with an offset signal. The third block determines if the sum realized in the second block is a low or high by checking whether the sum falls within a predetermined interval. | 01-03-2013 |
20130002294 | PROGRAMMABLE CIRCUIT - Provided is a programmable circuit. The programmable circuit includes a first path and a second path connected in parallel between a first voltage node and a second voltage node. The first path includes a first programmable element, a first node, a first pull-up transistor, a second node, and a first pull-down transistor connected in series between the first voltage node and the second voltage node. The second path includes a second programmable element, a third node, a second pull-up transistor, a fourth node, and a second pull-down transistor connected in series between the first and second voltage nodes. A gate electrode of the first pull-up transistor, a gate electrode of the first pull-down transistor, and the fourth node are electrically connected to one another. A gate electrode of the second pull-up transistor, a gate electrode of the second pull-down transistor, and the second node are electrically connected to one another. | 01-03-2013 |
20130002295 | APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS - Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs. | 01-03-2013 |
20130021057 | CONFIGURABLE CIRCUITS, IC'S, AND SYSTEMS - Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data. | 01-24-2013 |
20130021058 | SYSTEM AND METHOD FOR REDUCING RECONFIGURATION POWER USAGE - A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration. | 01-24-2013 |
20130038347 | CONFIGURABLE IC'S WITH LARGE CARRY CHAINS - Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two. | 02-14-2013 |
20130069691 | INTEGRATED CIRCUIT HAVING A STANDARD CELL AND METHOD FOR FORMING - An integrated circuit includes a first plurality of transistors and a second plurality of transistors coupled together to form a standard cell that performs a logic function. Each of the first plurality of transistors is more critical to a speed of operation of the standard cell than any of the transistors of the second plurality of transistors. Each of the first plurality of transistors has a gate length longer than a gate length of any of the transistors of the second plurality of transistors. | 03-21-2013 |
20130093460 | CONFIGURABLE STORAGE ELEMENTS - An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a row of the configurable logic circuits and multiple configuration retrieval circuits for providing configuration bits to the row of configurable logic circuits. The IC also includes a row configuration controller for forcing the multiple configuration retrieval circuits to output a particular configuration value based on a user signal that is received at runtime. | 04-18-2013 |
20130093461 | CONFIGURABLE STORAGE ELEMENTS - An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a configurable routing fabric for configurably routing signals among configurable logic circuits. The configurable routing fabric includes a particular wiring path that connects an output of a source circuit to inputs of a destination circuit. The particular wiring path includes a first path and a second path that is parallel to the first path. The first and second paths are for configurably storing output signals of the source circuit. The first path connects to a first input of the destination circuit and the second path connects to a second input of the destination path. | 04-18-2013 |
20130093462 | CONFIGURABLE STORAGE ELEMENTS - A low power sub-cycle reconfigurable conduit is provided. The low power reconfigurable conduit is a clocked storage element that consumes less power when performing low-throughput operations that do not require sub-cycle rate. The low power conduit includes a first configurable routing multiplexer that is reconfigurable to select one of several inputs at a first clock rate. The low power conduit also includes an array of storage elements for storing output data from the configurable routing multiplexer at the first clock rate. Each storage element in the array of storage elements operate at a second clock rate that is slower than the first clock rate. Each storage element receives a different phase of a clock that operates at the second clock rate. The low power conduit also includes a second configurable routing multiplexer that is reconfigurable to select from the array of storage elements at the first clock rate. | 04-18-2013 |
20130099819 | NON-SEQUENTIALLY CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit. | 04-25-2013 |
20130127493 | NEAREST NEIGHBOR SERIAL CONTENT ADDRESSABLE MEMORY - A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs. | 05-23-2013 |
20130135007 | LOGIC CIRCUIT FOR A SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF MANAGING AN OPERATION IN THE SEMICONDUCTOR MEMORY DEVICE - A logic circuit for a semiconductor memory device, includes a first logic portion which stores data from a first data signal, and generates a second data signal based on the first data signal, a second logic portion which generates a first address signal and stores an address from the first address signal where data from the second data signal is to be written, and a third logic portion which generates a flag signal which indicates whether the data stored in the first logic portion is valid. | 05-30-2013 |
20130147513 | RECURSIVE CODE LOGIC - A logic device includes a transmission gate block configured to receive a binary input and a control input, the transmission gate block configured to provide a multi-bit output that is correlated from the binary input and in response to the control input having a first value. A state driver block is activated to drive one of a low state bit pattern or a high state bit pattern to the multi-bit output in response to the control input having a second value, which is different from the first value. | 06-13-2013 |
20130147514 | CONFIGURATION CONTEXT SWITCHER - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 06-13-2013 |
20130147515 | Hierarchically-Scalable Reconfigurable Integrated Circuit Architecture With Unit Delay Modules - The exemplary embodiments provide a reconfigurable integrated circuit architecture having a predetermined, unit timing increment (or delay) for both data operations and data word transfers within every zone and between zones, which are independent of application placement and routing. An exemplary IC comprises a plurality of circuit zones, with each zone comprising: a plurality of composite circuit elements, a plurality of cluster queues, and a full interconnect bus. Each composite circuit element comprises: a configurable circuit element circuit and an element interface and control circuit, with the element interface and control circuit comprising an input queue and an output queue. Each cluster queue comprises an element interface and control having an input queue and an output queue. The full interconnect bus couples every output queue within the zone to every input queue within the zone. Any data operation performed by a composite circuit element, any data word transfer through a cluster queue, and any data word transfer over the first full interconnect bus, is completed within a predetermined unit time delay which is independent of application placement and application data routing on the reconfigurable IC. | 06-13-2013 |
20130154685 | BOOLEAN LOGIC IN A STATE MACHINE LATTICE - Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell. | 06-20-2013 |
20130162289 | METHOD AND APPARATUS FOR CONFIGURING AN INTEGRATED CIRCUIT - A method and apparatus configures an integrated circuit by determining a multi-bit configuration value on a single node. The multi-bit configuration value is determined by using at least a voltage level at the single node and also by detecting a time to reach a voltage threshold level at the single node, based on a voltage ramp generation circuit. The method and apparatus also includes configuring an operation mode of a circuit in the integrated circuit based on the determined multi-bit configuration value from the single node. Multi-bit configuration values may be obtained on multiple single nodes in an integrated circuit. In one example, a voltage level is employed in addition to a time to reach a voltage threshold level whereas in another example a current level on a single node is utilized in combination with detection of a time to reach a voltage threshold level. | 06-27-2013 |
20130162290 | PARTIAL RECONFIGURATION CIRCUITRY - Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring a portion of a memory array. The PR circuitry may include a host circuit, a control circuit, an address register, and first, second, and third data registers. The host circuit may send a series of PR instructions to the control circuit. The control circuit may include a decompression circuit for decompressing compressed instructions, a decryption circuit for decrypting encrypted instructions, an error checking circuit for detecting errors in the instructions, and a logic circuit. The address register may select a desired frame. The selected frame may be loaded into the third data register. The contents of the third data register may be shifted into the first data register. The contents of the first data register may be modified according to a desired logic function using the logic circuit, shifted into the second data register, and written into the selected frame. | 06-27-2013 |
20130162291 | Configuration Context Switcher with a Latch - Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data. | 06-27-2013 |
20130176051 | RECONFIGURABLE CIRCUIT - A reconfigurable circuit of the present invention is characterized in being provided with: a first programmable wiring group, which is disposed in the first direction; a second programmable wiring group, which is disposed in the second direction that intersects the first direction; a first switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and the branch line group of a functional block input wiring group or at the intersecting points of the branch line group of the first programmable wiring group and the functional block input wiring group; a second switch element array, which connects the programmable wiring groups to each other at the intersecting points of the first programmable wiring group and functional block output wiring; and a third switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the first programmable wiring group. The reconfigurable circuit is also characterized in being provided with a fourth switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the functional block input wiring group, and/or a fifth switch element array, which connects the programmable wiring groups to each other at the intersecting points of the second programmable wiring group and the branch lines of the functional block output wiring. | 07-11-2013 |
20130181739 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE CONTROL METHOD - A semiconductor device comprises: reconfigurable logic circuit that includes plurality of resistance change elements; logical configuration of the reconfigurable logic circuit being decided depending on whether each of plurality of resistance change elements is in first resistance state or in second resistance state whose resistance value is lower than resistance value of first resistance state; resistance value monitor circuit that includes resistance change element pre-programmed to the first resistance state; the resistance value monitor circuit detecting whether or not pre-programmed resistance change element retains the first resistance state; and controller that, in case it is detected that resistance change element provided in resistance value monitor circuit doe not retain first resistance state, applies voltage used in programming from second resistance state to first resistance state to resistance change element retaining first resistance states, out of plurality of resistance change elements provided in reconfigurable logic circuit. | 07-18-2013 |
20130194002 | RE-CONFIGURABLE MIXED-MODE INTEGRATED CIRCUIT ARCHITECTURE - An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells. | 08-01-2013 |
20130241595 | Data-Driven Integrated Circuit Architecture - The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data. | 09-19-2013 |
20130257476 | INTEGRATED CIRCUITS WITH MULTI-STAGE LOGIC REGIONS - A programmable logic region on a programmable integrated circuit may include a first set of look-up tables that receive programmable logic region input signals and a second set of look-up tables that produce programmable logic region output signals. Multiplexer circuitry may be interposed between the first and second sets of look-up tables. The multiplexer circuitry may receive the programmable logic region input signals in parallel with the output signals from the first set of look-up tables and may provide corresponding selected signals to the second set of look-up tables. The programmable logic region input signals may be shared by the first and second sets of look-up tables. Logic circuitry may be coupled to outputs of the first and second sets of look-up tables. The logic circuitry may be configured to logically combine output signals from the first and second sets of look-up tables. | 10-03-2013 |
20130257477 | SEMICONDUCTOR INTEGRATED CIRCUIT - One embodiment provides a semiconductor integrated circuit, including: a first input wire; a second input wire; a first look-up table (LUT) comprising: a plurality of first memories; a first number of first switches connected to the first input wire; and a second number of second switches connected to the second input wire, the second number being less than the first number, the first LUT being configured to output information which is stored in one of the first memories; and a second LUT including: a plurality of second memories; a third number of third switches connected to the second input wire; and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second LUT being configured to output information which is stored in one of the second memories. | 10-03-2013 |
20130278288 | IC OUTPUT SIGNAL PATH WITH SWITCH, BUS HOLDER, AND BUFFER - An electronic integrated circuit includes a signal path connected between the functional logic ( | 10-24-2013 |
20130278289 | Method and Apparatus for Improving Efficiency of Programmable Logic Circuit Using Cascade Configuration - An integrated circuit (“IC”) device capable of programmably performing user selected functions is disclosed. The IC device, in one embodiment, includes multiple input output (“I/O”) blocks, programmable interconnection blocks (“PIBs”), and programmable logic blocks (“PLBs”). While the I/O blocks can be selectively coupled to one of I/O pads, the PIB blocks can be selectively coupled to at least a portion of the I/O blocks. Each of the PLBs, in one aspect, is configured to have at least two programmable look-up tables (“LUTs”). The programmable LUTs are connected in a cascade configuration via a dedicated programmable wire (“DPW”). | 10-24-2013 |
20130285697 | PROGRAMMABLE LSI - An object is to achieve both suppression of operation delay and reduction in power consumption of a programmable LSI. A compiler generates, from source code, configuration data needed in a programmable LSI and a time schedule that shows a timing of using the data in the programmable LSI (a timing at which the data is held in a configuration memory) and a timing of storing the data in the programmable LSI before the data is used. Supply of new configuration data to the programmable LSI from the outside (storage of new configuration data) and data rewrite in the configuration memory in the programmable LSI (circuit reconfiguration) are performed independently and concurrently on the basis of the time schedule. | 10-31-2013 |
20130314122 | APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS - Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs. | 11-28-2013 |
20130335116 | RECONFIGURABLE CIRCUIT AND METHOD FOR REFRESHING RECONFIGURABLE CIRCUIT - A reconfigurable circuit ( | 12-19-2013 |
20140021980 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current. | 01-23-2014 |
20140028347 | IMPLEMENTING LOGIC CIRCUITS WITH MEMRISTORS - Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor. | 01-30-2014 |
20140035616 | RECONFIGURABLE INTEGRATED CIRCUIT DEVICE AND WRITING METHOD THEREOF - A reconfigurable integrated circuit device includes a memory unit for storing configuration information. The memory unit has a nonvolatile memory transistor having a gate connected to a first wire, a first terminal connected to a second wire, and a second terminal connected to a third wire. The memory unit also includes a switch circuit connected to the third wire. The switch circuit alters the configuration of the integrated circuit device by, for example, opening and closing to make wiring connections or disconnections. The integrated circuit device additionally includes a data supply circuit for supplying bit data and a first power supply circuit for supplying voltages to the first wire for storing bit data in the first nonvolatile memory transistor and for storing bit data as a charge level on the third wire. | 02-06-2014 |
20140077837 | LOGIC CIRCUIT DEVICE COMPRISING AT LEAST ONE DIGITAL INPUT - The invention pertains to a logic circuit device comprising at least one digital input furnished with a fuse (FUS) being, in the closed state, suitable for applying an electrical input voltage of the logic circuit corresponding to a first logic state from among the logic states 0 and 1, and, in the definitive open state, suitable for applying an electrical input voltage of the logic circuit corresponding to the second logic state from among the logic states 0 and 1, said fuse (FUS) being suitable for being placed definitively in the second logic state by injection of a current greater than a threshold current (CS). | 03-20-2014 |
20140077838 | BOOLEAN LOGIC IN A STATE MACHINE LATTICE - Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell. | 03-20-2014 |
20140091835 | APPARATUS AND METHODS FOR DIGITAL CONFIGURATION OF INTEGRATED CIRCUITS - Apparatus and method for digital configuration of integrated circuits (ICs) are provided herein. In certain implementations, an IC includes an impedance sensing circuit and at least one pin used for digital configuration. The impedance sensing circuit can detect an impedance value of an external passive network electrically connected to the pin, and can digitally configure the IC based on the detected impedance. For example, an end-user can connect an external resistor of a particular resistance to the pin, and the impedance sensing circuit can sense or detect the external resistor's resistance and digitally configure the IC based on the detected resistance. Accordingly, an end-user can digitally configure the IC by connecting a passive external component corresponding to a desired digital configuration to the pin. In certain implementations, the IC includes multiple pins, and the digital configuration is based on the impedances detected on each of the pins. | 04-03-2014 |
20140103958 | PROGRAMMABLE LOGIC DEVICE AND METHOD FOR DRIVING PROGRAMMABLE LOGIC DEVICE - Configuration is performed in accordance with a plurality of states when power supply voltage is supplied intermittently. At the time of start of supply of power supply voltage with configuration, a programmable logic device is sequentially changed into a first state where configuration data is not set in a configuration memory, a second state where the configuration memory is initialized, and a third state where the configuration data can be set in the configuration memory. At the time of start of supply of power supply voltage without configuration, the programmable logic device is sequentially changed into a fourth state where the configuration data is not set in the configuration memory and the third state. The first to fourth states are switched to any one of the states by control of a first state signal and a second state signal. | 04-17-2014 |
20140139263 | DATA PROCESSING APPARATUS AND METHOD IN PLC SYSTEM - A programmable logic controller (PLC) system, and more particularly, a data processing apparatus and method in the PLC system are provided. In the data processing method in a programmable logic controller (PLC) system, first dummy code data is output to an area having a chip selection signal for valid data output. The valid data is output after the first dummy code data is output. And second dummy code data is output when the valid data output is completed. | 05-22-2014 |
20140167814 | MAGNETIC FIELD CONTROLLED RECONFIGURABLE SEMICONDUCTOR LOGIC DEVICE AND METHOD FOR CONTROLLING THE SAME - A non-volatile reconfigurable logic device executing logical operations and a memory function and controlled by a magnetic field is provided. The reconfigurable logic device includes i) at least one semiconductor device; and ii) a pair of magnetic field controlled devices respectively spaced apart from both sides of the semiconductor device and that are adapted to generate magnetic field leakage to control the semiconductor device. The semiconductor device includes i) a first semiconductor layer; and ii) a second semiconductor layer located on the first semiconductor layer. One of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer and the other is an n-type semiconductor layer. | 06-19-2014 |
20140176185 | PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE - A programmable logic device having a small layout area even with an increasing circuit scale. The programmable logic device includes first programmable logic elements (PLEs); a second PLE; first wirings to which a signal including configuration data is supplied in a first period and which are electrically connected to respective output terminals of the first PLEs in a second period; a second wiring electrically connected to an input terminal of the second PLE; and circuits each connected to the corresponding first wiring. Each of the circuits includes at least a first switch, a second switch, and a third switch. An on/off state of the second switch depends on a potential of a node to which the signal is supplied from the corresponding first wiring through the first switch. The second switch and the third switch control an electrical connection between the corresponding first wiring and the second wiring. | 06-26-2014 |
20140176186 | GRAPHENE MULTIPLE-VALUED LOGIC DEVICE, OPERATION METHOD THEREOF, AND FABRICATION METHOD THEREOF - A graphene multiple-valued logic device and a fabrication method thereof are disclosed. The graphene multiple-valued logic device includes a substrate, a graphene channel layer disposed on the substrate, source and drain electrodes disposed at both ends of the graphene channel layer, respectively, an insulator film formed on the graphene channel layer; and at least two gate electrodes disposed on the insulator film with a predetermined gap defined therebetween. The device allows adjustment of conductivity and resistance of the graphene channel layer depending on a gate voltage, whereby electric current flowing in the device can be variously changed when applied to a multiple-valued logic system. | 06-26-2014 |
20140203840 | Circuit and method of driving the same - In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential. | 07-24-2014 |
20140210511 | Error Detection in Nonvolatile Logic Arrays Using Parity - A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected. | 07-31-2014 |
20140210512 | Rescaling - A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits. | 07-31-2014 |
20140210513 | Controllable Storage Elements for an IC - An integrated circuit (“IC”) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the IC. | 07-31-2014 |
20140232430 | METHODS AND SYSTEMS TO STRESS-PROGRAM AN INTEGRATED CIRCUIT - Methods and systems to stress-program a first integrated circuit (IC) block to output a pre-determined value upon activation/reset, such as to support time-zero compensation/trimming. To program, the first block is configured with first-block program parameters to cause the first block to output a pre-determined value. The first block is stressed while configured with the first-block program parameters, to cause the first block to output the pre-determined value without the first-block program parameters. The first block may include a latch designed as a fully balance circuit and may be asymmetrically stressed to alter a characteristic of one path relative to another. The pre-determined value may be selected to compensate for process corner variations and/or other random variations. | 08-21-2014 |
20140239999 | MULTIPLE-TIME CONFIGURABLE NON-VOLATILE LOOK-UP-TABLE - Innovative Non-Volatile Look-Up-Table (NV-LUT) has been constructed by Single Gate Logic Non-Volatile Memory (SGLNVM) devices processed with the standard CMOS logic process. One of a pair of complementary SGLNVM devices is always programmed to the high threshold voltage state and the other remains in the low threshold voltage state. By applying digital voltage rail (V | 08-28-2014 |
20140240000 | CONFIGURING DATA REGISTERS TO PROGRAM A PROGRAMMABLE DEVICE WITH A CONFIGURATION BIT STREAM WITHOUT PHANTOM BITS - Techniques and mechanisms dynamically configure shift registers among registers composing data registers in a circuit such as a Programmable Logic Device (PLD). A configuration bit stream used to configure the PLD may have a reduced size if “phantom bits” not corresponding to configuration elements are removed. Shift registers may be dynamically configured such that registers which do not correspond to physical configuration elements may be skipped. Thus, a PLD may be programmed with a configuration bit stream without phantom bits. | 08-28-2014 |
20140240001 | Operational Time Extension - Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit. The method then maintains a configuration of the particular reconfigurable circuit constant over at least two contiguous reconfiguration cycles in order to reduce signal delay through the signal path and thereby satisfy the timing constraint. | 08-28-2014 |
20140266300 | PHASE-CHANGE MATERIAL RECONFIGURABLE CIRCUITS - One embodiment of the invention includes a reconfigurable circuit comprising a phase-change material switch. The phase-change material switch includes an actuation portion configured to receive a control signal having one of a first state and a second state and to emit a first heat profile in response to the first state of the control signal and a second heat profile in response to the second state of the control signal. The phase-change material switch also includes a switch portion comprising a phase-change material in proximity with the actuation portion. The switch portion can be selectable between a conducting state in response to the first heat profile to conduct an input signal from an input to an output of the phase-change material switch and a blocking state in response to the second heat profile to substantially block the input signal from the input to the output. | 09-18-2014 |
20140285233 | EFFICIENT RECONFIGURABLE LOGIC TILE - An application specific integrated circuit (ASIC) that includes a digital signal processing (DSP) core and a configurable logic block coupled to the DSP core. The configurable logic block including a plurality of interconnected logic modules to apply a pre-configured logic function to an input. Each of the plurality of logic modules including a controller and a plurality of logic components, the controller of each logic module dynamically reconfigures the connections between the controller's logic module and another logic module. | 09-25-2014 |
20140285234 | SEMICONDUCTOR DEVICE - To provide a charge pump circuit to manufacture a low-power-consumption PLD. A semiconductor device includes a first circuit and a second circuit electrically connected to the first circuit. A charge pump circuit formed of a transistor including an oxide semiconductor and a boosting control circuit controlling the charge pump circuit are provided between the first circuit and the second circuit. The first circuit and the charge pump circuit operate at first power supply voltage, and the boosting control circuit and the second circuit operate at second power supply voltage. The first power supply voltage is lower than the second power supply voltage. | 09-25-2014 |
20140320164 | FAST DYNAMIC REGISTER WITH TRANSPARENT LATCH - A fast dynamic register including a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges first and second precharge nodes and then releases the first precharge node in response to a clock. The data block evaluates data by either pulling the first precharge node low in response to the clock or does not pull it low, in which case the second precharge node is discharged. The transparent latch passes a state of the second precharge node to a store node when transparent, and otherwise latches the store node. The output logic gate drives an output node to a state based on states of the second precharge node and the store node. The transparent latch may be implemented with relatively small devices to reduce size and power consumption to improve efficiency. | 10-30-2014 |
20140320165 | Runtime Loading of Configuration Data In A Configurable IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network. | 10-30-2014 |
20140327470 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY - A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, applying a first programming voltage to a shared node of a second electrode of the first resistive element, a first electrode of the second resistive element, and to a gate of a transistor element, and changing a resistance state of the first resistive element to a low resistance state while maintaining a resistance state of the second resistive element, when a voltage difference between the first programming voltage at the second terminal and the first input voltage at the first terminal exceeds a programming voltage associated with the first resistive element. | 11-06-2014 |
20140333344 | ADAPTIVE INTERFACE FOR COUPLING FPGA MODULES - A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA, whereby a serial interface is formed between the at least one FPGA and the at least one I/O module, comprising the steps of configuring a maximum number of registers to be transmitted for each FPGA application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side. | 11-13-2014 |
20140354328 | Programmable mixed-signal input/output (IO) - Techniques are described for providing highly integrated and configurable IO ports for integrated circuits that can be individually configured for a variety of general purpose digital or analog functions, such as multiple channel analog-to-digital converters (ADC), multiple channel digital-to-analog converters (DAC), multiplexers, GPIOs, analog switches, switch and multiplexers, digital logic level translators, comparators, temperature sensors and relays, and so forth. The configurations of individual ports can be set by a configuration register that can, for instance, designate the function and voltage range of the port without impacting the other ports. In embodiments, logic mapping of a port order sequence can be defined. A data register can also be included for handling microcontroller commands and storing conversion results from, for instance, a port functioning as an ADC input port. These capabilities can be combined with its multi-range, high voltage and high current capability to increase functionality. | 12-04-2014 |
20140354329 | ELECTRONIC DEVICE FOR FUNCTION RESETTING OF PINS AND METHOD THEREOF - An electronic device includes a chip and a pin configuration apparatus. The chip includes a plurality of pins with different functions. The pin configuration apparatus is used for resetting the pins from being configured to execute a first function to being configured to execute a second function. | 12-04-2014 |
20140361808 | System and Method for Spin Logic - Systems and methods can perform automatic computation developed using carbon nanotubes and graphene nanoribbons and/or InSb p-n bilayer channel avalanche diodes and wires. Spin logic can provide improvements in speed, power, and area, promising to be a high-performance logic family for the next generation of computing. The systems and methods can replace CMOS, for example, for general computing applications. | 12-11-2014 |
20140368235 | PROGRAMMABLE LOGIC DEVICE - Data of a register in a programmable logic element is retained. A volatile storage circuit and a nonvolatile storage circuit are provided in a register of a programmable logic element whose function can be changed in response to a plurality of context signals. The nonvolatile storage circuit includes nonvolatile storage portions for storing data in the register. The number of nonvolatile storage portions corresponds to the number of context signals. With such a structure, the function can be changed each time context signals are switched and data in the register that is changed when the function is changed can be backed up to the nonvolatile storage portion in each function. In addition, the function can be changed each time context signals are switched and the data in the register that is backed up when the function is changed can be recovered to the volatile storage circuit. | 12-18-2014 |
20150008957 | NON-INTRUSIVE MONITORING AND CONTROL OF INTEGRATED CIRCUITS - A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC. | 01-08-2015 |
20150028920 | MULTIPLEXER, LOOK-UP TABLE AND FPGA - The present invention relates to a multiplexer comprising at least a first input and a second input and one output connected to the first input via a first pass gate and to the second input via a second pass gate, wherein the first pass gate comprises at least a first double-gate transistor, and the second pass gate comprises at least a second double-gate transistor, and each of the first and second double-gate transistors has a first gate controlled based on a first control signal and a second gate controlled based on a second control signal. The invention further relates to a look-up table and a and an FPGA based on the multiplexer. | 01-29-2015 |
20150035560 | NON-VOLATILE ELECTRONIC LOGIC MODULE - A logic module includes a device for implementing a logic function the device including at least one input and at least one output, the output at least partially representing the result of the logic function; at least one first element including at least one resistance state, at least one second element formed by a bipolar resistive memory; the first element and the second element having a common electrode connected to the output. | 02-05-2015 |
20150042380 | APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY - The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access. | 02-12-2015 |
20150054543 | APPARATUS AND METHOD FOR RAPID FUSE BANK ACCESS IN A MULTI-CORE PROCESSOR - An apparatus includes a fuse array, a random access memory (RAM), and a plurality of cores. The fuse array is disposed on a die, where the fuse array has a plurality of semiconductor fuses programmed with compressed configuration data. The RAM is disposed separately on the die. The plurality of cores is disposed separately on the die, where each of the plurality of cores is coupled to the fuse array and the RAM, and where the each of the plurality of cores accesses either the fuse array or the RAM upon power-up/reset as indicated by contents of a load data register to obtain the compressed configuration data. | 02-26-2015 |
20150054544 | DUAL-PORT POSITIVE LEVEL SENSITIVE PRESET DATA RETENTION LATCH - In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D | 02-26-2015 |
20150054545 | DUAL-PORT POSITIVE LEVEL SENSITIVE RESET PRESET DATA RETENTION LATCH - In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode. | 02-26-2015 |
20150054546 | Storage Elements For A Configurable IC And Method And Apparatus For Accessing Data Stored In The Storage Elements - Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits. | 02-26-2015 |
20150077158 | Configurable IC Having a Routing Fabric with Storage Elements - Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC. | 03-19-2015 |
20150077159 | PROGRAMMABLE STRUCTURED ARRAYS - A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer. | 03-19-2015 |
20150091613 | Flexible Logic Unit - A flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten. | 04-02-2015 |
20150091614 | Robust Flexible Logic Unit - A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit stream, done tile by tile and column by column, using latches that are sequentially programmed and locked using a lock bit as part of the bit stream provided. A scheme of odd and even clocks prevent latch transparency and ensures that once data has arrived at its destination it is properly locked, not to be unintentionally overwritten. The robust FLU is further equipped with cyclic redundancy check capabilities to provide indication of faulty column configuration. | 04-02-2015 |
20150102836 | PLD EDITOR AND METHOD FOR EDITING PLD CODE - A PLD editor and method for editing PLD code to be programmed into a PLD are provided. The PLD editor includes an interface, a storage system, and a processing system configured to obtain a PLD code, with the PLD code comprising one or more logic instruction blocks and corresponding block parameters for each logic instruction block, with the PLD code being intended for programming into the PLD, compare the one or more logic instruction blocks of the PLD code to a subset of the library of logic instruction blocks applicable to the PLD according to the library of PLD devices, determine inconsistent logic instruction blocks of the one or more logic instruction blocks, indicate the inconsistent logic instruction blocks, and correct the inconsistent logic instruction blocks using the subset of the library of logic instruction blocks. | 04-16-2015 |
20150102837 | SEMICONDUCTOR DEVICE INCLUDING AN ARBITER CELL - A semiconductor device is implemented with a technology for removing a command bubbling generated when performing a rank-to-rank switching on chips that are stacked and interconnected through a through silicon via (TSV). The semiconductor device includes a first memory, a second memory stacked over the first memory to input/output data through a TSV, and an arbiter configured to adjust first data received from the first memory and second data received from the second memory through the TSV and provide the adjusted data to an input/output (I/O) pad. | 04-16-2015 |
20150116000 | PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE - To provide a PLD having a reduced circuit area and an increased operation speed. In the circuit structure, a gate of a transistor provided between an input terminal and an output terminal of a programmable switch element is in an electrically floating state in a period when a signal is input to the programmable switch element. The structure enables the voltage of a gate to be increased by a boosting effect in response to a signal supplied from programmable logic elements, suppressing a reduction in amplitude voltage. This can reduce a circuit area by a region occupied by a booster circuit such as a pull-up circuit and increase operation speed. | 04-30-2015 |
20150123703 | LOGIC GATE AND A CORRESPONDING METHOD OF FUNCTION - A logic gate ( | 05-07-2015 |
20150123704 | RECONFIGURABLE CIRCUIT, STORAGE DEVICE, AND ELECTRONIC DEVICE INCLUDING STORAGE DEVICE - A reconfigurable circuit suitable for a redundant circuit of a storage device is provided. A programmable logic element (PLE) includes k logic circuits (e.g., XNOR circuits), k configuration memories (CM), and another logic circuit (e.g., an AND circuit) to which the outputs of the k logic circuits are input. The output of the AND circuit represents whether k input data of the PLE all correspond to configuration data stored in the k CMs. For example, when the address of a defective block in the storage device is stored in the CM and address data of the storage device the access of which is requested is input to the PLE, whether the defective block is accessible can be determined from the output of the AND circuit. | 05-07-2015 |
20150123705 | MEMORY ELEMENT AND PROGRAMMABLE LOGIC DEVICE - To provide a memory element where a desired potential can be stored as data without an increase in the number of power source potentials. The memory element stores data in a node which is brought into a floating state by turning off a transistor a channel of which is formed in an oxide semiconductor layer. The potential of a gate of the transistor can be increased by capacitive coupling between the gate and a source of the transistor. With the structure, a desired potential can be stored as data without an increase in the number of power source potentials. | 05-07-2015 |
20150137851 | Configurable IC's With Large Carry Chains - Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two. | 05-21-2015 |
20150145558 | METHOD FOR CREATING DIGITAL CIRCUITS OF A FEEDBACK CONTROL SYSTEM THAT IMPLEMENTS AN APPROXIMATION TECHNIQUE FOR MODEL PREDICTIVE CONTROL (MPC) - Method for creating digital circuits of an MPC controller ( | 05-28-2015 |
20150145559 | SEMICONDUCTOR DEVICE - To provide a highly reliable and low-power-consumption semiconductor device functioning as a programmable logic device. A monitor circuit is provided to monitor a change in the potential of a configuration memory in which a transistor is turned off to hold charge and a potential corresponding to the charge is stored as configuration data. The reset of the configuration data is controlled in accordance with the potential change. With such a structure, the configuration memory can be reconfigured before the configuration data is lost, resulting in improved reliability of the semiconductor device. In addition, reconfiguration can be performed every time data is lost. Accordingly, power consumption can be reduced as compared with the structure where reconfiguration is performed periodically. | 05-28-2015 |
20150311900 | PROGRAMMABLE LOGIC CIRCUIT AND NONVOLATILE FPGA - A programmable logic circuit according to an embodiment includes: a first programmable device with a first and second terminals, a resistance of the first programmable device being changeable from a high resistance to a low resistance; a second programmable device with a third and fourth terminals, a resistance of the second programmable device being changeable from a high resistance to a low resistance; a first wiring line to which the first terminal is connected; a second wiring line to which the third terminal is connected; a third wiring line to which the second terminal and the fourth terminal are connected; and a fuse element of which one terminal is connected to the third wiring line. | 10-29-2015 |
20150311901 | A NONVOLATILE MAGNETIC LOGIC DEVICE - In one aspect, a nonvolatile magnetic logic device comprises an electrically insulating layer, a write path, and a read path. The write path comprises a plurality of write path terminals and a magnetic layer having a uniform magnetization direction that is indicative of a direction of magnetization of the magnetic layer in a steady state. A logic state is written to the nonvolatile magnetic logic device by passing a current through the plurality of write path terminals. The read path comprises a plurality of read path terminals for evaluation of the logic state. The electrically insulating layer promotes electrical isolation between the read path and the write path and magnetic coupling of the read path to the write path. | 10-29-2015 |
20150355887 | PLD EDITOR AND METHOD FOR EDITING PLD CODE - Technology for editing PLD code to be programmed into a PLD are provided. The technology includes an interface, a storage system, and a processing system configured to obtain a PLD code, with the PLD code comprising one or more logic instruction blocks and corresponding block parameters for each logic instruction block, with the PLD code being intended for programming into the PLD, compare the one or more logic instruction blocks of the PLD code to a subset of the library of logic instruction blocks applicable to the PLD according to the library of PLD devices, determine inconsistent logic instruction blocks of the one or more logic instruction blocks, indicate the inconsistent logic instruction blocks, and correct the inconsistent logic instruction blocks using the subset of the library of logic instruction blocks. | 12-10-2015 |
20150365091 | BOOLEAN LOGIC IN A STATE MACHINE LATTICE - Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell. | 12-17-2015 |
20150365092 | SOLVING CONSTRAINT SATISFACTION PROBLEMS USING A FIELD PROGRAMMABLE GATE ARRAY - A method for configuring a Field Programmable Gate Array (FPGA) with a Constraint Satisfaction Problem (CSP) assignment having multiple constraint expressions, the method comprising: setting each of the multiple constraint expressions as a configurable logic block (CLB) in the FPGA, to yield multiple CLBs; setting an assignment vector in the FPGA, wherein the assignment vector is a number vector configured to store a candidate solution to the CSP assignment; and forming a feedback loop by connecting the assignment vector to inputs of the multiple CLBs, and connecting outputs of the multiple CLBs to the assignment vector. Further disclosed is a design structure for the FPGA, optionally residing on a storage medium as a data format used for the exchange of layout data of integrated circuits. | 12-17-2015 |
20150381174 | CIRCUIT AND METHOD OF DRIVING THE SAME - In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential. | 12-31-2015 |
20150381181 | NON-VOLATILE LOGIC DEVICE BASED ON PHASE-CHANGE MAGNETIC MATERIALS AND LOGIC OPERATION METHOD THEREOF - A non-volatile logic device, including: a substrate, a magnetic head, a base electrode, an insulating layer, a phase-change magnetic film, and a top electrode. The substrate includes a silicon substrate and an active layer attached to the silicon substrate. The base electrode includes an N-type silicon layer, a P-type silicon layer and a heating layer, the N-type silicon layer and the P-type silicon layer constitute a PN diode structure, and the size of the heating layer is smaller than that of the P-type silicon layer. The phase-change magnetic film is deposited on the insulating layer and is electrically contacted with the heating layer. The top electrode and the base electrode are connected to an external electrical pulse signal, and an external magnetic field parallel to a two dimensional plane of the phase-change magnetic film is applied to the non-volatile logic device. | 12-31-2015 |
20150381182 | FINE-GRAIN DYNAMICALLY RECONFIGURABLE FPGA ARCHITECTURE - A field programmable gate array (FPGA) and method of reconfiguring a FPGA are disclosed. The FPGA includes a plurality of logic elements interconnected with reconfigurable switches and at least horizontal and vertical direct links A memory is coupled to the reconfigurable switches, the memory being configured to store at least two run time configurations. The reconfigurable switches are reconfigurable based on a selected run time configuration stored in the memory. The memory may be a nanoelectronic random access memory (RAM). The memory may be configured to store the at least two run time configurations for at least four logic elements. Each logic element may include a look-up-table (LUT), a flip-flop, inputs and outputs. Each logic element may include dedicated carry logic. At least four logic elements may be inter-connected with diagonal direct links | 12-31-2015 |
20160006439 | PROGRAMMABLE INPUT/OUTPUT CIRCUIT - A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the TO pads. | 01-07-2016 |
20160028396 | HIGH-PERFORMANCE LOW-POWER NEAR-VT RESISTIVE MEMORY-BASED FPGA - A Field Programmable Gate Array (FPGA) of the island-type comprising a plurality of cluster-based Configurable Logic Blocks (CLBs), whereby each of the cluster-based CLBs is surrounded by a global routing structure formed by a plurality of multiplexers and pass/transmission-gates organized in Switch Boxes (SBs) and Connection Blocks (CBs), the switch boxes and the connection blocks comprising at least a first plurality of resistive memories inserted in a data path of a first routing architecture of the switch boxes and the connection blocks. Each CLB contains Basic Logic Elements (BLEs), as well as local routing resources. | 01-28-2016 |
20160028399 | RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network. | 01-28-2016 |
20160028400 | FLEXIBLE RIPPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and a plurality of logic cells within at least one of the PLBs, where each logic cell includes a four input lookup table (4-LUT) configured to provide a 4-LUT output signal to associated carry logic. Each logic cell is configurable according to at least two selectable operational modes including a logic function output mode and a ripple arithmetic output mode, and at least three of the 4-LUT inputs are interchangeable when a selected operational mode comprises the ripple arithmetic output mode. | 01-28-2016 |
20160028401 | MULTIPLE MODE DEVICE IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell. | 01-28-2016 |
20160036447 | RECONFIGURABLE LOGIC DEVICE - [Problem] To be able to provide a reconfigurable logic device having a small area and enhanced reprogramming characteristics. | 02-04-2016 |
20160049940 | INTERCONNECT CIRCUITS HAVING LOW THRESHOLD VOLTAGE P-CHANNEL TRANSISTORS FOR A PROGRAMMABLE INTEGRATED CIRCUIT - An exemplary interconnect circuit for a programmable integrated circuit (IC) includes an input terminal coupled to receive from a node in the programmable IC, an output terminal coupled to transmit towards another node in the programmable IC, first and second control terminals coupled to receive from a memory cell of the programmable IC, and a complementary metal oxide semiconductor (CMOS) pass-gate coupled between the input terminal and the output terminal and to the first and second control terminals. The CMOS pass-gate includes a P-channel transistor configured with a low threshold voltage for a CMOS process used to fabricate the programmable IC. | 02-18-2016 |
20160055907 | NON-VOLATILE MEMORY BASED SYNCHRONOUS LOGIC - A method for setting resistance states of a first and a second resistive memory element (RME) is disclosed. The method may include coupling, via a common node, a first RME to a second RME. The method may include setting the first RME to either a high voltage resistance state or a low voltage resistance state. The method may include setting the second RME to a different state relative to the state of the first RME, wherein setting the second RME is substantially simultaneous with setting the first RME. | 02-25-2016 |
20160056821 | STATE-RETAINING LOGIC CELL - According to an example, a state-retaining logic cell may include a plurality of invertors. The state-retaining logic cell may further include an output node NVM storage cell connected adjacent an output node of one of the inverters. | 02-25-2016 |
20160065213 | LOGIC CELL FOR PROGRAMMABLE LOGIC DEVICE - A logic cell in a programmable logic device receives an external signal from a routing network that serves as a select signal that selects a combinatorial logic signal via a first multiplexor as well as a data input to a second multiplexor. The second multiplexor selects between the combinatorial logic signal and the external signal and provides an output signal to a register. Accordingly, the logic cell has the flexibility to support a combinatorial and/or sequential function using minimal routing resources. A third multiplexor may select the output from the register or another signal as the output signal from the logic cell. A clock signal to the register may be gated off when the register output is not selected as the output signal, thereby reducing dynamic power consumption. The programmable logic device may include a number of super logic cells, each of which includes a plurality of logic cells. | 03-03-2016 |
20160065216 | INTEGRATED CIRCUIT DEVICE WITH PROGRAMMABLE ANALOG SUBSYSTEM - An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks. | 03-03-2016 |
20160065217 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor device includes a field programmable gate array (FPGA), a controller and a memory. The controller controls the FPGA. The memory stores converted configuration data obtained by converting configuration data of the FPGA, based on defect data of the FPGA. | 03-03-2016 |
20160065218 | RECONFIGURABLE LOGIC CIRCUIT DEVICE - According to one embodiment, a reconfigurable logic circuit device includes a memory circuit including a cell group which includes unit cells connected in series, a control circuit connected to the unit cell at one end of the cell group, and an output terminal connected to the unit cell at the other end of the cell group; and a switch circuit connected to the output terminal and controlled by a signal from the memory circuit. Each of the unit cells includes a select element including first and second terminals and a control terminal to which a control signal is input, and a memory element including a third terminal connected to the first terminal and a fourth terminal connected to the second terminal. | 03-03-2016 |
20160094228 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD THEREFOR - An information processing apparatus comprises: a programmable processing unit capable of changing a circuit configuration by a configuration; a first control unit connected to the programmable processing unit, that instructs the programmable processing unit to perform a first configuration for a first job to be processed by the first control unit, and processes the first job by means of the programmable processing unit which has changed the circuit configuration according to the instruction; and a second control unit connected to the programmable processing unit, wherein the first control unit further instructs the programmable processing unit to perform a second configuration for a second job to be processed by the second control unit, and wherein the second control unit processes the second job by means of the programmable processing unit which has changed the circuit configuration according to the instruction. | 03-31-2016 |
20160094229 | CHIP AND METHOD FOR IDENTIFYING A CHIP - A chip includes a logic circuit which has a plurality of transistors and is configured to carry out a logical data processing function, the transistors being operated in a first direction when carrying out the data processing function, and a readout circuit which is configured to control the logic circuit in such a manner that the transistors are operated in a second direction opposite the first direction and is configured to determine an identification of the logic circuit on the basis of an output from the logic circuit when operating the transistors in the second direction. | 03-31-2016 |
20160105176 | SPIN WAVE DEVICE AND LOGIC CIRCUIT USING SPIN WAVE DEVICE - As a technique for attaining a reduction in power consumption, there is a technique for reducing power consumption using a spin wave. No specific proposal concerning spin wave generation, spin wave detection, and a latch technique for information has been made. | 04-14-2016 |
20160105178 | METHODS AND APPARATUSES FOR MULTIPLE CONCURRENT SUB-THRESHOLD VOLTAGE DOMAINS FOR OPTIMAL POWER PER GIVEN PERFORMANCE - A method and flow for implementing an ASIC using sub-threshold technology with optimized selection of voltage and process for a given application performance. An embodiment may also implement concurrently used multiple voltage domains inside a single place and route block. The voltage domain is dynamically changed between the cells at the placement time based on the timing path requirements. | 04-14-2016 |
20160105186 | SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING - Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers. | 04-14-2016 |
20160112048 | PSOC ARCHITECTURE - An example semiconductor chip includes analog circuits, digital circuits, and a digital input port. The digital input port is to receive an input signal. The analog circuit is to receive the input signal from the digital input port and produce a digital signal based on the input signal. | 04-21-2016 |
20160134289 | POWER MANAGEMENT SYSTEM FOR INTEGRATED CIRCUITS - An apparatus includes a plurality of programmable hardware resources and an analog-to-digital converter (ADC) disposed on an IC die. The ADC is configured to quantize values of one or more analog parameters of the IC die. The apparatus also includes a configuration control circuit configured to program the programmable hardware resources in response to a set of configuration data. The programmable hardware resources are programmed to implement a set of circuits specified by the configuration data and to connect the ADC to respective nodes of the IC die for sampling the analog parameters. The apparatus also includes an interface circuit coupled to the ADC and configured to generate a control signal based on quantized values of the one or more analog parameters from the ADC. The interface circuit outputs the control signal to a power supply coupled to a power terminal of the IC die. | 05-12-2016 |
20160173100 | SPINTRONIC LOGIC ELEMENT | 06-16-2016 |
20160173102 | DRAM-BASED RECONFIGURABLE LOGIC | 06-16-2016 |
20160182054 | Configurable Logic Circuit Including Dynamic Lookup Table | 06-23-2016 |
20160380629 | SCALABLE CROSSBAR APPARATUS AND METHOD FOR ARRANGING CROSSBAR CIRCUITS - Described is an apparatus (e.g., a router) which comprises: multiple ports; and a plurality of crossbar circuits arranged such that at least one crossbar circuit receives all interconnects associated with a data bit of the multiple ports and is operable to re-route signals on those interconnects. | 12-29-2016 |
20160380635 | COMPUTER ARCHITECTURE USING RAPIDLY RECONFIGURABLE CIRCUITS AND HIGH-BANDWIDTH MEMORY INTERFACES - A programmable device comprises one or more programming regions, each comprising a plurality of configurable logic blocks, where each of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block via a programmable interconnect fabric. The programmable device further comprises configuration logic configured to, in response to an instruction in an instruction stream, reconfigure hardware in one or more of the configurable logic blocks in a programming region independently from any of the other programming regions. | 12-29-2016 |