Class / Patent application number | Description | Number of patent applications / Date published |
326035000 | THRESHOLD (E.G., MAJORITY, MINORITY, OR WEIGHTED INPUTS, ETC.) | 35 |
20110115522 | MAGNETIC DEVICE FOR PERFORMING A LOGIC FUNCTION - A device for performing a “logic function” consisting of a magnetic structure including at least a first magnetoresistive stack including a first ferromagnetic layer and a second ferromagnetic layer separated by a non-ferromagnetic interlayer and at least one first line of current situated in the vicinity of the first magnetoresistive stack and generating in the vicinity of the first stack a magnetic field when an electric current passes through it. The first line includes at least two current input points so that two currents can be added together in the first line, with the sum of the two currents being determined by the logic function. | 05-19-2011 |
20120038387 | SPIN TORQUE MAGNETIC INTEGRATED CIRCUITS AND DEVICES THEREFOR - Spin torque magnetic integrated circuits and devices therefor are described. In an example, a spin torque magnetic device for a logic circuit includes a majority gate structure. An output is coupled to the majority gate structure. Three inputs are also coupled to the majority gate structure. | 02-16-2012 |
20120217993 | SPIN TORQUE MAGNETIC INTEGRATED CIRCUITS AND DEVICES THEREFOR - Spin torque magnetic integrated circuits and devices therefor are described. In an example, a spin torque magnetic device for a logic circuit includes a majority gate structure. An output is coupled to the majority gate structure. Three inputs are also coupled to the majority gate structure. | 08-30-2012 |
20140062529 | Majority Vote Circuit - Data words from a parallel communication channel are interleaved to two majority vote blocks that operate out of phase, using a divided clock signal that has half the clock frequency of the clock signal associated with the parallel communication channel. As one majority vote block evaluates a data word and outputs a result, the other majority vote block is in pre-charge mode awaiting the next data for evaluation. | 03-06-2014 |
20140312929 | Self-Recovering Bus Signal Detector - A detector circuit is disclosed that detects bus signal conditions. To detect a START condition, asynchronous sequential logic detects a first bus signal transition (e.g., from high to low) and a second bus signal (e.g., a high signal). The outputs of the asynchronous sequential logic are combined to produce a START signal that can be latched, so that the START signal can be used to wake up a system or for other purposes. To detect a STOP condition, asynchronous sequential logic is set by a transition (e.g., low to high) of the first bus signal and a second bus signal (e.g., a high signal), producing a STOP signal that can be used to reset the asynchronous sequential logic and the latch. | 10-23-2014 |
326036000 | With field effect-transistor | 15 |
20100148819 | Majority voter circuits and semiconductor device including the same - A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority. | 06-17-2010 |
20100321061 | THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE - Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology. | 12-23-2010 |
20110025375 | CMOS CIRCUITRY WITH MIXED TRANSISTOR PARAMETERS - CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example. | 02-03-2011 |
20110215832 | APPARATUS OF LOW POWER, AREA EFFICIENT FINFET CIRCUITS AND METHOD FOR IMPLEMENTING THE SAME - A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area. | 09-08-2011 |
20120062276 | CAPACITIVELY COUPLED LOGIC GATE - An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices. | 03-15-2012 |
20120133390 | ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN - A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead. | 05-31-2012 |
20130113518 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 05-09-2013 |
20130214813 | MULTI-THRESHOLD FLASH NCL CIRCUITRY - Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state. | 08-22-2013 |
20130214814 | SELF-READY FLASH NULL CONVENTION LOGIC - A self-ready flash null Convention Logic (NCL) gate includes a one-shot circuit to create the flash timing to reset the gate to a null state. The one-shot circuit may be any type of circuit to generate a pulse in response to a change of state of an input line. In one embodiment, the one-shot circuit may start the pulse in response to a change of a flash input line and end the pulse in response to the NCL output being reset to a null state. | 08-22-2013 |
20130249593 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 09-26-2013 |
20130249594 | IMPLEMENTATION METHOD FOR FAST NCL DATA PATH - An implementation method for a fast Null Convention Logic (NCL) data path includes a pipeline that is assembled from gates of various types of NCL. Self-ready flash NCL gates include a one-shot circuit to reset the gates to a null state and prepare the gates for the next wave of asserted data. In one embodiment, the one-shot circuit creates a flash pulse inside a gate in response to a change of a flash input line and ends the flash pulse in response to the gate output being reset to a null state. Conventional logic can be included in the data path as well. | 09-26-2013 |
20140043060 | CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC - A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output. | 02-13-2014 |
20140084959 | Analog Majority Vote Circuit - An analog majority voting circuit is formed of a cascade of two differential amplifiers and decouples heavily loaded nodes from a high voltage swing nodes, delivering high bandwidth while maintaining relatively high gain. A first stage's differential amplifier receives a first set of n input and a second set of n inputs and generates from these first and second intermediate outputs with a high capacitive load and low swing. These intermediate outputs are then the inputs for a second stage's differential amplifier, providing a low capacitive load, high swing output that can then be fed to an inverter for the final output of the voter. | 03-27-2014 |
20160006437 | THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS - This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations. | 01-07-2016 |
20160164526 | ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY - A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions. | 06-09-2016 |
20100148819 | Majority voter circuits and semiconductor device including the same - A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority. | 06-17-2010 |
20100321061 | THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE - Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology. | 12-23-2010 |
20110025375 | CMOS CIRCUITRY WITH MIXED TRANSISTOR PARAMETERS - CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example. | 02-03-2011 |
20110215832 | APPARATUS OF LOW POWER, AREA EFFICIENT FINFET CIRCUITS AND METHOD FOR IMPLEMENTING THE SAME - A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area. | 09-08-2011 |
20120062276 | CAPACITIVELY COUPLED LOGIC GATE - An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices. | 03-15-2012 |
20120133390 | ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN - A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead. | 05-31-2012 |
20130113518 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 05-09-2013 |
20130214813 | MULTI-THRESHOLD FLASH NCL CIRCUITRY - Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state. | 08-22-2013 |
20130214814 | SELF-READY FLASH NULL CONVENTION LOGIC - A self-ready flash null Convention Logic (NCL) gate includes a one-shot circuit to create the flash timing to reset the gate to a null state. The one-shot circuit may be any type of circuit to generate a pulse in response to a change of state of an input line. In one embodiment, the one-shot circuit may start the pulse in response to a change of a flash input line and end the pulse in response to the NCL output being reset to a null state. | 08-22-2013 |
20130249593 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 09-26-2013 |
20130249594 | IMPLEMENTATION METHOD FOR FAST NCL DATA PATH - An implementation method for a fast Null Convention Logic (NCL) data path includes a pipeline that is assembled from gates of various types of NCL. Self-ready flash NCL gates include a one-shot circuit to reset the gates to a null state and prepare the gates for the next wave of asserted data. In one embodiment, the one-shot circuit creates a flash pulse inside a gate in response to a change of a flash input line and ends the flash pulse in response to the gate output being reset to a null state. Conventional logic can be included in the data path as well. | 09-26-2013 |
20140043060 | CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC - A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output. | 02-13-2014 |
20140084959 | Analog Majority Vote Circuit - An analog majority voting circuit is formed of a cascade of two differential amplifiers and decouples heavily loaded nodes from a high voltage swing nodes, delivering high bandwidth while maintaining relatively high gain. A first stage's differential amplifier receives a first set of n input and a second set of n inputs and generates from these first and second intermediate outputs with a high capacitive load and low swing. These intermediate outputs are then the inputs for a second stage's differential amplifier, providing a low capacitive load, high swing output that can then be fed to an inverter for the final output of the voter. | 03-27-2014 |
20160006437 | THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS - This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations. | 01-07-2016 |
20160164526 | ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY - A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions. | 06-09-2016 |
326036000 | With field-effect transistor | 15 |
20100148819 | Majority voter circuits and semiconductor device including the same - A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority. | 06-17-2010 |
20100321061 | THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE - Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology. | 12-23-2010 |
20110025375 | CMOS CIRCUITRY WITH MIXED TRANSISTOR PARAMETERS - CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example. | 02-03-2011 |
20110215832 | APPARATUS OF LOW POWER, AREA EFFICIENT FINFET CIRCUITS AND METHOD FOR IMPLEMENTING THE SAME - A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area. | 09-08-2011 |
20120062276 | CAPACITIVELY COUPLED LOGIC GATE - An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices. | 03-15-2012 |
20120133390 | ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN - A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead. | 05-31-2012 |
20130113518 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 05-09-2013 |
20130214813 | MULTI-THRESHOLD FLASH NCL CIRCUITRY - Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state. | 08-22-2013 |
20130214814 | SELF-READY FLASH NULL CONVENTION LOGIC - A self-ready flash null Convention Logic (NCL) gate includes a one-shot circuit to create the flash timing to reset the gate to a null state. The one-shot circuit may be any type of circuit to generate a pulse in response to a change of state of an input line. In one embodiment, the one-shot circuit may start the pulse in response to a change of a flash input line and end the pulse in response to the NCL output being reset to a null state. | 08-22-2013 |
20130249593 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 09-26-2013 |
20130249594 | IMPLEMENTATION METHOD FOR FAST NCL DATA PATH - An implementation method for a fast Null Convention Logic (NCL) data path includes a pipeline that is assembled from gates of various types of NCL. Self-ready flash NCL gates include a one-shot circuit to reset the gates to a null state and prepare the gates for the next wave of asserted data. In one embodiment, the one-shot circuit creates a flash pulse inside a gate in response to a change of a flash input line and ends the flash pulse in response to the gate output being reset to a null state. Conventional logic can be included in the data path as well. | 09-26-2013 |
20140043060 | CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC - A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output. | 02-13-2014 |
20140084959 | Analog Majority Vote Circuit - An analog majority voting circuit is formed of a cascade of two differential amplifiers and decouples heavily loaded nodes from a high voltage swing nodes, delivering high bandwidth while maintaining relatively high gain. A first stage's differential amplifier receives a first set of n input and a second set of n inputs and generates from these first and second intermediate outputs with a high capacitive load and low swing. These intermediate outputs are then the inputs for a second stage's differential amplifier, providing a low capacitive load, high swing output that can then be fed to an inverter for the final output of the voter. | 03-27-2014 |
20160006437 | THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS - This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations. | 01-07-2016 |
20160164526 | ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY - A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions. | 06-09-2016 |
20100148819 | Majority voter circuits and semiconductor device including the same - A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority. | 06-17-2010 |
20100321061 | THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE - Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology. | 12-23-2010 |
20110025375 | CMOS CIRCUITRY WITH MIXED TRANSISTOR PARAMETERS - CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example. | 02-03-2011 |
20110215832 | APPARATUS OF LOW POWER, AREA EFFICIENT FINFET CIRCUITS AND METHOD FOR IMPLEMENTING THE SAME - A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area. | 09-08-2011 |
20120062276 | CAPACITIVELY COUPLED LOGIC GATE - An electronic logic circuit uses areal capacitive coupling devices coupled together to process a set of data inputs. Each areal capacitive coupling device can be configured such that a floating gate potential of such device can be altered to at least a first state or a second state in response to receiving an input signal from the set of data inputs, which is coupled electrically to the floating gate. A majority function logic circuit (and other similar circuits) can be interconnected this way using far fewer gates than with a conventional CMOS implementation. Selective logic gates can also be enabled or disabled by configuring them effectively as memory devices. | 03-15-2012 |
20120133390 | ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN - A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead. | 05-31-2012 |
20130113518 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 05-09-2013 |
20130214813 | MULTI-THRESHOLD FLASH NCL CIRCUITRY - Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state. | 08-22-2013 |
20130214814 | SELF-READY FLASH NULL CONVENTION LOGIC - A self-ready flash null Convention Logic (NCL) gate includes a one-shot circuit to create the flash timing to reset the gate to a null state. The one-shot circuit may be any type of circuit to generate a pulse in response to a change of state of an input line. In one embodiment, the one-shot circuit may start the pulse in response to a change of a flash input line and end the pulse in response to the NCL output being reset to a null state. | 08-22-2013 |
20130249593 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 09-26-2013 |
20130249594 | IMPLEMENTATION METHOD FOR FAST NCL DATA PATH - An implementation method for a fast Null Convention Logic (NCL) data path includes a pipeline that is assembled from gates of various types of NCL. Self-ready flash NCL gates include a one-shot circuit to reset the gates to a null state and prepare the gates for the next wave of asserted data. In one embodiment, the one-shot circuit creates a flash pulse inside a gate in response to a change of a flash input line and ends the flash pulse in response to the gate output being reset to a null state. Conventional logic can be included in the data path as well. | 09-26-2013 |
20140043060 | CONTROLLABLE POLARITY FET BASED ARITHMETIC AND DIFFERENTIAL LOGIC - A logic gate with three inputs A, B, and C, and one output implementing a function MAJ(A,B,C)=A*B+B*C+A*C comprising two mutually exclusive transmission gates (TGs) connected in series, based on two parallel double-gate controllable polarity devices, a polarity of each being controlled by input A and a conduction being controlled by input B, or vice-versa, in opposite polarities, and that route either an input A or C from one side of the transmission gates to the output. | 02-13-2014 |
20140084959 | Analog Majority Vote Circuit - An analog majority voting circuit is formed of a cascade of two differential amplifiers and decouples heavily loaded nodes from a high voltage swing nodes, delivering high bandwidth while maintaining relatively high gain. A first stage's differential amplifier receives a first set of n input and a second set of n inputs and generates from these first and second intermediate outputs with a high capacitive load and low swing. These intermediate outputs are then the inputs for a second stage's differential amplifier, providing a low capacitive load, high swing output that can then be fed to an inverter for the final output of the voter. | 03-27-2014 |
20160006437 | THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS - This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations. | 01-07-2016 |
20160164526 | ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY - A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions. | 06-09-2016 |