| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 326031000 | Signal level or switching threshold stabilization | 43 |
| 20100253386 | DATA TRANSMITTER AND RELATED SEMICONDUCTOR DEVICE - A semiconductor device transmitting a plurality of data using a multilevel signal includes a parity bit control unit generating a parity bit that varies with a number of data in which a most significant bit (MSB) and least significant bit (LSB) are different. A data conversion unit either inversely outputs the MSB or the LSB, or outputs the data without a change in response to the parity bit. Transmission units transmit data provided by the data conversion unit using the multilevel signal. | 10-07-2010 |
| 20090201048 | REDUCING ERRORS IN DATA BY DYNAMICALLY CALIBRATING TRIGGER POINT THRESHOLDS - Methods, systems, computer readable media and means for reducing errors in data caused by noise are provided. In some embodiments of the present invention, circuitry of the device receives timing data from one or more other circuitries and identifies noiseless periods from the timing data. The circuitry then actively adjusts the trigger point threshold of data being transmitted to and/or from the circuitry only during the noiseless periods. The circuitry subsequently monitors the timing data to identify noise periods. In response to identifying a noise period, the device ceases to adjust the trigger point threshold until the noise period is over. | 08-13-2009 |
| 20120176152 | Circuitry and Method Minimizing Output Switching Noise Through Split-Level Signaling and Bus Division Enabled by a Third Power Supply - Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals. | 07-12-2012 |
| 326032000 | Temperature compensation | 1 |
| 20080265935 | INTEGRATED MULTI-FUNCTION ANALOG CIRCUIT INCLUDING VOLTAGE, CURRENT, AND TEMPERATURE MONITOR AND GATE-DRIVER CIRCUIT BLOCKS - An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At least one temperature-sensing circuit is coupled to a fourth I/O pad. | 10-30-2008 |
| 326033000 | Bias or power supply level stabilization | 15 |
| 20130082734 | LOGIC CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is a logic circuit that can reduce the variation of a power supply voltage supplied thereto and a semiconductor integrated circuit including the logic circuit. The logic circuit includes a buffer unit, a voltage detection unit, and a switch unit. The buffer unit is connected between a first power supply or a voltage regulator and a second power supply to receive power supply, and outputs a signal having the same or inverted logic level as an input signal to an output terminal. The voltage detection unit detects a voltage at the output terminal and outputs a detection signal based on a detection result. The switch unit connects the buffer unit to the first power supply or the voltage regulator in accordance with the detection signal. | 04-04-2013 |
| 20130069690 | POWER CONTROL CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME - A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal. | 03-21-2013 |
| 20090251171 | Methods and Apparatus for Monitoring Power Gating Circuitry and for Controlling Circuit Operations in Dependence on Monitored Power Gating Conditions - A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage. | 10-08-2009 |
| 20090189636 | CIRCUIT HAVING LOGIC STATE RETENTION DURING POWER-DOWN AND METHOD THEREFOR - A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device. | 07-30-2009 |
| 20090009214 | Semiconductor device reducing power consumption in standby mode - A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the “H” and “L” levels, respectively. In response to this, a first switch is turned on so that a first node is electrically coupled to a power supply voltage, and attains the “H” level. Further, a second switch is turned on to couple electrically the ground voltage to a second node. In a standby mode, the first and second control signals are at the “L” and “H” levels, respectively. In response to this, a third switch is turned on to couple electrically the first and second nodes together. Since the power supply voltage was electrically coupled to the first node according to the turn-on of the first switch in the active mode, the path of the control signal including the first node to the switch has accumulated charged charges. | 01-08-2009 |
| 20090146685 | CALIBRATION CIRCUIT OF ON-DIE TERMINATION DEVICE - A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node connected to an external resistor and a reference voltage to generate pull-up calibration codes. The calibration circuit also includes a pull-up calibration resistor unit configured to pull up the calibration node in response to the pull-up calibration codes. The pull-up calibration resistor unit is calibrated such that its resistance becomes higher as a power supply voltage increases. | 06-11-2009 |
| 20080278194 | Semiconductor integrated circuit and operation method of the same - A semiconductor integrated circuit including on the same semiconductor substrate: a first circuit block including a switching transistor which is off when the first circuit block is inactive and on when the first circuit block is active, the first circuit block including internal circuits adapted to provide predetermined functions, the internal circuits being connected to a first power line maintained at a low-level source voltage; a second circuit block including internal circuits adapted to provide predetermined functions, the internal circuits being connected to a second power line maintained at a low-level source voltage; a power line switch section connected between the first and second power lines; and a control circuit adapted to control the power line switch section so that the first and second power lines are connected together at a later timing or gradually over a longer period of time than the switching transistor turns on. | 11-13-2008 |
| 20080211537 | Open drain output circuit - The transition time of an output is sometimes changed by a certain supply voltage connected to an output terminal of an output circuit. An output circuit to address this problem includes: a level detection circuit which detects a pull-up supply voltage applied to an output terminal OUT; and an open drain buffer circuit which can switch its driving ability on the basis of the detection result of the level detection circuit. Even if the output circuit is connected to a circuit whose supply voltage is different, it is made possible to produce an output while stabilizing the transition time of the output. | 09-04-2008 |
| 20110109345 | LOGIC CIRCUIT - A logic circuit includes two two-terminal switching devices and receives first and second pulses as inputs. Each of the two devices has two different stable resistivity values for each applied voltage that is greater than a first threshold voltage (Vth | 05-12-2011 |
| 20110175644 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes a first circuit block connected between first and second power lines, a logic circuit that receives an output signal of the first circuit block that is connected between the first power line and a fourth power line or a third power line and the second power line, and a second circuit block that receives an output signal of the logic circuit that is connected between the third and fourth power lines. In an active state, a first potential is supplied and in a standby state, a second potential lower than the first potential is supplied between the first and second power lines. In any of the active state and the standby state, the first potential is supplied between the third and fourth power lines. With this configuration, speeding-up of a critical path can be realized while maintaining a subthreshold current low. | 07-21-2011 |
| 20110133775 | INTERFACE CIRCUIT - An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive feedbacks an output signal of the second inverter circuit to the external input terminal. The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential. | 06-09-2011 |
| 20100066406 | Semiconductor device - The semiconductor device may include, but is not limited to, a first switching circuit, a second switching circuit, and a control circuit. The first switching circuit switches between first and second states. The second switching circuit switches between the first and second states. The second switching circuit reduces a first power impedance across the first switching circuit. The control circuit is coupled to the first and second switching circuits. The control circuit keeps the first switching circuit in the first state. The control circuit switches the second switching circuit from the second state to the first state. | 03-18-2010 |
| 20110316582 | Semiconductor integrated circuit including a power controllable region - A semiconductor chip includes a first power supply line and a second power supply line. A first switch is coupled between the first power supply line and the second power supply line, and a second switch is coupled between the first power supply line and the second power supply line. A circuit is coupled to the second power supply line. A first control signal line is coupled to the first switch, and a second control signal line coupled to the second switch. A logic gate is coupled to the first and the second control signal lines and a terminal is coupled to the logic gate to output a signal to an outside of the semiconductor chip. | 12-29-2011 |
| 20100231255 | Power Gating Circuit and Integrated Circuit Including Same - A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail. | 09-16-2010 |
| 20080224729 | INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT - In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential. | 09-18-2008 |
| 326034000 | With field effect-transistor | 12 |
| 20100109702 | SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM - A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed. | 05-06-2010 |
| 20080309369 | SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM - A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed. | 12-18-2008 |
| 20120068731 | CIRCUIT FOR RESTRAINING SHOOT THROUGH CURRENT - A circuit for restraining a shoot through current comprises a master selecting unit and a logic unit. The master selecting unit receives an input signal, and outputs first and second master selecting signals. The logic unit comprises first and second logic elements which generate first and second control signals for controlling two transistor switches connected in series. The first and second logic elements change the logic states of the first and second control signals according to the first and second master selecting signals. When the input signal is at a first logic level, the first logic element acquires a control privilege to change the logic state of the first control signal and trigger the second logic element to change the logic state of the second control signal. When the input signal is at a second logic, the second logic element acquires the control privilege. | 03-22-2012 |
| 20100148818 | HIGH SPEED CONDITIONAL BACK BIAS VIRTUAL GROUND RESTORATION CIRCUIT - A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, V | 06-17-2010 |
| 20100253387 | SYSTEM AND METHOD FOR AUTO-POWER GATING SYNTHESIS FOR ACTIVE LEAKAGE REDUCTION - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 10-07-2010 |
| 20100127730 | Internal charge transfer for circuits - The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture. | 05-27-2010 |
| 20080218201 | CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING - A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I | 09-11-2008 |
| 20100097097 | SEMICONDUCTOR DEVICE USING POWER GATING - A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode. | 04-22-2010 |
| 20110163779 | LOW POWER CONSUMPTION MIS SEMICONDUCTOR DEVICE - A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized. | 07-07-2011 |
| 20080218200 | Organic TFT inverter arrangement - An organic TFT (OTFT) inverter arrangement comprises an inverter stage including a series arrangement of first and second MOS OTFTs (T | 09-11-2008 |
| 20120161812 | LOGIC CIRCUIT WITHOUT ENHANCEMENT MODE TRANSISTORS - Embodiments of circuits, methods and systems for powering various stages of a logic circuit are disclosed. Other embodiments may also be described and claimed. | 06-28-2012 |
| 20100219857 | LOW POWER CONSUMPTION MIS SEMICONDUCTOR DEVICE - A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized. | 09-02-2010 |
| 20100109702 | SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM - A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed. | 05-06-2010 |
| 20080309369 | SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM - A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed. | 12-18-2008 |
| 20120068731 | CIRCUIT FOR RESTRAINING SHOOT THROUGH CURRENT - A circuit for restraining a shoot through current comprises a master selecting unit and a logic unit. The master selecting unit receives an input signal, and outputs first and second master selecting signals. The logic unit comprises first and second logic elements which generate first and second control signals for controlling two transistor switches connected in series. The first and second logic elements change the logic states of the first and second control signals according to the first and second master selecting signals. When the input signal is at a first logic level, the first logic element acquires a control privilege to change the logic state of the first control signal and trigger the second logic element to change the logic state of the second control signal. When the input signal is at a second logic, the second logic element acquires the control privilege. | 03-22-2012 |
| 20100148818 | HIGH SPEED CONDITIONAL BACK BIAS VIRTUAL GROUND RESTORATION CIRCUIT - A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, V | 06-17-2010 |
| 20100253387 | SYSTEM AND METHOD FOR AUTO-POWER GATING SYNTHESIS FOR ACTIVE LEAKAGE REDUCTION - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 10-07-2010 |
| 20100127730 | Internal charge transfer for circuits - The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture. | 05-27-2010 |
| 20080218201 | CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING - A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I | 09-11-2008 |
| 20100097097 | SEMICONDUCTOR DEVICE USING POWER GATING - A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode. | 04-22-2010 |
| 20110163779 | LOW POWER CONSUMPTION MIS SEMICONDUCTOR DEVICE - A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized. | 07-07-2011 |
| 20080218200 | Organic TFT inverter arrangement - An organic TFT (OTFT) inverter arrangement comprises an inverter stage including a series arrangement of first and second MOS OTFTs (T | 09-11-2008 |
| 20120161812 | LOGIC CIRCUIT WITHOUT ENHANCEMENT MODE TRANSISTORS - Embodiments of circuits, methods and systems for powering various stages of a logic circuit are disclosed. Other embodiments may also be described and claimed. | 06-28-2012 |
| 20100219857 | LOW POWER CONSUMPTION MIS SEMICONDUCTOR DEVICE - A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized. | 09-02-2010 |
| 326034000 | With field-effect transistor | 12 |
| 20100109702 | SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM - A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed. | 05-06-2010 |
| 20080309369 | SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM - A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed. | 12-18-2008 |
| 20120068731 | CIRCUIT FOR RESTRAINING SHOOT THROUGH CURRENT - A circuit for restraining a shoot through current comprises a master selecting unit and a logic unit. The master selecting unit receives an input signal, and outputs first and second master selecting signals. The logic unit comprises first and second logic elements which generate first and second control signals for controlling two transistor switches connected in series. The first and second logic elements change the logic states of the first and second control signals according to the first and second master selecting signals. When the input signal is at a first logic level, the first logic element acquires a control privilege to change the logic state of the first control signal and trigger the second logic element to change the logic state of the second control signal. When the input signal is at a second logic, the second logic element acquires the control privilege. | 03-22-2012 |
| 20100148818 | HIGH SPEED CONDITIONAL BACK BIAS VIRTUAL GROUND RESTORATION CIRCUIT - A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, V | 06-17-2010 |
| 20100253387 | SYSTEM AND METHOD FOR AUTO-POWER GATING SYNTHESIS FOR ACTIVE LEAKAGE REDUCTION - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 10-07-2010 |
| 20100127730 | Internal charge transfer for circuits - The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture. | 05-27-2010 |
| 20080218201 | CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING - A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I | 09-11-2008 |
| 20100097097 | SEMICONDUCTOR DEVICE USING POWER GATING - A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode. | 04-22-2010 |
| 20110163779 | LOW POWER CONSUMPTION MIS SEMICONDUCTOR DEVICE - A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized. | 07-07-2011 |
| 20080218200 | Organic TFT inverter arrangement - An organic TFT (OTFT) inverter arrangement comprises an inverter stage including a series arrangement of first and second MOS OTFTs (T | 09-11-2008 |
| 20120161812 | LOGIC CIRCUIT WITHOUT ENHANCEMENT MODE TRANSISTORS - Embodiments of circuits, methods and systems for powering various stages of a logic circuit are disclosed. Other embodiments may also be described and claimed. | 06-28-2012 |
| 20100219857 | LOW POWER CONSUMPTION MIS SEMICONDUCTOR DEVICE - A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized. | 09-02-2010 |
| 20100109702 | SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM - A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed. | 05-06-2010 |
| 20080309369 | SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM - A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed. | 12-18-2008 |
| 20120068731 | CIRCUIT FOR RESTRAINING SHOOT THROUGH CURRENT - A circuit for restraining a shoot through current comprises a master selecting unit and a logic unit. The master selecting unit receives an input signal, and outputs first and second master selecting signals. The logic unit comprises first and second logic elements which generate first and second control signals for controlling two transistor switches connected in series. The first and second logic elements change the logic states of the first and second control signals according to the first and second master selecting signals. When the input signal is at a first logic level, the first logic element acquires a control privilege to change the logic state of the first control signal and trigger the second logic element to change the logic state of the second control signal. When the input signal is at a second logic, the second logic element acquires the control privilege. | 03-22-2012 |
| 20100148818 | HIGH SPEED CONDITIONAL BACK BIAS VIRTUAL GROUND RESTORATION CIRCUIT - A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, V | 06-17-2010 |
| 20100253387 | SYSTEM AND METHOD FOR AUTO-POWER GATING SYNTHESIS FOR ACTIVE LEAKAGE REDUCTION - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 10-07-2010 |
| 20100127730 | Internal charge transfer for circuits - The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture. | 05-27-2010 |
| 20080218201 | CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING - A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I | 09-11-2008 |
| 20100097097 | SEMICONDUCTOR DEVICE USING POWER GATING - A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode. | 04-22-2010 |
| 20110163779 | LOW POWER CONSUMPTION MIS SEMICONDUCTOR DEVICE - A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized. | 07-07-2011 |
| 20080218200 | Organic TFT inverter arrangement - An organic TFT (OTFT) inverter arrangement comprises an inverter stage including a series arrangement of first and second MOS OTFTs (T | 09-11-2008 |
| 20120161812 | LOGIC CIRCUIT WITHOUT ENHANCEMENT MODE TRANSISTORS - Embodiments of circuits, methods and systems for powering various stages of a logic circuit are disclosed. Other embodiments may also be described and claimed. | 06-28-2012 |
| 20100219857 | LOW POWER CONSUMPTION MIS SEMICONDUCTOR DEVICE - A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized. | 09-02-2010 |
