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Bus or line termination (e.g., clamping, impedance matching, etc.)

Subclass of:

326 - Electronic digital logic circuitry

326021000 - SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY

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DocumentTitleDate
20130043900ADJUSTABLE DATA DRIVERS AND METHODS FOR DRIVING DATA SIGNALS - Apparatuses and methods for driving input data signals onto signal lines as output data signals are disclosed. An example apparatus includes a detection circuit, a driver adjust circuit, and a data driver. The detection circuit is configured to detect a characteristic(s) of a group of input data signals to be driven onto adjacent signal lines. A characteristic could be, for example, a particular combination of logic levels and/or transitions for, the group of input data signals. The driver adjust circuit is configured to provide a driver adjustment signal based at least in part on a detection signal, that is provided by the detection circuit. A data driver is configured to drive a respective one of the group of input data signals as a respective one of the output data signals, wherein the data driver is adjusted based at least in part on the driver adjustment signal.02-21-2013
20130043901ON-DIE TERMINATION CIRCUIT - An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.02-21-2013
20110187405TRANSCEIVER CIRCUITS - A transceiver circuit supports a bidirectional mode and the bidirectional transceiver circuit is signal-compatible with JEDEC SSTL 2. A differential transceiver circuit supports a bidirectional mode and is also signal-compatible with JEDEC SSTL 2. Finally, transceiver circuits which, in interaction with the bidirectional transceiver circuits, allow a bus system to be set up.08-04-2011
20090267640SYSTEM INCLUDING PREEMPHASIS DRIVER CIRCUIT AND METHOD - A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal and the auxiliary driver.10-29-2009
20100164539SYSTEM AND APPARATUS OF RECONFIGURABLE TRANSCEIVER DESIGN FOR MULTI-MODE SIGNALING - A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.07-01-2010
20090002018Impedance adjusting circuit and semiconductor memory device having the same - An impedance adjusting circuit includes: a first calibration resistor circuit configured to be calibrated with an external resistor and generate a first calibration code; a second calibration resistor circuit configured to be calibrated with the first calibration resistor circuit and generate a second calibration code, the second calibration resistor circuit being connected to a first node; and a transmission line circuit configured to be responsive to a control signal to connect the first node to a pin of a system employing the impedance adjusting circuit.01-01-2009
20080258756Semiconductor apparatus - The on-die termination circuit of the present invention includes a main resistance circuit and an adjustment circuit. The main resistance circuit is provided with a resistance element and a transistor that is turned OFF when the on-die termination circuit is to be placed in the OFF state and turned ON when the on-die termination circuit is to be placed in the ON state. The adjustment circuit is provided with transistors that are both connected together in parallel and connected in parallel to the main resistance circuit, and that are turned ON or OFF when the on-die termination circuit is placed in the ON state so as to adjust the termination resistance of the entire on-die termination circuit.10-23-2008
20110193590SEMICONDUCTOR DEVICE AND CIRCUIT BOARD HAVING THE SEMICONDUCTOR DEVICE MOUNTED THEREON - To provide a semiconductor device including a first replica buffer connected to a calibration terminal, an impedance adjusting circuit that changes an impedance of the first replica buffer according to a comparison result between a potential of the terminal and a reference potential, and an impedance adjusting circuit that changes an impedance of a third replica buffer according to a comparison result between a potential of a connection node of a second replica buffer and the third replica buffer and a potential of the terminal. According to the present invention, both impedances of the first and third replica buffers are adjusted based on the potential of the terminal, and therefore an adjustment error of one of the replica buffers is not superimposed with an adjustment error of the other replica buffer.08-11-2011
20090121742APPARATUS AND METHOD OF CALIBRATING ON-DIE TERMINATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for calibrating on-die termination for a semiconductor integrated circuit includes a comparing unit that compares a code conversion voltage, which is obtained by converting an internal code into an analog voltage, with a reference voltage, and outputs a comparison result signal, a code control unit that compares a current comparison result signal and a previous comparison result signal, among comparison result signals obtained by sequential comparison operations by the comparing unit, to determine whether or not the levels thereof are the same, and outputs an external code update signal according to the comparison result, and a counter that increases or decreases the internal code according to the comparison result signal and outputs the internal code as an external code according to the external code update signal05-14-2009
20090121741SEMICONDUCTOR APPARATUS, ON-DIE TERMINATION CIRCUIT, AND CONTROL METHOD OF THE SAME - An on-die termination circuit of a semiconductor apparatus can include: a code converting unit configured to change a code value of a termination code in response to a termination control signal; and a plurality of on-die termination blocks configured to commonly receive the termination code, and perform a termination operation.05-14-2009
20090121743Digital Method and Device for Transmission with Reduced Crosstalk - The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four parallel transmission conductors plus a reference conductor has each of its ends connected to a termination circuit. The transmitting circuit receives at its input the signals of the four channels of the source and its output terminals are connected to the conductors of the interconnection. The receiving circuit(s) input terminals are connected to the conductors of the interconnection, and its four output channels are connected to the destination. The signals of the four channels of the source are sent to the four channels of the destination, without noticeable crosstalk.05-14-2009
20100073023SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION - Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.03-25-2010
20130033288SEMICONDUCTOR DEVICE - A semiconductor device includes an impedance control signal generation unit configured to generate an impedance control signal for controlling an impedance value, a first processing unit configured to process the impedance control signal in response to a first setup value and generate a first process signal, a first clock termination unit configured to be coupled with a first clock path and determine an impedance value responding to the impedance control signal, and a second clock termination unit configured to be coupled with a second clock path and determine an impedance value responding to the first process signal.02-07-2013
20130033287Balanced Single-Ended Impedance Control - A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor. The impedances of the first and second transistors may be controlled by the first gate control voltage and the second gate control voltage respectively.02-07-2013
20100060316CALIBRATION CIRCUIT, ON DIE TERMINATION DEVICE AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A calibration circuit includes a gain control device configured to adjust a reference voltage to a predetermined level according to a variable gain; and a calibration device configured to update a calibration code by comparing a voltage generated by resistors and the reference voltage adjusted to the predetermined level by the gain control device, wherein the resistors are individually controlled to be turned on by the calibration code.03-11-2010
20100045341Method and Apparatus for High Resolution ZQ Calibration - A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.02-25-2010
20100045340CONTROL CIRCUIT FOR CONTROLLING ON-DIE TERMINATION IMPEDANCE - The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either one of the internal clock signal or the DLL clock signal according to the power mode to output a plurality of delayed clock signals; and an ODT control signal generation circuit which receives an ODT command, and controls the ODT command with the internal clock signal and a plurality of the delayed clock signals to generate and output an ODT control signal. According to the present invention, an ODT control signal for controlling an on-die termination resistor is synchronized with an external clock even during power-down mode, thereby more effectively controlling the ODT control signal.02-25-2010
20100045339 WIRELINE TRANSMISSION CIRCUIT - A wireline transmission circuit includes a first circuit that produces a first variable current, a second circuit that produces a first static current, a trans-impedance amplifier that outputs a first analog signal at a first output node in response to the first variable current and the first static current received at a first input node, and a first feedback resistor connected to the first input node and the first output node.02-25-2010
20100045338Semiconductor device and data processing system including the same - There is provided a semiconductor device that includes: an output buffer capable of adjusting an impedance based on an impedance adjustment signal, and a through-rate control circuit that adjusts a through rate of the output buffer based on at least the impedance adjustment signal, wherein the through-rate control circuit sets a relatively high through rate when the impedance adjustment signal designates a relatively low impedance, and sets a relatively low through rate when the impedance adjustment signal designates a relatively high impedance.02-25-2010
20110309857CIRCUITRY FOR MATCHING THE UP AND DOWN IMPEDANCES OF A VOLTAGE-MODE TRANSMITTER - Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.12-22-2011
20130038346APPARATUS AND METHOD FOR SIGNAL TRANSMISSION OVER A CHANNEL - Apparatus and methods related to data transmission are disclosed. One such apparatus includes a transmitter, a receiver, and a channel. The transmitter includes a pair of current sources and a pair of switches. Each of the switches conducts one of the current sources to the channel in response to input data. The receiver includes a first node configured to receive a signal over the channel. The receiver also includes a resistance generating a voltage drop between the first node and a second node. The receiver further includes a first transistor and a second transistor that are together configured to provide a voltage level to the second node based at least partly on the voltage drop. The resistance provides a negative feedback to center the mean signal level, thereby reducing intersymbol interference.02-14-2013
20090102510CONTROL CIRCUIT FOR CONTROLLING ON-DIE TERMINATION IMPEDANCE - The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either one of the internal clock signal or the DLL clock signal according to the power mode to output a plurality of delayed clock signals; and an ODT control signal generation circuit which receives an ODT command, and controls the ODT command with the internal clock signal and a plurality of the delayed clock signals to generate and output an ODT control signal. According to the present invention, an ODT control signal for controlling an on-die termination resistor is synchronized with an external clock even during power-down mode, thereby more effectively controlling the ODT control signal.04-23-2009
20090115450Circuit and method for controlling termination impedance - A termination impedance control circuit is capable of controlling a dynamic ODT operation in a DDR3-level semiconductor memory device. The termination impedance control circuit includes a counter unit configured to count an external clock and an internal clock to output a first code and a second code, respectively, and a dynamic controller configured to enable a dynamic termination operation by comparing the first code with the second code in response to a write command and disable the dynamic termination operation after a predetermined time, determined according to a burst length, has lapsed after the dynamic termination operation is enabled.05-07-2009
20100066404Reduced Power Differential Type Termination Circuit - A reduced power differential type termination circuit for use in SSTL, HSTL and other transmission line systems reduces power consumption. A differential type termination circuit may comprise first and second nodes for coupling, respectively, to first and second transmission lines; a first impedance coupled between the first transmission line and a third node; a second impedance coupled between the second transmission line and the third node; and a low direct current reference voltage generator for generating a reference voltage applied to the third node. The first and second transmission lines may transmit complimentary signals. The first and second impedances may be symmetric or asymmetric. The first impedance may match the second impedance. The first and second impedances may, respectively, match the impedances of the first and second transmission lines. The first and/or second impedances may include a bidirectional switch, such as a transmission gate, to enable and disable the termination circuit.03-18-2010
20120182044Methods and Systems for Reducing Supply and Termination Noise - Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.07-19-2012
20130049797IMPEDANCE CALIBRATION CIRCUIT AND METHOD - An embodiment of an impedance calibration circuit and method, a device including an impedance calibration circuit, and a transmission link system.02-28-2013
20130049798MOTHERBOARD WITH DUAL NETWORK CARD CONNECTORS AND LOW SIGNAL REFLECTIVITY - An exemplary motherboard includes a controller, and two different network card connectors. At least one of the two network card connectors is electronically connected to the controller via a resistor. A user of the motherboard may choose to use either the first network card connector, or the second network card connector, or the first network card connector and the second network card connector simultaneously.02-28-2013
20130088257SEMICONDUCTOR DEVICE HAVING IMPEDANCE CALIBRATION FUNCTION TO DATA OUTPUT BUFFER AND SEMICONDUCTOR MODULE HAVING THE SAME - Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit.04-11-2013
20100001758CONTROLLING FOR VARIABLE IMPEDANCE AND VOLTAGE IN A MEMORY SYSTEM - A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.01-07-2010
20130069689Method For Operating Memory Device And Apparatuses Performing The Method - According to example embodiments, a method for operating a memory device includes receiving an on-die termination (ODT) signal through an ODT pin, and issuing a command or controlling an ODT circuit according to the ODT signal.03-21-2013
20090146683CALIBRATION CIRCUIT OF ON-DIE TERMINATION DEVICE - A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node and a reference voltage, to generate calibration codes. The calibration unit also includes a calibration resistor unit having parallel resistors which are turned on/off in response to each of the calibration codes and connected to the calibration node, a turn-on strength of at least one of the parallel resistors being controlled by a control signal.06-11-2009
20130088258SEMICONDUCTOR DEVICE INCLUDING OUTPUT CIRCUIT CONSTITUTED OF PLURAL UNIT BUFFER CIRCUITS IN WHICH IMPEDANCE THEREOF ARE ADJUSTABLE - The semiconductor device comprises an output circuit that includes a plurality of unit buffer circuits each of which has an adjustable impedance, a control circuit that selectively activates one or ones of the unit buffer circuits, and an impedance adjustment unit that adjusts the impedances of the unit buffer circuits and includes a power line, a replica circuit, which has a replica impedance that is substantially equal to the adjustable impedance of each of the unit buffer circuits, and a load current generation circuit, which changes current flowing therethrough in accordance with the number of activated the one or ones of the unit buffer circuits. The replica circuit and the load current generation circuit are connected in common to the power line.04-11-2013
20120217992OUTPUT CIRCUIT FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE HAVING OUTPUT CIRCUIT, AND METHOD OF ADJUSTING CHARACTERISTICS OF OUTPUT CIRCUIT - To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.08-30-2012
20120217991IMPEDANCE CONTROL CIRCUIT AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME - A circuit, including a first impedance unit having an impedance value based on a first impedance code and configured to drive a first node coupled with a resistor with a first voltage, a first code generation unit configured to generate the first impedance code so that an impedance value of the first impedance unit and an impedance value of the resistor are at a ratio of X:Y, dummy impedance units that receive the first impedance code and drive a second node with the first voltage, a second impedance unit having an impedance value based on a second impedance code and configured to drive the second node with a second voltage, and a second code generation unit configured to generate the second impedance code so that an overall impedance value of the dummy impedance units and an impedance value of the second impedance unit are at a ratio of X:Y08-30-2012
20120217990TERMINATION CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - The semiconductor device includes a termination control unit configured to generate a termination enable signal and termination resistance information in response to termination activation information, dynamic activation information, normal resistance information, and dynamic resistance information wherein the termination enable signal is activated when a delay lock loop is inactivated, and a termination unit configured to be controlled in response to the termination enable signal and terminate an interface pad by using a resistance value determined by the termination resistance information.08-30-2012
20090039914SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION - A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.02-12-2009
20090039913SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.02-12-2009
20090091350METHOD AND CIRCUIT FOR OFF CHIP DRIVER CONTROL, AND MEMORY DEVICE USING SAME - An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.04-09-2009
20090267642METHOD AND APPARATUS FOR OUTPUT DRIVER CALIBRATION, AND MEMORY DEVICES AND SYSTEM EMBODYING SAME - A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration circuit includes a pull-up calibration circuit configured to generate an averaged pull-up count signal for calibrating p-channel devices in the output driver with the averaged pull-up count signal being an average of a plurality of pull-up count signals. The calibration circuit further includes a pull-down calibration circuit configured to generate an averaged pull-down count signal for calibrating n-channel devices in the output driver with the averaged pull-down count signal being an average of a plurality of pull-down count signals.10-29-2009
20090267641I/O Driver For Integrated Circuit With Output Impedance Control - An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.10-29-2009
20090267639INPUT CANCELLATION CIRCUIT - A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein both paths substantially match in resistance. In another embodiment, a differential signal is substantially cancelled by a pseudo differential arrangement including two independent input resistance paths each in parallel with a corresponding negative resistance path, wherein the resistance paths substantially match the input resistance paths. In yet another embodiment, a differential signal is substantially cancelled by a differential arrangement including two resistance paths wherein a first negative resistance path is coupled between the first differential input and the second differential output and the second negative resistance path is coupled between the second input and the first output. In yet another embodiment, a current controlled current source may provide the negative amplification for the negative resistance path.10-29-2009
20120223736TRANSCEIVING CIRCUIT AND TRANSCEIVING CIRCUIT RESISTANCE CALIBRATION METHOD - A transceiving circuit resistance calibrating method, which is applied to a transceiving circuit. The method includes: inputting a first current to a transmitter to generate a first output voltage, wherein the first current is generated according to a ratio between a predetermined voltage and an inner resistor of a chip; inputting a second current to a transmitter to generate a second output voltage, wherein the first current is generated according to a ratio between the predetermined voltage and a predetermined resistor; and adjusting a first adjustable resistance module according to a difference between the first output voltage and the second output voltage.09-06-2012
20120194215SEMICONDUCTOR APPARATUS AND IMPEDANCE CALIBRATION CIRCUIT FOR THE SAME - A semiconductor apparatus includes a data input/output circuit and an impedance calibration circuit. The impedance calibration circuit may be configured to output a code signal for controlling a resistance value of the data input/output circuit in response to a division voltage applied to a joining interconnection directly coupled to a ZQ pad and a preset reference voltage.08-02-2012
20130162288TERMINATION CIRCUIT - A termination circuit includes: a pull-up termination unit configured to pull-up terminate an interface node in response to a pull-up signal; a pull-down termination unit configured to pull-down terminate the interface node in response to a pull-down signal; one or more pull-up resistors connected to the interface node and enabled to affect termination resistance in response to a pull-up setting value when a termination signal is activated; and one or more pull-down resistors connected to the interface node and enabled to affect termination resistance in response to a pull-down setting value when the termination signal is activated.06-27-2013
20090237109Efficient method for implementing programmable impedance output drivers and programmable input on die termination on a bi-directional data bus - A combined input and termination circuit comprises a fixed portion of impedance and a programmable portion of impedance. The fixed portion is able to be fixed in a driver mode and a termination mode. The programmable portion is able to be configured to have a desired impedance in a driver mode or a termination mode while maintaining minimum associated capacitance.09-24-2009
20090009213Calibration circuit, semiconductor device including the same, and data processing system - A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impedance adjustments of the replica buffers; and a 32 tCK cycle counter that forcibly activates the latch circuits in response to a lapse of a predetermined period since issuance of the calibration command. Thereby, even when the adjustment is not completed during one calibration period, a subsequent calibration operation can be executed from a previous point.01-08-2009
20090009212Calibration system and method - A system and method to calibrate an output driver impedance of an output driver based on a termination device of a controller.01-08-2009
20120235704Redriver with Output Receiver Detection that Mirrors Detected Termination on Output to Input - A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.09-20-2012
20130162287SEMICONDUCTOR PACKAGE INCLUDING MULTIPLE CHIPS AND MEMORY SYSTEM HAVING THE SAME - A package includes a master chip including a storage circuit configured to store an impedance setting of the master chip and an impedance setting of a slave chip, and a termination circuit for an impedance matching with an outside of the package, and the slave chip connected to the master chip, wherein if a termination operation for the slave chip is activated, the termination circuit of the master chip performs an impedance matching operation using the impedance setting for the slave chip.06-27-2013
20120268161Termination device and system and method for termination for an alarm system peripheral device - A termination device and a system and a method terminate a peripheral device of an alarm system. The termination device connects to wiring extending from the peripheral device. The termination device may have a resistor, a diode and/or a similar component which provides electrical resistance. The termination device may have a potentiometer which may enable a user to adjust the electrical resistance. The termination device may have a blade which cuts the wiring.10-25-2012
20110025373Semiconductor devices having ZQ calibration circuits and calibration methods thereof - Provided is a semiconductor device for performing a calibration operation without an external ZQ calibration command and a calibration method thereof. The semiconductor device includes a calibration circuit for performing a pull-down calibration operation in response to a pull-down calibration enable signal and a command control unit for generating the pull-down calibration enable signal in response to a DLL reset signal. The calibration method includes adjusting an impedance of a first pull-up resistance structure in response to pull-up calibration codes having a default value. A pull-down calibration enable signal may be generated in response to a DLL reset signal. A voltage of the first node and a reference voltage are compared by a comparator. The comparator outputs pull-down calibration codes based on the comparison. An impedance of a pull-down resistance structure is adjusted, so a resistance of the pull-down resistance structure is equal to a resistance of the first pull-up resistance structure.02-03-2011
20110187406Semiconductor Chip And Semiconductor Module Including The Semiconductor Chip - A semiconductor chip including a termination resistance and a semiconductor module including the semiconductor chip. The semiconductor chip comprising a plurality of memory cells, the semiconductor chip including: at least one first center pads disposed on a center region of the semiconductor chip and connected to the plurality of memory cells; at least one first edge pads disposed on an edge region of the semiconductor chip and connected to a first transmission line of a semiconductor module; at least one second edge pads disposed on the edge region of the semiconductor chip and connected to a chipset voltage application unit of the semiconductor module; at least one first redistribution patterns connected between the at least one first center pads and the at least one first edge pads; and at least one second redistribution patterns connected between the at least one first edge pads and the at least one second edge pads, wherein an impedance of the at least one second redistribution patterns is impedance matched to an impedance of the first transmission line.08-04-2011
20110128040SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION - Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.06-02-2011
20110128039SEMICONDUCTOR CIRCUIT - A semiconductor circuit includes a pad, a pad driver connected to the pad at an output terminal thereof and configured to calibrate a voltage of the pad in response to code signals, a comparison section configured to compare a reference voltage and the voltage of the pad and generate a comparison signal, and a code generation section configured to calibrate code values of the code signals in response to the comparison signal.06-02-2011
20110291700SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes an impedance control signal generation block configured to transmit first impedance control signals and second impedance control signals through same signal lines at predetermined time intervals, and input/output blocks configured to separately receive the first impedance control signals and the second impedance control signals at corresponding time intervals and perform a data input/output operation based on set impedance.12-01-2011
20110291698IMPEDANCE ADJUSTING DEVICE - An impedance adjusting device includes a calibration unit configured to generate an impedance code for adjusting a termination impedance value, a plurality of termination units configured to be enabled by resistance selection information and terminate an interface node in response to the impedance code, a resistance providing unit coupled in parallel to the plurality of termination units and configured to provide a resistance in response to the resistance selection information, and a selection signal generation unit configured to generate the resistance selection information according to a target impedance value.12-01-2011
20110291699IMPEDANCE CODE GENERATION CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD FOR SETTING TERMINATION IMPEDANCE - An impedance code generation circuit includes a first code generation unit configured to compare a voltage of a calibration node with a reference voltage and generate a first impedance code, a code modification unit configured to generate a modified impedance code by performing an operation on the first impedance code according to a setting value, and a second code generation unit configured to generate a second impedance code based on the modified impedance code.12-01-2011
20090128185On-die termination circuit and driving method thereof - An on-die termination circuit is capable of increasing a resolution without enlargement of a chip or a layout size. The on-die termination circuit includes a control means, a termination resistance supply means, a code signal generating means. The control means sequentially generates a plurality of control signals in a response to a driving signal. The termination resistance supply means supplies a termination resistance in response to a coarse code signal having a plurality of bits and a fine code signal having a plurality of bits. The code signal generating means controls the fine code signal and the coarse code signal in response to the plurality of the control signals in order that the termination resistance has a level which is correspondent to an input resistance.05-21-2009
20110215831LOW POWER TELEMETRY SYSTEM AND METHOD - A telemetry system is described in which a plurality of channels are coupled to a bus. A control subsystem controls the channels so that one of the channels presents to the bus during its designated time period a channel characteristic. The control subsystem interrogates in the analog domain each of the channels during its designated time period, and forms a signal representative of the channel characteristic. The control subsystem may combine one or more of the signals into a digital packet, and transmit the same over a network. Each channel in the telemetry system can include a sample-and-hold circuit, a variable resistor circuit, and a control element. The sample-and-hold circuit is configured to hold a sample of a signal. The variable resistor circuit is configured to present a variable impedance to one or more signal lines during a time period designated for the channel an impedance representative of the sample held by the sample-and-hold circuit. The control element is configured to control the variable resistor circuit to present to the one or more signal lines an open circuit equivalent impedance during times other than the time period designated for the channel. In some implementations, the channel also includes a switch which decouples the sample-and-hold circuit from the variable resistor circuit during times other than the time period designated for the channel. In some implementations, the control element is a programmable control element that is programmable with a unique channel identifier, and may include a timing element which is updated responsive to a control signal. The programmable control element determines that the designated time period for the channel is occurring or will occur based on a comparison of the contents of the timing element with the unique channel identifier. The control element can be a zero power control element.09-08-2011
20110215830OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD - An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.09-08-2011
20090121740Audio/Video Router - Technique for Routing digital audio and digital video signals commences by routing a digital video signal, devoid of embedded digital audio, to at least one output, typically by way of a video cross-point switch. At least one digital audio signal undergoes buffering to obtain a prescribed amount of data prior re-timing of the digital audio signal to a prescribed timing format. Following buffering and re-timing, the digital audio signal undergoes routing to at least one output, typically by way of an audio cross-point switch. When routed to outputs associated with each other, the digital audio signal undergoes embedding in the digital video.05-14-2009
20090153186On-die-termination control circuit and method - On-die-termination control circuit includes a clock generator configured to generate shift clocks in response to an on/off control signal; and a shift register configured to delay the on/off control signal in synchronization with the shift clocks to control on/off timing of an ODT operation.06-18-2009
20090146684CIRCUIT FOR CONTROLLING DRIVER OF SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - A circuit for controlling a driver of a semiconductor memory apparatus includes a driving unit having an impedance that is set according to a code value; a driving reinforcing control unit configured to output an adjustment code for a predetermined time; and a driving reinforcing unit configured to output a reinforcing code obtained by adjusting the code value using the adjustment code, wherein the reinforcing code reinforce a driving capability of the driving unit.06-11-2009
20090002019APPARATUS FOR ADJUSTING RESISTANCE VALUE OF A DRIVER IN A SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for adjusting a resistance value of a driver of a semiconductor integrated circuit in which the resistance value of the driver is adjusted according to a code signal. The apparatus includes a control means that generates a plurality of counting mode signals such that the unit of counting is changed in a predetermined period, a counting means that counts the code signal in the unit of counting that is changed in response to the plurality of counting mode signals, according to a count up/down signal, and a comparing means that compares a voltage obtained by converting the code signal with a reference voltage to generate the count up/down signal.01-01-2009
20110193591Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.08-11-2011
20100007373IMPEDANCE MATCHING LOGIC - An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e.g., due to layout mismatch).01-14-2010
20090309628SEMICONDUCTOR MEMORY DEVICE AND ON-DIE TERMINATION CIRCUIT - An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a termination resistance in response to the ODT drive signals of a corresponding drive signal generator. The drive signal generators are configured to supply the ODT drive signals to the ODT drive units to output a plurality of ODT control signals through the terminals in a test mode.12-17-2009
20110062985SEMICONDUCTOR DEVICE - The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the code generator, code signals for adjusting resistance are adjusted in accordance with the detection result. The resistance value of each of the resistance adjusters is adjusted to an external resistor. Further, by code signals with which the resistance value of each of the resistance adjusters is adjusted to the resistance value of the external resistor, the resistance of the resistance value of an output buffer is adjusted.03-17-2011
20110062984Semiconductor device having plural unit buffers constituting output buffer - To include an output terminal, unit buffers, and plural output-wiring paths that respectively connect the unit buffers and the output terminal. The output wiring paths have individual output wiring sections individually allocated to corresponding unit buffers. Unit buffers corresponding to these output wiring paths are common output wiring sections shared by the output wiring paths, and are connected to the output terminal without via a common output wiring section having a higher resistance value than those of the individual output wiring sections. Accordingly, an deviation of impedance due to a parasitic resistance between the output terminal and the unit buffers is suppressed.03-17-2011
20090273364CALIBRATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE CALIBRATION CIRCUIT - Calibration circuit, semiconductor memory device including the same, and operation method of the calibration circuit includes a calibration unit configured to generate a calibration code for controlling a termination resistance value, a calibration control unit configured to count a clock and allow the calibration unit to be enabled during a predetermined clock and a clock control unit configured to selectively supply the clock to the calibration control unit according to an operation mode of a semiconductor device employing the calibration circuit.11-05-2009
20090091349High speed multiple memory interface I/O cell - An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.04-09-2009
20100097094Output circuit having variable output voltage swing level - An output circuit having a variable swing level of a terminated output data signal is disclosed. The output circuit includes a control circuit configured to generate a first control signal and a second control signal in response to a voltage swing level selection signal and an output enable signal. The output circuit further includes an output driving circuit configured to, in response to the first and second control signals, perform on-die termination in an input mode and configured to control swing level of a signal output from the output circuit in an output mode.04-22-2010
20110169523ADAPTIVE TERMINATION - A system for receiving data is provided. Too system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used for dynamically controlling ringing in the inductive data device, such as by damping ringing signals generated by circuit inductances or capacitances.07-14-2011
20080211534IMPEDANCE MATCHING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME - An impedance matching circuit of a semiconductor memory device performs a ZQ calibration with initial values that reflect an offset error according to variations in a manufacturing process. The impedance matching circuit includes a first pull-down resistance unit, a first pull-up resistance unit, and a code generation unit. The first pull-down resistance unit supplies a ground voltage to a first node, thereby determining an initial pull-down code. The first pull-up resistance unit supplies a supply voltage to the first node, thereby determining an initial pull-up code or a voltage level on the first node. The code generation unit generates pull-down and pull-up calibration codes using the initial pull-down and pull-up codes as respective initial values.09-04-2008
20080211533IMPEDANCE MATCHING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME - An impedance matching circuit includes a code generating unit for generating a calibration code in response to a reference voltage and a voltage on a node, a calibration resistance unit for supplying a power supply voltage to the node, being calibrated to an external resistor, wherein the calibration resistance unit includes a switching unit for turning on/off a plurality of resistors connected in parallel in response to the calibration code, a termination pull-up resistance unit provided at an output node for receiving the calibration code, wherein the termination pull-up resistance unit has a switching unit which is identical to that of the calibration resistance unit, and a termination pull-down resistance unit at the output node, for receiving the calibration code, wherein the termination pull-down resistance unit has a switching unit which is identical to that of the calibration resistance unit.09-04-2008
20090289658IMPEDANCE CALIBRATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE WITH THE IMPEDANCE CALIBRATION CIRCUIT AND LAYOUT METHOD OF INTERNAL RESISTANCE IN THE IMPEDANCE CALIBRATION CIRCUIT - An impedance calibration circuit for impedance matching between a semiconductor memory device and an external device includes a driving circuit and a comparing circuit. The driving circuit has a plurality of internal resistances, with one or more of the internal resistances being a variable resistance. The driving circuit compares the impedance of the internal resistances to the input/output impedance of the external device in order to provide a calibration voltage. The comparing circuit compares the calibration voltage to a reference voltage and provides a code signal for calibrating the impedance corresponding to output data with the input/output impedance of the external device. The impedance calibration circuit calibrates an impedance mismatch between the impedance calibration circuit and a data input/output driver by adjusting the impedance of the impedance calibration circuit through the variable resistance.11-26-2009
20090284281MEMORY-MODULE BUFFER WITH ON-DIE TERMINATION - In memory module having multiple data inputs to couple to signal lines of an external data path, multiple memory integrated-circuits (ICs) and a buffer IC, the buffer IC includes respective interfaces coupled to the data inputs and the memory ICs, a first termination circuit having a first load element and a first switch element to switchably couple the first load element to a first data input of the data inputs and a second termination circuit having a second load element and a second switch element to switchably couple the second load element to the first data input. The buffer IC further includes a configuration circuit to store, in response to control information from a memory controller, a first digital value and a second digital value, the first digital value being supplied to the first termination circuit to control an impedance of the first load element and the second digital value being supplied to the second termination circuit to control an impedance of the second load element.11-19-2009
20090289659Calibration circuit - In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK11-26-2009
20090295426DYNAMICALLY ADJUSTING OPERATION OF A CIRCUIT WITHIN A SEMICONDUCTOR DEVICE - Apparatus including a reference circuit configured to provide a particular impedance and having a first plurality of switching devices and a resistive device coupled to each other in parallel; a second plurality of switching devices coupled to each other in parallel and coupled in series with the reference circuit between a supply node and a supply return node; and processing logic coupled to the second plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the second plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance of the reference circuit than at least one other combination of enabled and disabled switching devices of the second plurality of switching devices.12-03-2009
20090261856CIRCUIT AND METHOD FOR CONTROLLING TERMINATION IMPEDANCE - A calibration circuit that can prevent a calibration operation from being delayed by a dummy capacitor when the calibration circuit starts to operate includes a switch unit configured to connect a calibration node to a precharge node in response to an enable signal. The calibration node is connected to an external resistor. The calibration circuit also includes a code generation unit configured to generate a calibration code in response to a voltage of the calibration node and a reference voltage, a calibration resistor unit configured to drive the calibration node in response to the calibration code and turn-off when the code generation unit is disabled, and a precharge unit configured to precharge the precharge node to a predetermined voltage level when the code generation unit is disabled.10-22-2009
20130099818METHODS AND APPARATUSES INCLUDING AN ADJUSTABLE TERMINATION IMPEDANCE RATIO - Methods of adjusting a centerline voltage of a data signal are described, along with apparatuses to adjust the centerline voltage. In one such method, portions of a termination circuit coupled to a node are selectively programmed to adjust an impedance of the termination circuit to adjust the centerline voltage of the data signal driven to the node. One such apparatus includes pull-up impedances and pull-down impedances that can be programmed to adjust the centerline voltage of the data signal. Additional embodiments are also described.04-25-2013
20110267099Semiconductor device generating complementary output signals - To include a first inverter that receives an input signal to output an inverted signal, a second inverter that receives the inverted signal to output a first internal signal, and a third inverter that receives the input signal and outputs a second internal signal by using the inverted signal as a power supply. According to the present invention, because a signal on one signal path is used as a power supply of an inverter included in the other signal path, phases of a pair of output signals based on the input signal can be exactly matched without adding a capacitor or a resistor for adjustment.11-03-2011
20080297193Techniques for Providing Calibrated On-Chip Termination Impedance - Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.12-04-2008
20080278192DATA OUTPUT DRIVING CIRCUIT FOR A SEMICONDUCTOR APPARATUS - A data output driving circuit for a semiconductor apparatus includes a code converter that varies an input on-die termination code according to a control signal and outputs the code, and a driver block having impedance which can be modified according to the code generated by the code converter.11-13-2008
20080284465On-die system and method for controlling termination impedance of memory device data bus terminals - A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.11-20-2008
20080284467On die termination circuit and method for calibrating the same - On die termination circuit and method for calibrating the same includes a external resistor connected to a first node, a plurality of calibration resistors connected to a second node, the plurality of calibration resistors being turned on/off in response to a calibration code set, a current mirror configured to mirror currents of the first node and the second node and a code generator configured to generate a calibration code set according to the mirrored currents. In accordance with a method for calibrating an on die termination circuit of the present invention, the method includes a step of mirroring a current of a first node connected to an external resistor and a current of a second node connected to a plurality of calibration resistors and a step of generating a calibration code set according to the mirrored currents.11-20-2008
20080303546DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS - A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.12-11-2008
20100201397TERMINATION CIRCUIT FOR ON-DIE TERMINATION - In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.08-12-2010
20110267098SEMICONDUCTOR DEVICE, MEMORY SYSTEM, AND METHOD FOR CONTROLLING TERMINATION OF THE SAME - A semiconductor device includes a plurality of first input units configured to receive a command, a second input unit configured to receive a termination command, a termination control unit configured to be enabled by the termination command and decode the command to control a termination operation, and a termination unit configured to be controlled by the termination control unit and terminate an interface pad.11-03-2011
20080284466Driver Circuit - A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.11-20-2008
20080315916CONTROLLING MEMORY DEVICES THAT HAVE ON-DIE TERMINATION - A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circuit memory devices coupled to the data line. The termination control signals control coupling and decoupling of termination elements to the data line according to which of the plurality of integrated circuit memory devices is selected to receive the first data signal. In particular, the termination control signals specify coupling a termination element having an impedance indicated by a first termination value to the data line within one of the plurality of integrated circuit memory devices selected to receive the first data signal, and wherein the termination control signals further specify coupling a termination element having an impedance indicated by a second termination value to the data line within at least one other of the plurality of integrated circuit memory devices.12-25-2008
20100007374ON-DIE THEVENIN TERMINATION FOR HIGH SPEED I/O INTERFACE - The method, system, and apparatus of on-die Thevenin termination for high speed I/O interface are disclosed. In one embodiment, a system of terminating a transmission line of a chip includes a pull-up circuit located within the chip comprising a voltage source and a positive switch device coupled with the transmission line of the chip, a pull-down circuit located within the chip comprising a ground and a negative switch device coupled with the transmission line of the chip, a resistor located within the chip coupled with the voltage source, the positive switch device, the ground, the negative switch device, and a pad coupled with the resistor to terminate the transmission line of the chip. The system may include resistors coupled in parallel with each other. The system may include an impedance module to determine a load impedance value as seen from the pad that matches a source impedance value.01-14-2010
20080315914Data transmission device and method thereof - A data transmission device may include a transmission chip, a plurality of reception chips and/or a pair of transmission lines. The transmission chip may transmit data and the reception chips may receive the data from the transmission chip. One of the plurality of reception chips may provide a corresponding terminal resistance when it receives the data. The transmission lines may be coupled between the transmission chip and the reception chips, and the transmission lines may have a daisy-chain configuration. Therefore, a data transmission device may provide a fixed terminal resistance in impedance matching and increase a transmission speed.12-25-2008
20080272800Dynamic dual control on-die termination - Controlling on-die termination on a bi-directional single-ended data bus carrying data between a controller and a memory device. The controller and the memory device respectively include input termination pull-ups and input termination pull-downs. An enabled state is maintained for the input termination pull-downs of the controller except when data is driven on the bi-directional single ended data bus by the controller. Similarly, an enabled state is maintained for the set of input termination pull-downs of the memory device except when data is driven on the bi-directional single ended data bus by the memory device. In conjunction with this, a disabled state is maintained for the input termination pull-ups of the memory device (or controller) except when data is being received from the bi-directional single-ended data bus by the memory device (or controller).11-06-2008
20100264954RECEIVE CIRCUIT FOR CONNECTORS WITH VARIABLE COMPLEX IMPEDANCE - Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance (which can be conductive, capacitive or both), a system that includes the circuit, and a communication technique are described. This inter-chip connection may be formed between a microspring or an anisotropic film and a metal connector on or proximate to a surface of a chip. Moreover, the circuit may mitigate signal distortion associated with the variable complex impedance. For example, the circuit may include an internal impedance that is electrically coupled in series with the metal connector, and that has an impedance which dominates the variable complex impedance over a range of operating frequencies. Separately or additionally, the circuit may be adapted to correct for the signal distortion.10-21-2010
20080211536Driver calibration methods and circuits - Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.09-04-2008
20110267101CONTROLLING DYNAMIC SELECTION OF ON-DIE TERMINATION - A control component outputs to an integrated circuit device an indication to apply one of a plurality of controllable termination impedance configurations at a data input of the integrated circuit device. The indication causes the integrated circuit device to apply a first of the controllable termination impedance configurations at the data input during a first internal state of the integrated circuit device corresponding to the reception of write data on the data input, and causes the integrated circuit device to apply a second of the controllable termination impedance configurations at the data input during a second internal state of the integrated circuit device that follows the first internal state.11-03-2011
20110006804CIRCUIT FOR CONTROLLING DATA COMMUNICATION WITH SYNCHRONOUS STORAGE CIRCUITRY AND METHOD OF OPERATION - A method and circuit includes providing at least one conductor for receiving an input signal. A termination circuit and a clamp circuit are coupled to the at least one conductor. The termination circuit is enabled while the clamp circuit remains enabled. The clamp circuit is disabled. After disabling the clamp circuit, while the termination circuit remains enabled, both a first differential comparator and a second differential comparator are enabled. The first differential comparator receives a first differential input signal at a first input and a second differential input signal at a second input. The second differential comparator detects when a difference between the first differential input signal and the second differential input signal is greater than a predetermined value and enables transfer of an output of the first differential comparator to a memory controller.01-13-2011
20120105100IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - An impedance calibration circuit includes: a first calibration unit configured to compare a first converted voltage obtained by converting a first calibration signal with a reference voltage and vary the first calibration signal; a voltage detection unit configured to activate a voltage detection signal according to a level of a power supply voltage; a multiplexing unit configured to select and output the reference voltage or the first converted voltage in response to the detection signal; and a second calibration unit configured to compare a second converted voltage obtained by converting a second calibration signal with the level of the output signal of the multiplexing unit and vary the second calibration signal.05-03-2012
20130214812IMPEDANCE TUNING CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - An impedance tuning circuit includes a calibration unit and a post-processing unit. The calibration unit generates an initial pull-up code and an initial pull-down code by performing a calibration operation using an external resistor during an initial impedance tuning operation. The post-processing unit outputs the initial pull-up code and the initial pull-down code as a final pull-up code and a final pull-down code during the initial impedance tuning operation, and generates the final pull-up code and the final pull-down code by using the initial pull-up code and the initial pull-down code during a subsequent impedance tuning operation.08-22-2013
20130120020ADAPTIVE OUTPUT SWING DRIVER - An adjustable gain line driver receives an input signal and a gain control signal and outputs a signal with a swing, and the swing is measured to generate a swing measurement signal. A target swing signal is generated having a target swing, and the target swing signal is measured to generate a target swing reference signal. The swing measurement signal is compared to the target swing reference control signal and a counter generating the gain control signal is incremented until the measurement signal meets the target swing reference signal. Optionally a reset signal resets the counter, and the gain control signal, at predetermined events.05-16-2013
20090160480Termination circuit - In order to prevent malfunction due to fluctuations in signal level, a terminating resistor circuit includes terminating resistors the connections whereof to an input/output terminal are capable of being turned on and off, whereby a Thevenin termination is formed. A control circuit exercises control so as to temporally stagger on/off timings of respective ones of the terminating resistors.06-25-2009
20090160479Transceiver Having an Adjustable Terminating Network for a Control Device - In a transceiver for a control unit having a transceiver core for adapting the level of messages received or to be sent, an adjustable terminating network is situated in the transceiver that makes it possible to adjust at least two connection resistance values, the terminating network and the transceiver core being monolithically integrated in a semiconductor circuit.06-25-2009
20090140766Signal transmission circuit and characteristic adjustment method thereof, memory module, and manufacturing method of circuit board - A signal transmission circuit comprising: first and second transmission lines connected to each other; a first impedance storage circuit storing an impedance of the first transmission line; and a control circuit that outputs match information between an impedance of the second transmission line and the impedance stored in the first impedance storage circuit.06-04-2009
20090140765On-Die Terminators Formed of Coarse and Fine Resistors - An integrated circuit includes a semiconductor substrate; a first node; a second node; and a first plurality of resistors, each in a first plurality of resistor units. Each of the first plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The integrated circuit further includes a second plurality of resistors, each in a second plurality of resistor units. Each of the second plurality of resistor units includes a first end connected to the first node, and a second end connected to the second node. The first plurality of resistors is formed of a first material. The second plurality of resistors is formed of a second material different from the first material. The integrated circuit further includes a switch in one of the first and the second plurality of resistor units and serially connected to a resistor.06-04-2009
20100259295Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.10-14-2010
20100259294ON-DIE TERMINATION LATENCY CLOCK CONTROL CIRCUIT AND METHOD OF CONTROLLING THE ON-DIE TERMINATION LATENCY CLOCK - A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.10-14-2010
20090015290ON-DIE TERMINATION DEVICE TO COMPENSATE FOR A CHANGE IN AN EXTERNAL VOLTAGE - An on-die termination (ODT) control in a semiconductor memory device compensates for a change in an external voltage. The on-die termination device includes a voltage comparator that compares an external voltage to a set internal reference voltage. The compared values are sent to a controller that controls an on-die termination impedance value according to the output signal from the voltage comparator. Based on the output of the controller, the present invention spontaneously controls an on-die termination resistance value according to the change in the external voltage without degrading device characteristics during high-speed operation.01-15-2009
20090085604MULTIPLE ADDRESS OUTPUTS FOR PROGRAMMING THE MEMORY REGISTER SET DIFFERENTLY FOR DIFFERENT DRAM DEVICES - A method, device, and system are disclosed. In one embodiment, the method includes programming a first On Die Termination (ODT) value into a first plurality of dynamic random access memory (DRAM) devices. The first plurality of DRAM devices are located on a dual inline memory module (DIMM). Additionally, the method also includes programming a second ODT value into a second plurality of additional DRAM devices. The second plurality of additional DRAM devices are also located on the DIMM. The method also specifies that the first and second ODT values are not the same value.04-02-2009
20090015289SIGNAL TRANSMITTING DEVICE SUITED TO FAST SIGNAL TRANSMISSION - A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.01-15-2009
20090201047Output Impedance Calibration Circuit with Multiple Output Driver Models - A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area on the integrated circuit are defined as a group, and an output model indicative of the operation of the output drivers and used to calibrate their output impedances is provided proximate to the output drivers. A state machine is used to query each output model, and to set the proper output enable signals for the enable transistors in the output drivers in each group so as to calibrate their output impedances. By decentralizing the output models, the process used to form the output models will, due to proximity to the output drivers in each group, be indicative of the process used to form the output drivers. Thus, when each group of output drivers is calibrated, the output models used for each will compensate for process variations as may occur across the surface of the integrated circuit. Each group of output drivers is thus separately calibrated, with the result that the output impedances are made more uniform across the various output drivers despite process variations.08-13-2009
20110128041Integrated Circuit With Configurable On-Die Termination - Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.06-02-2011
20090212816Impedance adjustment circuit - Disclosed is an impedance adjustment circuit including a comparator and a resistor control circuit. The comparator compares the resistance value of an external resistor and that of a replica resistor that forms a replica of a terminal resistor. The resistor control circuit includes a replica resistor control counter, a resistor-under-adjustment control signal holding circuit and a monitor circuit. The replica resistor control counter counts up and down based on the comparison result by the comparator to output a control signal to the replica resistor. The resistor-under-adjustment control signal holding circuit holds a control signal that is delivered to the terminal resistor. The monitor circuit receives the state of the counter and an output of the retention circuit and, in case the difference between the count state of the replica resistor control counter and an output of the resistor-under-adjustment control signal holding circuit is within a preset range, delivers the output of the resistor-under-adjustment control signal holding circuit as an input to the resistor-under-adjustment control signal holding circuit.08-27-2009
20090102511Semiconductor device and driver control method - A semiconductor device of the invention has a plurality of P-channel transistors, to which resistance elements are inserted in series, prepared on a pull-up side of a driver such that an ON resistance value on the P-channel transistor side and a resistance value of the resistance element can be selected. In addition, also on a pull-down side of the driver, a plurality of N-channel transistors to which resistance elements are inserted in series are prepared such that an ON resistance value on the N-channel transistor side and a resistance value of the resistance element can be selected. A driver section having a linear current-voltage characteristic is realized by combination of those described.04-23-2009
20090256586SEMICONDUCTOR DEVICE AND IMPEDANCE ADJUSTMENT METHOD OF THE SAME - A 4-bit counter outputs a 4-bit counted value CNTp based on an up-and-down signal Sp supplied from a comparator. A weighting selection circuit performs weighting based on a deviation from an average value of the DC characteristic of each PMOS transistor, and assigns a transistor having the smallest deviation to Bit 10-15-2009
20090256585DATA LINE TERMINATION CIRCUIT - A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.10-15-2009
20090256587SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the command input port based on the detection result.10-15-2009
20100156455IMPEDANCE CALIBRATION PERIOD SETTING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - An impedance calibration period setting circuit includes a command decoder and an impedance calibration activation signal generator. The command decoder combines external signals to generate a refresh signal. The impedance calibration activation signal generator is configured to generate an impedance calibration activation signal in response to the refresh signal and an address signal. The impedance calibration period setting circuit prevents abnormal changes in an impedance calibration code and reduces current consumption.06-24-2010
20100188116IMPEDANCE ADJUSTING CIRCUIT - An impedance adjusting circuit that includes an external terminal to which an external resistor is connected, a first transistor array of a first conductivity type that is connected in parallel between the external terminal and a first power supply terminal and changes a voltage of the external terminal by adjusting an impedance in response to a first control signal, a second transistor array of a second conductivity type that is connected in parallel between the external terminal and a second power supply terminal and changes the voltage of the external terminal by adjusting the impedance in response to a second control signal, and a control circuit that specifies the first control signal according to a comparison result between the voltage of the external terminal and a reference voltage and specifies the second control signal in a different period from a period to specify the first control signal.07-29-2010
20080315915Semiconductor device - When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of a dummy buffer circuit. A counter counts a clock signal until a comparison result of the comparison circuit matches. The dummy buffer circuit adjusts output impedance corresponding respectively to the output buffer circuits based on a count value of the counter. Adjustment value holders hold respective count values when a comparison result of the comparison circuit, obtained based on respective corresponding reference voltages, matches. The output buffer circuits respectively adjust output impedances based on respectively held count values.12-25-2008
20090045835Signal output circuit, optical pickup and optical device - Disclosed herein is a signal output circuit for outputting a signal onto a transmission line having a given transmission characteristic, the signal output circuit including a drive circuit adapted to drive an input signal by a current; and an output resistor which is connected to an output stage of the drive circuit and capable of adjusting the output signal waveform according to its resistance, wherein the drive current of the drive circuit and the resistance of the output resistor are variable.02-19-2009
20100237902SEMICONDUCTOR DEVICE CAPABLE OF TESTING A TRANSMISSION LINE FOR AN IMPEDANCE CALIBRATION CODE - A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode.09-23-2010
20100148817Reduced power output buffer - A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.06-17-2010
20100237903Configurable On-Die Termination - Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.09-23-2010
20100237901SEMICONDUCTOR APPARATUS AND DATA OUTPUT METHOD OF THE SAME - A semiconductor apparatus includes a driving control unit configured to receive an enable signal and a data signal. The driving control unit generates a pull-up source signal and a pull-down source signal. The driving control unit is configured to delay the generation timing of the pull-up source signal or the pull-down source signal. The semiconductor apparatus also includes a driver configured to generate a driving data signal by driving the pull-up source signal and the pull-down source signal from the driving control unit. A POD impedance control unit is connected to the output terminal of the driver and has a variable resistance value.09-23-2010
20100237904High Performance Output Drivers and Anti-Reflection Circuits - Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).09-23-2010
20100060315HIGH CAPACITIVE LOAD AND NOISE TOLERANT SYSTEM AND METHOD FOR CONTROLLING THE DRIVE STRENGTH OF OUTPUT DRIVERS IN INTEGRATED CIRCUIT DEVICES - An output driver calibration circuit includes a programmable drive strength output pullup driver including a strongest transistor and a number of other transistors, a programmable drive strength output pulldown driver including a strongest transistor and a number of other transistors, and a calibration circuit for generating a number of control signals for controlling the transistors in the output pullup driver and the transistors in the output pulldown driver, wherein the control signals are generated simultaneously, except for two the strongest driver transistors.03-11-2010
20110128038IMPEDANCE ADJUSTING DEVICE - An impedance adjusting device includes: a calibration node; a comparison unit configured to compare a reference voltage with a voltage of the calibration node; a counting unit configured to generate an impedance code according to a comparison result of the comparison unit; a reference impedance unit having an impedance value according to the impedance code and connected to the calibration node; a storage unit configured to store the comparison result of the comparison unit upon the generation of the impedance code being completed; an interface node; and a termination unit configured to terminate the interface node, the termination unit including a plurality of parallel resistors configured to be turned on/off according to the impedance code, and a parallel resistor configured to be turned on/off according to a value stored in the storage unit.06-02-2011
20090072855DYNAMICALLY ADJUSTING OPERATION OF A CIRCUIT WITHIN A SEMICONDUCTOR DEVICE - Systems and methods for dynamically adjusting operation of a circuit within a semiconductor device are described herein. At least some illustrative embodiments include a system that includes a matching circuit including a first plurality of switching devices coupled to each other in parallel and not coupled in parallel to a resistive device, a driver circuit including a plurality of driver devices (the driver circuit adjusted based upon which of the switching devices are enabled), and processing logic that couples to the matching and driver circuits. The processing logic derives a binary value indicative of which of the switching devices are to be enabled, the binary value reflecting one or more process comers associated with the switching devices, and not reflecting one or more process comers associated with the resistive device. The processing logic further maps the binary value to a control value used to adjust the driver circuit.03-19-2009
20090167344DATA OUTPUT DRIVING CIRCUIT OF SEMICONDUCTOR APPARATUS - A data output driving circuit for a semiconductor apparatus can include a code multiplier configured to multiply a received first code by a multiplication factor determined in response to a control signal and generating a second code; a signal line configured to transmit the second code; and a plurality of data output drivers commonly connected to the signal line and changed in an impedance thereof in response to the second code.07-02-2009
20090115449ON DIE TERMINATION DEVICE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration circuit configured to generate calibration codes for determining a termination resistance, a counting circuit configured to generate counting codes increasing with time. A transferring circuit of the device is configured sequentially to transfer the calibration codes in response to the counting codes. A receiving circuit is configured sequentially to receive the calibration codes from the transferring circuit in response to the counting codes. A termination resistance circuit of the device is configured to perform impedance matching using a resistance determined according to the calibration codes.05-07-2009
20090108867Method For Operating An Electronic Device With Reduced Pin Capacitance - A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-stating step is performed such that when a leg is not being utilized, the tuning transistors in the unused leg are placed in a tri-state. For example, during an ODT mode of the output driver, the tuning transistors in the non-ODT legs are tri-stated. During a READ mode of the output driver, the tuning transistors in the ODT legs are tri-stated. During a HiZ mode of the output driver, the tuning transistors in both legs are tri-stated. Tri-stating the tuning transistors in the unused output driver legs can reduce DQ pin capacitance by a total of approximately (Cgd+Cgs+Cgb). A circuit for performing the method includes tri-state components in electrical communication with the tuning transistors, and logic units configured to control the tri-state components. An electronic device includes the output driver having the tri-state components in electrical communication with the logic units.04-30-2009
20110001510SEMICONDUCTOR DEVICE - A semiconductor device is able to terminate internal transmission lines and including a pre-driving unit configured to generate a pull-up driving signal and a pull-down driving signal corresponding to an output data signal, and transfer the pull-up driving signal and the pull-down driving signal to a first transmission line and a second transmission line, respectively, a main driving unit configured to drive an output data in response to the pull-up driving signal and the pull-down driving signal transferred through the first transmission line and the second transmission line and a termination unit configured to be supplied with a termination voltage to terminate the first transmission line and the second transmission line.01-06-2011
20110241727DYNAMIC ON-DIE TERMINATION SELECTION - In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination control signal input is provided to receive an indication that the integrated circuit device is to apply one of the controllable termination impedance configurations at each of the data inputs, and a logic circuit applies one of a first and a second of the controllable termination impedance configurations at the data inputs based on the indication received at the termination control signal input and an internal state of the memory device, such that during a first internal state corresponding to the reception of write data on the data inputs, the first of the controllable termination impedance configurations is applied at each of the data inputs, and during a second internal state following the first internal state, the second of the controllable termination impedance configurations is applied at each of the data inputs.10-06-2011
20110109344Semiconductor devices having on-die termination structures for reducing current consumption and termination methods performed in the semiconductor devices - Example embodiments disclose a semiconductor device having an on-die termination (ODT) structure that reduces current consumption, and a termination method performed in the semiconductor device. The semiconductor device includes a calibration circuit for generating calibration codes in response to a reference voltage and a voltage of a calibration terminal connected to an external resistor and an on-die termination device for controlling a termination resistance of a data input/output pad in response to the calibration codes and an on-die termination control signal. The termination resistance of the data input/output pad is greater than a resistance of the calibration terminal.05-12-2011
20110001511OUTPUT CIRCUIT FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE HAVING OUTPUT CIRCUIT, AND METHOD OF ADJUSTING CHARACTERISTICS OF OUTPUT CIRCUIT - To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.01-06-2011
20110025374Multi-Drop Bus System - A multi-drop bus system and a method for operating such a system. The system includes a multi-drop bus having at least one bus line, each bus line being made up of a multiple of line segments. Each of the line segments terminates at a drop point and each drop point is coupled to a load impedance. The characteristic impedance of a line segment is matched to the equivalent impedance presented by the load impedance in combination with the characteristic impedance of a following segment, or is matched to the load impedance if there is no following segment.02-03-2011
20110037496SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR STORAGE DEVICE AND IMPEDANCE ADJUSTMENT METHOD - It is desired to reduce the current consumption of an autonomous impedance adjustment circuit. The semiconductor integrated circuit according to the present invention stops the change in the drive capability of a driver correspondingly to the output (count data) of a comparator which is sequentially outputted for changing the drive capability of a replica driver and an output driver.02-17-2011
20110043246DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS - A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.02-24-2011
20110241726ON-DIE TERMINATION CIRCUIT - An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.10-06-2011
20100171521SYSTEM FOR TRANSMISSION LINE TERMINATION BY SIGNAL CANCELLATION - A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.07-08-2010
20100164541TERMINATION CONTROL CIRCUIT AND METHOD FOR GLOBAL INPUT/OUTPUT LINE - A termination control circuit for a global input/output line includes a speed determination unit configured to output a termination enable signal which is activated in response to a frequency of an external clock signal and CAS latency information; and a pulse generation unit configured to output a driving signal for driving a termination circuit for the global input/output line in response to a termination control signal and the termination enable signal.07-01-2010
20100164540Semiconductor Memory Device - A semiconductor memory device includes a reference voltage pad for receiving a reference voltage from an external device, a calibration resistor connected to a calibration node where an external resistor is connected to and having a resistor value decided according to a calibration code, and a calibration code generator for generating the calibration code by comparing a voltage of the calibration node and the reference voltage.07-01-2010
20090322375PARALLEL RESISTOR CIRCUIT, ON-DIE TERMINATION DEVICE HAVING THE SAME, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE ON-DIE TERMINATION DEVICE - A parallel resistor circuit that can reduce an error of a resistance value, an on-die termination having the same, and a semiconductor device having the on-die termination device. The semiconductor memory device includes a calibration circuit configured to pull up or pull down a predetermined node and compare a voltage of the predetermined node with a reference voltage to generate calibration codes, by using parallel resistor units that are turned on or off in response to the calibration codes. An output driver is configured to terminate a data output node to a pull-up or pull-down level to output data, by using the parallel resistor units. At least one of the parallel resistor units having at least two resistivities includes resistors with different resistivities connected to each other in parallel.12-31-2009
20110128037DATA OUTPUT CIRCUIT - A data output circuit includes a plurality of drivers configured to be turned on/off according to impedance codes to output data to an output node. The impedance codes are divided into a first group having a value to turn on the drivers, and a second group having a value to turn off the drivers, and at least some of the drivers controlled by the second group are turned on during a pre-emphasis period.06-02-2011
20110128036DRIVING CIRCUIT WITH IMPEDENCE CALIBRATION - A driving circuit includes at least a driving unit. The driving circuit includes a first bias component, a second bias component, and four metal-oxide-semiconductor (MOS) transistors. The first bias component has a first node coupled to a first reference voltage and a second node for outputting a first bias current. The second bias component has a first node for draining a second bias current and a second node coupled to a second reference voltage different from the first reference voltage. Each of the MOS transistors has a control node for receiving one of input signal pairs, a node coupled to one of the bias components and another node coupled to one of the output ports of the driving circuit. The four MOS transistors are of a same conductive type.06-02-2011
20110084725HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL - An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.04-14-2011
20100013516DEVICES AND METHODS FOR CONTROLLING ACTIVE TERMINATION RESISTORS IN A MEMORY SYSTEM - A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node.01-21-2010
20100060314TERMINATION RESISTOR SCHEME - An example embodiment of the present invention relates to a method and corresponding apparatus that terminates circuit connectivity in a bus by determining location of an instrument on the bus, and based on coupling a terminating resistance to the instrument. The example embodiment may couple a terminating resistance with the instrument placed at the end of a bus by employing at least one male-to-male connector arranged to establish a connection between the female receptacles of the terminating resistance and the bus. In order to determine a state of termination of circuit connectivity in a bus, an example embodiment of the present invention may connect a transceiver to a terminating resistance and determine a state of termination of circuit connectivity in the bus as a function of sensing receive activity in the transceiver.03-11-2010
20100066405Line Driver With Tuned On-Chip Termination - A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current from a first stage transistor, and the output node is connected to receive an amplified current from a second stage transistor that is N times the unit current. The bridge resistor is formed with a resistance value set such that the voltages at the internal node and the output node are equal, i.e., such that no current flows through the series resistor. The resistance value of the series resistor is thus adjustable to optimize output impedance in a manner independent of the driver's gain. An echo cancellation circuit is utilized to eliminate noise from two associated line drivers.03-18-2010
20110248743ENHANCED PERFORMANCE MEMORY SYSTEMS AND METHODS - Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.10-13-2011
20110248742Calibration circuit, semiconductor device including the same, and data processing system - A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.10-13-2011
20130162286IMPEDANCE CODE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - An impedance code generation circuit includes an impedance code generation unit configured to generate an impedance code, a set value generation unit configured to generate a set value by counting an external signal, and an impedance code modification unit configured to generate a modified impedance code by performing a logic operation on the set value and the impedance code.06-27-2013
20100097093INPUT/OUTPUT CIRCUITRY WITH COMPENSATION BLOCK - Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wherein the plurality of selectable resistive elements of the first and second variable resistance blocks are selected based on a voltage level at the first node of the external resistor.04-22-2010
20090284280SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device comprises a transistor circuit exhibiting inductance at a desired frequency owing to capacitance between electrodes in a MOS transistor, the transistor circuit having an impedance that increases with an increase in frequency; and a first MOS transistor that functions as a source follower having the transistor circuit as a load.11-19-2009
20090153185On-die-termination control circuit and method - On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to delay an on/off control signal in synchronization with shift clocks in a non-power-down mode, and transfer the on/off control signal as received without delay in a power-down mode, a power-down delay configured to delay the on/off control signal in the power-down mode, and not to delay the on/off control signal in the non-power-down mode and a controller configured to control enabling/disabling of an on-die-termination operation according to information about enable/disable timing of an on-die-termination operation provided by the on/off control signal that have passed through the shift register and the power-down delay.06-18-2009
20090115448Design Structure for an Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry - A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver.05-07-2009
20080252333Resistor circuit, interface circuit including resistor circuit, and electronic instrument - A resistor circuit includes n-stage unit circuits, each of which includes a first resistor element provided between first and second terminals, a first disconnection element provided between the second and third terminals, and a second disconnection element and a second resistor element provided in series between the second and fourth terminals. The first terminal of each of the n-stage unit circuits is connected with a first interconnect, the fourth terminal of each of the n-stage unit circuits is connected with a second interconnect, the third terminal of the first-stage unit circuit is connected with a third interconnect, and the third terminal of the mth-stage unit circuit is connected with the second terminal of the (m−1)th-stage unit circuit.10-16-2008
20120169370SYSTEM AND PACKAGE INCLUDING PLURAL CHIPS AND CONTROLLER - A system includes an input/output channel and a plurality of chips coupled to the input/output channel, wherein only one chip of the plurality of chips performs a termination operation for impedance matching of the input/output channel.07-05-2012
20080252332SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A semiconductor integrated circuit includes an ODT signal generator that receives an ODT command signal, an ODT reset signal, and an ODT calibration end signal to generate an ODT control signal according to the phase of the ODT calibration end signal, and an ODT resistance adjusting unit that is to perform an on-die termination operation in response to the ODT control signal.10-16-2008
20100321060SEMICONDUCTOR LSI AND SEMICONDUCTOR DEVICE - In a signal transmission system, performing signal transmission via signal interconnections 12-23-2010
20110163778IMPEDANCE CALIBRATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE WITH THE IMPEDANCE CALIBRATION CIRCUIT AND LAYOUT METHOD OF INTERNAL RESISTANCE IN THE IMPEDANCE CALIBRATION CIRCUIT - An impedance calibration circuit for impedance matching between a semiconductor memory device and an external device includes a driving circuit and a comparing circuit. The driving circuit has a plurality of internal resistances, with one or more of the internal resistances being a variable resistance. The driving circuit compares the impedance of the internal resistances to the input/output impedance of the external device in order to provide a calibration voltage. The comparing circuit compares the calibration voltage to a reference voltage and provides a code signal for calibrating the impedance corresponding to output data with the input/output impedance of the external device. The impedance calibration circuit calibrates an impedance mismatch between the impedance calibration circuit and a data input/output driver by adjusting the impedance of the impedance calibration circuit through the variable resistance.07-07-2011
20110133774METHOD AND APPARATUS FOR HIGH RESOLUTION ZQ CALIBRATION - A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.06-09-2011
20110133772High Performance Low Power Output Drivers - Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. In combination with RC termination circuits, output drivers of the present invention can be fully compatible with HSTL, SSTL, GTL, BTL, SATA, PCIe, LVDS, MIPI, MDDI or other partial voltage interfaces.06-09-2011
20110133773High Performance Output Drivers and Anti-Reflection Circuits - Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).06-09-2011
20110133771EDGE RATE SUPPRESSION FOR OPEN DRAIN BUSES - An edge rate suppression circuit arrangement is provided for operation with an open drain bus. The circuit arrangement includes a variable resistive circuit having an input for receiving a variable voltage signal and an output coupled to the open drain bus, and a control circuit configured to operate the variable resistive circuit. The control circuit operates the variable resistive circuit in respective high and low resistance states in response to the variable voltage signal.06-09-2011
20110074462DATA DRIVING IMPEDANCE AUTO-CALIBRATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - A data driving impedance auto-calibration circuit includes: a detection block configured to calibrate a characteristic voltage generated by detecting an operation characteristic variation of an element, according to a code signal, and generate a calibrated characteristic voltage; a comparison block configured to compare the calibrated characteristic voltage with a reference voltage and output a comparison result signal; and a code calibration block configured to calibrate the code signal according to the comparison result signal.03-31-2011
20110254584Switchable Passive Termination Circuits - According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.10-20-2011
20110068822DATA LINE TERMINATION CIRCUIT - A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.03-24-2011
20110095783PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES - Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.04-28-2011
20100213972DEVICES AND METHODS FOR DRIVING A SIGNAL OFF AN INTEGRATED CIRCUIT - Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output of the differential driver circuitry is coupled to an externally-accessible output terminal of the package. The other output may be terminated off the chip, but within the package. By routing the output signal and a second complementary output through the package, crosstalk potentially caused by the output signal can be reduced. Simultaneous switching output noise may also be reduced through use of a current-steering differential driver topology. Signal symmetry may also improve, reducing inter-symbol interference.08-26-2010
20100060318Printed circuit board having a termination of a T-shaped signal line - Printed circuit board having a termination of a T-shaped signal line having at least two line ends, one line end being terminated using a terminating resistor against a supply voltage, and the other line end being terminated against the reference potential of the supply voltage.03-11-2010
20100060317DATA OUTPUT DEVICE AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A data output device includes a pre-driver unit configured to control a driving force according to an impedance control signal and to drive output data using the driving force. The data output device includes a main-driver unit configured to control an impedance according to pull-up and pull-down resistance control codes having values that correspond to the impedance control signal provided to the pre-driver unit and to drive an output of the pre-driver unit by utilizing the controlled impedance.03-11-2010
20100194428OUTPUT BUFFER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING SAME - An output buffer circuit includes a control unit and an output driver. The control unit generates a control signal in response to a mode signal applied from an internal circuit. The output driver selectively performs a driver operation, a termination operation or an electrostatic discharge (ESD) protection operation in response to the control signal.08-05-2010
20100321059IMPEDANCE ADJUSTMENT CIRCUIT - An impedance adjustment circuit according to the present invention includes a first input buffer which detects that an input signal exceeds VREFA, a second input buffer which detects that the input signal exceeds VREFB, VREFB being higher than VREFA, a counter circuit A which performs count based on an output from the first input buffer, a counter circuit B which performs count based on an output from the second input buffer, and a termination resistor control circuit which controls impedance of a termination resistor provided in a termination of a transmission path based on the count in the counter circuit A and the count in the counter circuit B.12-23-2010
20120146687IMPEDANCE CALIBRATION CIRCUIT AND IMPEDANCE CALIBRATION METHOD - An integrated circuit includes a first ODT (On Die Termination) unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code and calibrate a resistance value for impedance matching of a first line transferring data. The input buffer is configured to buffer the data in response to a reference voltage level and drive input data. Herein, the driving of the input data is controlled in response to the pull-up code and the pull-down code.06-14-2012
20120146686PRE-EMPHASIS TECHNIQUE FOR ON-CHIP VOLTAGE-DRIVEN SINGLE-ENDED-TERMINATION DRIVERS - A transmitter configured for pre-emphasis is described. The transmitter includes a voltage-driven single-ended-termination driver circuitry. The voltage-driven single-ended-termination driver circuitry includes a first termination point and a second termination point. The transmitter also includes a pre-emphasis encoder circuitry. The pre-emphasis encoder circuitry receives a pre-emphasis signal. The transmitter may reduce signal loss in transmission lines by detecting a transition in a data stream, adjusting a source determination resistance and obtaining a gain from the adjusted source determination resistance.06-14-2012
20120306531MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE, AND WIRING SUBSTRATE - A semiconductor device includes a first input terminal receiving a termination resistance control signal, and a termination resistance circuit that is able to be controlled to be turned on or off by the termination resistance control signal. The termination resistance circuit is turned off, irrespective of a level of said termination resistance control signal when the semiconductor device outputs data in response to a read command.12-06-2012
20120206165PROGRAMMING OF DIMM TERMINATION RESISTANCE VALUES - Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.08-16-2012
20110074463ON-DIE SYSTEM AND METHOD FOR CONTROLLING TERMINATION IMPEDANCE OF MEMORY DEVICE DATA BUS TERMINALS - A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.03-31-2011
20110050280METHODS AND SYSTEMS TO CALIBRATE PUSH-PULL DRIVERS - Methods and systems to calibrate an on-die resistor relative to an operating voltage of an on-die push-pull driver, and to calibrate the push-pull driver relative to the on-die resistor and relative to operating voltages of the push-pull driver. The calibrated on-die resistor may be used to calibrate receive terminations, a differential transmit termination, and a simulated far-end differential receive termination. The calibrated differential transmit termination and simulated far-end differential receive termination may be coupled in parallel to calibrate current drivers. Calibration of the current drivers may include calibrating voltage swing, and may include a first phase that simultaneously adjusts compensation to the current drivers, and a second phase that individually adjusts the compensation to the current drivers.03-03-2011
20100097095ON-DIE SYSTEM AND METHOD FOR CONTROLLING TERMINATION IMPEDANCE OF MEMORY DEVICE DATA BUS TERMINALS - A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor.04-22-2010
20100097096Calibration circuit, semiconductor device including the same, and data processing system - A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.04-22-2010
20110316581SEMICONDUCTOR DEVICE WITH BUS CONNECTION CIRCUIT AND METHOD OF MAKING BUS CONNECTION - A semiconductor device capable of achieving desirable communication behavior through a bus regardless of whether or not a pull-up resistor is connected on a bus line. The semiconductor device includes external pull-up determination unit and internal pull-up setting unit. The external pull-up determination unit applies a pull-down voltage through an internal pull-down resistor to the bus line, and determines whether an external pull-up resistor external to the semiconductor device is connected on the bus line on the basis of the voltage level of the bus line when the pull-down voltage is applied to the bus line. The internal pull-up setting unit stops application of the pull-down voltage, and applies a pull-up voltage through an internal pull-up resistor to the bus line if it is determined that no external pull-up resistor is connected on the bus line. The internal pull-up setting unit stops application of the pull-down voltage if it is determined that the external pull-up resistor is connected on the bus line.12-29-2011
20110316580METHOD AND APPARATUS FOR DYNAMIC MEMORY TERMINATION - Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.12-29-2011
20120206164USB ISOLATOR WITH ADVANCED CONTROL FEATURES - A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems.08-16-2012
20110156750INTEGRATED CIRCUIT DEVICE WITH DYNAMICALLY SELECTED ON-DIE TERMINATION - In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations. A termination control signal input is provided to receive an indication that the integrated circuit device is to apply one of the controllable termination impedance configurations at each of the data inputs, and a logic circuit applies one of a first and a second of the controllable termination impedance configurations at the data inputs based on the indication received at the termination control signal input and an internal state of the memory device, such that during a first internal state corresponding to the reception of write data on the data inputs, the first of the controllable termination impedance configurations is applied at each of the data inputs, and during a second internal state following the first internal state, the second of the controllable termination impedance configurations is applied at each of the data inputs.06-30-2011
20100283503REFERENCE VOLTAGE CIRCUITS AND ON-DIE TERMINATION CIRCUITS, METHODS FOR UPDATING THE SAME, AND METHODS FOR TRACKING SUPPLY, TEMPERATURE, AND/OR PROCESS VARIATION - Devices and methods for operating devices are provided, such as those that include a memory device having a reference voltage (Vref) circuit that has substantially similar paths and impedances as an on-die termination (ODT) circuit. One such Vref circuit tracks supply variations and temperature changes in a manner substantially similar to the ODT circuit. In some embodiments an update scheme is provide for the ODT circuit and the Vref circuit to enable simultaneous update of each circuit through the same digital codes.11-11-2010
20120007632CALIBRATING RESISTANCE FOR INTEGRATED CIRCUIT - An integrated circuit includes a first ODT unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code for impedance matching of a first line through which data is transferred, and adjust a resistance value. The input buffer is configured to drive input data by buffering the data in response to a level of a reference voltage, wherein the driving of the input data is adjusted in response to the pull-up code and the pull-down code.01-12-2012
20120007631INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING DATA OUTPUT IMPEDANCE - An integrated circuit for controlling data output impedance includes an address decoder, a selection signal decoder, and a transfer control unit. The address decoder is configured to decode an address signal and generate a selection mode signal and a first adjustment mode signal. The selection signal decoder is configured to decode a selection signal and generate an enable signal and a disable signal. The transfer control unit is configured to transfer a pull-up signal and a pull-down signal as a selection pull-up signal and a selection pull-down signal.01-12-2012
20120007630IMPEDANCE CALIBRATION MODE CONTROL CIRCUIT - An impedance calibration mode control circuit includes: a first signal generating unit configured to generate a first calibration control signal in response to a ZQ calibration command received after a power-up operation; and a second signal generating unit configured to generate a second calibration control signal during a refresh operation of a semiconductor device.01-12-2012
20120013361Synthetic Pulse Generator for Reducing Supply Noise - A source-terminated transmitter conveys digital signals over a short channel as a voltage signal that transitions between levels for each symbol transition. The transmitter produces each transition by issuing a charge pulse onto the channel, and thus creates a series of charge pulses. The number of charge pulses per unit time is proportional to the transition density of the signal, as no charge pulse is required between like symbols. The supply current used to deliver the pulses is therefore dependent upon the data pattern. This data dependency can induce supply fluctuations, which can in turn cause errors and otherwise reduce performance. The transmitter issues a synthetic charge pulse for each adjacent pair of like symbols to reduce the data dependency of the supply current. The synthetic pulses can be scaled to match the charge required for symbol transitions on a given channel.01-19-2012
20120056642DATA OUTPUT CIRCUIT - A data output circuit includes a main driver including a pull-up driver, coupled between a power supply terminal and a node coupled to the pad and a pull-down driver coupled between the node and a ground terminal, an impedance controller configured to control an output impedance at the node by sensing a voltage at the node and to generate pull-up control signals and pull-down control signals based on the sensed voltage, and a pre-driver configured to control driving strengths of the pull-up driver and the pull-down driver in response to the pull-up control signals, the pull-down control signals, and data.03-08-2012
20120056643SYSTEM FOR TRANSMISSION LINE TERMINATINO BY SIGNAL CANCELLATION - A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.03-08-2012
20120056641Semiconductor device and method of adjusting characteristic thereof - To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.03-08-2012
20120153988SEMICONDUCTOR DEVICE, CIRCUIT BOARD DEVICE, AND INFORMATION PROCESSING DEVICE - In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.06-21-2012
20120062275INTERFACE CIRCUIT - In performing calibration, a control circuit in a calibration circuit of an interface circuit controls a selector so that voltages V03-15-2012
20110057684TRANSCEIVER SYSTEM, SEMICONDUCTOR DEVICE THEREOF, AND DATA TRANSCEIVING METHOD OF THE SAME - A transceiver system includes a first semiconductor device having a first input/output (I/O) pad connected with an I/O channel and a second semiconductor device having a second I/O pad connected with the I/O channel. The first semiconductor device is configured to terminate the first I/O pad with a first voltage when data is received, and maintain the first I/O pad and the I/O channel at the first voltage when data is transmitted. The second semiconductor device is configured to terminate the second I/O pad with a second voltage higher than the first voltage when data is received, and maintain the second I/O pad and the I/O channel at the second voltage when data is transmitted.03-10-2011
20090278565Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.11-12-2009
20100289523ECHO CANCELING ARRANGEMENT - In a line driver/receiver circuit where the line driver is connected with its output terminals to a load for supplying a transmit signal thereto and where the receiver is connected with its input terminals to the load for simultaneously receiving a receive signal therefrom, the transmit signal on the input terminals of the receiver is canceled by connecting the output terminals of the line driver to the load via equal complex sense impedances of an impedance value that is much smaller than the impedance value of the load impedance to match the load impedance, connecting the input terminals of the receiver to the load via equal first resistors and to respective output terminal of the line driver via equal second resistors, and providing transconductance amplifiers to sense the voltage across the sense impedances and supply corresponding currents to respective input terminal of the line driver.11-18-2010
20100244891INTEGRATED CIRCUITS AND METHODS FOR PROVIDING IMPEDANCE OF DRIVER TO DRIVE DATA - An integrated circuit includes a pad coupled with a driver. The driver is capable of driving data to the pad. The driver is capable of providing a first set of resistance data substantially fitting to a first curve and a second set of resistance data substantially fitting to a second curve. A portion of at least one of the first set of resistance data and the second set of resistance data is an impedance of the driver to drive data09-30-2010
20120126849TERMINATION CIRCUIT FOR ON-DIE TERMINATION - In a semiconductor device having a terminal connected to an internal portion, a termination circuit for providing on-die termination for the terminal of the device. The termination circuit comprises a plurality of transistors, including at least one NMOS transistor and at least one PMOS transistor, connected between the terminal and a power supply; and control circuitry for driving a gate of each of NMOS transistor with a corresponding NMOS gate voltage and for driving a gate of each PMOS transistor with a corresponding PMOS gate voltage, the control circuitry being configured to control the NMOS and PMOS gate voltages so as to place the transistors in an ohmic region of operation when on-die termination is enabled. The power supply supplies a voltage that is less than each said NMOS gate voltage and greater than each said PMOS gate voltage.05-24-2012
20120161811DRIVER CIRCUIT CORRECTION ARM DECOUPLING RESISTANCE IN STEADY STATE MODE - A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and is operable, in pre-emphasis intervals as well as steady-state intervals, to connect a first impedance between an output terminal of the driver circuit and a constant reference potential. The correction arm is operable to connect a correction impedance in parallel with the first impedance in pre-emphasis intervals, and to decouple the correction impedance from the first impedance in steady-state intervals. The parallel connection of the first impedance and the correction impedance in pre-emphasis intervals increases the voltage level of the output signal of the driver circuit in pre-emphasis intervals. The use of the correction arm compensates for the effect of parasitic capacitance at one or more nodes of the driver circuit, thereby reducing the settling time of the output signal and enabling high-speed operation.06-28-2012
20090058458DIGITAL-TO-ANALOG CONVERTING CIRCUIT AND APPARATUS FOR ON-DIE TERMINATION USING THE SAME - A digital-to-analogue converting circuit includes a driver leg having a plurality of resistance elements between a power supply voltage terminal and a ground voltage terminal, wherein at least one of the plurality of resistance elements is a variable resistor, and a code level changing unit for outputting a level-changed code to a control terminal of the variable resistor based on an activation of a digital code, wherein the level-changed code is produced by converting a level of the digital code.03-05-2009
20120212254SEMICONDUCTOR DEVICE HAVING CALIBRATION CIRCUIT FOR ADJUSTING OUTPUT IMPEDANCE OF OUTPUT BUFFER CIRCUIT - Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.08-23-2012
20120074983Integrated Circuit with Configurable On-Die Termination - Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.03-29-2012
20100007375TERMINATION RESISTANCE CIRCUIT - A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal.01-14-2010
20090066363Semiconductor memory device - A semiconductor memory device includes a code channel for outputting a plurality of code signals based on a code control signal inputted from an external source; a termination resistor decoder for decoding a chip selection signal, an on die termination (ODT) control signal and the plurality of code signals and outputting a plurality of selection signals based on decoded signals; and an ODT block for providing an output data pad with impedance of a termination resistor which is selected in response to the plurality of selection signals.03-12-2009
20120256654REAL TIME AVERAGED IMPEDANCE CALIBRATION FOR ON-DIE TERMINATION - An averaged impedance calibration is obtained by utilizing two separately controlled resistive loads arranged in parallel and choosing two adjacent control codes to configure switch arrays to set the resistance of each of the separate resistive loads. The resistance of the resistive loads is averaged to provide greater accuracy. The two adjacent control codes are close to the target impedance value and typically one is slightly higher and one is slightly lower than the target impedance value.10-11-2012
20120187978Methods and Circuits for Calibrating Multi-Modal Termination Schemes - Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area.07-26-2012
20100259293Bus Terminating Part - A bus terminating component has a cylindrical housing that is designed to be inserted in a sealed manner into a PG screw connection. In the interior of the housing sits a circuit made from a bus terminating resistor and a cascade made from capacitors that are balanced by means of resistors connected in parallel. Therefore, no relevant power loss occurs on the bus terminating resistor.10-14-2010
20120262200HIGH DEFINITION MULTIMEDIA INTERFACE (HDMI) APPARATUS INCLUDING TERMINATION CIRCUIT - A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code.10-18-2012
20120299618BALANCED IMPEDANCE METHOD FOR DIFFERENTIAL SIGNALING - A system and method for implementing a differential signaling driver with a common-mode voltage not equal to one half the power supply voltage using voltage-mode techniques. Embodiments of the present invention maintain balanced impedance at the signal output. In an embodiment, a driver may have multiple operating modes for each potential supply voltage or common-mode voltage. In an embodiment, each potential mode may involve configuring the driver by activating or deactivating switches or resistors in the driver and each potential mode may have different resistor values.11-29-2012
20100327904SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.12-30-2010
20100327903CIRCUIT FOR CALIBRATING IMPEDANCE AND SEMICONDUCTOR APPARATUS USING THE SAME - A circuit for calibrating impedance includes an enable signal generator, a code generator and a connection controller. The enable signal generator generates an enable signal in response to a chip selection signal. The code generator generates an impedance calibration code in response to the enable signal by using an external resistance coupled to an electrode. The connection controller controls connection between the code generator and the electrode in response to the enable signal.12-30-2010
20100327902Power saving termination circuits for dram modules - The present invention provides power saving methods by replacing termination resistors used to support SSTL DRAM interfaces with RC termination circuits; the RC termination circuits consumes significant less power relative to prior art termination resistors at low frequency and behave as a matching impedance at high frequency. Similar methods and structures are also applicable for PCIe, SATA, or MIPI differential interfaces.12-30-2010
20080278193Reference voltage generators for reducing and/or eliminating termination mismatch - A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.11-13-2008
20120319726TERMINAL RESISTOR APPARATUS - A terminal resistor apparatus includes an input-side switch, an input-side terminal resistor, an output-side switch, and an output-side terminal resistor. When a plurality of the terminal resistor apparatus are connected, the input-side switch of the first terminal resistor apparatus will be conducted so that the input-side terminal resistor will be connected, but the output-side switch will not be conducted so that the output-side terminal resistor will not be connected. The input-side switch of the last terminal resistor apparatus will not be conducted so that the input-side terminal resistor will not be connected, but the output-side switch will be conducted so that the output-side terminal resistor will be connected. The input-side switches of the other terminal resistor apparatus will not be conducted so that the input-side terminal resistors will not be connected, and the output-side switches will not be conducted so that the output-side terminal resistors will not be connected.12-20-2012
20080309368CIRCUIT FOR GENERATING ON-DIE TERMINATION CONTROL SIGNAL - A circuit for generating an on-die termination control signal can include a first signal generation block configured to generate a first signal to prevent a first on-die terminal control from being performed in a frequency/voltage switching period, a second signal generation block configured to generate a second signal to perform a second on-die termination control at an initial stage of operation, and a signal output block configured to generate the on-die termination control signal by combining the first and second signals.12-18-2008
20100225349Techniques for Providing Calibrated On-Chip Termination Impedance - Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.09-09-2010
20120081146SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION - Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.04-05-2012
20120081145IMPEDANCE CONTROL SIGNAL GENERATION CIRCUIT AND IMPEDANCE CONTROL METHOD OF SEMICONDUCTOR CIRCUIT - An impedance control signal generation circuit includes an impedance control signal generation unit configured to generate an impedance control signal in response to a command, a storage unit configured to latch and output the impedance control signal in response to an update pulse signal, a control unit configured to determine whether the impedance control signal is within a predetermined range and generate an update enable signal according to a determination result, and a prohibition unit configured to control input of the update pulse signal to the storage unit in response to the update enable signal.04-05-2012
20120081144CIRCUIT AND METHOD FOR GENERATING ON-DIE TERMINATION SIGNAL AND SEMICONDUCTOR APPARATUS USING THE SAME - Various embodiments of an on-die termination (ODT) signal generating circuit are disclosed. In one exemplary embodiment, the ODT signal generating circuit includes a latency unit and an ODT control signal generating unit. The latency unit is configured to receive a clock signal and an ODT signal. The latency unit is configured to delay the ODT signal by a predetermined time to generate a first ODT signal. The latency unit is also configured to delay the ODT signal by less than the predetermined time to generate a second ODT signal. The ODT control signal generating unit is configured to provide either one of the first and second ODT signals as an ODT control signal in response to a control signal.04-05-2012
20120092039IMPEDANCE CODE GENERATION CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - An impedance code generation circuit includes an impedance unit configured to drive a calibration node to a first level by using an impedance value determined by an impedance code, a code generation unit configured to generate the impedance code so that a voltage of the calibration node has a voltage level between a first reference voltage and a second reference voltage, and a reference voltage generation unit configured to generate the first reference voltage and the second reference voltage in response to the impedance code.04-19-2012
20120326745Current-Mode Logic Buffer with Enhanced Output Swing - A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively. The first switching element is operative to electrically connect the first differential output to the second voltage source when the first transistor is turned off. The second switching element is operative to electrically connect the second differential output to the second voltage source when the second transistor is turned off.12-27-2012
20120326746METHODS AND APPARATUSES FOR DYNAMIC MEMORY TERMINATION - Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.12-27-2012
20130015879SEMICONDUCTOR DEVICEAANM ARAKI; HiroeiAACI TokyoAACO JPAAGP ARAKI; Hiroei Tokyo JP - A device includes an output circuit including a plurality of unit buffers, each of the unit buffers having an adjustable impedance; a controller circuit operable to selectively activate at least one of the unit buffers; and an impedance adjustment part operable to adjust the impedance of each of the unit buffers in response to a change of the number of the unit buffers that are selectively activated by the controller circuit.01-17-2013
20130015880SEMICONDUCTOR DEVICE AND METHOD OF ADJUSTING AN IMPEDANCE OF AN OUTPUT BUFFERAANM HARAGUCHI; YoshinoriAACI TokyoAACO JPAAGP HARAGUCHI; Yoshinori Tokyo JP - A semiconductor device has a ZQ circuit (01-17-2013
20130021056Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.01-24-2013
20080290894ON DIE TERMINATION (ODT) CIRCUIT HAVING IMPROVED HIGH FREQUENCY PERFORMANCE - An On Die Termination (ODT) circuit for performing an ODT operation. The ODT circuit includes a resistor having a first end to receive an ODT enable signal; and a switch unit coupled to a second end of the resistor. The ODT operation is performed in response to the ODT enable signal passing through the resistor.11-27-2008
20130135006HIGH-SPEED DRIVER CIRCUIT - An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream.05-30-2013
20080224728On-die termination circuit of semiconductor memory apparatus - An on-die termination circuit of a semiconductor memory apparatus includes a comparator that compares a voltage corresponding to a normal code with a reference voltage to output a comparison signal. A code adjusting unit varies the normal code according to the comparison signal, outputs the varied normal code, and resets the normal code to a predetermined reset code or a variable fuse code.09-18-2008
20130169311ADAPTIVE BUFFER - An embodiment of a buffer for a transmission line, a circuit including such a buffer, a high-speed data link, and a low-voltage differential signaling (LVDS) system.07-04-2013
20130113517IMPEDANCE CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An impedance control circuit includes a pull-up code generator configured to generate pull-up impedance control codes using a voltage of a first node, a pull-up impedance unit configured to pull-up-drive the first node in response to the pull-up impedance control codes, a plurality of dummy impedance units enabled in response to respective select signals and each configured to pull-up-drive a second node in response to the pull-up impedance control codes, a pull-down code generator configured to generate pull-down impedance control codes using a voltage of the second node, and a plurality of pull-down impedance units enabled in response to the respective select signals and each configured to pull-down-drive the second node in response to the pull-down impedance control codes.05-09-2013
20130113516TERMINATION CIRCUIT AND DC BALANCE METHOD THEREOF - A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.05-09-2013
20130093459TERMINATION DEVICE SYSTEM - A termination device system is provided that includes a device required to be terminated with a resistor and a termination circuit. The termination circuit includes a termination resistor circuit and a judgment circuit connected to the termination resistor circuit. The termination resistor circuit includes at least one controlled termination unit. Each controlled termination unit includes a termination connecting end for connecting the device required to be terminated with a resistor, a controlled switch and a resistor, and provides, based on on/off of the controlled switch, a termination resistor for the device connected to the termination connecting end. The judgment circuit judges whether the device is required to be connected to the termination resistor based on a control instruction of a control device controlling the device connected to the termination connecting end, to output an on/off control signal to the controlled switch of the termination resistor circuit to control on/off.04-18-2013
20110267100OUTPUT BUFFER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING SAME - An output buffer circuit includes a control unit and an output driver. The control unit generates a control signal in response to a mode signal applied from an internal circuit. The output driver selectively performs a driver operation, a termination operation or an electrostatic discharge (ESD) protection operation in response to the control signal.11-03-2011
20130127492TERMINATION FOR COMPLEMENTARY SIGNALS - Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described.05-23-2013
20100277200SELF-CALIBRATING WRITER - In accordance with the invention, a method, system and apparatus are presented that matches the output impedance of a driver to the impedance of a transmission line. A method for matching the impedance between a driver and a transmission line, wherein the transmission line is between the driver and a load can include transmitting a first pulse from the driver to the load through the transmission line, wherein a first reflection from the transmitted first pulse occurs after a first time, measuring a second reflection from the transmitted first pulse after a second time, and adjusting the calibration of the driver in response to the measured second reflection.11-04-2010
20080211535Pseudo-differential output driver with high immunity to noise and jitter - Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of the invention receives two differential input signals and outputs a single output signal with low voltage transistors and programmable impedance and on-die termination circuits. The pseudo-differential output driver consumes little circuit area and has low output capacitance.09-04-2008
20080204071On-die termination circuit, method of controlling the same, and ODT synchronous buffer - An on-die termination (ODT) circuit may include an ODT synchronous buffer and/or an ODT gate. The ODT synchronous buffer may be configured to generate a synchronous ODT command from an external ODT command in synchronization with a first clock signal delay-locked to an external clock signal. The ODT gate may be configured to generate signals for controlling ODT based on a second clock signal delay-locked to the external clock signal and the synchronous ODT command. The synchronous ODT command may be generated in a disabled period of the second clock signal.08-28-2008
20130147512ADAPTIVE TERMINATION - A system for receiving data is provided the system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used for dynamically controlling ringing in the inductive data device, such as by damping ringing signals generated by circuit inductances or capacitances.06-13-2013
20100289522SIGNAL TRANSMITTING DEVICE SUITED TO FAST SIGNAL TRANSMISSION - A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.11-18-2010
20100289521TERMINATION RESISTANCE ADJUSTING CIRCUIT - A termination resistance adjusting circuit includes a first termination resistor circuit, a second termination resistor circuit connected in parallel with the first termination resistor circuit, a resistor circuit for adjustment that adjusts resistances of the first and second termination resistor circuits, a first amplifier circuit that receives a first voltage determined by the resistor circuit for adjustment and a second voltage determined by a reference resistor connected externally, equalizes the first and second voltages, and outputs a resistance adjusting signal to the first and second termination resistor circuits, first and second terminals connected to the first and second termination resistor circuits respectively, and a second amplifier circuit that receives a voltage based on a common voltage of a differential signal supplied to the first and second terminals, and the first or second voltage, and equalizes the voltage based on the common voltage and the first or second voltage.11-18-2010
20120256655INTEGRATED CIRCUIT - An integrated circuit includes: an on-die-termination (ODT) circuit configured to drive an input signal with drivability adjusted according to an impedance calibration code and a reference voltage; and an input buffer configured to buffer the input signal in response to the reference voltage and generate an output signal.10-11-2012
20100308861TERMINATION CIRCUIT AND IMPEDANCE MATCHING DEVICE INCLUDING THE SAME - An impedance matching device includes a calibration circuit configured to generate impedance calibration codes for modification of impedance; a code modification unit configured to modify the impedance calibration codes according to impedance setting information and output modified impedance calibration codes; and a termination impedance unit configured to terminate an interface node with impedance determined according to the modified impedance calibration codes.12-09-2010
20100315122MEMORY CONTROLLER THAT CONTROLS TERMINATION IN A MEMORY DEVICE - A memory controller that controls termination in a memory device. The memory controller includes a data interface, command/address interface and termination control output. The data interface outputs write data onto a data line coupled to a data input of the memory device, and the command/address interfaces outputs, onto a command/address path coupled to the memory device, information that indicates whether the write data is to be received within the memory device. The termination control output asserts a first termination control signal on a termination control signal line coupled to the memory device to cause the memory device to either (i) couple a first termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is to be received within the memory device, or (ii) couple a second termination impedance to the data line while the write data is present at the data input of the memory device if the information indicates that the write data is not to be received within the memory device.12-16-2010
20100315121ADAPTIVE TERMINATION - A system for receiving data is provided. The system includes an inductive data device, such as a device that receives high-speed data over an inductive coupling. An adjustable impedance is coupled to the inductive data device, where the adjustable impedance is used for dynamically controlling ringing in the inductive data device, such as by damping ringing signals generated by circuit inductances or capacitances.12-16-2010
20100315120Dynamic adaptive terminal load adjusting method and circuit - A dynamic adaptive terminal load adjustment method includes comparing a voltage on an on-chip termination impedance driven by an on-chip current source with a voltage of a band gap reference circuit to get an optimal trimming parameter by an adaptive control mechanism, wherein the optimal trimming parameter is applied to a terminal by an output control circuit to have a feedback control. The present invention is on-chip so the cost is saved. The terminal is separated from the adjusting circuit, thus the present invention has a good dynamic performance. Compared with laser trimming, no expensive cost is needed in the present invention. The present invention saves an IO pin without an external device, has the good temperature characteristic and high resistance regulation accuracy. Furthermore, the adjusting circuit is separated from the terminal load circuit by high matching of relative resistance of CMOS process, thus reducing the adverse impact.12-16-2010
20100315119MEMORY CONTROLLER CALIBRATION - Components of a memory controller are calibrated in a select sequence to compensate for variances in skew and signal level variations. The offset bias of the receiver of the I/O cell and the termination resistance of the I/O cell are calibrated. The duty cycles of the transmit path and receive path associated with the I/O cell can be calibrated using the calibrated receiver. In one aspect, the driver of the I/O cell can be calibrated prior to calibrating the receiver. Performing the calibration processes of the memory controller in one of the particular sequences described herein improves the timing budgets for the signaling conducted by the memory controller.12-16-2010
20130187679ENHANCED PERFORMANCE MEMORY SYSTEMS AND METHODS - Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.07-25-2013
20120019282DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS - A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.01-26-2012
20130194001DATA OUTPUT CIRCUIT - A data output circuit includes a pre-code generation unit configured to generate one of a pre-pull-up code and a pre-pull-down code according to a calibration code in response to a voltage level of input data; and a plurality of main driving units configured to be selectively activated in response to an on-die termination code, wherein respective outputs of the plurality of main driving units are commonly connected to an output node, and wherein activated main driving units drive the output node in response to the pre-pull-up code or the pre-pull-down code.08-01-2013
20130194000ELECTROMAGNETIC RADIATION DISSIPATING DEVICES - Electromagnetic radiation (“EMR”) dissipating devices. One example embodiment includes an electrical circuit including an EMR source configured to generate an output signal at an operating bit rate. The output signal may include an EMR component. The electrical circuit may also include an EMR dissipating device electrically coupled to the EMR source and configured to have a resonance frequency corresponding to the operating bit rate.08-01-2013
20080315913Apparatus for measuring on-die termination (ODT) resistance and semiconductor memory device having the same - An apparatus for measuring an on-die termination (ODT) resistance includes an ODT controller and a driver. The ODT controller receives a plurality of decoding signals, a first test mode signal, and a second test mode signal to generate a plurality of pull-up signals and a plurality of pull-down signals. The pull-up signals are enabled in response to the decoding signals and the first test mode signal, and the pull-down signals are enabled in response to the decoding signals and the second test mode signal. The driver receives the pull-up signals and the pull-down signals to drive a data terminal. At least one of the decoding signals is enabled by a mode register set (MRS) for setting an ODT mode.12-25-2008
20120299617Method and Apparatus for A Low Power AC On-Die-Termination (ODT) Circuit - A method and apparatus for A Low Power AC On-Die-Termination (ODT) Circuit using active components reduces receiver power consumption.11-29-2012
20120299619Driver Calibration Methods and Circuits - Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.11-29-2012
20120086470CONSTANT IMPEDANCE LINE DRIVER WITH DIGITALLY CONTROLLED EDGE RATE - A constant impedance driver provides controlled output slew rates. The driver includes a plurality of buffers, each with an output impedance that is multiple of the output impedance of the driver. Outputs of buffers are coupled in parallel to form the output of the driver. Inputs to the buffers are coupled to an input signal or delayed versions of the input signal. The buffer inputs may be selectively coupled to taps of a delay line to provide selected slew rates on the output of the driver. The buffers may be selectively enabled to change or calibrate the output impedance of the driver.04-12-2012
20130207687LOGIC SIGNAL TRANSMISSION CIRCUIT WITH ISOLATION BARRIER - A logic signal transmission circuit includes a driving circuit, an isolation section, and a latch section. The driving circuit converts an input digital signal to a differential digital signal. The isolation section blocks direct current and passes the differential digital signal. The latch section has even numbers of inverters which are connected in a loop and output a logic signal by turning ON and OFF a power supply voltage in a complementary manner. An input impedance of the latch section is set so that when a logic level of the differential digital signal changes, a transient voltage inputted through the isolation section to the latch section changes across a threshold voltage of the latch section. When the transient voltage changes across the threshold voltage, a logic level of the logic signal changes.08-15-2013

Patent applications in class Bus or line termination (e.g., clamping, impedance matching, etc.)