Class / Patent application number | Description | Number of patent applications / Date published |
326022000 | Input noise margin enhancement | 13 |
20080258755 | Noise Reduction Among Conductors - Noise reduction among conductors, the conductors disposed adjacent to one another, the conductors characterized as two or more aggressor conductors and one or more victim conductors, a least two of the aggressor conductors driven with at least two signals that induce unwanted crosstalk upon at least one of the victim conductors, a programmable delay device disposed in a signal path of each of the at least two signals that induce unwanted crosstalk, including programming a delay period into each programmable delay device; receiving, simultaneously at the programmable delay devices, the at least two signals that induce unwanted crosstalk; and transmitting, on two aggressor conductors, the at least two signals that induce unwanted crosstalk, with the at least two signals separated in time by the delay period. | 10-23-2008 |
20090189635 | METHOD AND APPARATUS FOR IMPLEMENTING REDUCED COUPLING EFFECTS ON SINGLE ENDED CLOCKS - A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2). | 07-30-2009 |
20100271067 | DIGITAL NOISE PROTECTION CIRCUIT AND METHOD - A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state. | 10-28-2010 |
20110012639 | RECEIVER, TRANSCEIVER CIRCUIT, SIGNAL TRANSMISSION METHOD, AND SIGNAL TRANSMISSION SYSTEM - A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission. | 01-20-2011 |
20120153987 | DIGITAL NOISE PROTECTION CIRCUIT AND METHOD - A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state. | 06-21-2012 |
20130063177 | CIRCUIT AND METHOD FOR DEGLITCHING AN INPUT SIGNAL - System and method for deglitching an input signal. An output signal may be delayed to generate a delayed signal, the delayed signal determining a guard time interval following a desired transition in the input signal, and a logic circuit is used to keep the output signal unchanged during the guard time interval, and to allow the output signal to equal the input signal outside the guard time interval, based on a value of the delayed signal. | 03-14-2013 |
20130307581 | DIGITAL NOISE PROTECTION CIRCUIT AND METHOD - A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state. | 11-21-2013 |
326023000 | With field effect-transistor | 3 |
326024000 | Complementary FET`s | 3 |
20120062274 | SCHMITT CIRCUIT - The Schmitt circuit includes a first logic circuit that receives an output signal of the input logic circuit and has a first threshold voltage. The Schmitt circuit includes a second logic circuit that receives the output signal of the input logic circuit and has a second threshold voltage lower than the first threshold voltage. The Schmitt circuit includes a variable resistance circuit that adjusts the threshold voltage of the input logic circuit in accordance with an output signal of the first logic circuit and an output signal of the second logic circuit. The Schmitt circuit includes a third logic circuit that receives the output signal of the first logic circuit and the output signal of the second logic circuit, outputs a floating potential in the case where a potential of an input signal of the third logic circuit is between the first threshold voltage and the second threshold voltage, and outputs a fixed potential in the case where the potential of the input signal of the third logic circuit is equal to or exceeds the first threshold voltage or is equal to or below the second threshold voltage. | 03-15-2012 |
20140118025 | INPUT BUFFER CIRCUIT - There is provided an input buffer circuit having hysteresis characteristics. The input buffer circuit includes: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, wherein reference levels of the first and second operating units determining a high or low level of the input signal are set to be different. | 05-01-2014 |
20160006438 | THRESHOLD LOGIC ELEMENT WITH STABILIZING FEEDBACK - Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise. | 01-07-2016 |
20120062274 | SCHMITT CIRCUIT - The Schmitt circuit includes a first logic circuit that receives an output signal of the input logic circuit and has a first threshold voltage. The Schmitt circuit includes a second logic circuit that receives the output signal of the input logic circuit and has a second threshold voltage lower than the first threshold voltage. The Schmitt circuit includes a variable resistance circuit that adjusts the threshold voltage of the input logic circuit in accordance with an output signal of the first logic circuit and an output signal of the second logic circuit. The Schmitt circuit includes a third logic circuit that receives the output signal of the first logic circuit and the output signal of the second logic circuit, outputs a floating potential in the case where a potential of an input signal of the third logic circuit is between the first threshold voltage and the second threshold voltage, and outputs a fixed potential in the case where the potential of the input signal of the third logic circuit is equal to or exceeds the first threshold voltage or is equal to or below the second threshold voltage. | 03-15-2012 |
20140118025 | INPUT BUFFER CIRCUIT - There is provided an input buffer circuit having hysteresis characteristics. The input buffer circuit includes: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, wherein reference levels of the first and second operating units determining a high or low level of the input signal are set to be different. | 05-01-2014 |
20160006438 | THRESHOLD LOGIC ELEMENT WITH STABILIZING FEEDBACK - Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise. | 01-07-2016 |
326023000 | With field-effect transistor | 3 |
326024000 | Complementary FET's | 3 |
20120062274 | SCHMITT CIRCUIT - The Schmitt circuit includes a first logic circuit that receives an output signal of the input logic circuit and has a first threshold voltage. The Schmitt circuit includes a second logic circuit that receives the output signal of the input logic circuit and has a second threshold voltage lower than the first threshold voltage. The Schmitt circuit includes a variable resistance circuit that adjusts the threshold voltage of the input logic circuit in accordance with an output signal of the first logic circuit and an output signal of the second logic circuit. The Schmitt circuit includes a third logic circuit that receives the output signal of the first logic circuit and the output signal of the second logic circuit, outputs a floating potential in the case where a potential of an input signal of the third logic circuit is between the first threshold voltage and the second threshold voltage, and outputs a fixed potential in the case where the potential of the input signal of the third logic circuit is equal to or exceeds the first threshold voltage or is equal to or below the second threshold voltage. | 03-15-2012 |
20140118025 | INPUT BUFFER CIRCUIT - There is provided an input buffer circuit having hysteresis characteristics. The input buffer circuit includes: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, wherein reference levels of the first and second operating units determining a high or low level of the input signal are set to be different. | 05-01-2014 |
20160006438 | THRESHOLD LOGIC ELEMENT WITH STABILIZING FEEDBACK - Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise. | 01-07-2016 |
20120062274 | SCHMITT CIRCUIT - The Schmitt circuit includes a first logic circuit that receives an output signal of the input logic circuit and has a first threshold voltage. The Schmitt circuit includes a second logic circuit that receives the output signal of the input logic circuit and has a second threshold voltage lower than the first threshold voltage. The Schmitt circuit includes a variable resistance circuit that adjusts the threshold voltage of the input logic circuit in accordance with an output signal of the first logic circuit and an output signal of the second logic circuit. The Schmitt circuit includes a third logic circuit that receives the output signal of the first logic circuit and the output signal of the second logic circuit, outputs a floating potential in the case where a potential of an input signal of the third logic circuit is between the first threshold voltage and the second threshold voltage, and outputs a fixed potential in the case where the potential of the input signal of the third logic circuit is equal to or exceeds the first threshold voltage or is equal to or below the second threshold voltage. | 03-15-2012 |
20140118025 | INPUT BUFFER CIRCUIT - There is provided an input buffer circuit having hysteresis characteristics. The input buffer circuit includes: a first operating unit performing a NOR operation on an input signal and a first signal; a second operating unit performing a NAND operation on the input signal and a second signal; and an inverting unit inverting outputs of the first and second operating units to generate a second signal and a first signal, respectively, wherein reference levels of the first and second operating units determining a high or low level of the input signal are set to be different. | 05-01-2014 |
20160006438 | THRESHOLD LOGIC ELEMENT WITH STABILIZING FEEDBACK - Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise. | 01-07-2016 |