Entries |
Document | Title | Date |
20080204069 | Electronic Module With Organic Logic Circuit Elements - The invention relates to an electronic module having two or more organic circuit elements connected together to give a logic circuit, said organic circuit elements being made up of organic components, in particular organic field effect transistors. The logic circuit comprises at least one filter module ( | 08-28-2008 |
20090002017 | Multiple-Mode Compensated Buffer Circuit - A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode. | 01-01-2009 |
20090045834 | Digital circuits with adaptive resistance to single event upset - A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T. | 02-19-2009 |
20090079465 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention aims to make each power shutdown area appropriate. | 03-26-2009 |
20090153183 | NOISE FILTER CIRCUIT, DEAD TIME CIRCUIT, DELAY CIRCUIT, NOISE FILTER METHOD, DEAD TIME METHOD, DELAY METHOD, THERMAL HEAD DRIVER, AND ELECTRONIC INSTRUMENT - A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a signal based on a signal output from the second inverter circuit as a set signal and a reset signal. Each of the first inverter circuit and the second inverter circuit includes a first-conductivity-type transistor and a second-conductivity-type transistor, the capability of one of the first-conductivity-type transistor and the second-conductivity-type transistor being lower than the capability of the other of the first-conductivity-type transistor and the second-conductivity-type transistor. | 06-18-2009 |
20090201045 | INPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT COMPRISING THE INPUT CIRCUIT - A control signal input circuit for supplying control signals to a plurality of controlled circuits comprises N pieces of control signal preservation/output circuits provided one by one corresponding to plural-bit signals for delivering input data as it is when a trigger signal is at a first level, and holding previously delivered output data when the trigger signal is at a second level, and a controlled circuit selector circuit for setting the trigger signal for S pieces of the control signal preservation/output circuits to the first level, and setting the trigger signal for the rest of the control signal preservation/output circuits to the second level. | 08-13-2009 |
20090237107 | Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same - A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line. | 09-24-2009 |
20090243649 | MEMORY MODULE AND METHOD HAVING IMPROVED SIGNAL ROUTING TOPOLOGY - A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register. | 10-01-2009 |
20090267638 | Apparatus, System and Method of Power State Control - An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch. | 10-29-2009 |
20100134139 | SIGNAL ISOLATORS USING MICRO-TRANSFORMERS - A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals. | 06-03-2010 |
20100176842 | FAIL SAFE I/O DRIVER WITH PAD FEEDBACK SLEW RATE CONTROL - Disclosed are a method, system and apparatus for an improved fail safe I/O driver with pad feedback slew rate control are disclosed. In one embodiment, a pad driver circuit includes a pad node, an NMOS component, a feedback capacitor between the pad node and a gate of the NMOS component to control slew rate across a range of capacitor loads, a switch circuit between the pad node and the feedback capacitor, and a signal generator to generate a signal to control the switch circuit. The switch circuit to maintain a main driver circuit and a pre-driver circuit of the pad driver circuit in a fail safe state when an integrated circuit that includes the pad driver circuit is in the fail safe state. The pad driver circuit may include a PMOS component. | 07-15-2010 |
20100176843 | METHOD AND APPARATUS FOR SETTING SAMPLING POINT OF LOW VOLTAGE DIFFERENTIAL SIGNAL TRANSMITTED BETWEEN FIELD PROGRAMMABLE GATE ARRAYS - A method and apparatus for setting a sampling point of a low voltage differential signal transmitted between Field Programmable Gate Arrays (FPGAs) are provided. The method includes determining in which one a maintenance section or a transition section of a received signal of an initial sampling point is located in, determining a first boundary by shifting the received signal in a first direction if the initial sampling point is located in the maintenance section, determining a second boundary by shifting the first shifted signal in a second direction, and determining a sampling point for determining a sampling reference signal by shifting the second shifted signal in the first direction so that the sampling point may be located at a central position between the first and second boundaries. The method can guarantee the reliability of a data reception by preventing a signal distortion when determining a sampling point in case where the FPGA receives data at a high rate through existing input/output devices. | 07-15-2010 |
20100244890 | Preventing Erroneous Operation in a System Where Synchronized Operation is Required - This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention senses the multiple ready signals and waits until all the finite state machines generate the ready signal. This waiting can be accomplished with a precharge-conditional discharge circuit used for voting. | 09-30-2010 |
20100253383 | CIRCUIT TOPOLOGY FOR MULTIPLE LOADS - A circuit topology for multiple loads includes a driving terminal for transmitting a driving signal, a number of transmitting lines, and a number of loads operable to receive the driving signal from the driving terminal. The number of loads are connected to the driving terminal one by one via the number of transmitting lines. Two transmitting lines of the number of transmitting lines, which are nearest and farthest respectively from the driving terminal, are both greater than widths of the other transmitting lines. | 10-07-2010 |
20110031996 | LOW-JITTER HIGH-FREQUENCY CLOCK CHANNE - According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock signal, and may include a portion of a metal layer of an integrated circuit. In some embodiments, the shielding tunnel may be configured to shield, in at least four directions, the clock channel from other signals, and may include portions of a at least three metal layers of the integrated circuit. The shielding tunnel may be connected to the positive and negative supplies in order to provide the required power for the clock repeaters. | 02-10-2011 |
20110062982 | SEMICONDUCTOR INTEGRATED CIRCUIT - A chip is provided with a specific signal wire and two adjacent signal wires. Output signals based on a specific signal and two adjacent signals are transmitted to the specific signal wire and the two adjacent signal wires respectively. An adjustment coefficient is stored in a memory. The adjustment coefficient is used for reducing an occurrence amount of crosstalk arising between the specific signal wire and the two adjacent signal wires. An adjustment quantity calculation portion calculates an adjustment quantity representing a degree of decrease of a slew rate of the specific signal, based on the adjustment coefficient, the specific signal and the two adjacent signals. A driver adjusts the slew rate of the specific signal based on the adjustment quantity and to transmit one of the output signals corresponding to the specific signal. | 03-17-2011 |
20110074460 | DATA TRANSMISSION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A data transmission circuit includes a data transmission unit and a data receiving unit. The data transmission unit generates transmission data based on first chip data and transmit the transmission data via a Through Silicon Via (TSV). The data receiving unit differentially amplifies the transmission data with respect to a reference voltage to generate second chip data. | 03-31-2011 |
20110074461 | SERIAL OUTPUT CIRCUIT, SEMICONDUCTOR DEVICE, AND SERIAL TRANSMISSION METHOD - In an output circuit having a de-emphasis for use in high-speed serial transmission, a circuit for suppressing a fluctuation of a common mode potential which occurs in output amplitude is provided. A positive pole and a negative pole of an output circuit in a serial transmission device for differential transmission having de-emphasis are connected to the respective outputs of a differential circuit that differentially receives outputs of a detector device for a pattern of data to be transmitted, and a detector device for an inverted pattern of the data to be transmitted. When a specific pattern of data to be transmitted and its reverted pattern appear, a current of the output circuit is compensated by the connected differential circuit, thereby enabling a common mode noise to be prevented. | 03-31-2011 |
20110084724 | UNIVERSAL PINOUT FOR BOTH RECEIVER AND TRANSCEIVER WITH LOOPBACK - An integrated circuit capable of dual configuration of data flow and operable in a plurality of operational modes is provided. The circuit includes eight corner pins, wherein the eight corner pins comprise a first corner pin and a second corner pin on each side of the circuit in each of four side sets, wherein a first corner pin of one side of the circuit is proximate and adjacent to a second corner pin of an adjacent side counterclockwise from the first corner pin and together constitute a paired corner set, each paired corner set comprising a differential input and a differential output. | 04-14-2011 |
20110156749 | High-Speed Standard Cells Designed Using a Deep-Submicron Physical Effect - A system comprises signal paths. There are first through n signal paths, n being a positive integer. A critical one of the first through n signal paths is based on being a respective one of the first through n signal paths having a slowest signal propagation and/or a path in which a signal propagates slower than a clock cycle. The critical one of the first through n signal paths comprises a first size of a standard cell including corresponding logic devices. The non-critical ones of the first through n signal paths comprise a second size of a standard cell including corresponding logic devices, the second size being smaller than the first size. | 06-30-2011 |
20110175642 | SIGNAL ISOLATORS USING MICRO-TRANSFORMERS - A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals. | 07-21-2011 |
20110175643 | METHOD AND APPARATUS FOR HANDLING AN OUTPUT MISMATCH - A system comprises a first signal processing logic module and at least one further signal processing logic module. The system further comprises mismatch handler logic module arranged to detect a mismatch between outputs of the first and at least one further signal processing logic module, the mismatch between outputs indicating a failed operation. The mismatch handler logic module further arranged, upon detection of a mismatch between outputs of the first and at least one further signal processing logic module, to analyse internal states of the first and at least one further signal processing logic module, determine whether the cause of the output mismatch is due to a transient fault, and upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronise the first and at least one further signal processing logic module. | 07-21-2011 |
20110267097 | SEMICONDUCTOR DEVICE INCLUDING SWITCH FOR COUPLING POWER LINE - A semiconductor device whose operational state is switched between a test state and a normal operational state according to a logical value of a signal input from the outside is provided. The semiconductor device includes a first power line, a second power line, a switch that is controlled by a signal line to couple/isolate the first power line to/from the second power line, a control circuit that outputs a control signal, and a state switching circuit that drives the signal line to couple/isolate the first power line to/from the second power line according to a logical value of the control signal when the input signal is one of logical values, whereas the state switching circuit drives the signal line to couple the first power line to the second power line when the first signal is the other logical value. | 11-03-2011 |
20110291697 | DIGITAL LOGIC CIRCUIT AND MANUFACTURE METHOD THEREOF - A digital logic circuit and a manufacture method of the digital logic circuit thereof are provided. The digital logic circuit includes a voltage rail, a ground rail, and a plurality of logic circuit rails, wherein each of the logic circuit rails is electrically connected to the voltage rail and the ground rail. The logic circuit rail includes a logic unit and an auxiliary unit electrically connected to the voltage rail and the ground rail. The logic unit includes a logic voltage end electrically connected to the voltage rail and a logic ground end electrically connected to the ground rail. The auxiliary unit includes an auxiliary voltage end electrically connected to the voltage rail and an auxiliary ground end electrically connected to the ground rail. At least one of the width ratio between the auxiliary voltage end and the logic voltage end and the width ratio between the auxiliary ground end and the logic ground end is greater than 1. | 12-01-2011 |
20120074982 | DEVICE FOR MONITORING THE OPERATION OF A DIGITAL CIRCUIT - A digital electronic circuit includes: a plurality of sequential elements; at least one data-conducting path connecting an input sequential element to a destination sequential element; a clock outputting a clock signal on a clock tree for setting the speed of the sequential elements; a monitoring device receiving, as an input, at least one data signal traveling on a conducting path and arriving at a destination sequential element, the monitoring device including: a module for defining at least one detection window according to the clock tree; and a detector for detecting a transition of each data signal received during a detection window; and wherein each detection window is defined so as to enable the detection or anticipation of a fault corresponding to a violation of the rise time or the maintenance time of a data signal relative to a clock signal edge received by the destination sequential element receiving the data signal. | 03-29-2012 |
20120086469 | REDUCTION OF SIGNAL SKEW - Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced. | 04-12-2012 |
20120126848 | MULTI-CHIP STACKED SYSTEM AND CHIP SELECT APPARATUS THEREOF - A multi-chip stacked system and a chip select apparatus are provided. The chip select apparatus includes n ID code generators and n activation logic units. The first ID code generator generates a first ID code and a second seed code according to a first seed code, and an i | 05-24-2012 |
20120182043 | Method of Half-Bit Pre-Emphasis for Multi-Level Signal - Methods and apparatus for improving transmission channel efficiency are provided. In an example, a digital signal is received. A leading portion of a bit in the digital signal is pre-emphasized. The received digital signal is modulated with a pre-emphasis signal to pre-emphasize a leading portion of the bit in the digital signal. The pre-emphasis signal provides pre-emphasis substantially when a clock is high and the received digital signal transitions. The pre-emphasis signal does not provide pre-emphasis when the received digital signal is low or the received digital signal is unchanged. The pre-emphasized digital signal is then transmitted via the transmission channel. In an example, the received digital signal us a pulse-amplitude modulated multilevel signal. | 07-19-2012 |
20120293198 | ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN - A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to V | 11-22-2012 |
20130002289 | ELECTRONIC APPARATUS, CATEGORY DETERMINATION METHOD FOR TRANSMISSION CABLE AND TRANSMISSION CABLE - An electronic apparatus includes: a receptacle having a plurality of pins for connecting a plug of a transmission cable; and a transmission cable determination section adapted to apply a predetermined voltage to a predetermined one of the pins of the receptacle to determine a category of the transmission cable. | 01-03-2013 |
20130099817 | Sytems and Methods for Propagating Digital Data across an Isolation Barrier - Systems and methods pertaining to propagation of digital data from a transmit side domain to a receive side domain through an intermediate isolation barrier are described. Specifically, a carrier waveform is superimposed upon a first logic level of a digital signal that is referenced to a first local ground. The digital signal with the superimposed first carrier waveform is propagated through the intermediate isolation barrier. On the receive side domain, the propagated digital signal is processed using a second local ground that is different than the first local ground, the processing including the use of the carrier waveform to enforce the first logic level upon an output digital signal generated from the propagated digital signal. | 04-25-2013 |
20130249591 | SYSTEM AND METHOD FOR DECREASING SIGNAL INTEGRITY NOISE BY USING VARYING DRIVE STRENGTHS BASED ON LIKELIHOOD OF SIGNALS BECOMING VICTIMS - A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths. | 09-26-2013 |
20140062527 | ISOLATION RECEIVER - An isolation receiver includes at least one isolation capacitor to provide a first logic signal in response to a second logic signal that is provided by a transmitter. The receiver includes a signal processing circuit to amplify the first logic signal to generate an amplified signal, and the signal processing circuit includes a an amplifier to apply a nonlinear function. A comparator of the receiver provides a third logic signal in response to the amplified signal. | 03-06-2014 |
20150091610 | Self-Leveling Logic Receiver - Various implementations include circuits, devices and/or methods that provide closed-loop feedback crowbar current limiting for logic level-shifting between circuits with different voltage supplies. Some implementations include a level-shift circuit assembly including an input buffer and a current limiter. The input buffer is configured to receive an incoming logic signal that is set relative to a first electrical level, and in response, provide a level-shifted logic signal that is set relative to a second electrical level and is logically consistent with the incoming logic signal. The current limiter is configured to suppress the generation of current associated with the input buffer by providing a bias modification condition to the input buffer, in order to adjust the operation of the input buffer, in response to sensing a voltage difference between the first electrical level and the second electrical level. | 04-02-2015 |
20150145555 | POWER GATE SWITCH ARCHITECTURE - Inventive aspects include a method, apparatus, and system for reducing power switch cells in MTCMOS circuits. Such may include disposing columns of real and virtual power straps orthogonally over rows of logic cells. A first power switch cell can be disposed over a real and a virtual power strap in a first column, and collinear with a first row of logic cells. A second power switch cell can be disposed over a real a virtual power strap in a second column, and collinear with a fifth row of logic cells. A third power switch cell can be disposed over a real a virtual power strap in a third column, and collinear with a third row of logic cells. A fourth power switch cell can be disposed over a real a virtual power strap in a fourth column, and collinear with a seventh row of logic cells. | 05-28-2015 |
20160182027 | NOISE ANALYSIS APPARATUS, ELECTRONIC DEVICE, AND NOISE-SOURCE IDENTIFICATION SYSTEM | 06-23-2016 |