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Test of semiconductor device

Subclass of:

324 - Electricity: measuring and testing

324500000 - FAULT DETECTING IN ELECTRIC CIRCUITS AND OF ELECTRIC COMPONENTS

324537000 - Of individual circuit component or element

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
324766000 With barrier layer 50
Entries
DocumentTitleDate
20090058455Test structure and test method - The present invention discloses a wafer level test structure and a test method; in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other.03-05-2009
20100117676Method and system for non-destructive determination of dielectric breakdown voltage in a semiconductor wafer - According to one exemplary embodiment, a non-destructive method for determining a breakdown voltage of a dielectric layer on a semiconductor substrate includes injecting a test current in increasing ramp steps into the dielectric layer. The method further includes measuring a test voltage across the dielectric layer at each increasing ramp step of the test current. The method further includes detecting a dropped test voltage in response to the increasing ramp steps of the test current. The ramp steps of the test current can be substantially logarithmically increased. The breakdown voltage of the dielectric layer can be designated to be substantially equal to the dropped test voltage.05-13-2010
20080231310FLEXIBLE ON CHIP TESTING CIRCUIT FOR I/O'S CHARACTERIZATION - The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.09-25-2008
20100052727SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME - The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carry out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will resent a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.03-04-2010
20080204066Automatic test equipment capable of high speed test - Automatic test equipment is capable of performing a high-speed test of semiconductor devices, with a low cost and high efficiency. The automatic test equipment (ATE) comprises: an ATE body configured to electrically test semiconductor devices; a field programmable gate array (FPGA) controlling drivers and comparators on the ATE; an accelerator connected to an output terminal of the FPGA and that doubles an operating frequency of the FPGA; and a decelerator connected to an output terminal of the FPGA and that converts an operating frequency of data transferred from the semiconductor device to the operating frequency of the FPGA.08-28-2008
20090066356METHOD AND APPARATUS FOR INTERROGATING AN ELECTRONIC COMPONENT - A method and apparatus for interrogating an electronic component, includes a body having an interface for an interrogating device to use as a conduit in reliably performing multiple discrete interrogations of the electronic component without the interrogating device physically touching the electronic component.03-12-2009
20080258752METHOD AND APPARATUS FOR MEASURING DEVICE MISMATCHES - A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.10-23-2008
20100073022IN-SITU MONITORING AND METHOD TO DETERMINE ACCUMULATED PRINTED WIRING BOARD THERMAL AND/OR VIBRATION STRESS FATIGUE USING A MIRRORED MONITOR CHIP AND CONTINUITY CIRCUIT - A monitoring system includes a monitor chip or chips soldered to a printed wiring board. By mirroring a function IC chip interface with the monitor chip, the consumed and remaining thermal/and or vibration-fatigue life of the function IC chip based on the life-environment actually experienced through monitoring of the monitor chip is readily determined. The monitor chip includes monitoring interconnections and/or circuitry which determines the number and/or location of failed-open solder terminations of the monitor chip.03-25-2010
20100039134HIGH-POWER OPTICAL BURN-IN - Semiconductor lasers are aged to identify weak or flawed devices, resulting in improved reliability of the remaining devices. The lasers can be aged using a high-power optical burn-in that includes providing a high drive current to the lasers for a period of time, and maintaining the ambient temperature of the lasers at a low temperature. After the high-power optical burn-in, the output of the lasers can be measured to determine if the lasers are operating within specifications. Those that are not can be discarded, while those that are can be further aged using a high-temperature thermal burn-in that includes providing a drive current to the lasers while maintaining the ambient temperature of the lasers at a high-temperature.02-18-2010
20100045333GENERATING TEST BENCHES FOR PRE-SILICON VALIDATION OF RETIMED COMPLEX IC DESIGNS AGAINST A REFERENCE DESIGN - This invention (02-25-2010
20100045332TEST CIRCUIT, METHOD, AND SEMICONDUCTOR DEVICE - It is possible to provide a circuit and method for carrying out a parallel test using BOST (Built Out Self Test). The circuit includes first transfer circuits (02-25-2010
20100045331Method of locating failure site on semiconductor device under test - In an analysis of a semiconductor device under test (DUT) using a Thermal Induced Voltage Alteration (TIVA) tool, the TIVA is connected to an output of the DUT and the DC component on the output is decoupled from the TIVA. The remaining AC component from the output is analyzed by the TIVA while scanning the DUT with a scanning laser to identify locations on the DUT that produce signal anomalies at the DUT output.02-25-2010
20100045330APPARATUS FOR TESTING INTEGRATED CIRCUITRY - A testing apparatus for testing integrated circuits mounted in a carrier includes a support assembly. A controller is mounted in the support assembly. The controller is programmed to process test signals from the integrated circuits. A retaining assembly is arranged on the support assembly and is configured to receive and retain the carrier during testing. A displacement mechanism is arranged on the support assembly for displacing the retaining assembly relative to the support assembly into and out of an operative condition. Testing circuitry is operatively connected to the controller and has at least test signal generation and measurement circuitry and adaptor circuitry for operative engagement with the integrated circuits being tested, the adaptor circuitry being configured to provide both a physical and an electrical interface with the integrated circuits.02-25-2010
20100097090PUSHER ASSEMBLIES FOR USE IN MICROFEATURE DEVICE TESTING, SYSTEMS WITH PUSHER ASSEMBLIES, AND METHODS FOR USING SUCH PUSHER ASSEMBLIES - Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment of such a pusher assembly comprises a plate having a first side and a second side opposite the first side. An engagement assembly is removably coupled to the second side of the plate and positioned to contact a microfeature device being tested. The pusher assembly can include an urging member proximate the first side of the plate and configured to move the engagement assembly toward the device being tested. The pusher assembly can also include a heat transfer unit carried by the first side of the plate. In several embodiments, the pusher assembly can further include a plurality of pins carried by the engagement assembly such that the pins extend through the plate and engage the urging member to restrict axial movement of the urging member toward the device being tested.04-22-2010
20100109699METHODS, APPARATUS AND ARTICLES OF MANUFACTURE FOR TESTING A PLURALITY OF SINGULATED DIE - In one embodiment, a method for testing a plurality of singulated semiconductor die involves 1) placing each of the singulated semiconductor die on a surface of a die carrier, 2) mating an array of electrical contactors with the plurality of singulated semiconductor die, and then 3) performing electrical tests on the plurality of singulated semiconductor die, via the array of electrical contactors.05-06-2010
20090045833SEMICONDUCTOR DEVICE - A first power-cutoff switch is disposed between a power line and an internal power line dedicated for a circuit block, and has a current supply capacity having the level at which ON-current can protect an external examination environment. A second power-cutoff switch is disposed between a power line and an internal power line, and has a current supply capacity having the level at which ON-current can supply consumed current of the circuit block. A detecting circuit detects that a voltage of the internal power line matches a reference voltage. The first power-cutoff switch is ON/OFF by an operation state of the circuit block. The second power-cutoff switch is ON by detecting the matching of the volumes with the detecting circuit and is OFF by the ON/OFF operation of the first power-cutoff switch.02-19-2009
20100001754SEMICONDUCTOR TEST DEVICE - It is possible to provide a semiconductor test device capable improving the test efficiency. The semiconductor test device includes: a driver (01-07-2010
20100134135Semiconductor device test apparatus - A semiconductor device test apparatus may include a test handler using a customer tray and a test tray to sequentially transport a plurality of semiconductor devices to a loading part, a soak part, a test part, a desoak part, and an unloading part; and a test head electrically connected to the semiconductor devices in the test tray disposed in the test part to test electrical characteristics of the semiconductor devices. The test part is provided in the test handler such that the test tray is on an upper surface of the test handler. The test head is provided above the test handler such that a lower surface thereof having a test socket provided thereon faces the test part. The semiconductor devices in the test tray disposed in the test part of the test handler are electrically connected to the test socket by a downward movement of the test head.06-03-2010
20100134136OPERATING METHOD OF TEST HANDLER - Operation methods of test handler are disclosed. The pick-and-place apparatus picks up semiconductor devices from first loading compartments arrayed in a matrix on a first loading element, moves, and places onto second loading compartments arrayed in a matrix on a second loading element. Pickers of the pick-and-place apparatus pick up the semiconductor devices from the first loading compartments and place them selectively onto a plurality of adjacent odd rows or a plurality of adjacent even rows of the second loading compartments during one operation. The pick-and-place apparatus includes a relatively large number of the pickers, preferably arrayed in a matrix, and thus performs loading and unloading of semiconductor devices at a relatively high speed.06-03-2010
20080197872SEMICONDUCTOR CHIP, MULTI-CHIP SEMICONDUCTOR DEVICE, INSPECTION METHOD OF THE SAME, AND ELECTRIC APPLIANCE INTEGRATING THE SAME - A disclosed semiconductor chip includes a first connection pad adapted to input an input signal; and a second connection pad adapted to selectively output, according to a test mode signal input to the semiconductor chip, one of the input signal and an output signal from the semiconductor chip.08-21-2008
20100271065SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MEASURING SYSTEM - A semiconductor device includes: a well of a second conductive type formed on or above a semiconductor substrate of a first conductive type; a first diffusion layer of the second conductive type formed in a surface portion of the well; a second diffusion layer of the first conductive type formed separately from the first diffusion layer in the surface portion of the well; first to third first-layer conductive layers formed above the well; and first to third second-layer conductive layers formed above the first to third first-layer conductive layers. The first second-layer conductive layer, the first first-layer conductive layer, the first diffusion layer and the well are conductively connected as a first conductive path. The second second-layer conductive layer, the second first-layer conductive layer, and the second diffusion layer are conductively connected as a second conductive path. The third second-layer conductive layer, and the third first-layer conductive layer are conductively connected as a third conductive path.10-28-2010
20090302880Wide Area Soft Defect Localization - Various apparatus and methods of testing a semiconductor chip for soft defects are disclosed. In one aspect, a method of testing a semiconductor chip that has a surface and plural circuit structures positioned beneath the surface is provided. An external stimulus is applied to a series of fractional portions of the surface to perturb portions of the plural circuit structures such that at least one of the series of fractional portions is smaller than another of the series of fractional portions. The semiconductor chip is caused to perform a test pattern during the application of external stimulus to each of the fractional portions to determine if a soft defect exists in any of the series of fractional portions.12-10-2009
20090302879SEMICONDUCTOR DEVICE - When a stop condition is satisfied, a stop condition determination circuit (12-10-2009
20090039911METHOD TO MONITOR SUBSTRATE VIABILITY - An invention for detecting and reporting a condition is described. The components of the invention comprise an electronic package comprising a substrate with electrically conducting lines electrically connected to an integrated chip, and to a source of voltage. The integrated circuit chip is mounted onto a substrate and electrically connected to at least one electrically conducting line. A sensor, combined with a signal generator, connected to the substrate, is operable to generate an electrical signal upon detection of a condition selected from a condition of the substrate and a condition of an electrical connection to the substrate. The signal generator, after immediately receiving the aforesaid electrical signal from the sensor, emits the warning signal. The warning signal of indicated of an existing defect or a condition which can lower the longevity of the total electronic package.02-12-2009
20090091348CIRCUIT FOR TESTING INTERNAL VOLTAGE OF SEMICONDUCTOR MEMORY APPARATUS - An internal voltage test circuit of a semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during a test mode, and an output selecting unit for outputting the output signal to a data output pad during the test mode, and outputting a data signal to the data output pad during a normal operation mode.04-09-2009
20090091347Emulating Behavior of a Legacy Test System - An apparatus for use in testing a device includes a communication channel having a set of programmable parameters associated therewith. The programmable parameters result in a bias condition on the communication channel. A bias control circuit is used to affect the bias condition that results from the programmable parameters in order to emulate a desired bias condition.04-09-2009
20090091346CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS - A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.04-09-2009
20090267633SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF - A semiconductor device includes: a command control circuit for decoding a command signal to output a test signal and a normal control signal; a normal circuit for performing a predetermined operation in response to the normal control signal; and a test circuit for testing electrical characteristics of unit elements provided in the normal circuit in response to the test signal.10-29-2009
20090267632SYSTEM AND METHOD FOR TESTING A SOLAR PANEL - A system for testing a solar panel is described.10-29-2009
20090243645MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE, A SEMICONDUCTOR WAFER, AND A TEST METHOD - The present invention aims to increase the number of test elements of a TEG without increasing the area of each of slice areas. Test electrode pads are disposed in alignment in one row in each of areas separated from semiconductor chips provided over a semiconductor wafer. Test elements are formed corresponding to these test electrode pads and in areas lying directly therebelow. Electrode terminals of the test elements are electrically coupled to the test electrode pads adjacent to the corresponding electrode pads and the test electrode pads further adjacent thereto with being spaced one test electrode pad apart. Upon testing, probe pins are brought into contact with the odd-numbered test electrode pads to conduct testing. Next, the probe pins are brought into contact with the even-numbered test electrode pads while being shifted by one electrode pad pitch thereby to conduct testing.10-01-2009
20090237105Semiconductor Arrangement and Method for the Measurement of a Resistance - A semiconductor arrangement has a semiconductor body (CP), comprising a semiconductor layer (HL) with a first (AB09-24-2009
20090237104TESTING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND INFORMATION RECORDING MEDIUM - A testing method of semiconductor integrated circuit wherein the quality of diffusion for semiconductor chips can be tested before the semiconductor chips become packaged semiconductor integrated circuits is provided. Input data is set, and circuit current values I(L) and I(H) obtained for each of a plurality of circuit areas are compared with first test pass ranges I09-24-2009
20090237103IMAGE SENSOR MONITOR STRUCTURE IN SCRIBE AREA - A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.09-24-2009
20100019796METHOD FOR EVALUATING SILICON WAFER - The present invention is a method for evaluating a silicon wafer by measuring, after fabricating a MOS capacitor by forming an insulator film and one or more electrodes sequentially on a silicon wafer, a dielectric breakdown characteristic of the insulator film by applying an electric field from the electrodes thus formed to the insulator film, the method in which the silicon wafer is evaluated at least by setting an area occupied by all the electrodes thus formed to 5% or more of an area of a front surface of the silicon wafer when the one or more electrodes are formed. This provides an evaluation method that can detect a defect by a simple method such as the TDDB method with the same high degree of precision as that of the DSOD method.01-28-2010
20100085073ACCURATE MEASURING OF LONG STEADY STATE MINORITY CARRIER DIFFUSION LENGTHS - Surface photo-voltage measurements are used to accurately determine very long steady state diffusion length of minority carriers and to determine iron contaminant concentrations and other recombination centers in very pure wafers. Disclosed methods use multiple (e.g., at least two) non-steady state surface photovoltage measurements of diffusion length done at multiple (e.g., at least two) modulation frequencies. The measured diffusion lengths are then used to obtain a steady state diffusion length with an algorithm extrapolating diffusion length to zero frequency. The iron contaminant concentration is obtained from near steady state measurement of diffusion length at elevated frequency before and after iron activation. The concentration of other recombination centers can then be determined from the steady state diffusion length and the iron concentration measured at elevated frequency.04-08-2010
20090212811Semiconductor device and method for testing the same - A method for testing a semiconductor device having plural transmitting (TX) circuits and plural receiving (RX) circuits at a low cost and in a short time. The semiconductor device includes two or more pairs of transmitting and receiving circuits. Each of the transmitting circuits converts parallel data to serial data and transmits the converted serial data to external while each of the receiving circuits receives serial data from external and converts the received serial data to parallel data. Furthermore, the semiconductor device includes a device that enables two or more selected pairs of transmitting and receiving circuits to be connected serially and alternately. The semiconductor device can be configured so that the serially connected transmitting or receiving circuit in the first stage inputs a test signal to be compared with a signal output from the serially connected receiving or transmitting circuit in the last stage.08-27-2009
20090189631MOVEMENT APPARATUS AND ELECTRONIC DEVICE TEST APPARATUS - An air cylinder raising and lowering a pickup head for holding an IC device in an electronic device test apparatus, the air cylinder includes a cylinder tube; a piston; a first hollow chamber formed below the piston; a second hollow chamber formed above the piston and being larger than the first hollow chamber in terms of a pressure receiving area of the piston; and a rod with one end coupled with the piston and the other end coupled with the pickup head. The first hollow chamber is connected to the air feed device via a first feed system in which the air feed is secured even if the electric power supply of the electronic device test apparatus is cut off, and the second hollow chamber is connected to the air feed device via a second feed system having a shutoff valve.07-30-2009
20090121738SEMICONDUCTOR TEST DEVICE - A semiconductor test device of the present invention for conducting a test on a device under test, includes: a plurality of comparison units which compare a signal obtained from the device under test with a predetermined reference voltage and output a comparison result; a plurality of measuring units which are provided in correspondence with the plurality of comparison units, and measure a time from when a measurement start signal is input thereto to when the comparison result from a corresponding comparison unit is input thereto, and output a measuring result; a start signal output unit which outputs the measurement start signal at a same timing to each of the plurality of measuring units; and a computation unit which computes time differences between a plurality of signals obtained from the device under test based on the measuring results of the plurality of measuring units.05-14-2009
20100007367Packaged Die Heater - A heater for heating packaged die for burn-in and heat testing is described. The heater may be a ceramic-type heater with a metal filament. The heater may be incorporated into the integrated circuit package as an additional ceramic layer of the package, or may be an external heater placed in contact with the package to heat the die. Many different types of integrated circuit packages may be accommodated. The method provides increased energy efficiency for heating the die while reducing temperature stresses on testing equipment. The method allows the use of multiple heaters to heat die to different temperatures. Faulty die may be heated to weaken die attach material to facilitate removal of the die. The heater filament or a separate temperature thermistor located in the package may be used to accurately measure die temperature.01-14-2010
20090251165METHOD FOR CONTINUITY TEST OF INTEGRATED CIRCUIT - The present invention provides a method for continuity test of integrated circuit. By using both pins of integrated circuit to measure a current of an electrostatic discharge device, the contact resistance of the integrated circuit can be obtained by calculating. The method comprises the steps: First, a DUT (device under test) is provided, and the DUT includes a second pin and the second pin connecting zero reference potential. Then, a voltage is applied to a first pin of DUT. Finally, the current through said first pin and said second pin would be measured. Therefore, the testing result of the DUT could be more precise and the quality of the DUT would be made sure.10-08-2009
20100090718SEMICONDUCTOR DEVICE, AND DEVELOPMENT SUPPORTING DEVICE - States of LSI internal signals (04-15-2010
20090039912Method of Acceptance for Semiconductor Devices - A method of accepting semiconductor chips is provided using on-chip parametric measurements. An on-chip parametric measurement structure is determined for each parameter in a set of parametric acceptance criteria. An on-chip parametric measurement macro is included in a design of each semiconductor chip for each identified on-chip parametric measurement structure. Each on-chip parametric measurement macro is tested to determine compliance of the semiconductor chip to the set of parametric acceptance criteria. Compliance to the set of parametric acceptance criteria is validated.02-12-2009
20100033204SEMICONDUCTOR INSPECTION APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a wafer-level burn-in test, a sufficient power supply current must be supplied to operate semiconductor integrated circuits on a wafer, but the power supply current sometimes exceeds an allowable current level due to such as variations in transistor characteristics of the semiconductor integrated circuits. An operation power supply current at the burn-in test is measured by a current measurement device (02-11-2010
20100033203Methods And Apparatus For Translated Wafer Stand-In Tester - A translated wafer stand-in tester, being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The translated wafer stand-in tester may include several stacked and attached layers, at least one internal layer including electronic components operable to interact with a test system.02-11-2010
20090058451Adaptive test time reduction for wafer-level testing - A method is provided for dynamically increasing or decreasing the amount of test data that is applied to die locations on a wafer under test. As on-wafer locations are traversed and tested, the amount of test stimuli applied to subsequent locations is adjusted. This adjustment is based upon the results of previously tested locations. The effect is that the test program detects regions of the wafer that are more likely to fail and applies more complete testing to these areas. Other areas of the wafer may receive reduced testing. By automatically adapting the test mix to suit the potential failure patterns, wafer testing time is reduced.03-05-2009
20090189632Test board used for a reliability test and reliability test method - To conduct a reliability test for a tape automated bonding (TAB) package under a state being close to a mounting state to a product, the TAB package (07-30-2009
20090153175ELECTRONIC DEVICE TEST APPARATUS AND METHOD OF SETTING AN OPTIMUM PUSHING CONDITION FOR CONTACT ARM OF ELECTRONIC DEVICE TEST APPARATUS - An electronic device test apparatus comprises: a contact arm making an IC device move and pushing it against a socket 301; a control device controlling the contact arm; an instructing unit instructing the control device on a pushing torque of the contact arm; an acquiring unit acquiring from the tester the result whose a test of an IC device is executed when the contact arm pushes the IC device against the socket according to the torque instructed by the instructing unit; a correction unit correcting the torque on which the control device is instructed on the basis of the test result acquired by the acquiring unit; and a setting unit setting the stroke at the time when the test result is normal as an optimum stroke if the torque was not corrected by the correction unit.06-18-2009
20090153178METHOD FOR TRANSFERRING TEST TRAYS IN A SIDE-DOCKING TYPE TEST HANDLER - The present invention relates to a test tray for a test handler. According to this invention, there is disclosed a technique that an insert loaded in a loading part which is arranged in a matrix pattern in a frame of the test tray allows an amount and direction of free movement thereof to be determined in accordance with a location of the loading part, where the insert is loaded, on the matrix, thereby enabling a thermal expansion or contraction of a match plate or the test tray to be compensated.06-18-2009
20090153176Semiconductor device - Disclosed is a semiconductor device including chips having output terminals connected in common to an external terminal. Each of the chips includes a data input and output section that provides a difference during testing between a first driving capability setting the output terminal to a first power supply potential side and a second driving capability setting the output terminal to a second power supply potential side. During testing, the second driving capability is set so as to be higher than the first driving capability. The output signal level from each chip to the terminal equal to the second power supply potential indicates a fail, and the output signal level from each chip to the terminal equal to the first power supply potential indicate a pass. Under this condition, if at least one or more of the multiple chips outputs a fail signal, the second power supply potential is delivered to the external terminal to which the terminals are connected in common. A test method for the semiconductor memory is also disclosed (FIG. 06-18-2009
20090153174SIMPLE AND EFFECTIVE METHOD TO DETECT POLY RESIDUES IN LOCOS PROCESS - A test structure which can be used to detect residual conductive material such as polysilicon which can result from an under etch comprises a PMOS transistor and an OTP EPROM floating gate device. By testing the devices using different testing parameters, it can be determined whether residual conductive material remains subsequent to an etch, and where the residual conductive material is located on the device. A method for testing a semiconductor device using the test structure is also described.06-18-2009
20080265932SEMICONDUCTOR TEST APPARATUS - A semiconductor test apparatus including a test apparatus body generating a test pattern supplied to a semiconductor device; a test head directly contacting the semiconductor device and supplying to the semiconductor device the generated test pattern; a cable passing the test pattern from the test apparatus body to the test head; a holding platform holding the test head in a movable manner; and a movable support section holding the cable, moving in a direction to release tension on a side closer to the test head than the test apparatus body in a case where tension arises in the cable because the test head moves on the holding platform, and moving in a direction to pull the cable on a side closer to the test head than the test apparatus body in a case where slack arises in the cable because the test head moves on the holding platform is provided.10-30-2008
20100141292Method and system for measuring film stress in a wafer film - In a MEMS wafer, film stresses are measured by placing an inductor array over or under the wafer and measuring inductance variations across the array to obtain a map defining the amount of bowing of the wafer.06-10-2010
20090309624Method and Device of Measuring Interface Trap Density in Semiconductor Device - A method is provided for measuring interface trap density in a semiconductor device. In the method, measurement parameters are input to a host computer. A pulse condition is set at a pulse generator using the measurement parameters. A pulse of a predetermined frequency generated by the pulse generator is applied to a gate of a transistor, and a charge pumping current is measured from a bulk of the transistor. A charge pumping current measurement may be repeated for a plurality of frequencies while changing the frequency until a set frequency is reached. A pure charge pumping current is calculated for each frequency where a gate tunneling leakage current is removed from the charge pumping current measured for each frequency. Interface trap density is calculated from the calculated pure charge pumping current for each frequency.12-17-2009
20080204067SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME - The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.08-28-2008
20090309623Method for Assessment of Material Defects - A method is provided for measuring defects in semiconductor materials. In one embodiment the method includes placing deuterium in the material and directing an ion beam onto the material to cause a nuclear reaction with the deuterium. Products of the nuclear reaction are analyzed (NRA) to measure the concentration of defects. In other embodiments, a spectroscopic technique is used to detect the deuterium taggant. Lattice defect or total defect occurrences can be selected by selecting the method of placing deuterium in the sample. Defect concentration vs. depth below the surface of material can be determined by varying the energy of the ion beam or by measuring energy profiles of products of the nuclear reaction. The method may be applied to wafers, pixels or other forms of semiconductor materials and may be combined with X-ray analysis of elements on the material.12-17-2009
20090295421TEST PATTERN OF SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF TESTING DEVICE USING TEST PATTERN - Disclosed are a test pattern of a semiconductor device, a method of manufacturing the same, and a method of testing the device using the test pattern. The test pattern includes a lower metal pattern part formed over a semiconductor substrate, an intermetal insulating film formed over the lower metal pattern part, and upper metal pattern test parts formed over the intermetal insulating film such that the upper metal pattern parts are separated from each other by a designated distance.12-03-2009
20100085072DETECTION CONTROL CIRCUIT FOR ANTI-LEAKAGE - The present invention discloses a detection control circuit for preventing a leakage current, which comprises a register unit comprising a clock signal input terminal for receiving a clock signal; a reset signal input terminal, for receiving a reset signal; a signal generating terminal, for generating a logic signal; and a logic gate, coupled to said register unit, comprising a first signal input terminal for receiving said logic signal; a second signal input terminal for receiving a control signal; and a signal output terminal, for outputting an output signal according to said logic signal and said control signal; wherein said control signal controls said logic gate so as to keep said output signal to be in a fixed state which detects a leakage current in an integrated circuit due to the process flaw.04-08-2010
20090206869ELECTROMIGRATION TESTER FOR HIGH CAPACITY AND HIGH CURRENT - An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT.08-20-2009
20090206870METHOD FOR ANALYZING IC DEVICES AND WAFERS - A method for analyzing Integrated circuit (IC) devices is provided. The method comprises the following steps: dividing an IC device into n working units, wherein each working unit causes a corresponding current dissipation; selecting n operation parameters, wherein each of the operation parameters variably corresponds to the current dissipation of each working unit; selecting m sets of the operation parameters and separately operating the IC device under the m sets of the operation parameters, wherein m is not smaller than n, and obtaining the total current dissipations of the IC device; computering m sets of current dissipation data of the working units corresponding to the m sets of operation parameters by using the total current dissipations; computering a basic current dissipation of the IC device by using the total current dissipations of the IC device and the obtained corresponding current dissipation data set of the working units; and determining the defective working units by comparing the obtained data with the standard data, respectively.08-20-2009
20090206868METHODOLOGIES AND TOOL SET FOR IDDQ VERIFICATION, DEBUGGING AND FAILURE DIAGNOSIS - Quiescent supply current (I08-20-2009
20090140761METHOD OF TESTING SEMICONDUCTOR DEVICE - A method of testing a semiconductor device, which can reduce a period of time for testing a packaged semiconductor chip. First, semiconductor chips to be tested are classified in a lot unit. The semiconductor chips are fist tested in units of lots. The defective semiconductor chips among the semiconductor chips of a predetermined number of lots that are first time tested are collectively retested. First test data regarding the semiconductor chips may be classified and stored for each respective lot. Retest data regarding the semiconductor chips may be classified and stored for each respective lot. Test data regarding the semiconductor chips may be classified and stored into first test data and retest data for each respective lot.06-04-2009
20090128182DRIVER CIRCUIT AND TEST APPARATUS - Provided is a driver circuit that has a first operational mode and a second operational mode and outputs an output signal according to an input signal. The driver circuit includes a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, is controlled to be disabled; a high precision driver section that, in the first operational mode, is controlled to be disabled and, in the second operational mode, outputs a source power having a predetermined voltage; and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, receives the source power from the high precision driver section, generates the output signal according to the input signal, and outputs the thus generated signal to the outside.05-21-2009
20080315906FAULTY DANGLING METAL ROUTE DETECTION - A system is provided that facilitates locating long dangling metal routes in a semiconductor chip design. The system includes mechanisms for partitioning metal features of the chip design to discover dangling metal routes that could be potential violations. The system further comprises mechanisms for determining if the dangling metal routes of the chip design exceed a length limit that could result antenna violations, undesired noise in the circuit, circuitry breakdown or the like. The system enables excessively long dangling metal routes to be allowed as exceptional cases. Machine learning is provided to receive feedback to refine the exceptional cases and enable more efficient fault detection.12-25-2008
20080211531INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION - Methods for testing a semiconductor circuit (09-04-2008
20090278562Test Device and Test Method for Semiconductor Device - The objective of this invention is to provide a test device that can perform a variety of function tests with a relatively simple constitution. The test device is for testing semiconductor device 1, which contains input terminal IN, output terminal OUT and control terminal CTRL, and whose output terminal is in the high-impedance state corresponding to the control signal applied to control terminal CTRL. The test device comprises test signal supply circuit 11-12-2009
20090289654SYSTEM AND METHOD FOR REDUCING TEMPERATURE VARIATION DURING BURN IN - Systems and methods for reducing temperature variation during burn-in testing. In one embodiment, power consumed by an integrated circuit under test is measured. An ambient temperature associated with the integrated circuit is measured. A desired junction temperature of the integrated circuit is achieved by adjusting a body bias voltage of the integrated circuit. By controlling temperature of individual integrated circuits, temperature variation during burn-in testing can be reduced.11-26-2009
20090289653Inspection apparatus and method for semiconductor IC - The connection between a PTC element 11-26-2009
20090128184Testing High Frequency Signals on a Trace - A system, apparatus and method for testing and measuring high frequency signals on a trace is described. In one embodiment of the invention, a footprint is manufactured on a trace to allow the testing of a signal while reducing the amount of distortion caused by prior art structures and methods. The footprint is designed to reduce stub effects and capacitance on a signal being communicated on the trace.05-21-2009
20090261854AUTOMATED LOADING/UNLOADING OF DEVICES FOR BURN-IN TESTING - The automatic loading and unloading of devices for burn-in testing is facilitated by loading burn-in boards in a magazine with the stacked boards in the magazine moved into and out of a burn-in oven by means of a trolley. The trolley can include an elevator whereby a plurality of magazines can be stacked in the oven for the simultaneous burn-in testing of devices mounted on the burn-in boards. Each board has rollers on one end which are engagable by pneumatically actuated cam mechanisms for inserting the board into an electrical contact in the oven for burn-in tests. Preferably, the cam mechanisms allow for extraction of a single board for inspection.10-22-2009
20090261853Semiconductor device and method of testing the same - An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DC10-22-2009
20080231307TESTING METHOD USING A SCALABLE PARAMETRIC MEASUREMENT MACRO - Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts.09-25-2008
20100283499NON-CONTACT TESTING OF PRINTED ELECTRONICS - Apparatus and methods for non-contact testing of electronic components printed on a substrate (11-11-2010
20100207655Method and Apparatus for Small Die Low Power System-on-chip Design with Intelligent Power Supply Chip - A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.08-19-2010
20100102843SEMICONDUCTOR TEST HEAD APPARATUS USING FIELD PROGRAMMABLE GATE ARRAY - A semiconductor test head apparatus using a field programmable gate array (FPGA) is disclosed. A semiconductor test head apparatus using a field programmable gate array, includes a pattern generator for generating a predetermined memory test pattern, a driver/comparator unit comprising a first transceiver which performs a driver function capable of recording a memory test pattern generated from the pattern generator in a device under test and a comparator function capable of comparing a level of a signal read by the device under test with a predetermined high-level reference value, and a second transceiver which performs the driver function and a comparator function capable of comparing a level of a signal read by the device under test with a predetermined low-level reference value, and a connection unit for electrically connecting the first transceiver in parallel to the second transceiver, and connecting the first transceiver and the second transceiver to the device under test.04-29-2010
20100102844PROXIMITY CHARGE SENSING FOR SEMICONDUCTOR DETECTORS - A non-contact charge sensor includes a semiconductor detector having a first surface and an opposing second surface. The detector includes a high resistivity electrode layer on the first surface and a low resistivity electrode on the high resistivity electrode layer. A portion of the low resistivity first surface electrode is deleted to expose the high resistivity electrode layer in a portion of the area. A low resistivity electrode layer is disposed on the second surface of the semiconductor detector. A voltage applied between the first surface low resistivity electrode and the second surface low resistivity electrode causes a free charge to drift toward the first or second surface according to a polarity of the free charge and the voltage. A charge sensitive preamplifier coupled to a non-contact electrode disposed at a distance from the exposed high resistivity electrode layer outputs a signal in response to movement of free charge within the detector.04-29-2010
20080246505SEMICONDUCTOR DEVICE TEST SYSTEM AND METHOD - A semiconductor device test method and system. One embodiment provides a method for testing semiconductor devices forming a group of semiconductor devices to be tested. For addressing or selection of one of the semiconductor devices of the group, at least two different signals are supplied to the respective semiconductor device to be addressed or selected via at least two different semiconductor device connections.10-09-2008
20090167340SEMICONDUCTOR CHIP TEST APPARATUS AND TESTING METHOD - A semiconductor chip test apparatus includes a plurality of power supply units, each supplying power to a semiconductor chip having a power input terminal, and a tester configured to measure an output current of at least one of the plurality of power supply units, and to generate a switching control signal when the measured output current is greater than a predetermined current. The semiconductor chip test apparatus also includes a plurality of relays each arranged between a common ground of the tester and a different ground of the semiconductor chip. Further, the semiconductor chip test apparatus includes a relay controller, such as a control bit generator, configured to selectively close one or more of the plurality of relays in response to the switching control signal from the tester.07-02-2009
20090167339Contactless Testing of Wafer Characteristics - Systems and methods are provided for contactless testing of a wafer containing at least one integrated circuit. A test component responds to a supply voltage to indicate at least one property of the wafer. A voltage source wirelessly receives power from an external source and produces the supply voltage. A reference generator generates a reference voltage, having a known magnitude, from the supply voltage. A voltage evaluation component modifies the response of the test component as to represent a magnitude of the supply voltage.07-02-2009
20080278190Testing fuse configurations in semiconductor devices - Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal.11-13-2008
20080278189TEST CIRCUIT FOR PERFORMING MULTIPLE TEST MODES - A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse.11-13-2008
20080290890TESTING SYSTEM FOR TESTING ELECTRONIC ASSEMBLY - A testing system for testing performance of a number of image sensor modules includes a data transforms module, a number of selection switches and a testing processor. The data transform module has a pin assembly corresponding to the input/output pin assembly. The pin assembly includes a first pin and a second pin. The selection switches are configured for selecting the high level signal or the low level signal and providing the signal level to the control signal pins of the electronic assemblies. The testing processor is electronically connected to the data transform module and configured for processing data from the data transform module. In testing, the image sensor modules coupled together through a base do not need to be separated from each other, thus facilitating the next process. Therefore, the failure rate of the image sensor modules is decreased and cost is reduced.11-27-2008
20090033351TEST STRUCTURE FOR ELECTROMIGRATION ANALYSIS AND RELATED METHOD - A test structure for electromigration and related method are disclosed. The test structure may include an array of a plurality of multilink test sets, each multilink test set including a plurality of metal lines positioned within a dielectric material and connected in a serial configuration; each multilink test set being connected in a parallel configuration with the other multilink test sets, the parallel configuration including a first electrical connection to a cathode end of a first metal line in each multilink test set and a second electrical connection to an anode end of a last metal line in each multilink test set.02-05-2009
20100201395Semiconductor device and defect analysis method for semiconductor device - A semiconductor device and a defect analysis method of a semiconductor device, in which a failure location can be easily identified. The semiconductor device is provided with at least 2N resistor patterns having a fixed form, and being divided into N groups;08-12-2010
20080238470OPERATING METHOD OF TEST HANDLER - Operation methods of test handler are disclosed. The pick-and-place apparatus picks up semiconductor devices from first loading compartments arrayed in a matrix on a first loading element, moves, and places onto second loading compartments arrayed in a matrix on a second loading element. Pickers of the pick-and-place apparatus pick up the semiconductor devices from the first loading compartments and place them selectively onto a plurality of adjacent odd rows or a plurality of adjacent even rows of the second loading compartments during one operation. The pick-and-place apparatus includes a relatively large number of the pickers, preferably arrayed in a matrix, and thus performs loading and unloading of semiconductor devices at a relatively high speed.10-02-2008
20090085599Semiconductor device having ESD protection circuit and method of testing the same - A semiconductor device having an electrostatic discharge (ESD) protection circuit and a method of testing the same may provided. The semiconductor device may include one or more stacked chips, each stacked chip may include a test circuit configured to output a test control signal and a selection control signal in response to a test enable signal, an internal circuit configured to perform an operation and output a plurality of test signals in response to the test control signal, at least one multiplexer (MUX) configured to select and output one of the plurality of test signals based on the selection control signal, at least one test pad configured to receive the selected test signal, and at least one electrostatic discharge (ESD) protection circuit configured to discharge static electricity applied through the test pad externally.04-02-2009
20090128183DEVICE FOR MEASURING THICKNESS AND SQUARE RESISTIVITY OF INTERCONNECTING LINES - A microelectronic device comprising one or several metallic levels provided with one or several superposed metallic interconnecting levels and at least one test structure: 05-21-2009
20090160476FAILURE DETECTION DEVICE FOR POWER CIRCUIT INCLUDING SWITCHING ELEMENT - A failure detection device detects the voltage across the main electrodes of an IGBT via a diode. The failure detection device determines occurrence of short-circuit failure in the IGBT when the anode voltage of the diode is lower than a first predetermined reference voltage. Determination can be made, excluding the case of a proper operation corresponding to a flywheel diode in an ON state, preferably together with the condition that the anode voltage of the diode is higher than a second predetermined reference voltage.06-25-2009
20090160475Test pin reduction using package center ball grid array - An apparatus and method for reducing the number of package pins in a chip package which must be budgeted for test purposes. In one embodiment, the invention achieves this by housing test balls in the depopulated center of a package ball array. The test balls are used to test a chip package prior to connection with a printed wiring board (PWB)/printed circuit board (PCB). After tests are completed, and when the chip package is connected to a PWB/PCB, the test balls may be left electrically isolated and unconnected. In another embodiment, the test balls are located in previously unused interstitial sites in a package ball array.06-25-2009
20090128181DRIVER CIRCUIT AND TEST APPARATUS - Provided is a driver circuit that includes a first operational mode and a second operational mode and outputs an output signal according to an input signal, including a first driver section that, in the first operational mode, generates and outputs the output signal according to the input signal and, in the second operational mode, outputs a power supply power having a predetermined voltage and a second driver section that, in the first operational mode, receives the output signal output by the first driver section and outputs the received signal to the outside and, in the second operational mode, generates the output signal according to the input signal and outputs the thus generated signal to the outside. The second driver section includes a first transistor that, in the second operational mode, generates the output signal by operating according to the input signal and receives the power supply power from the first driver section and a second transistor that, in the second operational mode, operates differentially with respect to the first transistor and receives the power supply power from the first driver section commonly with the first transistor.05-21-2009
20090134904ANALOG IC HAVING TEST ARRANGEMENT AND TEST METHOD FOR SUCH AN IC - An integrated circuit (IC) comprises a plurality of analog stages (05-28-2009
20090134903LOOP-BACK TESTING METHOD AND APPARATUS FOR IC - A test system for testing operability of integrated circuits includes: a first IC, for modulating a first signal to generate a first modulated signal and transmitting the first modulated signal, and for receiving a second modulated signal and demodulating the second modulated signal to generate a second signal; a first loop antenna, coupled to the first IC, for receiving the first modulated signal and sending the first modulated signal back to the first IC as the second modulated signal; and a tester circuit coupled to the first IC, for generating the first signal to the first IC, receiving the second signal from the first IC, and comparing the first signal and the second signal to determine the operability of the first IC.05-28-2009
20090015287APPARATUS FOR TESTING AN OBJECT - An apparatus for testing an object includes a test chamber, a guiding member, testing units and a transferring unit. The test chamber is configured to receive the object. The guiding member is arranged extending along a first direction in the test chamber. The testing units are movably connected to the guiding member to test electrical characteristics of the object. The transferring unit is arranged in the test chamber to load the object into one of the testing units and unload the object from one of the testing units. The testing units may be transferred to a position for repair without suspension of the apparatus. The object may be tested using another testing unit while the other testing unit is being repaired.01-15-2009
20090102503SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, INTERCHIP INTERCONNECT TEST METHOD, AND INTERCHIP INTERCONNECT SWITCHING METHOD - A semiconductor device is provided with a first wiring (04-23-2009
20090085598INTEGRATED CIRCUIT TEST SYSTEM AND METHOD WITH TEST DRIVER SHARING - An integrated circuit test system and method for testing integrated circuits or chips is disclosed. One embodiment provides a test signal from a test driver via a primary test channel and distributed via parallel wiring paths to a plurality of contact pads of one or more integrated circuits or chips under test. At least one operational amplifier is arranged in the wiring path connected to the contact pads of the integrated circuits or chips.04-02-2009
20090189630ANGULAR SPECTRUM TAILORING IN SOLID IMMERSION MICROSCOPY FOR CIRCUIT ANALYSIS - A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.07-30-2009
20090096478RECONFIGURABLE CONNECTIONS FOR STACKED SEMICONDUCTOR DEVICES - Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.04-16-2009
20090201043Crack Sensors for Semiconductor Devices - Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure.08-13-2009
20090153177SEPARATE TESTING OF CONTINUITY BETWEEN AN INTERNAL TERMINAL IN EACH CHIP AND AN EXTERNAL TERMINAL IN A STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device is disclosed which is capable of conducting a test to determine whether or not there is continuity between an external terminal and a corresponding internal terminal in each chip, on an internal terminal-in each chip basis. The semiconductor device includes continuity test dedicated terminals for each chip, and continuity test elements each connected between an internal terminal in each chip and a continuity test dedicated terminal associated with the chip. A voltage is applied between an external terminal associated with an internal terminal whose connection status is to be checked and a continuity test dedicated terminal associated with a chip which includes the internal terminal such that a continuity test element associated with the internal terminal is rendered conductive. Thereafter, the value of current that flows through the continuity test element is measured to determine the connection status of the internal terminal.06-18-2009
20090102502PROCESS TESTERS AND TESTING METHODOLOGY FOR THIN-FILM PHOTOVOLTAIC DEVICES - The present invention generally relates to process testers and methods of fabricating the same using standard photovoltaic cell processes. In particular, the present invention relates to process tester layouts defined by laser scribing, methodology for creating process testers, methodology of using process testers for photovoltaic line diagnostics, placement of process testers in photovoltaic module production, and methodology for creating design rule testers.04-23-2009
20090102501TEST STRUCTURES FOR E-BEAM TESTING OF SYSTEMATIC AND RANDOM DEFECTS IN INTEGRATED CIRCUITS - In accordance with the invention, there are electron beam inspection systems, electron beam testable semiconductor test structures, and methods for detecting systematic defects, such as, for example contact-to-gate shorts, worm hole leakage paths, holes printing issues, and anomalies in sparse holes and random defects, such as, current leakage paths due to dislocations and pipes during semiconductor processing.04-23-2009
20090251166BALL GRID ARRAY CONNECTION MONITORING SYSTEM AND METHOD - A system for monitoring the connection on an integrated circuit ball grid array (BGA) comprises a connection indicator circuit coupled to at least one monitor pin of the BGA and configured to detect a pin connection failure of the BGA based on a signal change associated with the at least one monitor pin.10-08-2009
20100013512APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST - A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.01-21-2010
20100156451METHOD AND SYSTEM FOR MEASURING LASER INDUCED PHENOMENA CHANGES IN A SEMICONDUCTOR DEVICE - A method and system for measuring laser induced phenomena changes of at least one of a resistance, a capacitance and an inductance in a semiconductor device. The method comprises applying a biasing voltage from an emitter-follower circuit to a device under test (DUT); inducing said changes in the DUT; and measuring a voltage change in a collector portion of the emitter-follower circuit as a measure for said changes.06-24-2010
20090315584MEASURING BOARD FOR EXAMINING DIFFERENT TYPES OF SECTIONS OF MCP PRODUCT - A measuring board includes: a first memory section measuring socket having a first memory section measuring socket terminal, the first memory section measuring socket terminal being connected to a first memory section terminal of a first memory section of an MCP product; and a second memory section measuring socket having a second memory section measuring socket terminal, the second memory section measuring socket terminal being connected to a second memory section terminal of a second memory section of the MCP product, and the second memory section measuring socket terminal is connected to the first memory section measuring socket terminal.12-24-2009
20100156452TESTING APPARATUS AND METHOD FOR TESTING A SEMICONDUCTOR DEVICES ARRAY - A testing apparatus and a method for testing a semiconductor devices array, which includes a plurality of rows and a plurality of columns, are provided. The testing apparatus includes a first testing circuit and a second testing circuit. The first testing circuit connects and transmits a clock signal, an input command signal and a data signal to at least one of the rows of the semiconductor devices array. The second testing circuit connects and transmits a selecting signal to at least one of the columns of the semiconductor devices array. Between two devices in a row, a difference in arrival times of the clock signal, a difference in arrival times of the input command signal, and a difference in arrival times of the data signal are equal.06-24-2010
20100156453Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits - Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.06-24-2010
20100176838SEMICONDUCTOR DEVICE AND TEST METHOD - A semiconductor device includes a first circuit block, a second circuit block, a first lead-out line coupled to the first circuit block, a second lead-out line coupled to the second circuit block, a first pad coupled to the first lead-out line, a second pad coupled to the second lead-out line, and a shielding line provided between the first lead-out line and the second lead-out line.07-15-2010
20100176836Wafer Level Burn-In and Electrical Test System and Method - A burn-in and electrical test system (07-15-2010
20100182035SEMICONDUCTOR DEVICE TEST APPARATUS INCLUDING INTERFACE UNIT AND METHOD OF TESTING SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor device test apparatus is provided. The semiconductor device test apparatus includes a test unit on which a semiconductor device under test is disposed, and an automatic test equipment (ATE) unit that inputs a test signal to the test unit and reads a test result signal output by the test unit. The semiconductor device test apparatus includes an interface unit that is interposed between the test unit and the ATE unit, and that compares the test signal with the test result signal and outputs to the ATE unit comparison signals indicating whether the semiconductor device is a failure or not or whether a specific bit failure has occurred or not.07-22-2010
20100013515ELECTROSTATIC DISCHARGE PROTECTION DEVICE, METHOD OF MANUFACTURING THE SAME, METHOD OF TESTING THE SAME - An electrostatic discharge protection device, a method of manufacturing the same, and a method of testing the same. The electrostatic protection device includes a plurality of device isolation regions formed in a semiconductor substrate at a predetermined width and a predetermined depth that each sequentially increase from a circuit device formation region of the semiconductor substrate to a ground region of the semiconductor substrate, a plurality of gate electrodes formed over the semiconductor substrate in spaces between adjacent ones of the device isolation regions, and a plurality of source regions and drain regions formed in the semiconductor substrate at both lateral sides of the gate electrode.01-21-2010
20090079463Local defect memories on semiconductor substrates in a stack computer - A reconfigurable high performance computer includes a stack of semiconductor substrate assemblies (SSAs). Some SSAs involve FPGA dice that are surface mounted, as bare dice, to a semiconductor substrate. Other SSAs involve memory dice that are surface mounted to a semiconductor substrate. Elastomeric connectors are sandwiched between, and interconnect, adjacent semiconductor substrates proceeding down the stack. Each SSA includes a local defect memory and a self-test mechanism. The self-test mechanism periodically tests the SSA and its interconnects, and stores resulting defect information into its local defect memory. The computer is configured to realize a user design and then is run. A defect is then detected. If the defect is determined to be inma part of the computer used in the realization of user design, then the computer is reconfigured not to use the defective part and running of the computer is resumed, otherwise the computer resumes running without reconfiguration.03-26-2009
20100001753Position changing apparatus for test handler and power transferring apparatus - A test handler is disclosed. A posture changing unit for changing a posture of a test tray on which semiconductor devices have been loaded changes the posture of the test tray in a soak chamber. While the posture of the test tray is changed, the devices can be pre-heated/pre-cooled, thereby reducing the soak chamber length and the pre-heating/pre-cooling time.01-07-2010
20100013513Test device and semiconductor integrated circuit device - Test devices and integrated circuits with improved productivity are provided. In accordance with example embodiments, a test device may include a first test region with a first test element and a second test region with a second test element defined on a semiconductor substrate. The first test element may include a pair of first secondary test regions in the semiconductor substrate and a pair of first test gate lines. One of the first test gate lines may overlap one of the first secondary test regions and the other first test gate line may overlap the other first secondary test region. The second test element may include structures corresponding to the first test element except the second test element does not include structures corresponding to the pair of first secondary test regions and the pair of first test gate lines.01-21-2010
20100231254METHOD FOR CONFIGURING COMBINATIONAL SWITCHING MATRIX AND TESTING SYSTEM FOR SEMICONDUCTOR DEVICES USING THE SAME - A method for configuring a combinational switching matrix comprises the steps of setting a first switching module and a second switching module, coupling at least one of the output ports of the first switching module with at least one of the input ports of the second switching module to form the combinational switching matrix, building a connection mapping table based on the coupling relationship between the output port of the first switching module and the input port of the second switching module, and displaying a channel switching interface showing the input terminals, the output terminals, and the on/off states of the virtual switching devices of the combinational switching matrix.09-16-2010
20100237894METHOD TO DETERMINE NEEDLE MARK AND PROGRAM THEREFOR - Disclosed is a method to determine a needle mark, which can more accurately determine whether marks formed on electrode pads of devices are probe needle marks, thereby significantly reducing misdetermination of the marks as the probe needle marks. The method includes giving scores, which are used to determine the quality of marks as probe needle marks, to marks formed on a plurality of electrode pads of a plurality of devices, and selecting, based on the scores, an object device including an object electrode pad with an indefinite mark formed thereon, and selecting four comparison devices preceding the object device and nine time-successive comparison devices following the object device at successive times along the test direction, and determining if the indefinite mark of the object device is good or bad as a probe needle mark, by comparing a value of the score given to the indefinite mark of the object device plus scores given to marks formed on the comparison devices' comparison electrode pads corresponding to the object electrode pad, with a reference value.09-23-2010
20100237893SEMICONDUCTOR TEST APPARATUS AND TEST METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor test apparatus comprising: a contact-resistance calculating unit that calculates contact resistance of a measuring jig using power supply current and internal voltage obtained when power supply voltage is applied; a regression-expression calculating unit that calculates a stationary time power supply current characteristic expression using the power supply current and the internal voltage obtained when the power supply voltage is applied; and a measurement-voltage calculating unit that calculates power supply voltage for a test using operating time power supply current information, which is a corresponding relation between operating time power supply current obtained when a plurality of types of power supply voltages are applied and the types of power supply voltages, the contact resistance, and the stationary time power supply current characteristic expression.09-23-2010
20090033352HANDLER AND PROCESS FOR TESTING A SEMICONDUCTOR CHIPS USING THE HANDLER - A test handler includes a loading unit including a loading picker and a loading ascending/descending unit, an unloading unit including an unloading picker and an unloading ascending/descending unit, and a chamber system. A passage site connects the loading unit and the chamber system, and also connects the chamber system and the unloading unit. The arrangement of the handler reduces the time for the loading and unloading processes by performing the loading and unloading processes on separate test trays located at separate loading and unloading positions.02-05-2009
20090322371Measuring Arrangement, Semiconductor Arrangement and Method for Operating a Semiconductor Component as a Reference Source - The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.12-31-2009
20090072853METHOD FOR PRE-TREATING EPITAXIAL LAYER, METHOD FOR EVALUATING EPITAXIAL LAYER, AND APPARATUS FOR EVALUATING EPITAXIAL LAYER - An apparatus for evaluating an epitaxial layer, including pre-treating the epitaxial layer before evaluation of the epitaxial layer by making the epitaxial layer contact with a metal electrode by a capacitance-voltage measurement, the method comprising; applying carbon-bearing compound to a surface of the epitaxial layer; subsequently irradiating ultraviolet light to the surface of the epitaxial layer; and thereby forming an oxide film on the surface of the epitaxial layer.03-19-2009
20090072852SYSTEM THAT DETECTS DAMAGE IN ADJACENT DICE - A system including a tester configured to measure a first current from a first die of neighboring dice and a second current from a second die of the neighboring dice. The tester is configured to compare the first current to the second current to detect damage in the neighboring dice.03-19-2009
20090115443SYSTEM AND METHOD FOR TESTING INTEGRATED CIRCUIT MODULES COMPRISING A PLURALITY OF INTEGRATED CIRCUIT DEVICES - Embodiments of a system and method for testing an integrated circuit module comprising multiple integrated circuit devices, such as a memory module comprising multiple memory devices for example, is disclosed. Embodiments of the method may be employed to test an integrated circuit device of the integrated circuit module that provides a data strobe signal associated with at least one data signal provided by the same integrated circuit device. A determination of a test outcome for the integrated circuit module may be made after identifying data valid windows for each integrated circuit device, without having to both identify a common sampling window defined by an intersection of the identified data valid windows and verify that such common sampling window meets specification requirements, as may be performed by conventional testers.05-07-2009
20090115444ANISOTROPIC CONDUCTIVE SHEET, ITS PRODUCTION METHOD, CONNECTION METHOD AND INSPECTION METHOD - Provided is an anisotropic conductive sheet (05-07-2009
20090115445METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING REFERENCE DICE - Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted.05-07-2009
20090108863METHOD AND CIRCUIT FOR DETECTING AND COMPENSATING FOR A DEGRADATION OF A SEMICONDUCTOR DEVICE - A design structure and method comprising a degradation detection circuit configured to respond to degradation. The degradation detection circuit is located within a semiconductor device and comprises a process sensitive circuit, a measurement circuit, a calculation circuit, and a control circuit. The method comprises subjecting the semiconductor device to a first operating condition. A first value at a first time for a parameter of the process sensitive circuit is measured by the measurement circuit. The semiconductor device is operated to perform an intended function. A second value at a second time for the parameter of the circuit is measured by the measurement circuit. The second time is different from the first time. A first differential value between the first value and the second value is determined by the calculation circuit. The control circuit is configured to receive an enable signal.04-30-2009
20090108864SYSTEM AND METHOD FOR TESTING AN OPERATING CONDITION OF LEDS ON A MOTHERBOARD - A computer-implemented method for testing an operating condition of light emitting diodes (LEDs) on a motherboard includes assigning an LED identification for each LED according to positions of the LEDs on the motherboard, selecting a first LED identification for a first LED and a second LED identification for a second LED, setting the first LED in a bright state, the second LED in a dim state, and any remaining LEDs in a flicker state, and controlling the LEDs to operate. The method further includes determining whether the total count of the LEDs in the bright state is equal to one, and whether the total count of the LEDs in the dim state is equal to one, comparing the first LED identification input with the first LED identification, and comparing the second LED identification input with the LED identification, and reporting a comparison result.04-30-2009
20080231311PHYSICALLY HIGHLY SECURE MULTI-CHIP ASSEMBLY - A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.09-25-2008
20080231312Structure for modeling stress-induced degradation of conductive interconnects - A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.09-25-2008
20100301894SEMICONDUCTOR DEVICE CAPABLE OF VERIFYING RELIABILITY - A semiconductor device includes an integrated semiconductor circuit unit, a chip guard-ring disposed along an outer portion of the semiconductor device, and a reliability verifying unit disposed between the integrated semiconductor circuit unit and the chip guard-ring. The reliability verifying unit is configured to delay a reliability verifying signal to detect a fault while in a reliability detecting mode.12-02-2010
20100301895Test system and test method of semiconductor integrated circuit - Provided is a test system of a semiconductor integrated circuit including an output device and an input device for conducting an input/output characteristics test of the output device and the input device inside the semiconductor integrated circuit. In the system, a transmission line provided in a test board where the semiconductor integrated circuit is mounted on establishes a wired connection between an external terminal of one circuit of one of the output device and the input device and external terminals of a plurality of circuits of another one of the output device and the input device.12-02-2010
20080290891METHOD OF PERFORMING PARALLEL TEST ON SEMICONDUCTOR DEVICES BY DIVIDING VOLTAGE SUPPLY UNIT - Provided is a method of performing a parallel test on semiconductor devices, the method including coupling a power signal line to a set of at least two semiconductor devices through a switching device, performing at least one part of a parallel test on the set of semiconductor devices, and disconnecting a semiconductor device from the set in response to determining that the semiconductor device is defective as a result of the at least one part of the parallel test.11-27-2008
20090066357Method and apparatus for detecting impairment of a solar array - An apparatus for detecting an impairment of a solar array. The apparatus comprises an impairment detection module for performing a comparison of a power production profile and at least one reference profile, wherein the power production profile and the at least one reference profile are for at least one of the solar array, at least one solar subarray of the solar array, or at least one solar panel of the solar array. The apparatus determines, based on the comparison, whether the impairment exists.03-12-2009
20090033354Multi-purpose poly edge test structure - Multi-purpose poly edge test structure. According to an embodiment, the present invention provides a test structure. The test structure includes a doped silicon substrate, the doped silicon substrate being grounded, the doped silicon substrate including a first gate structure and a second gate structure, the first and second gate structures overlaying the doped silicon substrate. The test structure also includes a first conducting pad being electrically coupled to the first gate structure. The test structure also includes a second conducting pad being electrically coupled to the second gate structure.02-05-2009
20090033353SYSTEMS AND METHODS FOR ELECTRICAL CHARACTERIZATION OF INTER-LAYER ALIGNMENT - Systems and methods for electrical characterization of inter-layer alignment. In one embodiment, a wafer including a plurality of test structures are accessed. The plurality of test structures include chains of conductive segments on multiple layers, coupled by vias. The plurality of test structures are designed with varying amounts of intentional misalignment between the multiple layers. The reactance of each of the plurality of test structures is measured. The reactance is analyzed to determine the process-induced inter-layer misalignment of the integrated circuit wafer.02-05-2009
20100164530ADJUSTING CONFIGURATION OF A MULTIPLE GATE TRANSISTOR BY CONTROLLING INDIVIDUAL FINS - In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable inter-connect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices.07-01-2010
20100164529SEMICONDUCTOR DEVICE TEST SYSTEM - A test system for semiconductor devices including a tester, a test station, a first controller, and one or more second controllers, is disclosed. The tester handles operations of the test system. The test station, coupled to the tester, receives test information from the tester via a transmission path, where the test station performs a test process to a semiconductor device under test according to the test information, and then provides a test result to the tester. The first controller, electronically connected to the test station, receives the test information. The second controllers, electronically connected to the test station, handles the test process of the test station, where each the second controller corresponds to one or more semiconductor device under test. The first controller broadcasts the test information to one or more second controllers and receives the test result from the second controllers through an infrared communication interface.07-01-2010
20100164528Methods and Apparatus to Test Electronic Devices - Methods and apparatus to test electronic devices are disclosed. An example method includes setting a first controlled switch to prevent a current detect signal from tripping an overcurrent protection event controlling an operation of the device; setting a second controlled switch to route a first sensed voltage associated with the device to a voltage adjuster; sending a calibration current corresponding to a target threshold current through the device; detecting the first sensed voltage while the calibration current flows through the device; and setting a reference signal substantially equal to the first sensed voltage, wherein the reference signal is to be used to generate the current detect signal.07-01-2010
20100066400Method and apparatus for determining the operating condition of generator rotating diodes - A controller (03-18-2010
20100066401SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device in which a circuit in the semiconductor chip is divided into a plurality of sub-circuits. The semiconductor device includes switches between the respective sub-circuits and a power supply, and a circuit that variably controls on-resistances of the switches 03-18-2010
20100066402METALLIC PROBE, AND METHOD AND APPARATUS FOR FABRICATING THE SAME - A sharpened metallic probe having a top of main body including a carbon-containing metal and a method and an apparatus for fabricating the metallic probe. A metallic probe with an extremely sharpened tip is obtained by inducing a field emission from the tip of the main body of the metallic probe where a nanotube is joined thereto, heating and melting locally the tip of the main body of the metallic probe by a Joule heating, and tearing the nanotube toward a counter electrode by a Coulomb attractive force.03-18-2010
20090027077METHOD AND APPARATUS FOR IDENTIFYING OUTLIERS FOLLOWING BURN-IN TESTING - A method includes performing burn-in testing of a device in a tester to generate post burn-in data. Pre-burn-in data associated with the device is compared to the post burn-in data. The device is identified as an outlier device based on the comparison.01-29-2009
20090079461Test socket and test board for wafer level semiconductor testing - A test board for wafer level semiconductor testing is disclosed. The test board comprises a plurality of wires and microelectronic devices; and a plurality of test sockets on an upper surface of the test board. Each test socket comprises: a base member configured for attachment to the test board with a first set of screws, wherein the base member has a central opening exposing a portion of the underlying test board; an anisotropic conductive film disposed within the central opening of the base member; a chip to be tested, disposed on the anisotropic conductive film within the central opening of the base member; and a cover member overlying the chip, attached to the base member with a second set of screws.03-26-2009
20100253381On-Chip Logic To Support In-Field Or Post-Tape-Out X-Masking In BIST Designs - Techniques for masking unknown and irrelevant response values that may be produced by a BIST process. Masking circuitry is provided for selectively masking the response values obtained from a BIST process. The operation of the selective masking circuitry is controlled by a programmable mask circuitry controller that can be programmed after the integrated circuit has been manufactured. A user can analyze an integrated circuit after it has been manufactured to identify irrelevant and unknown data values in a BIST process. After the irrelevant and unknown data values have been identified, the user can program the programmable mask controller to have the selective masking circuitry mask the identified irrelevant and unknown data values.10-07-2010
20080238471ELECTRICAL INSPECTION METHOD AND METHOD OF FABRICATING SEMICONDUCTOR DISPLAY DEVICES - A method of electrically inspecting semiconductors display device, which is capable of inspecting whether a signal is normally input to the pixels and whether an electric charge is normally held by the holding capacitors without using the video signal line as a passage for reading the electric charge and without separately providing an inspection-dedicated circuit.10-02-2008
20100079163MEASUREMENT EQUIPMENT, TEST SYSTEM, AND MEASUREMENT METHOD - A measurement apparatus that detects a defect in a device based on the quiescent current (IDDQ) of a CMOS LSI or the like detects the defect by measuring the value of IDDQ that flows when a logic vector is applied. However, the miniaturization of CMOS LSIs has caused an increase in the leak current flowing through a normal CMOS circuit. This makes it difficult to distinguish between the power supply current flowing in a defective CMOS circuit and the leak current flowing through a normal CMOS circuit. By applying the logic vector after suppressing the fluctuation of the leak current by controlling the power supply voltage applied to the device under measurement and the voltage applied to the substrate of the device under measurement, the measurement apparatus of the present invention can measure the power supply current flowing through a defective CMOS circuit to detect the defect in the CMOS circuit.04-01-2010
20080265933Semiconductor Device Testing Apparatus and Power Supply Unit - The semiconductor device testing apparatus according to the present invention has a testing LSI; a power supply unit; and an intermediate substrate provided so that there is a connection between the testing LSI, and the power supply unit and tester. The testing LSI has a testing circuit and a waveform shaping circuit; a dielectric material layer disposed so as to face a tested semiconductor device; an electrode disposed in a position that corresponds to a position of an external terminal electrode of the tested semiconductor device on a surface of the dielectric material layer facing the tested semiconductor device; and a first penetrating electrode that passes completely through the dielectric material layer, is connected to the electrode, and is used for exchanging signals with the exterior. The power supply unit has mutually independent elastic probe pins that are disposed in positions that correspond to power electrodes of the tested semiconductor device, and that are provided with a metal protrusion at the distal ends thereof; a substrate that is electrically connected to the probe pins and on which a first wiring layer is formed; and a second penetrating electrode that passes through the substrate.10-30-2008
20100295572UNIVERSAL TEST SOCKET AND SEMICONDUCTOR PACKAGE TESTING APPARATUS USING THE SAME - A universal test socket includes a housing frame including a side wall, an inner protruding portion protruding inwardly from the side wall, and a through window formed at a center portion of the housing frame, wherein the through window is surrounded by the side wall, a pin plate assembly coupled to the housing frame and including a pin plate in which a plurality of test pins are arranged and a plurality of guide pins formed on periphery of the pin plate, and a package guide portion coupled to the housing frame and located above the pin plate assembly, a semiconductor package to be tested being mounted on the package guide portion. When the pin plate assembly is coupled to the housing frame, the positions of the test pins arranged in the housing frame are varied according to a rotation angle of the pin plate assembly with respect to the housing frame.11-25-2010
20080204065FAULT TOLERANT SELECTION OF DIE ON WAFER - In a functional mode, the functional core logic of a die is connected to the input and output pads and the die performs its intended function. In a bypass mode, the input and output buffers of the functional core logic are disabled and pad sites of corresponding position between a first set of opposite sides and between a second set of opposite sides are electrically connected. In bypass mode the die is transformed into a simple interconnect structure between the first sides and between the second sides. The interconnect structure includes plural conductors extending substantially parallel to one another between the first sides and further plural conductors extending substantially parallel to one another between the second sides. While in bypass mode, signals from a tester apparatus can flow through the conductors between the first sides and between the second sides to access and test a selected die on a wafer.08-28-2008
20080204064TEST SYSTEM AND HIGH VOLTAGE MEASUREMENT METHOD - Provided are a test system and a related high voltage measurement method. The method includes applying an external voltage signal to one or more of a plurality of DUTs via the shared channel, comparing the external voltage signal with a high voltage signal internally generated by the one or more DUTs and generating a corresponding comparison result, and determining a voltage level for each respective high voltage signal in accordance with the comparison result.08-28-2008
20100117677METHOD TO SYNCHRONIZE TWO DIFFERENT PULSE GENERATORS - This invention generates two pulses for semiconductor testing that have leading edges coordinated in time by synchronizing the pulses from two different styles of pulse generators (pulsers). One pulser uses spark discharge pulse generation and the other pulser is a typical solid state pulser. The spark discharge pulser has high power pulse generation but its pulse timing can not be tightly controlled. The output pulse of the spark discharge pulser is split unequally, with a small amount used to trigger the solid state pulser, and the large pulse energy delayed by a cable of length for a signal propagation delay equal or greater than the trigger-input-to-pulse-output delay of the solid state pulser. Variable attenuators control the trigger signal amplitude and a level shifting circuit makes the trigger signal compatible with standard logic signal levels. The two pulses can be applied to semiconductors with their leading edges adjustable relative to each other to measure the semiconductors operation.05-13-2010
20100117678Semiconductor device and method of testing the same - A semiconductor device is formed on a semiconductor wafer. The semiconductor device has: an output buffer configured to externally output an output signal received from an internal circuit; an input buffer configured to output an input signal externally received to the internal circuit; a switch configured to control electrical connection between an output terminal of the output buffer and an input terminal of the input buffer; a first transmission path provided in a scribe region of the semiconductor wafer and connecting between the output terminal and the switch; and a second transmission path provided in the scribe region and connecting between the input terminal and the switch.05-13-2010
20100213967TEST APPARATUS - A test apparatus is configured such that two adjacent channels form a pair. Timing comparators determine the level of first output data fed from a DUT, respectively, timed in accordance with strobe signals, respectively. Clock envelope extractors extract envelopes of a clock, respectively. A clock recovery circuit recovers a strobe signal. A first main latch latches an output from the first timing comparator, timed by the first strobe signal. A first sub-latch latches the envelope of the clock, timed by the first strobe signal. An output from the sub-latch is supplied to a second main latch of the second channel. A signal dependent on the strobe signal is assigned an adjustable delay by a first delay circuit and is supplied to a clock terminal of the second main latch.08-26-2010
20100213966Comparator with latching function - A comparison amplification unit compares a level of a signal in a positive line with that of a signal in a negative line and latches a comparison result. An input terminal of a first inverter is connected to the positive line and an output terminal thereof is connected to the negative line. An input terminal of a second inverter is connected to the negative line and an output terminal thereof is connected to the positive line. An activation switch selectively switches between a state where the activation switch outputs a power supply voltage to the other power supply terminals of the inverters that are connected in common, such that the comparison amplification unit is inactivated, and a state where the activation switch outputs the ground voltage such that the comparison amplification is activated. The comparator outputs a signal corresponding to at least one of the signal in the positive line and the signal in the negative line at a timing after the comparison amplification unit is activated.08-26-2010
20100213965METHOD AND APPARATUS OF TESTING DIE TO DIE INTERCONNECTION FOR SYSTEM IN PACKAGE - Method and apparatus of testing die to die interconnection for system in package (SiP). For testing a die to die interconnection connected between two pads of two dice, an IO buffer, e.g., a bi-directional IO buffer, in one of the two dice coupled to one of the two pads is arranged. An oscillating feedback is formed between an output port and an input port of the IO buffer, such that a state, e.g., an open state, a short state or a normal state of the die to die interconnection is tested according to a timing characteristic, e.g., a frequency, of a signal of the IO buffer.08-26-2010
20100213968TESTING INTEGRATED CIRCUITS - A test insert for an integrated circuit according to the present invention comprises access contacts and an electrical path. Furthermore, there may be additional access contacts and a plurality of different electrical paths. The electrical path is comprised of a plurality of tracks, each track provided at a single layer of the integrated circuit and connected to the other tracks by interconnecting vias. The vias provide interlayer contacts and thus allow the tracks to be connected into a single electrical track. In one embodiment, an access contact is connected to ground; another contact is connected to a reference voltage; and connected to various points in the electrical path are transistor-resistor pairs. The transistor-resistor pairs are in connected between earth and a third access contact. If the electrical path is intact at the track connected to a transistor-resistor pair, a current can flow between contact and the respective earth of the transistor-resistor pair. By analysing the current drawn from contact it can be deduced whether the path is operational as a whole and if not, how far along the path a fault lies. This can therefore isolate a particular interconnection between layers or a particular layer as being faulty.08-26-2010
20100182034CIRCUIT FOR CONTINUOUSLY MEASURING DISCONTINUOUS METAL INSULATOR TRANSITION OF MIT ELEMENT AND MIT SENSOR USING THE SAME - Provided are a circuit for continuously measuring a discontinuous metal-insulator transition (MIT) of an MIT element and an MIT sensor using the circuit. The circuit comprises a to-be-measured object unit including the MIT element having a discontinuous MIT occurring at the transition voltage thereof, a power supply unit applying a predetermined pulse current or voltage signal to the to-be-measured object unit, a measurement unit measuring the discontinuous MIT of the MIT element, and a microprocessor controlling the power supply unit and the measurement unit. The discontinuous MIT measurement circuit continuously measures the discontinuous MIT of the MIT element, and thus it can be used as a sensor for sensing a variation in an external factor.07-22-2010
20100060308SEMICONDUCTOR MODULE - A semiconductor module is provided. A recess portion is provided on the mounting face of the semiconductor module. A test terminal is provided as a terminal for the application of an external signal or the measurement of the electrical state of the semiconductor module in the test step for the semiconductor module. The test terminal is formed on the base of the recess portion such that, after the semiconductor module is mounted on a printed-circuit board, the test terminal is not in contact with the surface of the printed circuit board.03-11-2010
20100060307Electrical Characterization of Semiconductor Materials - A system and method for characterizing electronic properties of a semiconductor sample includes illuminating the surface of the semiconductor sample with a pulse of light, measuring a photoconductance decay in the semiconductor sample after the cessation of the first pulse of light, and analyzing the photoconductance decay. The electronic properties include properties associated with at least one of the bulk of the semiconductor sample and the surface of the semiconductor sample. The pulse of light has a predetermined duration and photon energy higher than energy gap of the semiconductor. The analyzing step determines a first component of the photoconductance decay substantially associated with point imperfections in the semiconductor sample and at least one second component of the photoconductance decay substantially associated with extended imperfections in the semiconductor sample.03-11-2010
20080218194STACKED PACKAGE SCREENING - A semiconductor device in which a plurality of devices provided with mutually identical functions are stacked includes: a chip selection terminal by which the semiconductor device selects devices, a prescribed terminal for generating a second internal signal that is selectively switched from a first internal signal from the chip selection terminal, and an input-switching circuit for selectively switching the first internal signal and the second internal signal.09-11-2008
20080218193SEMICONDUCTOR DEVICE EVALUATION METHOD AND APPARATUS USING THE SAME - In order to provide a semiconductor device evaluation method and a semiconductor device evaluation apparatus for correctly detecting an error position and providing a substrate for observing a cross section without difficulties, a transport unit of a SEM apparatus moves a substrate on a stage. A detection unit detects electric information of observed objects including an error position arranged on the substrate. A calculating unit calculates integrals based on the electric information in at least first and second directions among directions in which arrays of the observed objects are arranged, detects a first waveform obtained by calculating the integral in the first direction and detects a second waveform obtained by calculating the integral in the second direction, wherein the first waveform includes a peak which contains the array of the observed objects including the error position and is larger than at least one of the other peaks, and wherein the second integral-waveform has peaks of substantially the same height. A control unit controls the transport unit so as to move the semiconductor substrate in a direction for maintaining the peak of the first waveform that includes the error position and controls the calculating unit to count the peaks of the second waveform.09-11-2008
20080218192Methods and apparatus for translated wafer stand-in tester - A translated wafer stand-in tester (TWST), being a hybrid apparatus capable of emulating the form factor and some or all behaviors of a translated wafer under test, which is operable to store, quantify, encode and convey, either directly or remotely, data from a testing system, including but not limited to pad pressure, electrical contact and temperature. The TWST may include several stacked and attached layers,, at least one internal layer including electronic components operable to interact with a test system.09-11-2008
20100194423APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR AND SEMICONDUCTOR DEVICE TO BE TESTED - Provided is a semiconductor testing apparatus which can perform batch test of semiconductor wafers. In the semiconductor testing apparatus, an LSI apparatus for conducting a test and which provided with a circuit and an electrode for transmitting noncontact signals, and a probe card to which a contact-type probe pin is attached are separately arranged. The semiconductor testing apparatus is provided with a recognition unit for precisely aligning the electrodes of the LSI apparatus for conducting a test, the LSI wafer to be tested and the probe card. The LSI apparatus for conducting a test and a probe pin of the probe card are mounted on a stage or a pressurizing head, and contact can be made to sandwich an LSI wafer to be tested, from both the front surface and the rear surface of the LSI wafer to be tested at the same time.08-05-2010
20100194422Semiconductor integrated circuit device operating frequency determining apparatus, determining method and computer-readable information recording medium - A variation in manufacturing total costs is obtained by using an excessive loss amount caused by unnecessarily discarding elemental semiconductor integrated circuits occurring as a result of a negative result being obtained in an elemental test but a positive result obtained from a device test, and a short loss amount caused by packaging elemental semiconductor integrated circuits for semiconductor integrated circuit devices that are discarded as a result of a positive result being obtained from the elemental test but a negative result being obtained from the device test. A new operating frequency is determined by using the variation in manufacturing total costs with respect to an operating frequency.08-05-2010
20100026335LEAK CURRENT DETECTION CIRCUIT, BODY BIAS CONTROL CIRCUIT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE TESTING METHOD - A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential power supply and which is normally inactivated and generates a first leak current, at least one N-channel MOS transistor which is coupled between a low potential power and at least the one P-channel MOS transistor and which is normally inactivated and generates a second leak current, and a detector which detects a potential generated at a node between the at least one P-channel MOS transistor and the at least one N-channel MOS transistor in accordance with the first and second leak currents.02-04-2010
20100026334Testing Embedded Circuits With The Aid Of Test Islands - Embodiments of the present disclosure relate to a system and method for testing an embedded circuit in a semiconductor arrangement as part of an overall circuit that is located on a semiconductor wafer, the system and method comprising an arrangement comprising an overall circuit with at least one input and output. The overall circuit may be provided with an embedded circuit that is not directly connected to the inputs and outputs or may be connected thereto by being specially switched. Switching elements and test islands that are connected thereto may be provided such that the input or the output of the embedded circuit may be connected to the test islands via the switching elements in case of a test. The switching elements may be switched to said test mode in case of a test by applying a voltage to the test island, or the switching elements may be switched in this manner. The arrangement may thus allow for a flexible testing system and method while the used substrate area and the number of required inputs and outputs remain low.02-04-2010
20100019795VARIABLE DELAY CIRCUIT, TIMING GENERATOR AND SEMICONDUCTOR TESTING APPARATUS - The accuracy of the delay amount to be imparted to a timing signal is improved by increasing the delay amount obtained by a first stage of a delay element.01-28-2010
20090174427BURN-IN-BOARD ARCHITECTURE AND INTEGRATED CIRCUIT DEVICE TRANSFER METHOD - The present invention implements a mechanism using an inter-connection layer to couple a plurality of integrated circuit devices to a printed circuit board, thereby eliminating the need for sockets to hold the integrated circuit devices on the printed circuit board. The mechanism of the present invention is operative for integrated circuit devices packaged in a ball grid array, a quad flat pack or a leadless quad flat pack. The present invention also provides a mechanism to efficiently transfer a plurality of integrated circuit devices from an integrated circuit device delivery tray to a burn-in board in a single process without requiring an autoloader, resulting in increased transfer reliability and both cost and space savings.07-09-2009
20090002012Accurate Capacitance Measurement for Ultra Large Scale Integrated Circuits - Test structures and methods for measuring contact and via parasitic capacitance in an integrated circuit are provided. The accuracy of contact and via capacitance measurements are improved by eliminating not-to-be-measured capacitance from the measurement results. The capacitance is measured on a target test structure that has to-be-measured contact or via capacitance. Measurements are then repeated on a substantially similar reference test structure that is free of to-be-measured contact or via capacitances. By using the capacitance measurements of the two test structures, the to-be-measured contact and via capacitance can be calculated.01-01-2009
20100097089Test Handler and Loading Method Thereof - When a test handler loads semiconductor devices of user trays onto a test tray, the test handler adjusts a front/rear pitch or a right/left pitch between the semiconductor devices, adjusts the right/left pitch or the front/rear pitch, and loads the semiconductor devices. The test handler can sequentially adjust individually the front/rear pitch and the right/left pitch between the semiconductor devices, thereby reducing the apparatus weight and the loading time.04-22-2010
20080297188IC CHIP STRESS TESTING - Methods, systems and program products are disclosed for performing a stress test of a line in an integrated circuit (IC) chip. One embodiment of the method includes: applying a constant current I12-04-2008
20090134901INTEGRATED CIRCUIT DIE STRUCTURE SIMPLIFYING IC TESTING AND TESTING METHOD THEREOF - By adding multiplexing units to selectively transmit signals associated with a functional circuitry of an IC die to test pads, a probe card with less pin counts than the pad number of the IC die can be utilized for testing the functional circuitry. Therefore, the pad number/pad pitch of the IC die is not limited by the pitch of the conventional probe card. A high pin count IC die design is thereby available.05-28-2009
20090134905SYSTEM FOR MEASURING SIGNAL PATH RESISTANCE FOR AN INTEGRATED CIRCUIT TESTER INTERCONNECT STRUCTURE - Resistances of signal paths within a interconnect structure for linking input/output (I/O) ports of an integrated circuit (IC) tester to test points of an IC are measured by the IC tester itself. To do so the interconnect structure is used to link the tester's I/O ports to a similar arrangement of test points linked to one another through conductors. Drivers within the tester, which normally transmit digital test signals to IC test points via the I/O ports when the IC is under test, are modified so that they may also either transmit a constant current through the I/O ports or link the I/O ports to ground or other reference potential. The tester then transmits known currents though the signal paths interconnecting the tester's I/O ports. Existing comparators within the tester normally used to monitor the state of an IC's digital output signals are employed to measure voltage drops between the I/O ports, thereby to provide data from which resistance of signal paths within the interconnect structure may be computed.05-28-2009
20090134902INTEGRATED CIRCUIT PACKAGE HAVING REVERSIBLE ESD PROTECTION - Methods, systems, and apparatuses are provided for integrated circuit packages and for enabling electrostatic discharge (ESD) testing of the same. A package includes an integrated circuit chip, a substrate, a first electrically conductive trace, and a second electrically conductive trace. The substrate includes a first electrically conductive region and a second electrically conductive region. The first region is coupled to a first ground signal of the chip, and the second region is coupled to a second ground signal of the chip. The first trace is coupled to the first region and the second trace is coupled to the second region. A portion of the first trace is proximate to a portion of the second trace. An electrically conductive material may be deposited to electrically couple the first and second traces to enable ESD protection testing of the package.05-28-2009
20100244881TRANSMISSION CHARACTERISTICS MEASUREMENT APPARATUS, TRANSMISSION CHARACTERISTICS MEASUREMENT METHOD, AND ELECTRONIC DEVICE - Provided is a transfer characteristic measurement apparatus that measures a transfer characteristic of a circuit under test between input and output, comprising a test signal input section that generates a test signal by adding together a carrier signal having a prescribed frequency and an additional signal having a frequency that differs from the prescribed frequency, and inputs the test signal to the circuit under test; and a transfer characteristic measuring section that measures the transfer characteristic of the circuit under test at the frequency of the additional signal based on a result from a measurement of an output signal output by the circuit under test. The circuit under test may be formed on a semiconductor chip. The circuit under test may correct a signal input to the semiconductor chip, and outputs the corrected signal. The semiconductor chip may further include a sampling circuit that samples the output signal of the circuit under test at the frequency of the carrier signal.09-30-2010
20100244882Burn-In Test Method and System - A method for performing a burn-in test of a metal wire for a signal transmission of a semiconductor device including driving a first terminal of the metal wire with a first voltage and forming a current path in the metal wire by driving a second terminal of the metal wire with a second voltage whose level is different from that of the first voltage.09-30-2010
20100244880TEST APPARATUS AND DRIVER CIRCUIT - Provided is a test apparatus that tests a device under test, comprising a driver circuit that generates an output signal according to a prescribed input pattern, and supplies the output signal to the device under test; and a measuring section that measures a response signal output by the device under test to judge the acceptability of the device under test, wherein the driver circuit includes an input gate drive section that selects one of a plurality of input drive voltages supplied thereto, according to a logic value of the input pattern, and outputs the selected input drive voltage; a voltage switching section that includes a transistor and that outputs the output signal according to the drain voltage of the transistor, the transistor having a gate terminal that receives the input drive voltage output by the input gate drive section and a source terminal to which is applied a prescribed reference voltage; and an input drive voltage supplying section that generates the input drive voltages according to the reference voltage, and supplies the input drive voltages to the input gate drive section.09-30-2010
20100244883COMPENSATION FOR VOLTAGE DROP IN AUTOMATIC TEST EQUIPMENT - Providing reliable testing of a device under test (DUT) by compensating for a reduced voltage inside the device without changing the internal circuitry of the device. The DUT has multiple connection terminals for connecting to the test equipment including at least first and second power connection terminals that both connect to an internal power bus of the DUT. An adapter board connects to the multiple connection terminals of the DUT via a removably attachable socket which holds the DUT. A tester supplies power to the DUT through the adapter board. The adapter board is configured to supply power from the tester to the DUT through the first power connection terminal and to monitor voltage at the second power connection terminal. The tester includes a compensation unit which controls power based on the voltage monitored at the second power connection terminal.09-30-2010
20090079462Semiconductor device testing apparatus - A semiconductor device testing apparatus includes a test head Hifix, a tester coupled to the test head Hifix, two or more device-under-tests (DUTs), and one or more processor devices disposed on the test head Hifix and coupled to the DUTs for transmitting and receiving test signals between the tester and the DUTs and for receiving and processing a number of test signals from the DUTs into a single output signal and for transmitting the output signal to the tester for testing purposes. The tester may generate and transmit test signals to the test head Hifix and the DUTs for testing the DUTs to ensure that the DUTs function properly in the consumer domain.03-26-2009
20090058454DEVICE POWER SUPPLY EXTENSION CIRCUIT, TEST SYSTEM INCLUDING THE SAME AND METHOD OF TESTING SEMICONDUCTOR DEVICES - A test system includes a controller, a power supply circuit and a device power supply (DPS) extension circuit. The controller controls a test operation for a plurality of devices under test (DUTs). The power supply circuit generates a common power voltage in response to a voltage control signal from the controller. The DPS extension circuit includes a plurality of control modules providing a plurality of source currents based on the common power voltage to the DUTs. Each control module blocks a corresponding source current in response to a magnitude of the corresponding source current.03-05-2009
20090058453SEMICONDUCTOR DEVICE - A semiconductor device with technology for externally deciding if the stress test was performed or not. A semiconductor device includes a stress test circuit and a stress test decision circuit. The stress test circuit outputs control signals for executing the stress test to the stress test decision circuit and the object for testing. The stress test decision circuit then outputs the decision results if the stress test was performed, based on the control signals.03-05-2009
20090058452TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests fluctuation of a power supply voltage supplied to a device under test, including an oscillator that outputs a clock signal having a frequency that corresponds to the power supply voltage supplied to the power supply input terminal of the device under test, and a measuring section that measures the frequency of the clock signal. For example, the oscillator outputs as the clock signal an output signal of any one negative logic element from among an odd number of negative logic elements connected in a loop, and at least one of the negative logic elements operates using, as a voltage source, a voltage corresponding to the power supply voltage supplied to the power supply input terminal of the device under test.03-05-2009
20090058450METHOD OF AND SYSTEM FOR FUNCTIONALLY TESTING MULTIPLE DEVICES IN PARALLEL IN A BURN-IN-ENVIRONMENT - A method of and a system for testing semiconductor devices heat a plurality of devices to a burn-in temperature, and perform functional tests in parallel on the plurality of devices at the burn-in temperature. Systems include a burn-in oven and a test multiplexer. The burn-in oven is adapted to receive and heat the devices to the burn-in temperature. The test multiplexer is adapted to apply functional test signals to and receive output signals from the devices in the burn-in oven.03-05-2009
20100052726POWER SOURCE NOISE MEASURING DEVICE, INTEGRATED CIRCUIT, AND SEMICONDUCTOR DEVICE - To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.03-04-2010
20100052725ADAPTIVE TEST TIME REDUCTION FOR WAFER-LEVEL TESTING - In a method for testing a plurality of consecutively indexed sites, a default test sequence is applied to the consecutively indexed sites until a first defective site is identified. If a first defective site is identified, then a more stringent test sequence is applied to a predefined number of sites subsequent to the first defective site. If the more stringent test sequence does not identify a second defective site in the predefined number of sites subsequent to the first defective site, then the default test sequence is resumed.03-04-2010
20100052724CIRCUIT AND METHOD FOR PARALLEL TESTING AND SEMICONDUCTOR DEVICE - Disclosed is a test circuit including a first transfer circuit, a second transfer circuit and comparators and performing parallel testing of a plurality of chips under test. The first transfer circuit includes flip-flops. A data pattern from a tester is supplied to the initial stage chip under test. To the remaining chips under test, output data from the corresponding stages of the first transfer circuit are supplied. The second transfer circuit sequentially transfers an output of the initial stage chip under test, as an expected value pattern, in response to clock cycles. The comparator compares output data of the chip under test with an expected value pattern from the corresponding stage of the second transfer circuit.03-04-2010
20100052723INTERCONNECTION SUBSTRATE, SKEW MEASUREMENT METHOD, AND TEST APPARATUS - There is provided an interconnection substrate used in skew adjustment between output pins in a test apparatus, the test apparatus supplying a test signal to a device under test to test the device under test, the interconnection substrate including: a first terminal coupled to a first output pin that outputs the test signal; a second terminal coupled to a second output pin that outputs the test signal; a first interconnection connecting the first terminal to a bonding node; a second interconnection connecting the second terminal to the bonding node; and a third interconnection connecting the bonding node to an output node, where the first interconnection and the second interconnection have a length equal to each other.03-04-2010
20080211530INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION - Methods for testing a semiconductor circuit (09-04-2008
20100007368Semiconductor integrated circuit and method of testing the same - Provided is a semiconductor integrated circuit including: a first path that includes a first logic circuit; a second path that includes a second logic circuit; and a subsequent-stage circuit that is connected to an output of the first path and is connected to an output of the second path, in which the second path further includes a first internal path that is selected as a propagation path during a normal operation period; and a second internal path that is selected as a propagation path during a test operation period and includes a delay circuit having a delay amount larger than a delay amount of the first internal path.01-14-2010
20100001755METHOD FOR TESTING NOISE IMMUNITY OF AN INTEGRATED CIRCUIT AND A DEVICE HAVING NOISE IMMUNITY TESTING CAPABILITIES - A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit.01-07-2010
20100264951INTERCONNECTION CARD FOR INSPECTION, MANUFACTURE METHOD FOR INTERCONNECTION CARD, AND INSPECTION METHOD USING INTERCONNECTION CARD - Recesses are formed on one surface of a substrate. A conductive film covers an inner surface of each of the recesses. This conductive film contacts a bump of a semiconductor device to be inspected and is electrically connected to the bump. It is therefore possible to prevent damages of the bump to be caused by contact of a probe pin.10-21-2010
20100259292SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TEST METHOD THEREFOR - A semiconductor integrated circuit device includes: a normal output signal counter that counts number of times a normal output signal is output by the circuit under test in response to a preset one of the input signals of the input signal set, in case where a circuit under test repeats processing on each of one or more input signals of an input signal set sequentially, a plural number of times.10-14-2010
20100259291DEVICE FOR CHARACTERIZING THE ELECTRO-OPTICAL PERFORMANCE OF A SEMICONDUCTOR COMPONENT - A device for characterizing the electro-optical performance of a semiconductor component includes a chamber containing a controlled atmosphere; a measuring head equipped with conductive probes for contacting the electrical interfaces of said component and connected to a data processing system in order to determine said electro-optical performance; and a staging fixture support to accommodate said component(s), the staging fixture being capable of being cooled and being moved in an upward and downward translational movement to bring the electrical interfaces of said component(s) into contact with the tip of the measuring probes of the measuring head. The staging fixture has bumps and the components are positioned in contact with these and the staging fixture accommodates, in the area of each of these bumps, two positioning grids which are capable of sliding relative to each other and cooperating with each other to define pockets suitable for accommodating the component(s) to be characterized.10-14-2010
20090021279SEMICONDUCTOR TESTING CIRCUIT AND SEMICONDUCTOR TESTING METHOD - A semiconductor testing circuit of the present invention includes a signal line which is connected to a terminal not to be tested and a plurality of terminals to be tested of a semiconductor device; switch circuits for controlling electrical connection/disconnection between the signal line and the terminals to be tested; and a resistor connected to one end of the signal line. With this configuration, in a test on the AC characteristics of an input signal, a test signal generated by an LSI tester can be inputted to the terminals to be tested through the terminal not to be tested and the signal line by turning on the switch circuits.01-22-2009
20090021278Commutation failure detection circuit for back-to-back SCR circuit and controlling method thereof having relatively better efficiency - The configurations of a commutation failure detection circuit for a back-to-back SCR circuit and the controlling methods thereof are provided. The proposed commutation failure detection circuit includes a first detecting signal generator coupled to the back-to-back SCR circuit for detecting a commutation at a negative half cycle of an AC input voltage and including a first non-conductive signal amplifier circuit generating a first non-conductive signal when the back-to-back SCR circuit is not conductive at the negative half cycle of the AC input voltage and a second detecting signal generator coupled to the back-to-back SCR circuit for detecting the commutation at a positive half cycle of the AC input voltage and including a second non-conductive signal amplifier circuit generating a second non-conductive signal when the back-to-back SCR circuit is not conductive at the positive half cycle of the AC input voltage.01-22-2009
20090212812Multi-chip package semiconductor device and method of detecting a failure thereof - A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.08-27-2009
20080297190SYSTEM AND METHOD FOR TESTING SEMICONDUCTOR DEVICE - According to an example embodiment, a semiconductor device test system includes a semiconductor device and a test apparatus. The semiconductor device includes a plurality of function blocks for performing predetermined functions at different operating speeds and a plurality of ports, each corresponding to a respective function block. The test apparatus is adapted to generate a plurality of signals with different frequencies corresponding to each of the operating speeds of the function blocks, to output a plurality of input test data to the ports in response to the signals, and to receive a plurality of output test data from the ports to determine if the semiconductor device is normal.12-04-2008
20080297189MOBILITY MEASUREMENTS OF INVERSION CHARGE CARRIERS - A method and device for determining the quality of the interface surface between a layer of a dielectric material and the top surface of the semiconductor substrate are disclosed. In one aspect, the method comprises providing a semiconductor substrate with a top surface whereon a layer of a dielectric material is deposited thereby forming an interface surface, the surface of the layer of the dielectric material being or not in direct contact with the semiconductor substrate defining a top surface. A charge is then applied on a dedicated area of the top surface. A voltage Vs is measured on the top surface. The dedicated area is illuminated to define an illuminated spot. The photovoltage is measured inside and outside the determined illuminated spot during the illumination of the area.12-04-2008
20100176837ULTRA-THIN ORGANIC TFT CHEMICAL SENSOR, MAKING THEREOF, AND SENSING METHOD - An embodiment of the invention is an organic thin film transistor chemical sensor. The sensor includes a substrate. A gate electrode is isolated from drain and source electrodes by gate dielectric. An organic ultra-thin semiconductor thin film is arranged with respect to the gate, source and drain electrodes to act as a conduction channel in response to appropriate gate, source and drain potentials. The organic ultra-thin film is permeable to a chemical analyte of interest and consists of one or a few atomic or molecular monolayers of material. An example sensor array system includes a plurality of sensors of the invention. In a preferred embodiment, a sensor chip having a plurality of sensors is mounted in a socket, for example by wire bonding. The socket provides thermal and electrical interference isolation for the sensor chip from associated sensing circuitry that is mounted on a common substrate, such as a PCB (printed circuit board). A method of operating an organic thin film transistor chemical sensor exposes the sensor to a suspected analyte. A low duty cycle voltage pulse train is applied to the gate electrode to reduce baseline drift while sensing for a conduction channel change.07-15-2010
20100225347Circuit for Measuring Magnitude of Electrostatic Discharge (ESD) Events for Semiconductor Chip Bonding - A circuit for recording a magnitude of an ESD event during semiconductor assembly includes a voltage divider connected between an input and a ground. The circuit also includes a measurement block having a recorder device. Each measurement block receives current from a segment of the voltage divider. The magnitude of the ESD event is determined based upon a read-out of the measurement devices after the ESD event. The recorder device may be a capacitor that would be damaged during the ESD event. During the ESD event the capacitor may be damaged. Reading out the recorder device determines if the magnitude of the ESD event exceeded a threshold magnitude that damages the capacitor.09-09-2010
20100225346DEVICE AND METHOD FOR EVALUATING ELECTROSTATIC DISCHARGE PROTECTION CAPABILITIES - A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal.09-09-2010
20100231253METHOD AND APPARATUS FOR INSPECTING SEMICONDUCTOR DEVICE - The magnitude of an amplitude waveform of an electromagnetic wave generated when irradiating a pulse laser beam to a structure A including diffusion regions provided in the structure of a semiconductor device to be inspected is compared with the magnitude of an amplitude waveform of an electromagnetic wave radiated when irradiating the pulse laser beam to a structure A of a reference device measured in advance, and the detection sensitivity of the electromagnetic wave is corrected (S14). Thereafter, measurement errors caused by variations in the detection sensitivity of electromagnetic waves of an inspecting apparatus are eliminated by inspecting the semiconductor device as an inspection target, so that the quality of the semiconductor device is precisely determined (S16).09-16-2010
20100231252TESTABLE INTEGRATED CIRCUIT AND IC TEST METHOD - An integrated circuit (09-16-2010
20080252330METHOD AND APPARATUS FOR SINGULATED DIE TESTING - In accordance with one embodiment of the invention, a method of singulated die testing can be implemented. This can be implemented by obtaining a wafer and singulating the dies into individual die pieces. The singulated dies can be arranged in a separated testing arrangement and can even combine dies from multiple wafers as part of the combined arrangement. Then, testing can be implemented on the combined test arrangement.10-16-2008
20080290889Method of destructive testing the dielectric layer of a semiconductor wafer or sample - In a method of testing a semiconductor wafer or sample having a dielectric layer overlaying a substrate of semiconducting material, a contact is caused to touch a top surface of the dielectric layer. At least a portion of the contact touching the dielectric layer is formed of iridium. A controlled electrical stimulus that causes the dielectric layer to breakdown and an electrically conductive path to form through the dielectric layer is applied to the contact touching the top surface of the dielectric layer. Either a value of the controlled electrical stimulus where breakdown of the dielectric layer occurs or a time for the breakdown of the dielectric layer to occur in response to the application of the controlled electrical stimulus is determined. From the thus determined value or time, a determination can be made whether the dielectric layer is within acceptable tolerance.11-27-2008
20080246504APPARATUS AND METHOD TO MANAGE EXTERNAL VOLTAGE FOR SEMICONDUCTOR MEMORY TESTING WITH SERIAL INTERFACE - A serial-interface flash memory device includes a data/address I/O pin and a clock input pin. A bidirectional buffer is coupled to the data/address I/O pin. A serial interface logic block including data direction control is coupled to the clock pin, the bidirectional buffer, to internal control logic, and to read-voltage and modify-voltage generators. A first switch is coupled to the read-voltage generator and the clock buffer and a second switch is coupled to the modify-voltage generator and the clock buffer, the first and second switches each having a control input. Memory drivers are coupled to the read-voltage generator and the modify-voltage generator through the first and second switches. First and second registers coupled between the serial interface logic and the first and second switches. A memory array is coupled to the memory drivers and read amplifiers and program buffers are coupled between the serial interface logic and the memory drivers.10-09-2008
20080231309PERFORMANCE BOARD AND COVER MEMBER - A performance board which is attached to a semiconductor test apparatus and on which devices under test are mounted is provided. The performance board includes: a substrate; sockets which are attached to the surface of the substrate and on which devices under test are mounted; and an adiathermic cover member attached to the rear surface of a region of the substrate on which the sockets are mounted.09-25-2008
20080231308Sub-Sampling of Weakly-Driven Nodes - A method and apparatus for performing on-chip voltage sampling of a weakly-driven node of a semiconductor device are disclosed. In some embodiments, the node is a floating node or is capacitively-driven. In some embodiments, it is involved in proximity-based communication. Sampling the node may include isolating the signal to be sampled using a source-follower amplifier before passing it to the sampling circuit. Sampling the node may include biasing the node to a desired voltage using a leaky transistor or other biasing circuit. In some embodiments, the biasing circuit may also be used to calibrate the sampler by coupling one or more calibration voltages to the node in place of a biasing voltage and measuring the sampler output. The sampler may be suitable for sub-sampling high frequency signals to produce a time-expanded, lower frequency version of the signals. The output of the sampler may be a current communicated off-chip for testing.09-25-2008
20080224723METHOD FOR TESTING A SEMICONDUCTOR WAFER AND APPARATUS THEREOF - Reliability of results of a test such as a wafer burn-in test is raised. The present invention is a method for testing a plurality of semiconductor devices in a semiconductor wafer held in a cartridge. Each of the semiconductor devices has electrodes and the cartridge has a lower cartridge portion provided with a chuck holding the semiconductor wafer thereon, and an upper cartridge portion provided with a probe assembly having probes capable of contacting said electrodes. After constituting the cartridge and before placing the cartridge in the thermostatic chamber, a contact check to determine whether or not electrical contact between the electrodes of the semiconductor devices in the cartridge and the probes of the probe assembly is appropriate is performed.09-18-2008
20080197874TEST APPARATUS HAVING MULTIPLE TEST SITES AT ONE HANDLER AND ITS TEST METHOD - A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.08-21-2008
20080197873CLOCK SIGNAL DISTRIBUTING CIRCUIT, INFORMATION PROCESSING DEVICE AND CLOCK SIGNAL DISTRIBUTING METHOD - An integrated circuit includes a test pattern input unit for inputting a test pattern into cells, a clock distributing unit for distributing a clock signal to the cells, a first cell that receives the clock signal distributed by the clock distributing unit, a second cell that receives the clock signal after the clock signal is received by the first cell, a data transfer unit for transferring a data signal from the first cell to the second cell, a clock transfer unit for distributing the clock signal to the first cell and the second cell and transferring the clock signal in the same direction as the transfer direction of the data signal, and a failure detecting unit for inputting the test pattern into the cells and detecting failures of the cells on the basis of the results of the test pattern output from the cells.08-21-2008
20080197871Sequential semiconductor device tester - A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test pattern data.08-21-2008
20100289517BUILT OFF TESTING APPARATUS - A built off testing apparatus coupled between a semiconductor device and an external testing apparatus to test a semiconductor device. The built off testing apparatus can include a frequency multiplying unit to generate a test clock frequency by multiplying the frequency of a clock input by the external testing apparatus according to the operation speed of the semiconductor device, an instruction decoding unit to generate test information by decoding test signals input by the external testing apparatus according to the test clock frequency, and a test execution unit to test the semiconductor device according to the test information, and can determine whether the semiconductor device is failed or not based on test data output by the semiconductor device, and can transmit resulting data to the external testing apparatus.11-18-2010
20090140762LAYOUT FOR DUT ARRAYS USED IN SEMICONDUCTOR WAFER TESTING - A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.06-04-2009
20100013514Test device and semiconductor integrated circuit device - A test device and a semiconductor integrated circuit are provided. The test device may include a first test region and a second test region defined on a semiconductor substrate. The first test region may include a first test element and the second region may include a second test element. The first test element may include a pair of first secondary test regions in the semiconductor substrate extending in a first direction. The second test element may include structures corresponding to the first test element except the second test element does not include structures corresponding to the pair of first secondary test regions.01-21-2010

Patent applications in class Test of semiconductor device

Patent applications in all subclasses Test of semiconductor device