Entries |
Document | Title | Date |
20080197870 | Apparatus and Method For Determining Reliability Of An Integrated Circuit - In an embodiment, an integrated circuit or chip is supplied to its intended application and a measurement quantity representing the state of one or a plurality of electrical connections in the chip is determined within the application environment of the chip and, if the measurement quantity determined does not correspond to predefined criteria, a corresponding signal is output. | 08-21-2008 |
20080204063 | Testable Intergrated Circuit - An integrated circuit ( | 08-28-2008 |
20080211529 | INTEGRATED CIRCUIT FOR BEING APPLIED TO ELECTRONIC DEVICE, AND ASSOCIATED TESTING SYSTEM - An integrated circuit (IC) for being applied to an electronic device includes: a control circuit for controlling the electronic device; and a signal generation unit coupled to the control circuit for generating at least one signal inside the IC as an output signal and outputting the output signal to another IC for testing. A testing system includes at least one testing device and a plurality of ICs that are tested by the testing device. The ICs are coupled to the testing device. Each IC of the ICs is for being applied to an electronic device and includes: a control circuit for controlling the electronic device; and a signal generation unit coupled to the control circuit for generating at least one signal inside the IC as an output signal and outputting the output signal to one of the other IC(s) for testing. | 09-04-2008 |
20080224722 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a clock generator which generates a first clock, a test data generator which modulates a phase of the first clock, and generates test data to which jitter is added by using the modulated clock, a data extractor which samples the test data and extracts recovery data, and a detector which detects an error of the recovery data. | 09-18-2008 |
20080231306 | INTEGRATED CIRCUIT BURN-IN TEST SYSTEM AND ASSOCIATED METHODS - An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry. | 09-25-2008 |
20080238468 | Integrated circuit chip and method for testing an integrated circuit chip - In a method or apparatus such as an integrated circuit (IC) chip including a plurality of circuits for executing a plurality of testmodes, a testmode entry code specifying one of the plurality of testmodes and one of an unrestricted private testmode category and a restricted public testmode category is received. Execution of only a public testmode of the plurality of testmodes is enabled when the testmode entry code specifies the restricted public testmode category. Execution of all of the plurality of testmodes is enabled when the testmode entry code specifies the unrestricted private testmode category. | 10-02-2008 |
20080238469 | Semiconductor Device and Semiconductor Device Module - To provide a semiconductor module and a semiconductor device enabling more accurate testing of the connection state of the internal wiring between the semiconductor devices. The semiconductor device has switches SW | 10-02-2008 |
20080246502 | SEMICONDUCTOR DEVICE FOR TESTING SEMICONDUCTOR PROCESS AND METHOD THEREOF - A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing group includes a first testing block and a second testing. The first testing block includes: a first input node; a first output node; a plurality of first selecting nodes; a first reference device, coupled to the first input node and the first output node; and a first target device, coupled to the first selecting nodes and the first output node. The second testing block includes: a second input node; a second output node; a plurality of second selecting nodes; a second reference device, coupled to the second input node and the second output node; and a second target device, coupled to the second selecting nodes and the second output node. | 10-09-2008 |
20080246503 | Method of testing a semiconductor integrated circuit - A method of testing a semiconductor integrated circuit is disclosed. Specifically, a method of testing a semiconductor integrated circuit comprising a plurality of flip-flops is provided. The disclosed method includes connecting the plurality of flip-flops in series so that the plurality of flip-flops forms a scan-chain; inputting data to the scan-chain while supplying a clock signal to the plurality of flip-flops so that the data is set in the plurality of flip-flops; retaining the data in the plurality of flip-flops while inhibiting the clock signal for a predetermined period; restarting the clock signal to the plurality of flip-flops so that the data retained in the plurality of flip-flops is output from the scan-chain; and comparing the data output from the scan-chain and the data input to the scan-chain to test data retention of the plurality of flip-flops. | 10-09-2008 |
20080252329 | On-chip frequency degradation compensation - Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold. | 10-16-2008 |
20080258749 | TEST APPARATUS, AND ELECTRONIC DEVICE - A test apparatus that tests a device under test is provided. The test apparatus includes: a main memory that stores a test data row for testing the device under test; a cache memory that caches the test data row read from the main memory; a pattern generation control section that reads each test data which is not aligned in units of word being a data transfer unit of the main memory and writes the same to cache entries different from each other in the cache memory for each test data; and a pattern generating section that sequentially reads the test data stored of each cache entry in the cache memory and generates a test pattern for testing the device under test. | 10-23-2008 |
20080258750 | METHOD FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY - A method of measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The characterization array imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically. | 10-23-2008 |
20080258751 | On-Chip Power Supply Noise Detector - Techniques for on-chip detection of integrated circuit power supply noise are disclosed. By way of example, a technique for monitoring a power supply line in an integrated circuit includes the following steps/operations. A first signal and a second signal are preconditioned. The first signal is representative of a voltage of the power supply line being monitored. The second signal is representative of a voltage of a reference power supply line. Preconditioning includes shifting respective levels of the voltages such that the voltages are within an input voltage range of comparator circuitry. Then, the preconditioned first signal and the preconditioned second signal are compared in accordance with the comparator circuitry. Comparison includes detecting when a difference exists between the voltage level of the preconditioned first signal and the voltage level of the preconditioned second signal. | 10-23-2008 |
20080265928 | Semiconductor device and test method therefor - A semiconductor device, in which a test element group (TEG) including check patterns is formed together with a chip on a wafer so as to measure electric characteristics thereof, includes an interface circuit for selecting the check pattern from the test element group, a protection resistor connected in series with the test element group so as to protect the test element group, and a dummy element connected in series with the test element group. It allows the TEG test, which can be performed after packaging, to be easily performed at a high precision irrespective of dispersions of parasitic resistances and protection resistors. The test result is corrected based on the calculated values of the parasitic resistance and protection resistor and is then stored in a specific table form, wherein a pass/fail decision is made as to whether or not the test result falls within the prescribed range. | 10-30-2008 |
20080265929 | Process Monitor for Monitoring and Compensating Circuit Performance - A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operational circuit having at least one controllable circuit parameter. Each integrated circuit chip also includes a process monitor module at least partially constructed thereon. The controller is coupled to each process monitor module and to each operational circuit. The controller includes logic for evaluating the performance of an operational circuit based on data obtained from process monitor module and operational circuit related data stored in a memory. Based on the evaluation, the controller determines whether any deviations from desired or optimal performance of the circuit exist. If deviations exist, the controller generates a control signal to initiate adjustments to the operational circuit to compensate for the deviations. | 10-30-2008 |
20080265930 | Semiconductor device including analog voltage output driver LSI chip having test circuit - An LSI chip includes a plurality of output terminals and a test circuit. The test circuit includes a single test signal input terminal, a single test signal output terminal, a shift register, and a plurality of switches. The shift register includes an input terminal, which is connected to the test signal input terminal, output bits of the shift register being equal to a number of the output terminals of the LSI chip, and a voltage level of one of the output bits of the shift register being different from these of other output bits of the shift register in response to a clock pulse. Each switch includes an input terminal, an output terminal and a control terminal. A number of the switches is equal to the number of the output terminals of the LSI chip, each input terminal of the switches is connected to one of the output terminals of the LSI chip, the output terminals of the switches is commonly connected to the test signal output terminal, and each control terminal of each switch is connected to one of the output bits of the shift register. | 10-30-2008 |
20080265931 | On-chip electromigration monitoring - A method is provided for monitoring interconnect resistance within a semiconductor chip assembly. A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition. | 10-30-2008 |
20080272797 | Intergrated Circuit Self-Test Architecture - An integrated circuit ( | 11-06-2008 |
20080284459 | Testing Using Independently Controllable Voltage Islands - A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands, each powered by a respective island source voltage, and a testing circuit, coupled to the voltage islands, and powered by a global source voltage that is always on during test, wherein each island source voltage may be independently controlled during test. | 11-20-2008 |
20080303542 | TESTING CIRCUIT AND INTEGRATED CIRCUIT - A testing circuit includes at least two contact terminals and a plurality of first resistors. The contact terminals are located on a substrate and respectively connected to two ends of an original circuit on the substrate. The first resistors are embedded in the substrate and respectively connected to a plurality of devices of the original circuit in parallel or in series. | 12-11-2008 |
20080309364 | METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT - A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence. | 12-18-2008 |
20090009206 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively. A second multiplexer selects a reference data input bit that corresponds to one of the internal data strobe input signals of the input/output bit pair signals s from the delay line blocks and a third multiplexer for selecting a reference data output bit that corresponds to one of the phase shifted data strobe output signals from the input/output bit pair signals. A phase detector for determining a phase difference between the reference data input bit and the reference data output bit and outputting a phase difference value. | 01-08-2009 |
20090009207 | Sensor unit with safety system - A sensor unit is disclosed with a safety system for use with a signal generator, where at least one evaluation unit is provided for evaluating a signal from a sensor and for producing a first trigger signal based on the signal. In at least one embodiment, a more compact and less expensive version of a sensor unit is provided, which operates reliably under high safety demands. In at least one embodiment, this is achieved by a safety system which has a checking unit for checking the operation of the evaluation unit using a test signal. The test signal is processed by the evaluation unit in the same way as the signal from the sensor. The two-channel output is provided on the basis of a conclusiveness check in the checking unit. | 01-08-2009 |
20090015285 | TEST STRUCTURES FOR ELECTRICALLY DETECTING BACK END OF THE LINE FAILURES AND METHODS OF MAKING AND USING THE SAME - Test structures for electrically detecting BEOL failures are provided. In an embodiment, the structure comprises: an input/output connection disposed above a primary conductive pad which is embedded in an insulator; a dielectric layer disposed upon the insulator; a primary via extending through the dielectric layer down to the primary conductive pad for providing electrical connection between the input/output connection and the primary conductive pad; and a secondary via filled with a conductive material in electrical connection with the input/output connection, the secondary via extending through the dielectric layer down to a secondary interconnect in electrical connection with a secondary conductive pad that is insulated from the primary conductive pad. | 01-15-2009 |
20090015286 | Power supply voltage detection circuit and semiconductor integrated circuit device - A semiconductor integrated circuit device includes a first chip, a second chip to transmit and receive data to and from the first chip, and a through circuit provided in the first chip to transfer a clock signal and a test signal to the second chip. The clock signal and the test signal is inputted from an external device. The through circuit adjusts timing relation between the clock signal and the test signal based on a timing adjust signal. The timing adjust signal is inputted from the external device. | 01-15-2009 |
20090027074 | Test structure and test method - The present invention discloses a wafer level test structure and a test method; in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other. | 01-29-2009 |
20090027075 | System And Method of Digitally Testing An Analog Driver Circuit - A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal. The method of the present invention comprises digitally testing the differential driver circuit by activating a test enable signal, skewing the differential output termination impedance in response to the test enable signal, adjusting a voltage offset of the differential receiver circuit in response to the test enable signal, selecting a power level for the differential driver circuit in response to the test enable signal, enabling a decoder in response to the test enable signal, wherein the decoder activates only one segment of the differential driver circuit during any one test sequence, activating one of the segments for testing, stimulating the differential driver circuit with digital test patterns, receiving an output of the differential driver circuit by the differential receiver circuit, converting the received differential driver output to a single-ended signal, observing the single-ended signal; and deactivating the test enable signal. | 01-29-2009 |
20090027076 | DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUIT DICE IN AN INTEGRATED CIRCUIT MODULE - An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. | 01-29-2009 |
20090033350 | Element Substrate, Inspecting Method, and Manufacturing Method of Semiconductor Device - A substrate including a semiconductor layer, where characteristics of an element can be evaluated with high reliability, and an evaluating method thereof are provided. A substrate including a semiconductor layer of the invention has a closed-loop circuit in which an antenna coil and a semiconductor element are connected in series, and a surface of an area over which the circuit is formed is covered with an insulating film. By using such a circuit, a contactless inspection can be carried out. Further, a ring oscillator can be substituted for the closed-loop circuit. | 02-05-2009 |
20090045832 | CIRCUIT AND DATA CARRIER WITH RADIO FREQUENCY INTERFACE - A circuit ( | 02-19-2009 |
20090051383 | Test Method and Production Method for a Semiconductor Circuit Composed of Subcircuits - Test method and production method for testing a semiconductor circuit comprising a plurality of subcircuits. The semiconductor circuit is produced according to specification stipulations comprising a design based on a hardware description language for a functional implementation, a logic synthesis for a structural implementation, a layout design for a topological implementation and processing a semiconductor substrates in accordance with the layout design. A test pattern having test signal sequences is coupled into the semiconductor circuit and functional results are coupled out. Test signal lengths and/or test signal levels are selected from a previously generated test parameter list, wherein the test parameter list is generated during the logic synthesis. | 02-26-2009 |
20090058448 | PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit ( | 03-05-2009 |
20090066354 | Electrostatic Discharge Test System And Electrostatic Discharge Test Method - A method of conducting an electrostatic discharge test on an integrated circuit is described. The method comprises configuring a test board assembly to emulate characteristics of a system in which the integrated circuit is to be used, coupling the integrated circuit to the test board assembly, and applying an electrostatic discharge test signal of system-level type to the test board assembly. | 03-12-2009 |
20090066355 | Circuit Arrangement with Switchable Functionality and Electronic Component - A circuit with switchable functionality has a first integrated circuit, which has, in a first operating mode, full functionality and which has, in at least one other operating mode, a functionality which is reduced in comparison with the full functionality. The circuit further has an output terminal to which a coupling element can be coupled, an identification device which identifies whether a first supply potential has been applied to the output terminal via the coupling element and in this case produces a status signal with a first value and otherwise produces a status signal with a second value, a setting device, which sets the full or reduced functionality as a function of the value of the status signal in the first integrated circuit. The invention also relates to an electronic component having such a circuit arrangement. | 03-12-2009 |
20090079456 | APPARATUS, SYSTEM, AND METHOD FOR INTEGRATED COMPONENT TESTING - An apparatus, system, and method are disclosed for integrating component testing. A voltage module modifies a reference voltage integral to an electronic device to a plurality of reference voltage values. A test module tests a component of the electronic device at each of the plurality of reference voltage values. In addition, the test module determines a voltage range for the component, wherein the voltage range comprises voltage values between a high voltage failure and a low voltage failure. An optimization module sets the reference voltage value to within the voltage range. | 03-26-2009 |
20090079457 | CONNECTION TESTING APPARATUS AND METHOD AND CHIP USING THE SAME - A connection testing apparatus, a connection testing method, and a chip using the same are provided. The method can be used for testing connections between chips, so as to solve the problems that a conventional multi-chip connection test needs a plenty of test patterns, resulting in a long test time and a high test cost, and the condition of a connection failure is hard to be analyzed after a test failure. In the present invention, a voltage variation caused when an ESD element in a chip is conducted and a comparison circuits are used to determine whether a connection is correct. Furthermore, the test apparatus is built in the chip, so that the connection test may be accomplished quickly and efficiently. Once a connection failure occurs, the failed connection pin can also be found, so as to be favorable for engineering analysis and thereby effectively saving the test cost. | 03-26-2009 |
20090079458 | Small pitch ball grid array of a package assembly for use with conventional burn-in sockets - A package assembly ( | 03-26-2009 |
20090079459 | Evaluation pattern suitable for evaluation of lateral hillock formation - An evaluation pattern for evaluation of lateral hillock formation is provided with a lattice pattern; and an isolated metallization. The lattice pattern includes: a loop interconnection; and lattice interconnections laterally and vertically arranged to intersect with one another so that a region surrounded by the loop interconnection is divided into a plurality of sub-regions arranged in rows and columns. The width of the lattice interconnections is narrower than the width of the loop interconnection. The isolated metallization is provided in an outmost one of the sub-regions, the outmost one being surrounded by the loop interconnection and corresponding ones of the lattice interconnections. | 03-26-2009 |
20090079460 | SYSTEMS AND METHOD FOR MEASURING NEGATIVE BIAS THERMAL INSTABILITY WITH A RING OSCILLATOR - An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT), a first ring oscillator, a second DUT and a second ring oscillator. The first DUT is biased such that interface traps are generated during a first mode. The generated interface traps result in a decrease in a first drive current of the first DUT. The second device under test is biased to maintain a reference drive current during the first mode. The operating frequency of the first ring oscillator, during a second mode, is a function of the first drive current. The operating frequency of the second ring oscillator, during the second mode, is a function of the reference drive current. The integrated circuit may also include a comparator for generating an output signal as a function of a difference between the operating frequency of the first and second ring oscillator. | 03-26-2009 |
20090085597 | Process Monitor for Monitoring an Integrated Circuit Chip - A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip; and a digitizer module configured to produce, responsive to the one or more sense signals, one or more digitized signals each representative of a corresponding one of the sense signals. A controller is configured to determine a value of one or more of the process-dependent circuit parameters based on one or more of the digitized signals. | 04-02-2009 |
20090091344 | MAGNETIC SENSOR INTEGRATED CIRCUIT WITH TEST CONDUCTOR - A magnetic sensor integrated circuit includes a plurality of magnetically sensitive elements, and at least one test conductor positioned adjacent to at least one of the magnetically sensitive elements and configured to generate a differential magnetic field that is adapted to be applied to the plurality of magnetically sensitive elements during a test mode. | 04-09-2009 |
20090091345 | STRUCTURE FOR PROVIDING A DUPLICATE TEST SIGNAL OF AN OUTPUT SIGNAL UNDER TEST IN AN INTEGRATED CIRCUIT - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure provides a duplicate test signal of an output signal under test in an integrated circuit including selecting through a multiplexer an output signal under test, the output signal under test selected from a plurality of output signals of the integrated circuit; providing through the multiplexer a duplicate signal of the selected output signal under test; adding a high impedance load on the duplicate signal thereby reducing the amplitude of the duplicate signal; and amplifying the reduced duplicate signal thereby creating the duplicate test signal. | 04-09-2009 |
20090096476 | Method of inspecting semiconductor circuit having logic circuit as inspection circuit - A semiconductor circuit includes an inspection circuit for inspecting terminal open of the semiconductor circuit. The semiconductor circuit has a plurality of input terminals. The semiconductor circuit includes an input circuit portion connected to the plurality of input terminals. The inspection circuit includes a logic circuit, supplied with a plurality of input signals from the input circuit portion, for performing a predetermined logic operation to the plurality of input signals to produce a logic operation result. Whereby the semiconductor circuit enables to decide the presence or absence of the terminal open on the basis of the logic operation result. | 04-16-2009 |
20090096477 | APPARATUS AND METHODS FOR PERFORMING A TEST - A circuit structure has a circuit portion with negative resistance and a test resonator structure. Furthermore, the circuit structure has a unit for coupling the test resonator structure to the circuit portion with negative resistance during testing and for decoupling the test resonator structure from the circuit portion with negative resistance after testing. | 04-16-2009 |
20090115442 | Semiconductor integrated circuit and electronic device - A dummy wiring | 05-07-2009 |
20090121736 | DISPOSABLE BUILT-IN SELF-TEST DEVICES, SYSTEMS AND METHODS FOR TESTING THREE DIMENSIONAL INTEGRATED CIRCUITS - A device and method for self-testing an integrated circuit layer for a three-dimensional integrated circuit includes integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested. The first circuit forms a layer in a three-dimensional integrated circuit structure. The first circuit is tested using circuitry of the self-test circuit. The self-test circuit is removed by detaching the self-test circuit from the first circuit. | 05-14-2009 |
20090121737 | CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY - An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified. | 05-14-2009 |
20090134900 | Test apparatus, pin electronics card, electrical device and switch - Provided is a test apparatus for testing a device under test, the test apparatus including: a pattern generating section that inputs a test pattern to the device under test; a judging section that receives an output signal of the device under test, and makes judgment concerning pass/fail of the device under test based on the output signal; an internal circuit that exchanges signals between the device under test and the pattern generating section or the judging section; a first transmission line that connects the internal circuit to the device under test; and a first switch that connects the first transmission line to a ground potential in not testing the device under test, and cuts off the first transmission line from the ground potential in testing of the device under test. | 05-28-2009 |
20090146677 | TEST APPARATUS AND PIN ELECTRONICS CARD - There is provided a test apparatus including a driver that outputs a test signal to a device under test, a first switch that switches whether to connect the driver to the device under test, a comparator that receives an output signal from the device under test via the first switch, and compares a voltage of the output signal with a predetermined reference voltage, a reference voltage input section that inputs the reference voltage into the comparator, a second switch that is provided between the reference voltage input section and the comparator, and a dummy resistance that is connected at one end thereof to a connection point between the comparator and the second switch and at the other end thereof to a predetermined potential. Here, a resistance ratio between an output resistance of the driver and an on-resistance of the first switch is substantially equal to a resistance ratio between the dummy resistance and an on-resistance of the second switch. | 06-11-2009 |
20090153172 | STRUCTURE FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM - A design structure embodied in a machine readable medium used in a design process includes a system for indicating status of an on-chip power supply system with multiple power supplies, having a power system status register for receiving digital compliance signals, each compliance signal associated with one of the multiple power supplies, and having an associated compliance level, wherein each digital compliance signal indicates whether its associated power supply is operating at the associated compliance level, and wherein the power system status register generates a power supply status signal based on the digital compliance signals indicating status of the digital compliance signals; and an output for outputting the power supply status signal, wherein if a power supply is operating at its associated compliance level, the power supply status signal indicates that the power supply is passing, otherwise the power supply status signal indicates that the power supply is failing. | 06-18-2009 |
20090153173 | Semiconductor Device - An object of the invention is to manage variation of electrical characteristics of an element in a semiconductor device due to a vapor deposition process by measuring electrical characteristics of a TEG. A substrate | 06-18-2009 |
20090160474 | PRINTED CIRCUIT BOARD AND IMPEDANCE GUARANTEE METHOD OF PRINTED CIRCUIT BOARD - According to one embodiment, a printed circuit board includes a coupon portion having, for each of a plurality of signal layers, an impedance guarantee coupon as a reference for the layer, and a product portion having, in at least one of the plurality of signal layers, a transmission line requiring impedance guarantee having an impedance decision factor different from the coupon formed in the coupon portion, wherein an impedance of the transmission line is guaranteed on the basis of a known impedance decision factor of the transmission line and a measured value of the coupon. | 06-25-2009 |
20090167336 | METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS - A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects. | 07-02-2009 |
20090167337 | Semiconductor integrated circuit device which has first chip and second chip accessed via the first chip and test method thereof - A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line. | 07-02-2009 |
20090167338 | TEST PATTERN FOR ANALYZING CAPACITANCE OF INTERCONNECTION LINE - Disclosed is a test pattern for analyzing capacitances of interconnection lines that accounts for parasitic capacitance components. The test pattern includes a first metal line having a comb-type structure including a plurality of tines, a second metal line having a comb-type structure including a plurality of tines engaged with the tines of the first metal line, a first probe pad switchably connected to the first metal line, and a second probe pad switchably connected to the second metal line. Switchable connections between the first metal line and the first probe pad and between the second metal line and the second probe pad may be provided by first and second switch terminals, respectively. The test pattern enables a capacitance measurement that accounts for parasitic capacitance components of pads and portions of interconnection lines leading from the pads, which otherwise interfere with accurate measurement of capacitances of the interconnection lines. | 07-02-2009 |
20090174425 | TEST CIRCUIT FOR A SEMICONDUCTOR INTEGRATED CIRCUIT - A test circuit includes an output control section for generating a plurality of output buffer control signals in response to a plurality of data masking signals when a test mode signal is activated in read operation; and a data output buffer for masking some of data input and output pins in response to the plurality of output buffer control signals. | 07-09-2009 |
20090174426 | Semiconductor Device with Fault Detection Function - A semiconductor device ( | 07-09-2009 |
20090179660 | Non-invasiv, low pin count test circuits and methods utilizing emulated stress conditions - An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode. | 07-16-2009 |
20090189628 | Reworkable bonding pad layout and debug method thereof - The reworkable bonding pad layout includes a first point, a second point, a reworkable bonding pad, a first leading wire, and a second leading wire. There is a debug position defined between the first point and the second point. The reworkable bonding pad is formed at the debug position. The first leading wire may connect the reworkable bonding pad and the first point. The second leading wire may connect the reworkable bonding pad and the second point. The reworkable bonding pad is cut into a first debug area connecting with the first leading wire, and a second debug area connecting with the second leading wire. | 07-30-2009 |
20090189629 | SEMICONDUCTOR WAFER HAVING A MULTITUDE OF SENSOR ELEMENTS AND METHOD FOR MEASURING SENSOR ELEMENTS ON A SEMICONDUCTOR WAFER - In the measurement of sensor elements in a wafer composite, whereby non-electric stimuli are to be applied to the sensor elements, a semiconductor wafer having a multitude of sensor elements, each sensor element having a voltage supply connection, a grounded connection, and at least one sensor signal output, is configured such that a bus system is integrated in the semiconductor wafer, to which bus system at least the grounded connections of the sensor elements are connected and via which a supply voltage may be applied to the sensor elements, and that each sensor element is equipped with at least one controllable switching element for selecting the sensor element, so that only a selected sensor element supplies a sensor signal to a diagnosis device. | 07-30-2009 |
20090195265 | DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUITS - A method and device for testing an integrated circuit. The method includes selecting between a shadow latch data retention mode and a shadow latch test mode; performing first test of an integrated circuit; storing, at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing a second test of the integrated circuit; and generating a test equipment detectable signal if the first test-imposed state differs from a second test-imposed state of the tested latch. | 08-06-2009 |
20090201042 | THIN FILM TRANSISTOR ARRAY HAVING TEST CIRCUITRY - A thin film transistor (TFT) array having test circuitry includes a thin film transistor array body having a plurality of pixels. Test circuitry is integrally formed with the body. The test circuitry includes a power supply for supplying power via the test circuitry to the body; and a plurality of wireless switches to activate selected pixels. | 08-13-2009 |
20090206863 | System and Method for Testing a Plurality of Circuits - A system for, and method of, testing a plurality of circuits, which may be unsingulated die on a wafer. In one embodiment, the system includes: (1) a test data interconnect that connects a test data output of a first circuit directly to a test data input of a second circuit located adjacent to the first circuit, (2) a test clock interconnect that connects a test clock output of the first circuit directly to a test clock input of the second circuit, (3) a test mode select interconnect that connects a test mode select output of the first circuit directly to a test mode select input of the second circuit and (4) a contact region coupled to provide test data, a test clock signal and a test mode select signal respectively to the test data interconnect, the test clock interconnect and the test mode select interconnect. | 08-20-2009 |
20090206864 | On-chip servo loop integrated circuit system test circuitry and method - Internal servo loop circuitry is included on the same chip ( | 08-20-2009 |
20090206865 | ELECTRICAL TEST STRUCTURE AND METHOD FOR CHARACTERIZATION OF DEEP TRENCH SIDEWALL RELIABILITY - A test structure and testing method are provided for characterizing the time-dependent drift in the parasitic PFET leakage current that flows along the sidewall of a deep trench isolation structure from the P-type active area to the P-type substrate in a semiconductor integrated circuit structure. The capacitive coupling characteristics of the deep trench isolation structure are used to control the electrical “bias” of the deep trench structure through the use of a large auxiliary trench mesh network that is formed as part of the deep trench structure. The trench mesh network can be placed adjacent to a Vdd ring or a ground ring and then, by using a ratioed capacitive voltage dividing network, the electrical potential at the trench can be controlled. | 08-20-2009 |
20090206866 | DEVICE AND METHOD FOR TESTING A DEVICE - A device that includes a core and a wrapper. The wrapper includes at least one shared wrapper cell that is shared by a group of core pins that belong to a single clock domain. A method for designing a wrapper. The method includes receiving design information representative of a design of a core, locating a group of mutually independent core pins that belong to a single clock domain; and designing a shared wrapped cell that is shared by the group of core pins. | 08-20-2009 |
20090206867 | Self-Test Method for Interface Circuit - An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal. | 08-20-2009 |
20090212808 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - An electro-optical device includes a test circuit for testing drive of a plurality of pixel units and a plurality of test terminals that output inputted signals to the test circuit or that output signals inputted from the test circuit. The test terminals including a first test terminal input with a high frequency signal with a frequency higher than a frequency of a signal output from a second terminal. A third test terminal is interposed between the first test terminal and the second test terminal. | 08-27-2009 |
20090212809 | DEVICE TEST AND DEBUG USING POWER AND GROUND TERMINALS - The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals. | 08-27-2009 |
20090212810 | ISOLATION CIRCUIT - The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor configured for connection to a supply voltage via a first terminal; a register connected to the first transistor; a second transistor in parallel with a resistor, wherein the second transistor is configured for connection to the first terminal, with a gate of the second transistor configured for connection to an output of the register; and wherein the second transistor is configured for connection to a second terminal, the second transistor having a state that depends on a status of the register. | 08-27-2009 |
20090219048 | Image Display Device and Testing Method of the Same - It is the primary object of the present invention to provide a simple and accurate testing circuit and a testing method while occupying as small space as possible in an image display device. The testing circuit including a NAND circuit connected in series is mounted on the image display device. A broken wiring on a data signal line and a defect in a data latch circuit can be detected by observing an output waveform from the testing circuit. Accordingly, a broken wiring or the like on the data signal line and a scanning line and a defect in the latch circuit can be tested simply and accurately without an expensive testing apparatus and a great deal of time while occupying as small space as possible. | 09-03-2009 |
20090230986 | SEMICONDUCTOR INTEGRATED CIRCUIT, FUSE CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD OF THE SAME - A fuse circuit for a semiconductor integrated circuit includes a control unit configured to activate a fuse set control signal in response to an external command signal, and a plurality of fuse sets, each configured so that power is supplied to internal fuses in response to the activation of the fuse set control signal. | 09-17-2009 |
20090251164 | PROCESS AND TEMPERATURE INSENSITIVE FLICKER NOISE MONITOR CIRCUIT - In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range. | 10-08-2009 |
20090273360 | SYSTEM FOR ISOLATING A SHORT-CIRCUITED INTEGRATED CIRCUIT (IC) FROM OTHER ICs ON A SEMICONDUCTOR WAFER - A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are interconnected with the short-circuited IC includes control circuitry within the short-circuited IC for sensing the short circuit. The control circuitry may sense the short circuit in a variety of ways, including sensing excessive current drawn by the short-circuited IC, and sensing an abnormally low or high voltage within the short-circuited IC. Switching circuitry also within the short-circuited IC selectively isolates the short-circuited IC from the other ICs on the wafer in response to the control circuitry sensing the short circuit. As a result, if the wafer is under probe test, for example, testing can continue uninterrupted on the other ICs while the short-circuited IC is isolated. | 11-05-2009 |
20090284278 | DISPLAY DEVICE AND ELECTRONIC APPARATUS HAVING THE DISPLAY DEVICE - To provide a display device having a test circuit with high accuracy for testing in the step after a counter substrate is attached and before shipping, and to provide a display device having a correction circuit inside the display device, for the case where a defect occurs. A pixel circuit operated by a gate line and a source line, a first wiring formed at the same time as the gate line, a second wiring formed at the same time as the source line, and a test circuit of detecting a defect of the pixel circuit by using potentials of the first wiring and the second wiring are provided over a substrate. | 11-19-2009 |
20090295418 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, including a first pipeline that sequentially propagates pieces of pattern data included in a first test pattern, according to a first test period, and outputs the resulting data to the device under test; a second pipeline that sequentially propagates pieces of pattern data included in a second test pattern, according to a second test period that is different from the first test period, and outputs the resulting data to the device under test; a timing control section that controls at least one of a timing at which the first pipeline begins propagating a predetermined first pattern data and a timing at which the second pipeline begins propagating a predetermined second pattern data, based on the first test period and the second test period; and a judging section that judges pass/fail of the device under test based on a signal output by the device under test. | 12-03-2009 |
20090295419 | MEMORY CHIP AND METHOD FOR OPERATING THE SAME - A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip. | 12-03-2009 |
20090295420 | SEMICONDUCTOR DEVICE AND TESTING METHOD - A semiconductor device, comprising: a wafer; a radio receiving circuit chip that is formed on the wafer, and receives electric power and a test start signal transmitted by radio from outside; and a plurality of non-volatile memory chips that are formed on the wafer and respectively have self-diagnosis test circuits mounted thereon, wherein, in a test in a wafer state, in response to supply of the electric power and the test start signal from the radio receiving circuit chip through an interchip interconnection, all of the non-volatile memory chips on the wafer simultaneously execute tests by the self-diagnosis test circuits, and respectively write results of the tests into their own memory areas. | 12-03-2009 |
20090309621 | IDDQ TESTING - Embodiments of the invention relate to device-embedded IDDQ testing in the field to detect defects, aging, and other reliability reducing problems. Methods of testing integrated circuits and integrated circuit devices are disclosed. For example, an integrated circuit device can comprise an integrated circuit, a buffer capacitor coupled to the integrated circuit; and IDDQ test circuitry coupled to the buffer capacitor and configured to suspend normal operation of the integrated circuit and measure a discharge time of the buffer capacitor, wherein the discharge time is related to a leakage current of the integrated circuit. | 12-17-2009 |
20090309622 | METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT - A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence. | 12-17-2009 |
20090315582 | Test mode enable circuit - A test mode enable circuit for putting a device in a test mode includes a serial-to-parallel shift register reset by a reset signal, a decoder circuit, and a gate circuit. The shift register receives and converts a control signal in serial form to control data in parallel form. The decoder circuit receives and decodes the control data to a test mode enable signal that puts the device in the test mode. The decoder circuit outputs the test mode enable signal to the gate circuit only when the control data matches a predetermined key pattern. The gate circuit outputs the test mode enable signal to the device only when at least one of the control signal and the reset signal has a predetermined voltage level. | 12-24-2009 |
20090315583 | TESTABLE INTEGRATED CIRCUIT AND IC TEST METHOD - A circuit portion ( | 12-24-2009 |
20090322365 | INTEGRATED MEMS METROLOGY DEVICE USING COMPLEMENTARY MEASURING COMBS - The present invention provides a device for in-situ monitoring of material, process and dynamic properties of a MEMS device. The monitoring device includes a pair of comb drives, a cantilever suspension comprising a translating shuttle operatively connected with the pair of comb drives, structures for applying an electrical potential to the comb drives to displace the shuttle, structures for measuring an electrical potential from the pair of comb drives; measuring combs configured to measure the displacement of the shuttle, and structures for measuring an electrical capacitance of the measuring combs. Each of the comb drives may have differently sized comb finger gaps and a different number of comb finger gaps. The shuttle may be formed on two cantilevers perpendicularly disposed with the shuttle, whereby the cantilevers act as springs to return the shuttle to its initial position after each displacement. | 12-31-2009 |
20090322366 | Integrated Tester Chip Using Die Packaging Technologies - By constructing a universal test circuit on a tester chip, and stacking the tester chip in an IC package together with operational circuit chips to be tested, the problems inherent with external IC testing are reduced. The tester chip can be standardizes across a number of different chip combinations and, if desired, pre-programmed during manufacturing for a particular package. The tester chip interfaces to other chips in the stack advantageously are standardized. | 12-31-2009 |
20090322367 | INTEGRATED CIRCUIT AND A METHOD FOR MEASURING A QUIESCENT CURRENT OF A MODULE - A method for evaluating a quiescent current, the method includes: measuring, when a module is at a first mode, a first voltage drop on a first resistor that is coupled between a supply pin of an integrated circuit that comprises the module and a first test pin of the integrated circuit; assessing, when the module is at a second mode, a second voltage drop on a second resistor that is coupled between the supply pin and a second test pin of the integrated circuit; and evaluating a quiescent current of the module in response to the first and second voltage drops; wherein expected values of quiescent current of the module differ from one mode to the other; and wherein a resistance of the first resistor differs from the resistance of the second resistor. | 12-31-2009 |
20090322368 | Integrated Tester Chip Using Die Packaging Technologies - By constructing a universal test circuit on a tester chip, and stacking the tester chip in an IC package together with operational circuit chips to be tested, the problems inherent with external IC testing are reduced. The tester chip can be standardized across a number of different chip combinations and, if desired, pre-programmed during manufacturing for a particular package. The tester chip interfaces to other chips in the stack advantageously are standardized. | 12-31-2009 |
20090322369 | Test system - A test system may include a test device, a switching unit and/or a test board. The test device may be configured to generate a first test signal swinging between a first voltage level and a second voltage level, and the first voltage level may be lower than the second voltage level. The switching unit may be coupled to the test device, and configured to switch the first test signal to provide a second test signal swinging between a third voltage level and a fourth voltage level. The third voltage level may be lower than the fourth voltage level. A plurality of devices under test (DUTs) may be mounted on the test board. Each of the plurality of DUTs may be connected in parallel with respect to one another to the switching unit through a transmission line. | 12-31-2009 |
20090322370 | Method And Apparatus For Test And Characterization Of Semiconductor Components - A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system. | 12-31-2009 |
20100007366 | TEST EQUIPMENT AND SEMICONDUCTOR DEVICE - An interface circuit is connected to an ATE via a test control bus BUS | 01-14-2010 |
20100013510 | SYSTEMS AND METHODS FOR DEFECT TESTING OF EXTERNALLY ACCESSIBLE INTEGRATED CIRCUIT INTERCONNECTS - Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad. | 01-21-2010 |
20100019794 | INTEGRATED CIRCUIT AND A METHOD FOR TESTING A MULTI-TAP INTEGRATED CIRCUIT - An integrated circuit that includes a controller for defining a test path that comprises at least one test access port out of multiple test access ports characterized by further comprising at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path. Conveniently, the length of the test path remains substantially fixed regardless of changes in a configuration of the test path. A method for testing an integrated circuit, the method includes a stage of propagating test signals across a test path. Whereas the method is characterized by a stage of defining a configuration of the test path, whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic; whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path. | 01-28-2010 |
20100045326 | THERMAL MONITORING AND MANAGEMENT OF INTEGRATED CIRCUITS - The invention, in one aspect, provides a semiconductor device ( | 02-25-2010 |
20100045327 | TEST CIRCUIT AND TEST METHOD FOR POWER SWITCH - For on-chip testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, after the power switch enters a test mode, the decoupling capacitance is pre-charged or discharged; the power switch is turned ON or OFF according to test patterns; and a voltage level at the decoupling capacitance is analyzed or a leakage current flowing the power switch is measured. So that, whether the power switch is passed or failed is identified. | 02-25-2010 |
20100045328 | CIRCUIT FOR DETECTING BONDING DEFECT IN MULTI-BONDING WIRE - An integrated circuit for detecting a bonding defect in a multi-bonding wire. The integrated circuit includes a plurality of pads each connectable by a bonding wire to a lead terminal. Voltage supplied to the lead terminal is applied in common to the plurality of pads. A detection circuit is operably connected to the plurality of pads. The detection circuit detects breakage of the bonding wires based on potentials at the plurality of pads. | 02-25-2010 |
20100045329 | Probeless DC testing of CMOS I/O circuits - A method and implementation is described by which I/O input and output circuitry of a CMOS chip are measured without the need to probe the chip. Output driver transistors are used to provide marginal voltages to test input circuits, and the output driver transistors are segmented into portions where a first portion is used to provide a representative “on” current, which is coupled to a test bus that is further connected to a current comparator circuit contained within the chip. Both leakage and “on” current of the driver transistors is measured using segmented driver transistors. The output of the current comparator circuit is connected to a test scan register or to a test output from which test results are obtained digitally. The testing techniques are also applicable for other semiconductor devices. | 02-25-2010 |
20100052722 | TEST JIG - A test jig is for testing electrical characteristics of a high frequency semiconductor device in a package having a ground electrode and a high frequency signal electrode. The test jig includes a test circuit substrate with a microstrip line structure, a grounding block and a high frequency signal contact pin. The test circuit substrate includes an insulating substrate, a ground conductor on a bottom surface of the insulating substrate and high frequency signal wiring on a top surface of the insulating substrate. The grounding block is disposed on the top surface of the insulating substrate and connected to the ground conductor. The high frequency signal contact pin is disposed on the top surface of the insulating substrate and connected to the high frequency signal wiring. The high frequency signal contact pin is spaced from the grounding block. | 03-04-2010 |
20100060306 | FREQUENCY SPECIFIC CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS - Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit. | 03-11-2010 |
20100079162 | DATA PROCESSING DEVICE AND METHODS THEREOF - A data processing device includes a first memory for use during normal operation of the device and a second memory for use during testing. The second memory stores a set of test patterns for testing of a functional module. When the data processing device is in a normal (i.e. non-test) mode of operation, data is retrieved from a first memory based on a received memory address. The retrieved data is applied to the functional module of the data processing device to perform a designated function. When the data processing device is in a test mode of operation, received memory addresses are provided to the second memory for retrieval of a test pattern associated with the address. The test pattern is applied to the functional module to generate an output pattern. The result of a test is determined by comparing the output pattern to an expected pattern. | 04-01-2010 |
20100090716 | Integrated Circuit Device to Support Inductive Sensing - An integrated circuit device inductive touch analog front end (AFE) excites selected ones of a plurality of inductive touch sensors, measures voltages across the coils of the plurality of inductive touch sensors, and provides analog output signals representative of these coil voltages. A physical displacement (touch) to the inductive sensor causes the inductance value of the inductive touch sensor to change with a corresponding change in a voltage across the coil of the inductive touch sensor. A digital processor controls selection of each one of the plurality of inductive touch sensors and receives the respective analog output voltage signal from the inductive touch AFE. When a sufficient change in the coil voltage is determined by the digital processor, that inductive touch sensor is assumed to have been actuated and the digital processor takes action based upon which one of the plurality of inductive touch sensors was actuated (touched). | 04-15-2010 |
20100090717 | Programmable Integrated Circuit Device to Support Inductive Sensing - An integrated circuit device inductive touch analog front end excites selected ones of a plurality of inductive touch sensors and provides analog output signals representative of voltages across the coils of the plurality of inductive touch sensors. Various characteristics of the inductive touch analog front end are programmable. A digital processor controls selection of each one of the plurality of inductive touch sensors and receives the respective analog output voltage signal from the inductive touch AFE. The digital processor may program the characteristics of the inductive touch analog front end. When a sufficient change in the coil voltage is determined by the digital processor, that inductive touch sensor is assumed to have been actuated and the digital processor takes action based upon which one of the plurality of inductive touch sensors was actuated (touched). | 04-15-2010 |
20100097087 | EYE MAPPING BUILT-IN SELF TEST (BIST) METHOD AND APPARATUS - A built-in self test for receiver operation is provided through a testing method that evaluates characteristics of a received signal eye diagram. The receiver receives a serial data signal and applies compensation to that received serial data signal to generate a compensated serial data signal. The properties of an eye diagram associated with the compensated serial data signal are measured. In this context, certain desired eye diagram properties are characterized by parameters indicative of pass/fail criteria for receiver testing. The measured eye diagram properties are then compared against the parameters. A receiver testing conclusion signal is then output based on results of the comparison. | 04-22-2010 |
20100097088 | SENSOR APPARATUS - The present invention includes an output circuit section for digitally outputting from an output terminal in a time division system a failure detection signal from a failure diagnosis circuit and a sense signal from a process circuit section, leading to reduction in size of a sensor apparatus. Further, outputting a failure detection signal earlier than a sense signal leads to improvement in reliability at the time of abnormality. | 04-22-2010 |
20100102842 | SYSTEM AND METHOD FOR MEASURING NEGATIVE BIAS THERMAL INSTABILITY WITH A RING OSCILLATOR - An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT) module coupled to a first ring oscillator module and a second DUT module coupled to a second ring oscillator module. The first DUT module is biased such that interface traps are generated during a first mode. The generated interface traps result in a decrease in a first drive current of the first DUT module. The second device under test module is biased to maintain a reference drive current during the first mode. The operating frequency of the first ring oscillator module, during a second mode, is a function of the first drive current. The operating frequency of the second ring oscillator module, during the second mode, is a function of the reference drive current. The integrated circuit may also include a comparator module for generating an output signal as a function of a difference between the operating frequency of the first and second ring oscillator modules. | 04-29-2010 |
20100117675 | LIQUID CRYSTAL DISPLAY DEVICE AND ANALYSIS DEVICE INCLUDING THE SAME - In order to provide a liquid crystal display device which can detect a defective indication due to short circuit which occurs between a common electrode and a counter electrode by a conductive impurity enters into a liquid crystal display panel, and an analysis device including the same, a blood glucose meter includes a display section and a microcomputer. For performing an inspection for a defective indication on a liquid crystal display panel of the display section, the microcomputer uses ports as input/output ports for a defective indication inspection. The microcomputer detects whether an inspection signal sent from the port can be received at the other port or not to perform the inspection for a defective indication. | 05-13-2010 |
20100127729 | IC TESTING METHODS AND APPARATUS - An integrated circuit comprises a device under test and embedded test circuitry. The embedded test circuitry comprises a plurality of process monitoring sensors ( | 05-27-2010 |
20100134132 | MONITORING CIRCUIT HAVING A SELF TEST FUNCTION - A measuring apparatus including a self test function, the circuit comprising a capacitor; first to fourth switches; a test signal injector; at least one comparator having a signal input and a reference input the first switch being interposed between a first plate of the capacitor and a first input node, the second switch being interposed between a second plate of the capacitor and a second input node, the third switch being interposed between the first plate of the capacitor and the signal input of the comparator and the fourth switch being interposed between the second plate of the capacitor and a voltage reference, wherein the self test function comprises the steps of i) operating the signal injector to produce a first signal representative of an out of range voltage for an expected voltage difference between the first and second input nodes, and using the signal to cause the at least one comparator to place its output in an error state, and to charge the capacitor to the out of range voltage, ii) isolating the capacitor from the signal injector and voltage reference, and connecting the capacitor between the first and second input nodes such that the voltage stored on the capacitor is overwritten by the voltage difference between the first and second nodes, and iii) and reconnecting the capacitor to the comparator and monitoring the comparator's output. | 06-03-2010 |
20100134133 | METHOD FOR PERFORMING AN ELECTRICAL TESTING OF ELECTRONIC DEVICES - A method of electrical testing electronic devices DUT, comprising: connecting at least an electronic device DUT to an automatic testing apparatus suitable for performing the testing of digital circuits or memories or of digital circuits and memories; sending electrical testing command signals to the electronic device DUT by means of the ATE apparatus; performing electrical testing of the electronic device DUT by means of at least one advanced supervised self testing system “Advanced Low Pin Count BIST” ALB which is built in the electronic device DUT, the ALB system being digitally interfaced with the ATE through a dedicated digital communication channel; and sending reply messages, if any, which comprise measures, failure information and reply data to the command signals from the electronic device DUT toward the ATE apparatus by means of the digital communication channel. | 06-03-2010 |
20100134134 | TEST ELECTRONICS TO DEVICE UNDER TEST INTERFACES, AND METHODS AND APPARATUS USING SAME - In one embodiment, a test system has a set of test electronics for testing a device under test (DUT). The test system also has at least one test electronics to DUT interface having a zero insertion force (ZIF) connector. Each ZIF connector has a ZIF connector to DUT clamping mechanism configured to i) apply a first orthogonal force to a probe card that interfaces with a DUT, by pressing the ZIF connector against the probe card, and simultaneously ii) exert at least one second orthogonal force on the probe card, the at least one second orthogonal force being opposite in direction to the first orthogonal force. | 06-03-2010 |
20100148815 | TEST APPARATUS - Provided is a test apparatus that tests a device under test having a test function for sequentially outputting, from a single test terminal, signals that would be output from a plurality of terminals, the test apparatus comprising: a test section that supplies the device under test with a test signal and receives signals that are sequentially output from the test terminal in response to the test signal; an identifying section that identifies a correspondence between each signal sequentially received by the test section and a signal that would be output from one of the terminals of the device under test; and a counting section that counts a number of signals judged to be unacceptable from among the signals sequentially received by the test section for each terminal of the device under test, based on the correspondence identified by the identifying section. | 06-17-2010 |
20100156450 | Enabling higher operation speed and/or lower power consumption in a semiconductor integrated circuit device - A semiconductor integrated circuit device | 06-24-2010 |
20100164527 | TEST MODULE WITH BLOCKS OF UNIVERSAL AND SPECIFIC RESOURCES - A test module for a test apparatus for testing a device under test, the test module being adapted for performing a specific test function and having a universal section adapted to provide test resources being unspecific with regard to the test function of the test module, the universal section having a control interface adapted to be connected to a central control device of the test apparatus, and having a specific section to be coupled to the universal section and adapted to provide test resources being specific with regard to the test function of the test module, the specific section having a device under test interface adapted to be connected to the device under test. | 07-01-2010 |
20100171520 | FLAT-PANEL DISPLAY HAVING TEST ARCHITECTURE - A flat-panel display having simplified test architecture is disclosed for reducing substrate border area. The flat-panel display includes a plurality of data lines, a plurality of gate lines, a plurality of first conductive lines, a plurality of first one-way switching units, a plurality of second one-way switching units, a plurality of control units and a second conductive line. The gate lines are used to deliver gate signals for use in a test. Each first one-way switching unit functions to allow one-way signal transmission from a corresponding first conductive line to a corresponding gate line. Each second one-way switching unit functions to allow one-way signal transmission from a corresponding first conductive line to the second conductive line. The second conductive line is employed to deliver a corresponding gate signal furnished by a corresponding second one-way switching unit. Each control unit controls inputting of test data signals to one corresponding data line. | 07-08-2010 |
20100176835 | TEST APPARATUS AND TRANSMISSION APPARATUS - A test apparatus for testing a device under test includes a test signal generating section that generates a test signal to be supplied to the device under test, a main driving section that outputs an output voltage determined in accordance with the test signal, to an input/output pin connected to a signal input/output terminal of the device under test, a replica driving section that outputs a comparison voltage determined in accordance with the test signal, a resistance voltage dividing section that generates a divided voltage by resistance-dividing the comparison voltage, a comparing section that compares a voltage of the input/output pin with the divided voltage, a judging section that judges acceptability of the device under test based on a result of the comparison by the comparing section, and an adjusting section that adjusts a voltage dividing ratio of the resistance voltage dividing section so that the divided voltage becomes equal to a voltage obtained by adding together a predetermined threshold voltage and a voltage of the input/output pin that is observed when the main driving section has output the output voltage and the signal input/output terminal of the device under test has not output a response signal. | 07-15-2010 |
20100182033 | TESTABLE INTEGRATED CIRCUIT AND TEST METHOD - An integrated circuit ( | 07-22-2010 |
20100188114 | Circuit for Detecting Tier-to-Tier Couplings in Stacked Integrated Circuit Devices - A first semiconductor tier has a first tier-to-tier connector for detecting a tier-to-tier coupling in a stacked integrated circuit (IC) device. A second semiconductor tier has a second tier-to-tier connector configured to electrically couple to the first tier-to-tier connector. A tier-to-tier detection circuit electrically couples to the second tier-to-tier connector. The tier-to-tier detection circuit generates an output signal indicative of an electrical coupling between the first semiconductor tier and the second semiconductor tier. | 07-29-2010 |
20100194421 | TEST EQUIPMENT AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern for testing the device under test; a signal supplying section that supplies the device under test with a test signal corresponding to the test pattern; a trigger generating section that supplies a trigger signal to an external instrument connected to the device under test; and a synchronization control section that outputs, to the trigger generating section, a synchronization signal instructing generation of the trigger signal, based on at least a portion of the test pattern generated by the pattern generating section. | 08-05-2010 |
20100201393 | CHIP CARD WITH A MEASURING CIRCUIT THAT HAS A SENSOR, AND METHOD OF MAKING THE CHIP CARD - The chip card ( | 08-12-2010 |
20100201394 | TEST CIRCUIT AND TEST METHOD FOR TESTING DIFFERENTIAL INPUT CIRCUIT - A test circuit includes a signal level modifying circuit. The signal level modifying circuit modifies at least one of signal levels of an inverting input signal and a noninverting input signal supplied to a differential input circuit in response to a test signal outputted from a signal output circuit to make a difference between signal levels of the inverting input signal and the noninverting input signal smaller than that in a normal operation. Here, the test signal indicates a test mode in which input/output characteristics of the differential input circuit is tested. | 08-12-2010 |
20100213964 | TIMER UNIT, SYSTEM, COMPUTER PROGRAM PRODUCT AND METHOD FOR TESTING A LOGIC CIRCUIT - A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit. The system has a mode control unit containing a set of instructions which is executable by the logic circuit, for switching the logic circuit from and to a test mode in which a part of the logic circuit can be subjected to a selected test by executing a selected test routine. | 08-26-2010 |
20100219855 | Semiconductor device having CMOS transfer circuit and clamp element - A semiconductor device includes an internal power-supply circuit which produces an internal potential, an external terminal which outputs the internal potential and inputs and outputs a signal with an outside, and a test mode signal terminal which transfers a test mode signal. The semiconductor device further includes a first CMOS transfer circuit and a second CMOS transfer circuit which are provided between the internal power-supply circuit and the external terminal, and which are controlled by the test mode signal, a clamp element which is connected between the first and second CMOS transfer circuits and suppresses a potential variation, and a delay element provided between the clamp element and the first CMOS transfer circuit. | 09-02-2010 |
20100237890 | SYSTEM THAT MEASURES CHARACTERISTICS OF OUTPUT SIGNAL - A system including a first circuit and a second circuit. The first circuit includes analog components configured to receive an input signal and provide an output signal based on the input signal. The second circuit is configured to measure characteristics of the output signal to test the first circuit. At least one of the output signal and another output signal is fed back to provide the input signal and generate an oscillation in the output signal. | 09-23-2010 |
20100237891 | Method, apparatus and system of parallel IC test - A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones. | 09-23-2010 |
20100237892 | FLEXIBLE SUBSTRATE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE - A flexible substrate includes a substrate body; a plurality of lines that are arranged on the substrate body; a plurality of connection terminals that are arranged on an end portion of the substrate body and electrically connected to the respective lines; an integrated circuit that is arranged on the substrate body and electrically connected to at least one of the lines; and an inspection electrode that is arranged on the substrate body and electrically connected to the integrated circuit and capable of outputting a signal processed in the integrated circuit. | 09-23-2010 |
20100244878 | PLL BURN-IN CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a PLL which does not include a loop filter, an additional circuit for subjecting a voltage-controlled oscillator to a burn-in test with an appropriate oscillation frequency is realized by a less circuit configuration. | 09-30-2010 |
20100244879 | APPARATUS FOR MASS DIE TESTING - A test system for testing a large number of dice on a semiconductor wafer without repositioning test probes is disclosed. The test system includes a set of dice under test (DUT) connected together by a plurality of signal buses formed on a semiconductor wafer, at least one test die designed for carrying out tests of the dice under test, the test die having a set of pads to be connected to one or more probes of an external test apparatus, and a probe card with at least one multiplexer implemented in the probe card, such that the test die is capable of receiving signals from the external test apparatus to select any die under test within the set via the multiplexer and the signal buses without repositioning the probes. | 09-30-2010 |
20100253380 | DIELECTRIC FILM AND LAYER TESTING - A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line. | 10-07-2010 |
20100264950 | Electronic device including electronic part and wiring substrate - An electronic device includes an electronic part and a wiring substrate. The electronic part includes a rewiring substrate, a semiconductor chip, and solder bumps arranged in a matrix form. The wiring substrate includes a wire and lands arranged in a matrix form corresponding to the solder bumps. Each of the lands is coupled with corresponding one of the solder bumps so as to form connection portions. The connection portions include nonfunctional connection portions that do not provide an electric connection between the semiconductor chip and the wire. The lands forming the nonfunctional connection portions include a power source land and a ground land arranged next to each other in a row direction or a column direction. The lands that are arranged next to the lands forming the nonfunctional connection portions in the row direction or the column direction are set to signal lands. | 10-21-2010 |
20100271064 | Integrated Circuit Self-Monitored Burn-In - An IC adapted for self-monitored burn-in includes a first memory and at least one BIST circuit coupled to the memory and operative to test the IC by executing a burn-in test and to generate test results indicative of at least one parameter of the burn-in test. The test results are at least temporarily stored in the first memory as a function of a first control signal. | 10-28-2010 |
20100301893 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT OPERATION METHOD - In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage V | 12-02-2010 |