Entries |
Document | Title | Date |
20080203589 | VARIABLE FILL AND CHEESE FOR MITIGATION OF BEOL TOPOGRAPHY - A method of designing features on a semiconductor wafer. A design of active or functional features is provided for chiplets separated by kerf areas on the wafer. The method then includes determining pattern density of the chiplet features, and applying a pattern of spaced dummy features on chiplet area not covered by active or functional features, as well as in the kerf areas. The dummy features are uniformly expanded or reduced in size until a desired dummy feature pattern density is reached. | 08-28-2008 |
20080203590 | INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE WITH OVERLAY KEY AND ALIGNMENT KEY AND METHOD OF FABRICATING THE SAME - An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench. | 08-28-2008 |
20080217794 | Overlay Measurement Target - In an overlay metrology method used during semiconductor device fabrication, an overlay alignment mark facilitates alignment and/or measurement of alignment error of two layers on a semiconductor wafer structure, or different exposures on the same layer. A target is small enough to be positioned within the active area of a semiconductor device combined with appropriate measurement methods, which result in improved measurement accuracy. | 09-11-2008 |
20080230929 | OVERLAY MARK OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE OVERLAY MARK - Provided are an overlay mark of a semiconductor device and a semiconductor device including the overlay mark. The overlay mark includes: reference marks formed in rectangular shapes comprising sides in which fine patterns are formed; and comparison marks formed as rectangular shapes which are smaller than the rectangular shapes of the reference marks and formed of fine patterns, wherein the number of comparison marks is equal to the number of reference marks, wherein the reference marks and the comparison marks are formed on different thin films formed on a semiconductor substrate to be used to inspect alignment states of the different thin films, and the overlay mark reflects an effect of aberration of patterns of memory cells through the fine patterns during a calculation of MR (mis-registration). | 09-25-2008 |
20080251950 | SEMICONDUCTOR DEVICE AND PROCESSING METHOD OF THE SAME - A disclosed semiconductor device includes a semiconductor substrate including semiconductor integrated circuit forming areas; semiconductor integrated circuits formed on the semiconductor integrated circuit forming areas; and an alignment pattern formed on a periphery of at least one of the semiconductor integrated circuit forming areas. | 10-16-2008 |
20080251951 | USE OF A DUAL TONE RESIST TO FORM PHOTOMASKS AND INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES - An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed. | 10-16-2008 |
20080265445 | Marks for the Alignment of Wafer-Level Underfilled Silicon Chips and Method to Produce Same - A semiconductor wafer and the process for aligning wafer level underfill material coated chips with a substrate via alignment marks made visible through laser dicing. | 10-30-2008 |
20080272504 | Package-in-Package Using Through-Hole via Die on Saw Streets - A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die. | 11-06-2008 |
20080277806 | SEMICONDUCTOR WAFER WITH ASSISTING DICING STRUCTURE AND DICING METHOD THEREOF - A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed. | 11-13-2008 |
20080284048 | Alignment mark, semiconductor chip including the same, semiconductor package including the chip and methods of fabricating the same - Provided are an alignment mark with a higher rate of recognition, a semiconductor chip including the alignment mark, a semiconductor package including the semiconductor chip, and methods of fabricating the alignment mark, the semiconductor chip, and the semiconductor package. The alignment mark may include an align metal pad on a substrate and may be electrically isolated. A protective film may be on the align metal pad and may include an aperture exposing a part of the align metal pad. A metal alignment bump may be on the align metal pad exposed in the aperture such that the metal alignment bump protrudes above the protective film. | 11-20-2008 |
20080290530 | SEMICONDUCTOR DEVICE HAVING PHOTO ALIGNING KEY AND METHOD FOR MANUFACTURING THE SAME - Embodiments consistent with the present invention provide a semiconductor device having a photo aligning key and a method for manufacturing the same. The semiconductor device includes a pattern photo aligning key formed on a scribe line of a semiconductor substrate, and a plurality of dummy pattern keys formed around the pattern photo aligning key, the dummy pattern keys having a width smaller than that of the pattern photo aligning key. | 11-27-2008 |
20090001615 | SEMICONDUCTOR TEST STRUCTURES - Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds. | 01-01-2009 |
20090001616 | METHOD AND APPARATUS FOR WAFER MARKING - A semiconductor substrate is provided. The substrate includes a first surface and an opposing second surface, wherein the first surface includes a marking in a centroid region of the first surface. The marking indicates a location of a center point on the first surface of the semiconductor substrate or identification data unique to the substrate. A system, methods of transporting and marking, and a device for reading the substrate markings are also provided. | 01-01-2009 |
20090001617 | Alignment key, method for fabricating the alignment key, and method for fabricating thin film transistor substrate using the alignment key - Provided are an alignment key, a method for fabricating the alignment key, and a method for fabricating a thin film transistor substrate using the alignment key. The method for fabricating the alignment key includes forming a first metal layer on a base substrate, forming a first alignment key and a first mark portion of a second alignment key by selectively patterning the first metal layer, forming a dielectric on the first metal layer, forming a second metal layer on the dielectric, and forming a second mark portion of the second alignment key on the dielectric by selectively patterning the second metal layer. | 01-01-2009 |
20090032978 | MICROELECTRONIC STRUCTURE INCLUDING DUAL DAMASCENE STRUCTURE AND HIGH CONTRAST ALIGNMENT MARK - A microelectronic structure, and in particular a semiconductor structure, includes a substrate and a dielectric layer located over the substrate. In addition at least one alignment mark is located interposed between the dielectric layer and the substrate. The at least one alignment mark comprises, or preferably consists essentially of, at least one substantially present element having an atomic number at least 5 greater than a highest atomic number substantially present element within materials surrounding the alignment mark Also included within the microelectronic structure is a dual damascene aperture located within the dielectric layer. The dual damascene aperture may be fabricated using, among other methods, a hybrid lithography method that uses direct write lithography and optical lithography, in conjunction with the at least one alignment mark and an electron beam as an alignment beam. | 02-05-2009 |
20090032979 | SEMICONDUCTOR DEVICE HAVING ALIGNMENT MARK AND ITS MANUFACTURING METHOD - Many holes are formed in an interlayer insulating film and the surface of the interlayer insulating film is covered with a metal film, with its surface undulated by openings or recesses formed to scatter reflection light. The size of the recesses is about the size of contact holes of elements. Hence the recesses are not detectable by an image recognition apparatus. The size of the metal film, however, is set so that it can be detected by the image recognition apparatus. | 02-05-2009 |
20090045530 | MICROELECTRONIC LITHOGRAPHIC ALIGNMENT USING HIGH CONTRAST ALIGNMENT MARK - A microelectronic structure, and in particular a semiconductor structure, includes a substrate that includes an alignment mark comprising a substantially present element that has an atomic number at least 5 greater than a highest atomic number substantially present element within the substrate. Alignment to the alignment mark may be effected using an electron beam as an alignment beam with respect to both a direct write exposure and a reticle filtered optical exposure of a mask layer (i.e., photoresist mask layer) located over the alignment mark and the substrate. The electron beam alignment beam may effectively penetrate through other layers, including conductor layers comprising elements having appropriately low atomic number, located interposed between the alignment mark and the mask layer. | 02-19-2009 |
20090085233 | ALIGNMENT FEATURES FOR PROXIMITY COMMUNICATION - Embodiments of a semiconductor die that includes proximity connectors proximate to a first surface of the semiconductor die are described. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. Moreover, the semiconductor die includes a positive feature coupled to a second surface of the semiconductor die that facilitates mechanical alignment of the semiconductor die with the other semiconductor die. Note that a first region around the positive feature defines a first plane, and the positive feature protrudes above the first plane. | 04-02-2009 |
20090096116 | ALIGNMENT MARK AND MEHTOD FOR FORMING THE SAME - The invention is directed to an alignment mark in a material layer in an alignment region of a wafer. The alignment mark comprises a plurality of sub-marks. Each of the sub-mark comprises a first element and a plurality of second elements. The second elements are embedded in the first element and a first top surface of the first element is at the same height as a second top surface of each of the second elements. | 04-16-2009 |
20090102069 | INTEGRATED CIRCUIT SYSTEM WITH ASSIST FEATURE - An integrated circuit system comprising: providing a substrate; forming a main feature using a first non-cross-junction assist feature over the substrate; forming the main feature using a second non-cross-junction assist feature, adjacent a location of the first non-cross-junction feature, over the substrate; and forming an integrated circuit having the substrate with the main feature thereover. | 04-23-2009 |
20090102070 | Alignment Marks on the Edge of Wafers and Methods for Same - A semiconductor wafer having alignment marks a sufficient distance from the outer wafer edge that reference dicing channels and a method for same. A process for dicing WLUF coated wafers into singulated chips using said alignment marks on the outer edge of the wafer. | 04-23-2009 |
20090102071 | Semiconductor substrate and method for manufacturing semiconductor device - The present invention includes a first recognition mark which is arranged in a frame part of a perimeter of an implementation region having a plurality of semiconductor chips implemented therein so that the position of the semiconductor substrate can be macroscopically detected by using a recognition camera, and a second recognition mark which is formed into a smaller shape than the first recognition mark so that the position of the dividing line can be microscopically detected by using a recognition camera. The second recognition mark is arranged so that its center line is positioned on a line that extends from a dicing line, and has a pattern shape which is formed so as to be linearly symmetric with respect to the center line. This pattern shape is formed so that the ratio of a length occupying a direction parallel to the dicing line is larger than that occupying a direction perpendicular to the dicing line, and includes a flow region for promoting the flow of an etchant for forming the pattern shape. | 04-23-2009 |
20090127722 | Method for Processing a Spacer Structure, Method of Manufacturing an Integrated Circuit, Semiconductor Device and Intermediate Structure with at Least One Spacer Structure - Method for processing at least one spacer structure in a manufacturing process of a semiconductor device, wherein the at least one spacer structure is subjected to at least one etch process step with an isotropic component and the spacer structure comprises at least one point on the surface with a large solid angle opening towards the environment. Method of manufacturing an integrated circuit, including a regional removal of a spacer structure, wherein the removal is determined by a pattern density in the vicinity of the spacer structure. | 05-21-2009 |
20090127723 | AIM-Compatible Targets for Use with Methods of Inspecting and Optionally Reworking Summed Photolithography Patterns Resulting from Plurally-Overlaid Patterning Steps During Mass Production of Semiconductor Devices - Alignment targets include optically resolvable regions and SEM resolvable regions. SEM measurements taken of the SEM resolvable regions produce correction factors that can be applied to optical measurements taken of the optically resolvable regions where the correction factors improve the accuracy of the optical measurements. When one or more batches of wafers from a continuous production run are to be measured, a small sub-sample is measured with use of an SEM scan of their SEM resolvable regions. Then the correction factors developed from the SEM scans are applied to optical measurements taken of others of the wafers in the same mass production run. | 05-21-2009 |
20090134531 | OVERLAY MARK AND METHOD FOR FORMING THE SAME - The invention is directed to an overlay mark in a first material layer in an overlay alignment region of a wafer and the first material layer is made from a first material. The overlay mark includes a plurality of mark regions and each of the mark regions comprises a plurality mark elements embedded in the first material layer. Each of the mark elements is made of a second material different from the first material of the first material layer and the mark elements evenly distribute in the mark region. | 05-28-2009 |
20090146325 | ALIGNMENT FOR BACKSIDE ILLUMINATION SENSOR - An apparatus and manufacturing method thereof, wherein an integrated circuit is located in a first region of a substrate having first and second opposing major surfaces, and wherein an alignment mark is located in a second region of the substrate and extends through the substrate between the first and second surfaces. The alignment mark may protrude from the first and/or second surfaces, and/or may comprise a plurality of substantially similar alignment marks. The second region may interpose the first region and a perimeter of the substrate. The second region may comprise a scribe region. | 06-11-2009 |
20090146326 | Method and Structures for Indexing Dice - A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the method including providing a visible index on each die indicative of the respective die position, wherein providing the visible index on each die includes: forming in a first material layer of the die a reference structure adapted to defining a mapping of the wafer; and forming in a second material layer of the die a marker associated with the reference structure, a position of the marker with respect to the reference structure being adapted to provide an indication of the die position in the wafer. | 06-11-2009 |
20090166898 | Method of increasing reliability of packaged semiconductor integrated circuit dice - A method increases a reliability of packaged semiconductor integrated circuit dice by identifying one or more dice on a wafer having failed an electrical test. One or more failed dice are added to a character map. A first tier of buffer dice is added to the initial character map adjacent to each die on the character map. Both the failed dice and the first tier of buffer dice are indicated or marked, such as by inking, thereby indicating dice not requiring packaging. A wafer may include multiple die, with die corresponding to the die in the character map being marked. The marked die thus include die that have failed an electrical test plus die that may be likely to fail in the future due to their proximity to the failed die. | 07-02-2009 |
20090166899 | Method of Creating an Alignment Mark on a Substrate and Substrate - In an embodiment, a method of creating an alignment mark on a substrate includes forming a plurality of lines segmented into electrically conducting line segments and space segments, thereby forming spaces between the lines to form a macroscopic structure in a first layer of the substrate, creating a plurality of electrically conducting trenches in a second layer of the substrate, and arranging the plurality of trenches to be in electrical contact with the line segments and overlapping the space segments at least partially. | 07-02-2009 |
20090206495 | Semiconductor Device and Method for Manufacturing Same - A semiconductor device wherein a force of peeling a chip from a substrate does not operate even the semiconductor device is exposed under a high temperature condition after bonding and a bonding state of the substrate and the chip can be maintained, and a method for manufacturing such semiconductor device are provided. Specifically, in the semiconductor manufacture, a recessed alignment mark is formed on a front plane of a high distortion point glass substrate as a target for alignment for bonding, and the recessed alignment mark is permitted to have a shape which extends to an external side of the semiconductor device. Thus, excellent bonding between the high distortion point glass substrate and the semiconductor device can be provided, and at the same time, since the recessed alignment mark is not sealed, the bonding state can be maintained even when the high distortion point glass substrate is exposed under the high temperature condition after bonding the semiconductor device. | 08-20-2009 |
20090212447 | Mark Structure for Coarse Wafer Alignment and Method for Manufacturing Such a Mark Structure - A mark structure includes on a substrate, at least four lines. The lines extend parallel to each other in a first direction and are arranged with a pitch between each pair of lines that is directed in a second direction perpendicular to the first direction. The pitch between each pair of selected lines differs from the pitch between each other pair of selected lines. | 08-27-2009 |
20090230571 | MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE - A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherein the second location is substantially directly above the first location. The device structure also includes an intermediate layer between the first layer and the second layer, the intermediate layer including a blocking structure, wherein the blocking structure is vertically interposed between the first occurrence of the first reference mark and the second occurrence of the first reference mark. Other aspects are also described. | 09-17-2009 |
20090236760 | SUBSTRATE FOR A DISPLAY PANEL, AND A DISPLAY PANEL HAVING THE SAME - A substrate for a display panel includes an alignment accuracy measurement mark which is used for measuring alignment accuracy between patterns on the substrate without decreasing an aperture ratio of a pixel. The substrate for a display panel includes the alignment accuracy measurement mark in an isolated configuration which is used for measuring alignment accuracy between a pattern of a gate signal line and an auxiliary capacitance line and a pattern of a source signal line and a drain line, where the alignment accuracy measurement mark has a shape such that at least one straight line portion is included, is formed in a layer where the pattern of the source signal line and the drain line is formed, and is positioned on the gate signal line. | 09-24-2009 |
20090243122 | ALIGNMENT MARK FOR OPAQUE LAYER - An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process. | 10-01-2009 |
20090243123 | Increasing Exposure Tool Alignment Signal Strength for a Ferroelectric Capacitor Layer - An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials. | 10-01-2009 |
20090267240 | METHOD OF MANUFACTURING AN OVERLAY MARK - A method of manufacturing an overlay mark is provided. Two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, and two second Y-direction isolation structures are formed in a substrate, where the first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, and the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle. The second rectangle is located in the first rectangle. A first dielectric layer and a conductive layer are formed sequentially on the substrate. A planarization process is performed to remove a portion of the conductive layer till the isolation structures are exposed. A second dielectric layer is formed on the substrate. A rectangle pattern is formed on the second dielectric layer. The sides of the rectangle pattern are located above the isolation structures. | 10-29-2009 |
20090267241 | Substrate with Check Mark and Method of Inspecting Position Accuracy of Conductive Glue Dispensed on the Substrate - The invention relates to a substrate with a check mark and a method of inspecting position accuracy of conductive glue dispensed on the substrate. The method is implemented on the substrate having at least one transfer pad and at least one check mark arranged near the border of the transfer pad. After the conductive glue spot is dispensed on the transfer pad, the method includes first capturing an image by a video capturing element, then determining whether the conductive glue spot exist in the image and determining whether the conductive glue spot from the image matches a predetermined standard, if not, generating a report and a warning. | 10-29-2009 |
20090273102 | Semiconductor Substrate and Method for Manufacturing the Same - A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an epitaxial film. | 11-05-2009 |
20090289377 | SEMICONDUCTOR WAFER - The present invention is a semiconductor wafer including an orientation identification mark, which is used for identifying crystal orientation, on a peripheral surface thereof, in which the orientation identification mark has a terraced structure that is concave toward an inner diameter direction of the semiconductor wafer with respect to a portion outside of the orientation identification mark on the peripheral surface, and has a planar surface that is orthogonal to a diameter direction of the semiconductor wafer; and has a gloss different from that of the portion outside of the orientation identification mark on the peripheral surface. | 11-26-2009 |
20090289378 | SEMICONDUCTOR WAFER - The present invention is a semiconductor wafer including an orientation identification mark, which is used for identifying crystal orientation, on a peripheral surface thereof, in which the orientation identification mark is smoothly joined with a portion outside of the orientation identification mark on the peripheral surface, has a planar surface that is orthogonal to an inner diameter direction of the semiconductor wafer, and has a gloss different from that in the portion outside of the orientation identification mark on the peripheral surface. | 11-26-2009 |
20090294995 | OVERLAY MARK - An overlay mark applicable in a non-volatile memory includes two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, two second Y-direction isolation structures, a first dielectric layer, and a conductive layer. The first X-direction isolation structures, the first Y-direction isolation structures, the second X-direction isolation structures, and the second Y-direction isolation structures are disposed in a substrate. The first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle, and the second rectangle is located in the first rectangle. The first dielectric layer is disposed on a surface of the substrate. The conductive layer is disposed on the first dielectric layer. | 12-03-2009 |
20090302486 | SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor substrate whose columnar member for alignment is difficult to fall off and a manufacturing method thereof. An alignment mark | 12-10-2009 |
20090315193 | SEMICONDUCTOR CHIP INCLUDING IDENTIFYING MARKS - A semiconductor chip includes a first mark for identifying a position of the chip within an exposure field. The semiconductor chip includes a first matrix in a first layer of the chip and a second mark within the first matrix identifying a position of the exposure field on a wafer. | 12-24-2009 |
20090315194 | Semiconductor chip having alignment mark and method of manufacturing the same - Disclosed is a semiconductor chip having an alignment mark which is formed on the surface of the semiconductor chip where no external connection bump is formed, and which has the position information of the external connection bump. A method of manufacturing the semiconductor chip having an alignment mark is also provided. Because the semiconductor chip includes the alignment mark having the position information of the external connection bump, the external connection bump is matched with a via which is formed in the external circuit layer of a printed circuit board including the semiconductor chip, thus improving electrical connection with the printed circuit board, and increasing the reliability of the printed circuit board including the semiconductor chip. | 12-24-2009 |
20100001416 | WAFER LASER-MARKING METHOD AND DIE FABRICATED USING THE SAME - A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the tape and marks a pattern on the second surface of the wafer. There are glue residuals remained in the laser-marking pattern of the die manufactured according to the laser-marking method of the invention, and the components of the glue residuals at least include elements of silicon, carbon and oxygen. | 01-07-2010 |
20100044890 | SEMICONDUCTOR SUBSTRATE MANUFACTURE APPARATUS, SEMICONDUCTOR SUBSTRATE MANUFACTURE METHOD, AND SEMICONDUCTOR SUBSTRATE - [Problems] To perform predetermined processing such as annealing and coating application of a semiconductor material with high accuracy on a number of semiconductor formation areas formed over a wide region on a surface of a substrate having elasticity such as a plastic substrate even when the substrate expands and contracts. | 02-25-2010 |
20100052191 | Metrology Mark with Elements Arranged in a Matrix, Method of Manufacturing Same and Alignment Method - A method of manufacturing an integrated circuit provides a metrology mark (e.g., alignment mark or overlay mark). The method includes forming a first plurality of first structures arranged in a matrix in a substrate. Portions of the matrix are covered with a mask such that first portions of the matrix are left exposed and second portions of the matrix are covered. Signal response properties of exposed ones of the first structures in the matrix are altered to form a metrology mark. The metrology mark includes first and second mark portions with different signal response properties and which are aligned to a virtual grid. The evaluation of precisely positioned metrology marks may be improved with low impact on process complexity. | 03-04-2010 |
20100052192 | ELECTRONIC ELEMENT WAFER MODULE AND METHOD FOR MANUFACTURING ELECTRONIC ELEMENT WAFER MODULE, ELECTRONIC ELEMENT MODULE AND METHOD FOR MANUFACTURING ELECTRONIC ELEMENT MODULE, AND ELECTRONIC INFORMATION DEVICE - An electronic element wafer module is provided, in which a transparent support substrate is disposed facing a plurality of electronic elements formed on a wafer and a plurality of wafer-shaped optical elements are disposed on the transparent support substrate, where a groove is formed along a dicing line between the adjacent electronic elements, penetrating from the optical elements through the transparent support substrate, with a depth reaching a surface of the wafer or with a depth short of the surface of the wafer; and a light shielding material is applied on side surfaces and a bottom surface of the groove or is filled in the groove, and the light shielding material is applied or formed on a peripheral portion of a surface of the optical element, except for on a light opening in a center of the surface. | 03-04-2010 |
20100072635 | Protecting Sidewalls of Semiconductor Chips using Insulation Films - A method of forming an integrated circuit structure includes providing a wafer having a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjoining the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, wherein the notch has a bottom no higher than a top surface of a semiconductor substrate in the wafer; forming a first insulation film over the wafer, wherein the first insulation film extends into the notch; removing a portion of the first insulation film from a center of the notch, wherein a remaining portion of the first insulation film comprises an edge in the notch; and sawing the wafer to separate the first semiconductor chip and the second semiconductor chip. | 03-25-2010 |
20100140816 | METHOD OF FORMING A MARKER, SUBSTRATE HAVING A MARKER AND DEVICE MANUFACTURING METHOD - A marker, for example an alignment marker or an overlay marker is formed in two steps. First, a pattern of two chemically distinct feature types having a pitch comparable to product features is formed. This pattern is then masked by resist in the form of the desired marker, which has a larger pitch than the pattern. Finally, one of the two feature types is selectively etched in the open areas. The result is a marker with a large pitch suitable to be read with long wavelength radiation but the edges of the features are defined in an exposure step having a pitch comparable to the product features. | 06-10-2010 |
20100155967 | INTEGRATED CIRCUITS ON A WAFER AND METHOD OF PRODUCING INTEGRATED CIRCUITS - Integrated circuits (Ia, Ib) on a wafer ( | 06-24-2010 |
20100155968 | Overlay Metrology Target - In one embodiment, a metrology target for determining a relative shift between two or more successive layers of a substrate may comprise; an first structure on a first layer of a substrate and an second structure on a successive layer to the first layer of the substrate arranged to determine relative shifts in alignment in both the x and y directions of the substrate by analyzing the first structure and second structure overlay. | 06-24-2010 |
20100193974 | Substrate with Check Mark and Method of Inspecting Position Accuracy of Conductive Glue Dispensed on the Substrate - The invention relates to a substrate with a check mark and a method of inspecting position accuracy of conductive glue dispensed on the substrate. The method is implemented on the substrate having at least one transfer pad and at least one check mark arranged near the border of the transfer pad. After the conductive glue spot is dispensed on the transfer pad, the method includes first capturing an image by a video capturing element, then determining whether the conductive glue spot exist in the image and determining whether the conductive glue spot from the image matches a predetermined standard, if not, generating a report and a warning. | 08-05-2010 |
20100207283 | Wafer level chip scale package and method of laser marking the same - A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer | 08-19-2010 |
20100207284 | METHOD FOR PROVIDING ROTATIONALLY SYMMETRIC ALIGNMENT MARKS FOR AN ALIGNMENT SYSTEM THAT REQUIRES ASYMMETRIC GEOMETRIC LAYOUT - A method and apparatus includes an integrated circuit device, and at least one alignment mark on the integrated circuit device, the alignment mark comprises a first coded region, a second coded region adjacent the first coded region, and a third coded region adjacent the second coded region, the second coded region located between the first coded region and the third coded region, and markings on the first coded region and the third coded region being identical. | 08-19-2010 |
20100225011 | System and Method for Integrated Circuit Fabrication - A system and method for integrated circuit fabrication is provided. A wafer holding system includes a wafer carrier that holds the wafer at a specified alignment, and a top ring disposed on a top surface of the wafer and of the wafer carrier. The top ring holds the wafer and the wafer carrier together as a single unit. The wafer carrier includes an alignment mechanism to hold the wafer in the specified alignment. | 09-09-2010 |
20100237514 | INGOT MARKING FOR SOLAR CELL DETERMINATION - The invention relates to a method for marking wafers, in particular wafers for solar cell production: The method comprises the steps of manufacturing a position line ( | 09-23-2010 |
20100244287 | METHOD OF MEASUREMENT IN SEMICONDUCTOR FABRICATION - Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side and a back side, the device substrate having a first refractive index, forming an embedded target over the front side of the device substrate, forming a reflective layer over the embedded target, forming a media layer over the back side of the device substrate, the media layer having a second refractive index less than the first refractive index, and projecting radiation through the media layer and the device substrate from the back side so that the embedded target is detected for a semiconductor process. | 09-30-2010 |
20100244288 | METHOD AND APPARATUS FOR FABRICATING SEMICONDUCTOR CHIPS USING VARYING AREAS OF PRECISION - A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region. | 09-30-2010 |
20110012271 | INTEGRATED ALIGNMENT AND OVERLAY MARK - An integrated alignment and overlay mark includes a pre-layer pattern for reticle-to-wafer registration implemented in an exposure tool, and a current-layer pattern incorporated with the pre-layer pattern. The pre-layer pattern and the current-layer pattern constitute an overlay mark for determining registration accuracy between two patterned layers on a semiconductor wafer. | 01-20-2011 |
20110018146 | SPACER DOUBLE PATTERNING FOR LITHOGRAPHY OPERATIONS - Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the filled pattern to remove portions of the final material beyond dimensions of the layout elements. | 01-27-2011 |
20110018147 | ALIGNMENT KEY, METHOD FOR FABRICATING THE ALIGNMENT KEY, AND METHOD FOR FABRICATING THIN FILM TRANSISTOR SUBSTRATE USING THE ALIGNMENT KEY - An alignment key, a method for fabricating the alignment key, and a method for fabricating a thin film transistor substrate using the alignment key are provided. The alignment key includes a base substrate, a first alignment key and a first mark portion of a second alignment key, which are formed on the base substrate using a printing roll, a dielectric that is formed on the base substrate to cover the first alignment key, and a second mark portion of the second alignment key, which is formed on the dielectric and at least partly overlaps the first mark portion of the second alignment key. | 01-27-2011 |
20110024924 | METHOD AND STRUCTURE OF STACKING SCATTEROMETRY-BASED OVERLAY OR CD MARKS FOR MARK FOOTPRINT REDUCTION - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch. | 02-03-2011 |
20110057333 | METHOD FOR THE REAL-TIME MONITORING OF INTEGRATED CIRCUIT MANUFACTURE THROUGH LOCALIZED MONITORING STRUCTURES IN OPC MODEL SPACE - The present disclosure relates to a method of controlling the manufacturing of integrated circuits, comprising steps of determining parameters that are characteristic of a curve of radiation intensity applied to a semiconductor wafer through a mask, in critical zones of structures to be formed on the wafer, for each of the critical zones, placing a measuring point in a multidimensional space each dimension of which corresponds to one of the characteristic parameters, placing control points in the multidimensional space that are spread around an area delimited by the measuring points, so as to delimit an envelope surrounding the area, for each control point, defining control structures each corresponding to a control point, generating a mask containing the control structures, applying a process involving the generated mask to a semiconductor wafer, and analyzing the control structures transferred to the wafer to detect any defects therein. | 03-10-2011 |
20110074049 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, MASK AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement. | 03-31-2011 |
20110084412 | INDEXING OF ELECTRONIC DEVICES WITH MULTIPLE WEIGHT MARKERS - A solution for indexing electronic devices includes corresponding electronic device including a die integrating an electronic circuit, the die having at least one index including a reference defining an ordered alignment of a plurality of locations on the die and a marker for defining a value of the index according to an arrangement of the marker with respect to the reference. In one embodiment, the marker includes a plurality of markers each one arranged at a selected one of the locations, the selected location of the marker defining a value of a digit associated with a corresponding power of a base higher than 2 within a number in a positional notation in the base representing the value of the index. | 04-14-2011 |
20110089581 | SEMICONDUCTOR WAFER HAVING SCRIBE LANE ALIGNMENT MARKS FOR REDUCING CRACK PROPAGATION - A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material. | 04-21-2011 |
20110101546 | System and Method for Directional Grinding on Backside of a Semiconductor Wafer - A semiconductor device includes a backing plate, a semiconductor wafer, and integrated devices. The semiconductor wafer includes a plurality of semiconductor die having edges oriented along a reference line, a front surface facing the backing plate, and a backside surface. The backside surface is formed opposite the front surface and includes linear grind marks oriented along the reference line and diagonal with respect to the edges of the plurality of semiconductor die. The linear grind marks are formed by a linear motion of an abrasive surface, such as by a cylinder or wheel having an abrasive surface, and in one embodiment are oriented at 45 degrees with respect to the reference line. The linear grind marks increase a strength of the plurality of semiconductor die to resist cracking. Integrated devices are formed on the front surface of the semiconductor wafer. | 05-05-2011 |
20110133347 | METHOD AND APPARATUS OF PROVIDING OVERLAY - Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions. | 06-09-2011 |
20110156284 | DEVICE AND METHOD FOR ALIGNMENT OF VERTICALLY STACKED WAFERS AND DIE - A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively. | 06-30-2011 |
20110156285 | INTEGRATED ALIGNMENT AND OVERLAY MARK, AND METHOD FOR DETECTING ERRORS OF EXPOSED POSITIONS THEREOF - An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process. | 06-30-2011 |
20110156286 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an alignment mark formed over a semiconductor substrate and an inhibition pattern arranged over the alignment mark with a pattern edge of the inhibition pattern located in a mark functional region of the alignment mark in order to inhibit the alignment mark being recognized as such by an image detector of an exposure device. | 06-30-2011 |
20110169175 | OVERLAY MARK - An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that each set forms one side of a box shape. | 07-14-2011 |
20110285036 | OVERLAY MARK ASSISTANT FEATURE - A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector. | 11-24-2011 |
20110309532 | SEMICONDUCTOR STRUCTURE WITH ALIGNMENT CONTROL MASK - A semiconductor structure includes a semiconductor substrate, formed on which are a first layer and a second layer, and an alignment-control mask. The alignment-control mask includes a first direction reference element, formed in a first region of the first layer and extending in a first alignment direction, and first position reference elements, formed in a first region of the second layer that corresponds to the first region of the first layer accommodating the first direction reference element. The first position reference elements are arranged in succession in the first alignment direction and in respective staggered positions with respect to a second alignment direction perpendicular to the first alignment direction. | 12-22-2011 |
20120032356 | PRODUCTION OF HIGH ALIGNMENT MARKS AND SUCH ALIGNMENT MARKS ON A SEMICONDUCTOR WAFER - The invention relates to production of alignment marks on a semiconductor wafer with the use of a light-opaque layer ( | 02-09-2012 |
20120032357 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor package, a stamp is provided on at least one of at least a pair of opposed sides on an outer peripheral portion in contact with an edge of the package, which is a blank space up to now. With this configuration, the amount of stamp can be increased even in a narrow stamp area. | 02-09-2012 |
20120091598 | HANDLING LAYER FOR TRANSPARENT SUBSTRATE - A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device. | 04-19-2012 |
20120112370 | TEMPLATE, METHOD OF FORMING TEMPLATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a template includes a pattern part which is provided on a substrate and corresponds to a pattern of a semiconductor device, the pattern of the semiconductor device being to be transferred to a wafer, and an alignment mark part which is provided on the substrate, used for positioning of the substrate with respect to the wafer. The alignment mark part has a refractive index that is higher than a refractive index of the substrate. | 05-10-2012 |
20120168970 | SPACER FORMATION FILM, METHOD OF MANUFACTURING SEMICONDUCTOR WAFER BONDING PRODUCT, SEMICONDUCTOR WAFER BONDING PRODUCT AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor wafer bonding product according to the present invention includes: a step of preparing a spacer formation film including a support base having a sheet-like shape and a spacer formation layer provided on the support base and having photosensitivity; a step of attaching the spacer formation layer to a semiconductor wafer having one surface from a side of the one surface; a step of forming a spacer by subjecting exposure and development to the spacer formation layer to be patterned and removing the support base; a step of bonding a transparent substrate to a region of the spacer, with which the removed support base made contact, so as to be included within the region. This makes it possible to manufacture a semiconductor wafer bonding product in which the semiconductor wafer and the transparent substrate are bonded together through the spacer uniformly and reliably. | 07-05-2012 |
20120175789 | ALIGNMENT MARKS TO ENABLE 3D INTEGRATION - Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark. | 07-12-2012 |
20120223445 | SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL HAVING AN INTEGRATED ALIGNMENT MARK - In semiconductor devices, the alignment mark for performing alignment processes of measurement tools and the like may be positioned within the die seal area on the basis of a geometric configuration, which still preserves mechanical integrity of the die seal without compromising the spatial information encoded into the alignment marks. For example, L-shaped alignment marks may be provided at one or more corners of the die seal area. | 09-06-2012 |
20120267802 | POSITION DETERMINATION IN A LITHOGRAPHY SYSTEM USING A SUBSTRATE HAVING A PARTIALLY REFLECTIVE POSITION MARK - The invention relates to a substrate for use in a lithography system, said substrate being provided with an at least partially reflective position mark comprising an array of structures, the array extending along a longitudinal direction of the mark, characterized in that said structures are arranged for varying a reflection coefficient of the mark along the longitudinal direction, wherein said reflection coefficient is determined for a predetermined wavelength. In an embodiment a specular reflection coefficient varies along the substrate, wherein high order diffractions are substantially absorbed by the substrate. A position of a beam on a substrate can thus be determined based on the intensity of its reflection in the substrate. The invention further relates to a positioning device and lithography system for cooperation with the substrate, and a method of manufacture of the substrate. | 10-25-2012 |
20120292789 | SEMICONDUCTOR WAFER AND METHOD OF PRODUCING THE SAME - Provided is a method of producing a semiconductor wafer. The method includes forming an alignment mark on a base wafer, forming, on the base wafer in a region that includes the alignment mark, an inhibition layer for inhibiting crystal growth after forming the alignment mark, forming, in a region of the inhibition layer where no alignment mark is provided, an opening in which the base wafer is exposed, on the basis of information that indicates a location where the opening is to be formed with reference to the position of the alignment mark, and growing a semiconductor crystal inside the opening. | 11-22-2012 |
20120299204 | OVERLAY MARK AND METHOD FOR FABRICATING THE SAME - A method for fabricating an overlay mark, including the steps of: forming a patterned layer on a substrate, wherein the patterned layer comprises at least one mark element forming region, wherein each mark element forming region comprises two column recesses and a plurality of row recesses, and the row recesses connect the two column recesses; growing a mark material from the sidewalls of the column recesses and the row recesses so that the mark material merges in the column recesses and the row recesses; and removing the patterned layer. Consequently, an overlay mark including mark elements with high image contrast is fabricated. | 11-29-2012 |
20120319307 | IDENTIFICATION OF DIES ON A SEMICONDUCTOR WAFER - A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer. | 12-20-2012 |
20130009328 | ALIGNMENT MARK, SEMICONDUCTOR HAVING THE ALIGNMENT MARK, AND FABRICATING METHOD OF THE ALIGNMENT MARK - An alignment mark with a sheet or a layer of copper, which is compatible with a copper process, is provided herein. In one embodiment, a whole sheet of copper (Cu) is used as a background of the alignment mark, by which the color of the background of the alignment mark is stable and reliable. By such arrangement, the contrast between colors of a main pattern and the background of the alignment mark can be significantly improved, without considering a problem the homogeneity of manufacturing process. If the alignment mark is applied for manufacturing of a display, a recognition successful rate of alignment to attach an integrated circuit (IC) to a panel of the display is increased. | 01-10-2013 |
20130032956 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes a first photolithography step of forming a first device pattern corresponding to a first pattern, and a plurality of alignment marks corresponding to a plurality of marks, upon a step of exposing the entire device region in one shot using a first mask including the first pattern and the plurality of marks, and a second photolithography step of, after the first photolithography step, forming second device patterns respectively corresponding to second patterns in a plurality of divided regions which form the device region, upon steps of individually exposing the plurality of divided regions using second masks each including the second pattern corresponding thereto. | 02-07-2013 |
20130037968 | SEMICONDUCTOR APPARATUS AND SUBSTRATE - A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall formed in the same layer as an uppermost layer of the multilayer structure circuit so as to surround the multilayer structure circuit in plan view, and an alignment mark formed in the same layer as the uppermost layer. The alignment mark is formed so as to contact at least part of the protective wall. | 02-14-2013 |
20130056886 | Method and Apparatus of Providing Overlay - Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions. | 03-07-2013 |
20130075938 | PHOTOLITHOGRAPHY ALIGNMENT MARK, MASK AND SEMICONDUCTOR WAFER CONTAINING THE SAME MARK - A photolithography alignment mark and a mask and semiconductor wafer containing said mark are described. The alignment mark comprises: a plurality of first alignment lines arranged parallel with each other in a first direction; a plurality of second alignment lines arranged parallel with each other in a second direction perpendicular to the first direction, and wherein each of the plurality of first alignment lines is composed of a predetermined number of first fine alignment lines uniformly spaced from each other, and each of the plurality of second alignment lines is composed of a predetermined number of second fine alignment lines uniformly spaced from each other. Alignment marks can be located in non-circuit pattern regions of the mask and on a plurality of layers in mark regions on the wafer. | 03-28-2013 |
20130082408 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing semiconductor device includes: performing first, second and third exposures of a photoresist film formed on a semiconductor wafer via a mask; wherein: first, second and third shot regions respectively defined by the first, second and third exposures are aligned in a first direction; the mask has a shot region including a peripheral scribe region having a first and second side crossing the first direction; the photoresist film is of positive type, a first pattern is formed as a light shielding pattern disposed on the first side, and a second pattern is formed as a light transmitting region disposed on the second side; the first and second exposures are performed in such a manner that the first and second patterns do not overlap each other; and the second and third exposures are performed in such a manner that the first and second patterns overlap each other. | 04-04-2013 |
20130087934 | SUBSTRATE FOR DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a substrate for a display device comprises forming a first pattern within an active region of the substrate and at the same time forming a first overlay pattern at corner regions of the active region; and forming a second pattern within the active region of the substrate and at the same time forming a second overlay pattern at corner regions of the active region, wherein the first overlay pattern includes gradations arranged in a predetermined direction, and the second overlay pattern includes gradations arranged in the predetermined direction to face the gradations of the first overlay pattern. | 04-11-2013 |
20130106000 | ALIGNMENT ACCURACY MARK | 05-02-2013 |
20130147066 | STRUCTURE AND METHOD FOR E-BEAM IN-CHIP OVERLAY MARK - The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction. | 06-13-2013 |
20130161841 | ALIGNMENT MARK AND METHOD OF MANUFACTURING THE SAME - An alignment mark includes a plurality of mark units. Each mark unit includes a first element and a plurality of second elements. Each second element includes opposite first and second end portions. The plurality of second elements are arranged along a direction. The first element extends adjacent to the first end portions of the plurality of second elements and parallel to the direction of the plurality of second elements. | 06-27-2013 |
20130168877 | MASK OVERLAY METHOD, MASK, AND SEMICONDUCTOR DEVICE USING THE SAME - A mask overlay method, and a mask and a semiconductor device using the same are disclosed. According to the disclosed mask overlay technique, test marks and front layer overlay marks corresponding to a plurality of overlay mark designs are generated in a first layer of a semiconductor device. The test patterns generating the test marks each include a first sub pattern and a second sub pattern. Note that the first sub pattern has the same design as a front layer overlay pattern (which generates the front layer overlay mark corresponding thereto). Based on the test marks, performances of the plurality of overlay mark designs are graded. The front layer overlay mark corresponding to the overlay mark design having the best performance is regarded as an overlay reference for a mask of a second layer of the semiconductor device. | 07-04-2013 |
20130200535 | OVERLAY MARK FOR MULTIPLE PRE-LAYERS AND CURRENTLY LAYER - An overlay mark is described, including N (N≧2) groups of first x-directional linear patterns each defined from a different one of N pre-layers, N groups of second x-directional linear patterns of a current layer, N groups of first y-directional linear patterns each defined from a different one of the N pre-layers, and N groups of second y-directional linear patterns of the current layer. Each group of second x-directional linear patterns is disposed together with one group of first x-directional linear patterns, wherein the second linear patterns and the x-directional linear patterns are arranged alternately. Each group of second y-directional linear patterns is disposed together with one group of first y-directional linear patterns, wherein the second linear patterns and the first linear patterns are arranged alternately. | 08-08-2013 |
20130285264 | WAFER ASSEMBLY WITH CARRIER WAFER - A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark. | 10-31-2013 |
20130328221 | Alignment mark design for semiconductor device - Better alignment mark designs for semiconductor devices may substantially lessen the frequency of layer misalignment scanner alignment problems. Exemplary alignment mark designs substantially avoid or minimize damage during the fill-in and etching and chemical mechanical processing processes. Thus, additional processing steps to even out various layers or to address the misalignment problems may also be avoided. | 12-12-2013 |
20140015150 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - A semiconductor device manufacturing method includes forming a film on at least a portion of one surface of a semiconductor wafer, forming an alignment mark by providing a recessed portion on the film, and adhering a sheet to the one surface of the semiconductor wafer on which the alignment mark is formed. | 01-16-2014 |
20140027933 | DEVICE AND METHOD FOR ALIGNMENT OF VERTICALLY STACKED WAFERS AND DIE - A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively. | 01-30-2014 |
20140035171 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE HAVING ALIGNMENT MARK - An exemplary display device includes a transparent substrate and a semiconductor device bonded to the transparent substrate. The transparent substrate includes a first alignment mark. The semiconductor device includes a substrate and a second alignment mark positioned on the substrate. The second alignment mark includes a first pattern structure positioned on the substrate and a second pattern structure positioned on the first pattern structure. The first pattern structure includes a plurality of first non-transparent marks. The second pattern structure includes a second pattern surrounded by the first non-transparent marks. The second pattern is an alignable shape that corresponds to a shape of the first alignment mark on the transparent substrate. | 02-06-2014 |
20140103547 | ALIGNMENT KEY OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - An alignment key of a semiconductor device includes: a material layer formed at a scribe region of a semiconductor substrate, a first dummy hole and a second dummy hole passing through the material layers, a first channel insulation layer formed inside the first dummy hole, a second channel insulation layer formed inside the second dummy hole, a first capping layer formed on a side wall of an upper portion of the first dummy hole and an upper portion of the first channel insulation layer, and a second capping layer formed on a side wall of an upper portion of the second dummy hole and an upper portion of the channel insulation layer, having a height of a lower surface portion greater than that of a lower surface portion of the first capping layer. | 04-17-2014 |
20140110867 | Substrate and Method for Cutting the Substrate - The present invention discloses a method for cutting a substrate. The method includes the steps of 1) creating a etching groove in the first surface of the first sheet and the third surface of the second sheet; 2) laminating the first and second sheets with the etching grooves aligned with each other; and 3) using a cutter to cut through the second surface of first sheet and the fourth surface of the second sheet along a preset set cutting line such that a crack extending vertically to the etching grooves so as to sever the first and second sheets. The present invention further discloses a substrate. By way of the foregoing, the taper and gradient along the cutting edge can be reduced. | 04-24-2014 |
20140145354 | Fabrication Method For Semiconductor Device And Semiconductor Device - A fabrication method for semiconductor devices is provided. The method comprises: depositing a dielectric layer that includes a plurality of functional layers, and forming a contact hole, or through hole, and a metal layer. The forming of the contact hole, or through hole, and the metal layer comprises performing photolithography on regions corresponding to a marking label for the photolithography of the dielectric layer and the metal layer. On at least one of the functional layers, the performing photolithography on regions corresponding to a marking label for the photolithography comprises limiting the photolithography to the metal layer thereof. A semiconductor device thus fabricated is also provided. The method and device do not affect the reading of the marking label, and also can avoid the problem of defocusing in the vicinity of the marking label. | 05-29-2014 |
20140167297 | ALIGNMENT MARK DESIGN FOR SEMICONDUCTOR DEVICE - Better alignment mark designs for semiconductor devices may substantially lessen the frequency of layer misalignment scanner alignment problems. Exemplary alignment mark designs substantially avoid or minimize damage during the fill-in and etching and chemical mechanical processing processes. Thus, additional processing steps to even out various layers or to address the misalignment problems may also be avoided. | 06-19-2014 |
20140197553 | METHOD FOR MANUFACTURING A SUBSTRATE FOR A DISPLAY DEVICE - A method for manufacturing a substrate for a display device comprises forming a first pattern within an active region of the substrate and at the same time forming a first overlay pattern at corner regions of the active region; and forming a second pattern within the active region of the substrate and at the same time forming a second overlay pattern at corner regions of the active region, wherein the first overlay pattern includes gradations arranged in a predetermined direction, and the second overlay pattern includes gradations arranged in the predetermined direction to face the gradations of the first overlay pattern. | 07-17-2014 |
20140210113 | ALIGNMENT MARK RECOVERY WITH REDUCED TOPOGRAPHY - When opaque films are deposited on semi-conductor wafers, underlying alignment marks may be concealed. The re-exposure of such alignment marks is one source of resulting surface topography. In accordance with one implementation, alignment marks embedded in a wafer may be exposed by removing material from one or more layers and by replacing such material with a transparent material. In accordance with another implementation, the amount of material removed in an alignment mark recovery process may be mitigated by selectively ashing or etching above a stop layer. | 07-31-2014 |
20140264961 | Invisible Dummy Features and Method for Forming the Same - A method and apparatus for alignment are disclosed. An exemplary apparatus includes an overlay mark formed on a substrate; and a plurality of dummy features formed nearby the overlay mark. The dummy features have dimensions below a minimum resolution of an alignment detection tool. A minimum distance separating the overlay mark from its closest dummy feature is correlated to a semiconductor fabrication technology generation under which the overlay mark is formed. | 09-18-2014 |
20140264962 | Wafer Mapping Process Control with Indicator Line - A method for providing alignment in a die picking process may include aligning a semiconductor wafer based on a reference die, forming an indicator line relative to the reference die by picking a number of dice along a line extending across the wafer, and using the reference line to monitor a position of the picking machine relative to the wafer. A die attach machine may include a control system for automatically implementing such method. | 09-18-2014 |
20140306357 | DICING DIE-BONDING FILM AND METHOD OF FORMING A CUT ON THE DICING DIE-BONDING FILM - A dicing die-bonding film and a method of forming a groove in a dicing die-bonding film, the film including a base film; a pressure-sensitive adhesive layer stacked on the base film; and a bonding layer stacked on the pressure-sensitive adhesive layer, wherein the pressure-sensitive adhesive layer includes a first region overlapping with the bonding layer, and a second region not overlapping with the bonding layer, the second region including a third region adjacent to the first region, and a fourth region adjacent to the third region and having a groove formed therein. | 10-16-2014 |
20140339714 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate and at least one alignment mark disposed on the substrate and having at least one hollow pattern. Therefore, the identification rate of the alignment mark can be high by the hollow pattern. | 11-20-2014 |
20140353852 | METHOD FOR PROCESSING A CARRIER AND A CARRIER - A method for processing a carrier may include forming at least one recess structure at least one of over and in the carrier; and annealing the at least one recess structure such that at least one hollow chamber is formed by material of the at least one recess structure, wherein the at least one hollow chamber may form an optical alignment structure. | 12-04-2014 |
20140367869 | Enhanced FinFET Process Overlay Mark - An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin. | 12-18-2014 |
20150008598 | ALIGNMENT MARK, PHOTOMASK, AND METHOD FOR FORMING ALIGNMENT MARK - According to one embodiment, an alignment mark provided on an underlayer includes a plurality of first guide pattern features, and a first self-assembled film. The first guide pattern features extend in a first direction and are aligned in a second direction crossing the first direction. The first self-assembled film is provided between adjacent ones of the first guide pattern features and includes a plurality of first line pattern features and a second line pattern feature. The first line pattern features extends in the first direction, is aligned in the second direction, and has a pitch in the second direction narrower than a pitch in the second direction of the first guide pattern features. The second line pattern feature is provided between adjacent ones of the first line pattern features and extends in the first direction. | 01-08-2015 |
20150014868 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - Embodiments of the present invention disclose a thin film transistor array substrate, a method of manufacturing the same, and display device. A method of manufacturing a thin film transistor array substrate, comprises: forming a resin layer on a substrate formed with a thin film transistor array, patterning the resin layer by using a mask process to form a spacer and a contact hole filling layer, the contact hole filing layer is used for filling contact holes on the thin film transistor array substrate; forming an alignment film on the substrate patterning with the spacer and the contact hole filing layer. | 01-15-2015 |
20150028499 | Apparatus and Method for Forming Alignment Features for Back Side Processing of a Wafer - A method for forming an alignment feature for back side wafer processing in a wafer fabrication process involves forming a trench into but not entirely through a wafer from a top side of the wafer; forming a contrasting material on surfaces of the trench; and grinding a bottom side of the wafer to expose the trench using the handling wafer to handle the wafer during such grinding, wherein the contrasting material lining the exposed trench provides an alignment reference for precise alignment of the wafer for back side processing the wafer. | 01-29-2015 |
20150028500 | FORMING ALIGNMENT MARK AND RESULTING MARK - Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an alignment mark by combining the first shape and one or more of the second shape, wherein the alignment mark has rotational symmetry. | 01-29-2015 |
20150048525 | METROLOGY MARKS FOR UNIDIRECTIONAL GRATING SUPERPOSITION PATTERNING PROCESSES - Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating an angled template mask that extends across and resides at an angle with respect to such spacer gratings. Angled, cut spacer gratings are etched into a second layer using the angled template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer. | 02-19-2015 |
20150145150 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ALIGNMENT MARK OF SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a stacked layer in a memory cell region and a mark region, forming a first mask layer above the stacked layer, and forming a second mask layer above the first mask layer; forming the second mask layer into first mask pattern features and forming a first alignment mark pattern feature; forming second mask pattern features and then removing the first mask pattern features; opening part of the second mask pattern features and forming a third mask layer having an opening; removing part of the second mask pattern features; removing the third mask layer; forming a fourth mask layer; etching the first mask layer; removing the fourth mask layer and then removing the second mask pattern features; and etching the stacked layer. | 05-28-2015 |
20150145151 | Metrology Method and Apparatus, Lithographic System, Device Manufacturing Method and Substrate - A lithographic process is used to form a plurality of target structures ( | 05-28-2015 |
20150333015 | DESIGNING AND MANUFACTURING METHODS OF TFT LCD ARRAY POSITIONING MARK - The present invention relates to TFT LCD array positioning mark designing and manufacturing methods. The TFT LCD array positioning mark manufacturing method includes: (1) forming a passivation layer of TFT LCD array; (2) providing a mask corresponding to the passivation layer, the mask comprising a passivation layer positioning mark that corresponds to a metal positioning mark of the TFT LCD array; and (3) using the mask to form a corresponding passivation layer positioning mark on the passivation layer. The TFT LCD array positioning mark designing method includes: forming a passivation layer positioning mark on a passivation layer of an TFT LCD array to correspond to a metal positioning mark of the TFT LCD array. The present invention provides TFT LCD array positioning mark designing and manufacturing method, wherein a passivation layer positioning mark that is designed and manufactured with them shows a pattern that is more stable and is not susceptible to deformation so as to eliminate the problem of positioning failure of the metal positioning mark occurring in the cell and module processes. | 11-19-2015 |
20150357287 | METHOD FOR SEMICONDUCTOR WAFER ALIGNMENT - A semiconductor wafer is provided. The semiconductor wafer includes a base layer having an active region and an edge region. A number of semiconductor devices is formed on the active region. The semiconductor wafer also includes a wafer identification. The wafer identification is formed on the edge region and used for identifying the semiconductor wafer. The semiconductor wafer further includes an alignment mark. The alignment mark is formed on the edge region and is used for performing an alignment process of the semiconductor wafer. | 12-10-2015 |
20150380358 | Methods and Apparatus Using Front-to-Back Alignment Mark and Placement for Narrow Wafer Scribe Lines - Methods and apparatus for front-to-back alignment using narrow scribe lines are disclosed. An apparatus is disclosed that includes a semiconductor wafer comprising a plurality of areas for the fabrication of integrated circuit devices on a device side, the integrated circuit devices arranged in rows and columns and spaced from one another by a plurality of scribe lines disposed on the semiconductor wafer in areas between the integrated circuit devices and free from integrated circuit devices; and one or more alignment marks disposed on the semiconductor wafer, the alignment marks positioned in an intersection of two of the scribe lines; wherein the scribe lines have a first minimum dimension and the one or more alignment marks have a second minimum dimension that is greater than the first minimum dimension. Methods and additional apparatus are disclosed. | 12-31-2015 |
20160043037 | MARK, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR WAFER - According to one embodiment, there is provided a mark comprising a first mark pattern, a second mark pattern, and an opening pattern. The first mark pattern is arranged in a lower layer of a semiconductor wafer that includes a substrate, the lower layer, an intermediate layer, and an upper layer. The second mark pattern is arranged in the upper layer. The opening pattern exposes the first mark pattern. | 02-11-2016 |
20160071770 | PLASMA ETCHING AND STEALTH DICING LASER PROCESS - Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed. | 03-10-2016 |
20160079180 | OVERLAY MARK DEPENDENT DUMMY FILL TO MITIGATE GATE HEIGHT VARIATION - A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer. | 03-17-2016 |
20160079182 | METHOD FOR PROCESSING A CARRIER AND A CARRIER - A method for processing a carrier may include forming at least one recess structure at least one of over and in the carrier; and annealing the at least one recess structure such that at least one hollow chamber is formed by material of the at least one recess structure, wherein the at least one hollow chamber may form an optical alignment structure. | 03-17-2016 |
20160099217 | LINE LAYOUT AND METHOD OF SPACER SELF-ALIGNED QUADRUPLE PATTERNING FOR THE SAME - A line layout and a spacer self-aligned quadruple patterning method thereof are provided. The line layout includes a first line, a second line, a third line, and a fourth line. The second line and the third line are disposed between the first line and the fourth line. The first line, the second line, the third line, and the fourth line respectively extend in a first direction. An end segment of the second line and an end segment of the third line respectively include a first protrusion portions that extend in a second direction. The first protrusion portion of the end segment of the second line protrudes toward the first line. The first protrusion portion of the end segment of the third line protrudes toward the fourth line. | 04-07-2016 |
20160126194 | MEASUREMENT MARK STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a measurement mark structure, including a plurality of inner patterns, the inner patterns being arranged along a first direction, and an outer pattern, positioned surrounding the inner patterns, and the outer pattern is rectangular frame shaped. | 05-05-2016 |
20160181205 | DISCRETE COMPONENT BACKWARD TRACEABILITY AND SEMICONDUCTOR DEVICE FORWARD TRACEABILITY | 06-23-2016 |
20190148130 | WAFER STRUCTURE AND TRIMMING METHOD THEREOF | 05-16-2019 |