Entries |
Document | Title | Date |
20080203588 | PACKAGED INTEGRATED CIRCUIT - A packaged integrated circuit has an integrated circuit over a support structure. A plurality of bond wires connected between active terminals of the integrated circuit and the support structure. An encapsulant overlies the support structure, the integrated circuit, and the bond wires. The encapsulant has a first open location in the encapsulant so that a first bond wire is exposed and a second open location in the encapsulant so that a second bond wire is exposed. First and second conductive structures are exposed outside the packaged integrated circuit and are located at the first and second open locations, respectively, and electrically connected to the first and second bond wires, respectively. | 08-28-2008 |
20080224333 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is disclosed that includes a wiring board having a via formed therein; a semiconductor element provided on the wiring board; a resist layer covering a surface of the wiring board, the resist layer having an opening in a part thereof positioned on the via; and a sealing resin covering the surface of the via in the opening and the resist layer, and sealing the semiconductor device. | 09-18-2008 |
20080237895 | Semiconductor device - The invention provides a semiconductor device including a rectangular chip provided on a mounting region of a substrate, a liquid resin layer provided under the rectangular chip and on a side surface of the chip, and a plurality of dams formed on the substrate so as to extend along the side surface of the rectangular chip. The configuration allows the semiconductor device to be provided with the substrate having a reduced size which is achieved by preventing a liquid resin from flowing out. | 10-02-2008 |
20080251949 | Molding apparatus, molded semiconductor package using multi-layered film, fabricating and molding method for fabricating the same - Example embodiments include molding apparatuses, semiconductor packages, a fabricating methods for fabricating the same. The molding apparatus may include a first mold die for adhering a partially completed package, a second mold die including a cavity formed such that the partially completed package is positioned inside the cavity and a molding resin for encapsulating the partially completed package inserted into the cavity, and a multi-layered film supply unit for supplying a multi-layered film to the cavity of the second mold die. The semiconductor package may include a substrate, a semiconductor chip electrically connected to the substrate, a molding resin for encapsulating the semiconductor chip and an electrical portion of the substrate, and a marking film, adhered to an outer surface of the molding resin such that a mark is marked in the marking film. | 10-16-2008 |
20080265443 | Semiconductor device and method of manufacturing the same - A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin. | 10-30-2008 |
20080272503 | Semiconductor Device and Method for Making Same - A transfer mold process for encapsulation of a matrix array package of dice on a substrate is proposed wherein the flow of the mold compound between dice is at least partly obstructed. In other words, the flow velocity of the mold compound between dice is constrained with the goal of approximating it to the flow velocity above the dice. It is to be understood that every limitation of the flow velocity between the dice, even if it does not result in equal or uniform velocity throughout the cross-sectional area, will bring about a positive effect in terms of reducing the clustering of filler particles in certain areas of the mold compound. The semiconductor device thus produced is part of the present disclosure. | 11-06-2008 |
20080284047 | Chip Package with Stiffener Ring - Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices in the first side. A polymeric stiffener ring is formed on the first side. The stiffener ring embeds the first plurality of passive devices without covering a central portion of the first surface of the substrate. A semiconductor chip is mounted on the central portion of the first surface of the substrate. | 11-20-2008 |
20080315440 | Method of Manufacturing a Plurality of Semiconductor Devices and Carrier Substrate - Individual devices ( | 12-25-2008 |
20090001612 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION - An integrated circuit package system comprising: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the integrated circuit die and the bottom connection structure with the bottom connection structure exposed; and placing a top connection structure over the adhesive encapsulation at an opposing side to the bottom connection structure. | 01-01-2009 |
20090001613 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANG DIE - An integrated circuit package system comprising: forming a substrate having a solder mask with a support structure formed from the solder mask; mounting a first integrated circuit device over the support structure; connecting the substrate and the first integrated circuit device; and encapsulating the first integrated circuit device and the support structure. | 01-01-2009 |
20090008804 | Power semiconductor package - A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode. | 01-08-2009 |
20090032976 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Provided are a semiconductor device producing method making production steps therein simple while preventing a matter that wire bonding cannot be attained due to contamination of a bonding pad and preventing the generation of a warp in an adherend such as a substrate, a lead frame, or a semiconductor element, thereby improving the yield; an adhesive sheet used in this method; and a semiconductor device obtained by this method. The invention includes a pre-setting step of pre-setting a semiconductor element | 02-05-2009 |
20090032977 | SEMICONDUCTOR DEVICE - The present invention is disclosed a semiconductor device which enables to easily perform a visual inspection of the bonded state between a lead and a land of wiring board. This semiconductor device comprises a lead in which at least a part of the lower surface thereof is exposed form the lower surface of the encapsulation resin and the end face thereof is exposed from the lateral surface of the encapsulation resin. The lower surface of the lead is provided with a groove which reaches the outer end edge of the lead. | 02-05-2009 |
20090051051 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first insulator film having a first opening, a first wiring layer extending from the first opening onto the first insulator film, a first semiconductor chip mounted on the first insulator film so as to be electrically coupled with the first wiring layer, and a resin portion applied on the first insulation film to cover the first semiconductor chip. | 02-26-2009 |
20090079096 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICE UNITS - An integrated circuit package system comprising forming a first device unit, having a first external interconnect, and a second device unit, having a second external interconnect, in an array configuration; mounting an integrated circuit die over the first device unit; connecting the integrated circuit die and the first external interconnect; and encapsulating the integrated circuit die, the first device unit, and the second device unit with both the first external interconnect and the second external interconnect partially exposed. | 03-26-2009 |
20090079097 | ELECTRONIC COMPONENT WITH WIRE BONDS IN LOW MODULUS FILL ENCAPSULANT - An electronic component that has a support structure with a plurality of electrical conductors, a series of wire bonds, each of the wire bonds extending from one of the electrical conductors respectively, each of the wire bonds having an end section contacting the electrical conductor and an intermediate section contiguous with the end section, a bead of dam encapsulant encapsulating the electrical conductors and the end section of each of the wire bonds, and a bead of fill encapsulant contacting the bead of dam encapsulant and encapsulating the intermediate portion of each of the wire bonds. The dam encapsulant has a higher modulus of elasticity than the fill encapsulant. | 03-26-2009 |
20090085231 | METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY PARTICLE BLASTING - A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, a panel of semiconductor packages may undergo a first cutting process which cuts the curvilinear edges of the packages. Next, the partially singulated panel of packages may undergo an abrasion process for smoothing the cut curvilinear edges. The abrasion process may occur by forcing abrasive particles over the jagged side edges of a semiconductor package as a result of a pressure differential above and below the semiconductor packages. Upon completion of the abrasive process, a second cutting process may be performed which cuts along straight edges and singulates the respective packages from the panel. | 04-02-2009 |
20090102068 | SYSTEM AND METHOD TO MANUFACTURE AN IMPLANTABLE ELECTRODE - The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason. | 04-23-2009 |
20090115075 | METHOD FOR MANUFACTURING THIN SUBSTRATE USING A LAMINATE BODY - Provided is a laminated body comprising a substrate to be ground and a support, where the substrate may be ground to a very small (thin) thickness and can then be separated from the support without damaging the substrate. One embodiment is a laminated body comprising a substrate to be ground, a curable silicone adhesive layer in contact with the substrate to be ground, a photothermal conversion layer comprising a light absorbing agent and a heat decomposable resin, and a light transmitting support. After grinding the substrate surface which is opposite that in contact with the adhesive layer, the laminated body is irradiated through the light transmitting layer and the photothermal conversion layer decomposes to separate the substrate and the light transmitting support. | 05-07-2009 |
20090121363 | Process for Producing Circuit Substrate and Circuit Substrate Obtained in Accordance With the Process - A process for producing a circuit substrate having a resin sheet having embedded circuit chips which is obtained by embedding circuit chips into a resin sheet, which comprises steps of (a) arranging and fixing circuit chips on a substrate for processing, (b) coating the substrate for processing on which the circuit chips have been arranged and fixed with a liquid material for forming a resin sheet of an energy curing type to form an uncured coating layer, (c) curing the uncured coating layer by impressing energy to form a layer of a resin sheet having embedded circuit chips, and (d) removing the substrate for processing from the layer of a resin sheet having embedded circuit chips, and a circuit substrate obtained in accordance with the process. A circuit substrate having a resin sheet having embedded circuit chips for controlling pixels of displays and the like can be produced efficiently with excellent quality and excellent productivity. | 05-14-2009 |
20090166896 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Objects are to reduce damage to a semiconductor integrated circuit by external stress and to increase the manufacturing yield of a thinned semiconductor integrated circuit. A single crystal semiconductor layer separated from a single crystal semiconductor substrate is used for a semiconductor element included in the semiconductor integrated circuit. Moreover, a substrate which is formed into a thin shape and provided with the semiconductor integrated circuit is covered with a resin layer. In a separation step, a groove for separating a semiconductor element layer is formed in the supporting substrate, and a resin layer is provided over the supporting substrate in which the groove is formed. After that, the resin layer and the supporting substrate are cut in the groove so as to be divided into a plurality of semiconductor integrated circuits. | 07-02-2009 |
20090189300 | Sealing Film and a Semiconductor Device Using the Same - The present invention provides a sealing film excellent in filling properties and adhesiveness as a sealing film which comprises a resin layer containing the following (A), (B) and (C) and having a flow within the range of 150 to 1800 μm at 80° C.: (A) a resin component containing (a1) a high-molecular-weight component comprising crosslinking functional groups and having a weight-average molecular weight of 100,000 or more and a Tg within the range of −50 to 50° C. and (a2) a thermoplastic component comprising an epoxy resin as main component, (B) a filler having an average particle size within the range of 1 to 30 μm, and (C) a colorant, as well as a method for manufacturing the same and a semiconductor device using the same. The present invention also provides a sealing film excellent in adhesiveness and shape retention as a sealing film which comprises a resin layer containing the above (A), (B) and (C) and having a resin layer having a viscosity within the range of 10000 to 100000 Pa·s in a B-stage state at 50 to 100° C. in thermosetting viscoelasticity measurement, as well as a semiconductor device using the same. | 07-30-2009 |
20090194890 | Integrated Circuit and Memory Module - Embodiments of the invention relate generally to an integrated circuit and a memory module. In an embodiment of the invention, an integrated circuit is provided. The integrated circuit may include a semiconductor carrier including at least one electrically inactive region on an upper surface thereof, a passivation layer structure disposed above the upper surface of the semiconductor carrier, and at least one lithographic trench in the passivation layer structure above the at least one electrically inactive region on the upper surface of the semiconductor carrier. | 08-06-2009 |
20090212446 | Semiconductor Device - A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non warpage compensation portion adjacent the die and a warpage compensation portion in a relatively thermally inactive zone with an approximate discontinuity and/or abrupt change in gradient between the non warpage compensation portion and the warpage compensation portion. | 08-27-2009 |
20090230568 | Adhesive Film for Semiconductor and Semiconductor Device Therewith - There is provided an adhesive film for a semiconductor, comprising a thermoplastic resin (A), an epoxy resin (B) and a curing agent (C), wherein a minimum melt viscosity of said adhesive film for a semiconductor is 0.1 Pa·s to 500 Pa·s both inclusive in a temperature range of 50° C. to 180° C. both inclusive at a temperature-rise rate of 10° C./min from room temperature and a content of volatile component is 5.0% or less. | 09-17-2009 |
20090230569 | DEVICE COMPRISING A SEMICONDUCTOR CMPONENT, AND A MANUFACTURING METHOD - A device having at least one semiconductor component, which is covered by a protective material on its outer surface. The invention provides for the outer surface to be provided with a surface structure so as to enlarge the heat transfer area to the protective material. The invention furthermore relates to a manufacturing method. | 09-17-2009 |
20090250825 | PROCESS FOR PRODUCING ACID ANHYDRIDE-BASED EPOXY RESIN CURING AGENT, ACID ANHYDRIDE-BASED EPOXY RESIN COMPOSITION, AND CURED PRODUCT AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to a process for producing an acid anhydride-based epoxy resin curing agent, an acid anhydride-based epoxy resin curing agent, an epoxy resin composition, and a cured product and optical semiconductor device using the same. The process for producing an acid anhydride-based epoxy resin curing agent according to the present invention comprises heating a mixture containing a polyvalent carboxylic acid anhydride and a polyester resin in the presence of hydrogen gas and a hydrogenation catalyst. | 10-08-2009 |
20090267239 | POSITIVE PHOTOSENSITIVE RESIN COMPOSITION - A photosensitive resin composition comprising parts by mass of polycondensate (A) having a structure resulting from dehydration condensation between one or two or more tetracarboxylic acid dianhydride and one or two or more armatic diamines having mutually ortho-positioned amino and phenolic hydroxyl groups and 1 to 100 parts by mass of photosensitive diazonaphthoquinone compound (B), wherein the polycondensate (A) has a weight average molecular weight of 3000 to 70,000. | 10-29-2009 |
20090278265 | ELECTRONIC COMPONENT AND RESIN PACKAGING METHOD FOR ELECTRONIC COMPONENT - An electronic component, in which the outer perimeter portion of a component ( | 11-12-2009 |
20090315192 | Method of manufacturing semiconductor device and semiconductor device - A method of manufacturing a semiconductor device includes at least bonding wires between electrode pads on a main surface of a semiconductor chip and connection pads on a wiring board. The wires form loop shapes from the electrode pads of the semiconductor chip. The method of manufacturing a semiconductor device also includes at least forming flat parts on the loop-shaped wires, and using a sealing material to seal the semiconductor chip such as to bury the flat parts. | 12-24-2009 |
20090321963 | INJECTION MOLDED METAL STIFFENER FOR PACKAGING APPLICATIONS - In some embodiments, an injection molded metal stiffener for packaging applications is presented. In this regard, an apparatus is introduced comprising a microelectronic device package substrate, a microelectronic device coupled with a top surface of the package substrate, and an injection-molded, metal stiffener coupled with the package substrate, wherein the stiffener includes a central opening and at least partially surrounds the microelectronic device. Other embodiments are also disclosed and claimed. | 12-31-2009 |
20090321964 | Stress Buffer Layer for Ferroelectric Random Access Memory - An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer. | 12-31-2009 |
20090321965 | ELECTRONIC DEVICE HAVING A WIRING SUBSTRATE - A semiconductor chip of the present invention has a wiring substrate and a chip part. The wiring substrate has an insulating resin layer having a first major surface and a second major surface, and a first wiring layer disposed on the insulating resin layer on the second major surface side. The chip part has a projection electrode on the bottom surface. The insulating resin layer holds the chip part such that the bottom and side surfaces of the chip part are in contact with the insulating resin layer, and the top surface of the chip part is exposed on the insulating layer on the first major surface side. The projection electrode of the chip part is connected with the first wiring layer. | 12-31-2009 |
20100038804 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD GATE - An integrated circuit package system includes: providing a substrate; forming a conductive layer over the substrate; forming a mold gate layer having an organic material without polymerization over the conductive layer; and attaching an integrated circuit over the substrate adjacent the mold gate layer. | 02-18-2010 |
20100044887 | METHOD FOR PRODUCING CIRCUIT SUBSTRATE, AND CIRCUIT SUBSTRATE - The method for producing a circuit substrate of the present invention is characterized in that the circuit substrate is produced using as sheet a circuit substrate sheet including an uncured layer a part of which, the part being other than a part at which a circuit chip is disposed, is selectively curable before or after disposal of said circuit chip, wherein the uncured layer has a softness that enables embedding of the circuit chip in the circuit substrate sheet upon pressing the circuit chip that has been disposed on a surface of the uncured layer. According to the method for producing the circuit substrate of the present invention, the circuit chip can be embedded inwards with high accuracy, and the circuit substrate can be produced easily with high accuracy. | 02-25-2010 |
20100052190 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a base plate; a semiconductor element provided on the base plate; a holder provided on an opposite side of the semiconductor element from the base plate and holding terminals electrically connected to the semiconductor element; a casing surrounding the semiconductor element and opposed to a side surface of the holder; and a sealing resin filled among the base plate, the casing, and the holder. The side surface of the holder is provided with a first protrusion protruding toward the casing. The first protrusion is nearer to the base plate than a major surface of the holder on an opposite side from the base plate. A surface of the first protrusion on an opposite side from the base plate is at least partly buried in the sealing resin. | 03-04-2010 |
20100059899 | IC CARD AND MANUFACTURING METHOD THEREOF - This IC card is provided with a module having an inlet, an adhesive layer covering the module, and a first base material and second base material sandwiching the module with interposition of the adhesive layer. The module is disposed on one face of the first base material with interposition of a viscous layer which has a thickness that varies according to the thickness at each area of the module, and its two ends are narrower than its other parts when viewed from the outer face side of the first base material or the outer face side of the second base material. According to this IC card, it is possible to offer the IC card with a flat surface, and without occurrence of strain in the embedded IC chip. | 03-11-2010 |
20100072634 | PLANAR ENCAPSULATION AND MOLD CAVITY PACKAGE IN PACKAGE SYSTEM - An integrated circuit package system includes: providing a substrate; mounting a first package above the substrate, the first package having a mold cavity exposing an exposed portion on a first integrated circuit from a first package encapsulation; mounting a second package above the first package and attached to the exposed portion of the first integrated circuit; mounting a structure above the second package and connected to the substrate around the first package; and encapsulating the first package and the second package with an outer encapsulation having a completely planar top or a planar top co-planar to a top surface of the structure. | 03-25-2010 |
20100078831 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SINGULATION PROCESS - An integrated circuit package system includes: providing a die attach pad; forming a package contact pad adjacent the die attach pad; attaching an integrated circuit over the die attach pad; attaching a die connector to the integrated circuit and the package contact pad; and forming an encapsulant over the die connector and the integrated circuit, the encapsulant having an encapsulant edge from a sawless singulation process. | 04-01-2010 |
20100078832 | SENSOR NODE MODULE - A method of manufacturing a sensor node module includes forming a protruding structure on a carrier. A sensor die is applied onto the protruding structure with an active sensing surface of the sensor die facing the carrier. The sensor die is encapsulated with mold material, wherein the protruding structure prevents the mold material from covering the active sensing surface. The carrier and the protruding structure are removed from the sensor die. | 04-01-2010 |
20100078833 | CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a thin circuit device with show-through of thin metal wires prevented and a method of manufacturing the circuit device. A circuit device mainly includes: a substrate including a first substrate and second substrates; pads formed respectively on upper surfaces of the second substrates; a semiconductor element fixed on an upper surface of the first substrate; thin metal wires each connecting the semiconductor elements and a corresponding one of the pads; and a sealing resin with which the semiconductor element and the thin metal wires are covered, and which thereby seals the circuit device with the semiconductor element and the thin metal wires disposed therein. Furthermore, filler particles located in the uppermost portion of the sealing resin are covered with a resin material constituting the sealing resin. | 04-01-2010 |
20100102461 | Semiconductor device and method of manufacturing the same - A semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and an encapsulation resin encapsulating the semiconductor chip, wherein the encapsulation resin contains a first resin region composed of a first resin composition, a second resin region composed of a second resin composition, and a mixed layer formed between the first resin region and the second resin region so as to have the first resin composition and the second resin composition mixed therein is provided. | 04-29-2010 |
20100109169 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING THE SAME - A stiffener is provided for use in making semiconductor devices. The stiffener and method of use provided prevent or reduce warpage of a semiconductor package during the assembly process. More particularly, the stiffener functions to prevent or reduce warpage during molding of an assembly of wafers and/or dies. The stiffener may be positioned above the backside or non-active side of an assembly of wafer and/or dies during molding. The presence of the stiffener prevents or reduces warpage caused by CTE mismatch between the mold material and the wafer and/or under the high temperatures encountered in the process of molding. After molding, the stiffener may continue to provide support to the assembly. | 05-06-2010 |
20100140815 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR 3-D DEVICES USING ENCAPSULANT FOR STRUCTURAL SUPPORT - A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV. | 06-10-2010 |
20100148377 | INTERMEDIATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An intermediate structure for semiconductor devices includes a wiring board, a plurality of semiconductor chips mounted on the wiring board, and a sealing body for collectively sealing the plurality of semiconductor chips and having a region with a different thickness. | 06-17-2010 |
20100164125 | METHOD OF EVALUATING THE FLAME RETARDANCY OF SEALING RESIN AND TEST SAMPLE FOR EVALUATION OF FLAME RETARDANCY - A method of evaluating the flame retardancy of a sealing resin comprises a step of fusion cutting a heating element by causing the heating element to generate heat by the passage of electric current to a test sample of a molded body of the sealing resin including the heating element therein; a step of igniting the sealing resin by continuing the passage of electric current even after the heating element is fusion-cut; and a step of measuring voltage and/or current applied in a period from when the heating element is fusion-cut to the ignition of the sealing resin. The test sample is used in the method of evaluating the flame retardancy and provided with a heating wire; conducting terminals made of metal having an electric resistance lower than the heating wire and connected to both ends of the heating wire; and a sealing resin layer covering the outer periphery of the heating wire. The evaluation can be performed on the flame retardancy of the sealing resin used for the electronic equipment based on its actual use. | 07-01-2010 |
20100171228 | INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface. | 07-08-2010 |
20100181688 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip, and an encapsulation resin which covers and encapsulates the semiconductor chip, the semiconductor chip having a recess formed in the surficial portion thereof; the recess having, on the deeper side than a predetermined portion thereof, a portion having a larger width than the predetermined portion has; and the encapsulation resin being anchored in the recess. | 07-22-2010 |
20100187700 | Method and apparatus for manufacturing an electronic module, and electronic module - A substrate which has at least one component, such as a semiconductor chip, arranged on it is manufactured from a film made of plastic material laminated onto a surface of the substrate and of the at least one component, where the surface has at least one contact area. First, the film to be laminated onto the surface of the substrate and the at least one component, or a film composite including the film, is arranged in a chamber such that the chamber is split by the film or film composite into a first chamber section and a second chamber section, which is isolated from the first chamber section so as to be gastight. A higher atmospheric pressure is provided or produced in the first chamber section than in the second chamber section; and contact is made between the surface of the substrate arranged in the second chamber section and the at least one component and the film or the film composite, which contact brings about the lamination of the film onto the surface. | 07-29-2010 |
20100213621 | Moisture-proof device, moisture-proof IC, and method for increasing moisture-proof capability of IC - Method for increasing the moisture-proof capability of a chip includes coating moisture-proof glue at the chink of the chip. More particularly, when the packaging structure carries a chink exposed to outside of the chip, the chink is coated with the moisture-proof glue for preventing moisture from entering the internal part of the chip so as to increase the moisture-proof capability of the chip. | 08-26-2010 |
20100244283 | METHOD OF JOINING ELECTRONIC COMPONENT AND THE ELECTRONIC COMPONENT - Dummy electrodes ( | 09-30-2010 |
20100244284 | METHOD FOR ULTRA THIN WAFER HANDLING AND PROCESSING - A method for thin wafer handling and processing is provided. In one embodiment, the method comprises providing a wafer having a plurality of semiconductor chips, the wafer having a first side and a second side. A plurality of dies are attached to the first side of the wafer, at least one of the dies are bonded to at least one of the plurality of semiconductor chips. A wafer carrier is provided, wherein the wafer carrier is attached to the second side of the wafer. The first side of the wafer and the plurality of dies are encapsulated with a planar support layer. A first adhesion tape is attached to the planar support layer. The wafer carrier is then removed from the wafer and the wafer is diced into individual semiconductor packages. | 09-30-2010 |
20100258957 | SEMICONDUCTOR PACKAGE STRUCTURE AND ENCAPSULATING MODULE FOR MOLDING THE SAME - A semiconductor package structure and encapsulating module for molding the same and an encapsulating mold for molding the same are provided. The encapsulating mold is used for packaging a substrate having a chip so as to mold the substrate having the chip as a package structure. The encapsulating mold has a pressing surface, a smooth surface and a cavity. The smooth surface having a curvature radius is connected with the pressing surface and disposed at a mouth of the cavity. When the encapsulating mold and an encapsulating lower mold are jointed to hold the substrate, the pressing surface contacts and presses the substrate. | 10-14-2010 |
20100320624 | DIE PACKAGE INCLUDING ENCAPSULATED DIE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized. | 12-23-2010 |
20110006444 | MICROMECHANICAL COMPONENT AND METHOD FOR PRODUCING A MICROMECHANCAL COMPONENT HAVING A THIN-LAWYER CAP - A micromechanical component having a substrate, a micromechanical functional layer situated above the substrate, and an encapsulation layer situated above the functional layer, and a method for producing the micromechanical component are provided, the encapsulation layer having at least one trench, and a bridging of the trench by at least one electrically insulating connection link is provided. | 01-13-2011 |
20110024922 | SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD - The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion. | 02-03-2011 |
20110024923 | Wafer level hermetic bond using metal alloy with keeper layer - Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate. At least one of the substrates may include a raised feature formed under at least one of the metal layers. One of the metal layer may have a diffusion barrier layer and a “keeper” layer formed thereover, wherein the keeper layers keeps the metal confined to a particular area. By using such a “keeper” layer, the substrate components may be heated to clean their surfaces, without activating or spending the bonding mechanism. | 02-03-2011 |
20110049730 | Device Comprising an Encapsulation Unit - A device in accordance with one embodiment comprises a component ( | 03-03-2011 |
20110062602 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FAN-IN PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; connecting a base component directly to the base substrate; mounting a stack component over the base component; attaching a flattened exposed interconnect directly on the stack component; and applying an encapsulant over the stack component with a portion of the flattened exposed interconnect exposed. | 03-17-2011 |
20110062603 | Encapsulation architectures for utilizing flexible barrier films - An article and method of using spacer layer regions is provided, containing a gas compound, to reduce gas permeation through barrier films overlying a substrate comprising creating a spacer layer between one or more of the barrier films, wherein the spacer layer comprises at least one inert gaseous compound. In another embodiment, an article and method is provided comprising creating alternating thin films of hybridized sol-gel spin-on glass and PDMS based and olefin based elastomers. | 03-17-2011 |
20110074048 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of the present invention includes: a base material ( | 03-31-2011 |
20110109000 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - Provided are a semiconductor package and a method of forming the same. The semiconductor package includes a stress reliever disposed on a part (more specifically, a weak part) of a semiconductor chip. The stress reliever relieves thermal and/or physical stresses caused by a molding layer. As a result, the semiconductor chip does not suffer from the thermal and/or physical stresses. | 05-12-2011 |
20110115101 | ELECTRONIC CIRCUIT - An electronic circuit includes at least two organic components interconnected by conductor tracks and having a common carrier substrate. The components and the conductor tracks are formed from layer portions. An uppermost layer portion, remote from the carrier substrate, of the electronic circuit is of a patterned configuration comprising an electrically conducting material. The patterned uppermost layer portion on its side remote from the carrier substrate is provided with at least one protective layer arranged in congruent relationship with the uppermost layer portion. The at least two organic components include at least one first component of a first component type and at least one second component of a second component type different therefrom. Components of the same component type are respectively protected by a protective layer of the same composition and/or the same structure corresponding to that component type and differing from one another according to the corresponding component type. | 05-19-2011 |
20110121468 | SEMICONDUCTOR PACKAGE AND METHOD OF MAKING SAME - An improved semiconductor package includes thermal tape placed over a top side of a die that is attached to a substrate with an underfill material. The tape extends to the substrate. The tape deforms with heat and entraps the die and underfill material. Air bubbles are trapped between the tape and the die and underfill material. The tape can be weighted and lined with an adhesive material. The tape aids in preventing the die from cracking due to mishandling. | 05-26-2011 |
20110175242 | METHOD OF FORMING A SEMICONDUCTOR DIE - In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer. | 07-21-2011 |
20110180943 | Thin Film Wafer Level Package - Anchor designs for thin film packages are disclosed that, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing. Depending on the release process, additional manufacturing process steps are performed in order to obtain a desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti—TiN interlayer in the anchor region may be added. The ratio of the total SiGe—SiGe anchor area to the SiO | 07-28-2011 |
20110204528 | POSTIVE-TYPE PHOTOSENSITIVE RESIN COMPOSITION, METHOD FOR PRODUCING RESIST PATTERN, AND ELECTRONIC COMPONENT - A positive tone photosensitive composition comprising: (A) an alkali-soluble resin having a phenolic hydroxyl group; (B) a phenol resin modified by a compound having an unsaturated hydrocarbon group containing 4 to 100 carbon atoms; (C) a compound that generates an acid by the action of light; (D) a thermal cross-linker that crosslinks the ingredient (A) and the ingredient (B) by heating; and (E) a solvent. | 08-25-2011 |
20110210454 | Phase Separated Curable Compositions - A curable composition, suitable for underfill encapsulant, has two distinct phase domains after cure, a continuous phase and a discontinuous phase, in which one phase has a modulus value of 2 GPa or greater, and the second phase has a modulus value at least 1 Gpa less than the first phase, characterized in that the phases are generated in situ as the composition cures. | 09-01-2011 |
20110215484 | Integrally Molded Die And Bezel Structure For Fingerprint Sensors And The Like - A biometric sensor device, such as a fingerprint sensor, comprises a substrate to which is mounted a die on which is formed a sensor array and at least one conductive bezel. The die and the bezel are encased in a unitary encapsulation structure to protect those elements from mechanical, electrical, and environmental damage, yet with a portion of the sensor array and the bezel exposed or at most thinly covered by the encapsulation or other coating material structure. | 09-08-2011 |
20110241226 | METHOD FOR PRODUCING A MICROFLUID COMPONENT, AS WELL AS MICROFLUID COMPONENT - A method for producing a microfluid component includes: Producing a single polymer layer made of at least one plastic or a plastic composite and having a microfluid structure, fitting the polymer layer with at least one semiconductor element, and/or with at least one electronic component, and/or with an optical or optoelectronic component, sealing the microfluid structure. | 10-06-2011 |
20110248412 | CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE - A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip. | 10-13-2011 |
20110285035 | SEALED CAVITY - Embodiments disclosed herein generally include methods of sealing a cavity in a device structure. The cavity may be opened by etching away sacrificial material that may define the cavity volume. Material from below the cavity may be sputter etched and redeposited over and in passageways leading to the cavity to thereby seal the cavity. Material may be sputter etched from above the cavity and redeposited in the passageways leading to the cavity as well. The sputter etching may occur in a substantially inert atmosphere. As the sputter etching is a physical process, little or no sputter etched material will redeposit within the cavity itself. The inert gases may sweep out any residual gases that may be present in the cavity after the cavity has been opened. Thus, after the sputter etching, the cavity may be substantially filled with inert gases that do not negatively impact the cavity. | 11-24-2011 |
20110304062 | CHIP PACKAGE STRUCTURE, CHIP PACKAGE MOLD CHASE AND CHIP PACKAGE PROCESS - A chip package structure including a carrier, a chip and a molding compound is provided. The chip is disposed on the carrier. The molding compound encapsulates a portion of the carrier and the chip. The top surface of the molding compound has a pin one dot and a pin gate contact. The pin one dot is located at a first corner on the top surface. The pin gate contact is located at a second corner except the first corner. The invention further provides a chip package mold chase and a chip package process using to form the chip package structure. | 12-15-2011 |
20120025404 | FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE - The present invention relates to a film for flip chip type semiconductor back surface to be formed on the back surface of a semiconductor element flip chip-connected to an adherend, the film for flip chip type semiconductor back surface having a tensile storage elastic modulus at 25° C. after thermal curing within a range of from 10 GPa to 30 GPa, in which the tensile storage elastic modulus at 25° C. after thermal curing of the film for flip chip type semiconductor back surface falls within a range of from 4 times to 20 times the tensile storage elastic modulus at 25° C. before thermal curing thereof. | 02-02-2012 |
20120061857 | Electronic Packaging With A Variable Thickness Mold Cap - An electronic package with improved warpage compensation. The electronic package includes a mold cap having a variable thickness. The variable thickness can have a mound or dimple design. In another embodiment, a method is provided for reducing unit warpage of an electronic package by designing the topography of a mold cap to compensate for warpage. | 03-15-2012 |
20120061858 | Semiconductor Device and Method of Forming Mold Underfill Using Dispensing Needle Having Same Width as Semiconductor Die - A semiconductor device has a semiconductor die mounted over a surface of a substrate. A mold underfill dispensing needle has a width substantially equal to a width of the semiconductor die. The dispensing needle is placed in fluid communication with a side of the semiconductor die. A mold underfill is deposited from an outlet of the dispensing needle evenly across a width of the semiconductor die into an area between the semiconductor die and substrate without motion of the dispensing needle. The dispensing needle has a shank and the outlet in a T-configuration. The dispensing needle can have a plurality of pole portions between a shank and the outlet. The dispensing needle has a plate between a shank and the outlet. The outlet has an upper edge with a length substantially equal to or greater than a length of a lower edge of the outlet. | 03-15-2012 |
20120061859 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULANT CONTAINMENT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming layers having non-horizontal strip patterns and non-vertical strip patterns over the substrate; mounting an integrated circuit device on the substrate adjacent the non-horizontal strip patterns and the non-vertical strip patterns; and applying an encapsulation over the integrated circuit device, the encapsulation restricted by the layers to prevent the encapsulation from reaching an edge of the substrate. | 03-15-2012 |
20120061860 | Method for Constructing an Electrical Circuit, and Electrical Circuit - A method for constructing an electrical circuit that includes at least one semiconductor chip encapsulated with a potting compound is disclosed. The method includes applying a galvanic layer arrangement for forming an electrochemical element on an element of the electrical circuit including the at least one semiconductor chip. | 03-15-2012 |
20120086135 | INTERPOSERS, ELECTRONIC MODULES, AND METHODS FOR FORMING THE SAME - In various embodiments, an electronic module features a first cavity in a first side of a substrate, a fill hole extending from the first cavity, and a second cavity in a second side of the substrate. The second cavity is in fluidic communication with the fill hole, and a die is encapsulated within the second cavity. | 04-12-2012 |
20120098146 | FORMATION OF BARRIER LAYER ON DEVICE USING ATOMIC LAYER DEPOSITION - The configuration of one or more barrier layers for encapsulating a device is controlled by setting parameters of atomic layer deposition (ALD). A substrate formed with the device is placed on a susceptor and exposed to multiple cycles of source precursor gas and reactant precursor gas injected by reactors of a deposition device. By adjusting one or more of (i) the relative speed between the susceptor and the reactors, (ii) configuration of the reactors, and (iii) flow rates of the gases injected by the reactors, the configuration of the layers deposited on the device can be controlled. By controlling the configuration of the deposited layers, defects in the deposited layers can be prevented or reduced. | 04-26-2012 |
20120126433 | METHODS AND SYSTEMS FOR FABRICATION OF MEMS CMOS DEVICES IN LOWER NODE DESIGNS - A method for manufacturing an integrated circuit including producing layers that form one or more electrical and/or electronic elements on a semiconductor material substrate. Then, producing ILD layers above the layers forming one or more electrical and/or electronic elements, including the steps of depositing a first layer of etch stopper material, depositing a second layer of dielectric material above and in contact with the first layer, forming at least one track extending through the first and second layers, and filling the at least one track with a non-metallic material. | 05-24-2012 |
20120139131 | WAFER MOLD MATERIAL AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - The invention provides a wafer mold material for collectively subjecting a wafer having semiconductor devices on a surface thereof to resin molding, wherein the wafer mold material has a resin layer containing a filler and at least any one of an acrylic resin, a silicone resin having an epoxy group, an urethane resin, and a polyimide silicone resin, and the wafer mold material is formed into a film-like shape. There can be a wafer mold material that enables collective molding (wafer molding) with respect to a wafer having semiconductor devices formed thereon, has excellent transference performance with respect to a large-diameter thin-film wafer, can provide a flexible hardened material with low-stress properties, and can be preferably used as a mold material in a wafer level package with less warp of a formed (molded) wafer. | 06-07-2012 |
20120146247 | PRE-TREATMENT OF MEMORY CARDS FOR BINDING GLUE AND OTHER CURABLE FLUIDS - A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of a curable fluid such as glue or ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface. | 06-14-2012 |
20120181708 | SUBSTRATE FOR MOUNTING SEMICONDUCTOR, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns. | 07-19-2012 |
20120187582 | INJECTION MOLDING SYSTEM AND METHOD OF CHIP PACKAGE - The injection molding system comprises a substrate, an inner cover, a molding tool, and a bottom plate. The substrate is used to locate at least one semiconductor device under molding and the inner cover with at least one first injection via, cavity and runner placed over the substrate. In addition, the molding tool includes at least one second injecting via aligned with the runner and the bottom plate is placed under the substrate. Furthermore, a filling material is filled into the cavity and runner of the inner cover during molding. In order to avoid overflowing the filling material, the system further comprises an O-ring placed between the molding tool and the inner cover. The inner radius of the O-ring corresponds with the inner radius of the injection via and is aligned with it. | 07-26-2012 |
20120187583 | METHODS AND APPARATUSES TO STIFFEN INTEGRATED CIRCUIT PACKAGE - A dam stiffener for a package substrate is presented. In an embodiment, the dam stiffener comprises a thermally curable polymer, and is simultaneously cured with the underfill material to act as stiffener to the substrate. In another embodiment, a curable reservoir material can be dispensed to fill the space between the integrated circuit die and the dam stiffener, forming a thick reservoir layer, acting as an additional stiffener for the package substrate. | 07-26-2012 |
20120193816 | Electronic Component and Method for Producing an Electronic Component - An electronic component having an encapsulation which has at least two double layers is described. In addition, a method for producing an electronic component in which a layer sequence is encapsulated is described. | 08-02-2012 |
20120205821 | EXTERNAL GETTERING METHOD AND APPARATUS - Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed. | 08-16-2012 |
20120211904 | Semiconductor Device and Method of Forming Mold Underfill Using Dispensing Needle Having Same Width as Semiconductor Die - A semiconductor device has a semiconductor die mounted over a surface of a substrate. A mold underfill dispensing needle has a width substantially equal to a width of the semiconductor die. The dispensing needle is placed in fluid communication with a side of the semiconductor die. A mold underfill is deposited from an outlet of the dispensing needle evenly across a width of the semiconductor die into an area between the semiconductor die and substrate without motion of the dispensing needle. The dispensing needle has a shank and the outlet in a T-configuration. The dispensing needle can have a plurality of pole portions between a shank and the outlet. The dispensing needle has a plate between a shank and the outlet. The outlet has an upper edge with a length substantially equal to or greater than a length of a lower edge of the outlet. | 08-23-2012 |
20120223444 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface. | 09-06-2012 |
20120248632 | PHOTOSENSITIVE ADHESIVE COMPOSITION, FILM-LIKE ADHESIVE, ADHESIVE SHEET, ADHESIVE PATTERN, SEMICONDUCTOR WAFER WITH ADHESIVE LAYER, SEMICONDUCTOR DEVICE - The present invention relates to a photosensitive adhesive composition that has thermal press bondability to an adherent after being patterned by exposure and development and enables alkali development, wherein a storage elastic modulus at 110° C. after exposure and further heat curing is not less than 10 MPa. | 10-04-2012 |
20120248633 | THIN-FILM DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING IMAGE DISPLAY APPARATUS - There is provided a method of manufacturing a thin-film device, the method including forming a first substrate on a supporting base by a coating method, the first substrate being formed by using a resin material; forming a second substrate on the first substrate by using any one of a thermosetting resin and energy ray-curable resin; forming an active element on the second substrate; and removing the supporting base from the first substrate. The resin material used to form the first substrate has a glass transition temperature of at least 180° C. | 10-04-2012 |
20120261841 | Article and Panel Comprising Semiconductor Chips, Casting Mold and Methods of Producing the Same - A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer. | 10-18-2012 |
20120267801 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING MOLD FLASH PREVENTION TECHNOLOGY - An integrated circuit package system that includes: a support structure including an electrical contact; a solder mask over the support structure, the solder mask including a solder mask flange, the solder mask flange directly on a support structure first surface; an integrated circuit over the support structure; and encapsulant over the integrated circuit and in contact with the solder mask flange. A mold system that includes a first mold having a projection along a first mold bottom surface, the projection between a first cavity and a recess. | 10-25-2012 |
20120286434 | BLANK INCLUDING A COMPOSITE PANEL WITH SEMICONDUCTOR CHIPS AND PLASTIC PACKAGE MOLDING COMPOUND AND METHOD AND MOLD FOR PRODUCING THE SAME - A blank and a semiconductor device include a composite panel with semiconductor chips embedded in a plastic package molding compound. The blank includes a composite panel with semiconductor chips arranged in rows and columns in a plastic package molding compound with active upper sides of the semiconductor chips forming a coplanar surface area with the upper side of the composite panel. The blank further includes an orientation indicator impressed into the plastic package molding compound when the semiconductor chips are embedded within the molding compound. | 11-15-2012 |
20120319302 | Semiconductor Device and Method of Forming RF FEM and RF Transceiver in Semiconductor Package - A semiconductor device has a first semiconductor die containing a low pass filter and baluns. The first semiconductor die has a high resistivity substrate. A second semiconductor die including a bandpass filter is mounted to the first semiconductor die. The second semiconductor die has a gallium arsenide substrate. A third semiconductor die including an RF switch is mounted to the first semiconductor die. A fourth semiconductor die includes an RF transceiver. The first, second, and third semiconductor die are mounted to the fourth semiconductor die. The first, second, third, and fourth semiconductor die are mounted to a substrate. An encapsulant is deposited over the first, second, third, and fourth semiconductor die and substrate. A plurality of bond wires is formed between the second semiconductor die and first semiconductor die, and between the third semiconductor die and first semiconductor die, and between the first semiconductor die and substrate. | 12-20-2012 |
20120319303 | Wafer level hermetic bond using metal alloy with keeper layer - Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate. At least one of the substrates may include a raised feature formed under at least one of the metal layers. The two metals may for an alloy of a predefined stoichiometry in at least two locations on either side of the midpoint of the raised feature. This alloy may have advantageous features in terms of density, mechanical, electrical or physical properties that may improve the hermeticity of the seal, for example. | 12-20-2012 |
20120319304 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer. | 12-20-2012 |
20120326339 | SEMICONDUCTOR DEVICE, AND METHOD AND APPARATUS FOR MANUFACTURING THE SAME - According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. | 12-27-2012 |
20130001807 | METHOD OF FLIP-CHIP HYBRIDIZATION FOR THE FORMING OF TIGHT CAVITIES AND SYSTEMS OBTAINED BY SUCH A METHOD - A method for manufacturing a microelectronic assembly including stacked first and second microelectronic components having a cavity therebetween including defining said cavity by means of a lateral wall forming a closed frame extending around a determined area of the first component except for an opening used as a vent; forming within the closed frame and opposite to the vent an obstacle capable of forming, in cooperation with the lateral wall, a bypass duct for the filling material; performing a flip-chip hybridization of the first and second components, a surface of the second component resting on the upper edge or end of the lateral wall formed on the first component to form said at least one cavity; injecting the filling material in liquid form between the two hybridized components to embed said at least one cavity and to make it tight by obstruction of the vent as said filling material solidifies. | 01-03-2013 |
20130020726 | PACKAGE MODULE STRUCTURE FOR HIGH POWER DEVICE WITH METAL SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a package module structure of a high power device using a metal substrate that can improve reliability by minimizing stress due to a thermal expansion coefficient difference between a metal substrate and a semiconductor device includes: preparing a metal substrate; forming an oxide layer by selectively anodizing the metal substrate; forming a mounting groove for mounting a semiconductor device by etching a portion of the oxide layer; installing a shock-absorbing substrate that is made of a material having a thermal expansion coefficient in a range similar to a material of a semiconductor device to expose the entirety or a portion of a bottom portion of the mounting groove; mounting the semiconductor device in the shock-absorbing substrate exposed to the mounting groove; and electrically connecting an electrode terminal of the semiconductor device and an electrode line formed in an upper surface of the oxide layer. | 01-24-2013 |
20130032955 | Low-K Dielectric Layer and Porogen - A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5. | 02-07-2013 |
20130069252 | Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus - A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die. | 03-21-2013 |
20130082407 | Integrated Circuit Package And Method - A method of making integrated circuit package assemblies including encapsulating a plurality of dies in an encapsulation layer having an exterior surface and attaching a heat sink strip to the exterior surface of the encapsulation layer. An integrated circuit package assembly and an intermediate product used in making an integrated circuit package assembly are also disclosed. | 04-04-2013 |
20130093105 | SEALING FILM AND A SEMICONDUCTOR DEVICE USING THE SAME - A method for sealing electrodes on a semiconductor device using a sealing film which includes a resin layer having a flow within the range of 150 to 1800 μm at 80° C., or having a resin layer with a viscosity within the range of 10,000 to 100,000 Pa·s in a B-stage state at 50 to 100° C. in thermosetting viscoelasticity measurement, and containing: (A) both (a1) a high-molecular-weight component including crosslinking functional groups and having a weight-average molecular weight of 100,000 or more and a Tg within the range of −50 to 50° C. and (a2) a thermosetting component including an epoxy resin as a main component, (B) a filler having an average particle size within the range of 1 to 30 μm, and (C) a colorant. | 04-18-2013 |
20130113121 | RESIN PASTE COMPOSITION - The present invention relates to a resin paste composition including an organic compound, and a granular aluminum powder having an average particle diameter of from 2 to 10 μm and a flake-shaped silver powder having an average particle diameter of from 1 to 5 μm which are uniformly dispersed in the organic compound, and a semiconductor device manufactured by bonding a semiconductor element onto a supporting member through the resin paste composition and then encapsulating the resulting bonded product. According to the present invention, it is possible to provide a resin paste composition used for bonding an element such as semiconductor chips onto a lead frame which is excellent in not only electrical conductivity and bonding property but also working efficiency without using a large amount of rare and expensive silver, and a semiconductor device having a high productivity and a high reliability. | 05-09-2013 |
20130119563 | ANISOTROPIC CONDUCTIVE FILM COMPOSITION AND SEMICONDUCTOR DEVICE BONDED BY THE SAME - An anisotropic conductive film composition for bonding a semiconductor device, the composition including: a binder system including a urethane resin having a glass transition temperature of about 100° C. or higher, a radical polymerizable compound, an organic peroxide, and conductive particles. | 05-16-2013 |
20130140718 | CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE - A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip. | 06-06-2013 |
20130175710 | Display Device and Method of Manufacturing Thereof - A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided. According to the present invention, a display device and a method of manufacturing the same comprising: a display portion formed by aligning a light-emitting element using an organic light-emitting material between a pair of substrate, wherein the display portion is formed on an insulating layer formed on any one of the substrates, the pair of substrates is bonded to each other with a sealing material formed over the insulating layer while surrounding a periphery of the display portion, at least one layer of the insulating layer is made of an organic resin material, the periphery has a first region and a second region, the insulating layer in the first region has an opening covered with a protective film, the sealing material is formed in contact with the opening and the protective film, an outer edge portion of the insulating layer in the second region is covered with the protective film or the sealing material. | 07-11-2013 |
20130187295 | SENSOR MODULE, PRODUCTION METHOD OF A SENSOR MODULE, AND INJECTION MOLD FOR ENCAPSULATING A SENSOR MODULE - A sensor module an injection mold for covering the sensor module, and to a production method for a covered sensor module including a chip carrier and a sensor chip disposed thereon. A channel is formed between the chip carrier and the sensor chip, by which a medium can be fed to the sensor chip. | 07-25-2013 |
20130200534 | SEALANT LAMINATED COMPOSITE, SEALED SEMICONDUCTOR DEVICES MOUNTING SUBSTRATE, SEALED SEMICONDUCTOR DEVICES FORMING WAFER, SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - Described herein is a sealant laminated composite for collectively sealing a semiconductor device's mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor device's forming surface of a wafer on which semiconductor devices are formed. The composite can include a support wafer and an uncured resin layer constituted of an uncured thermosetting resin formed on one side of the support wafer. In certain aspects, the sealant laminated composite is very versatile, even when a large diameter or thin substrate or wafer is sealed. In certain aspects, this can prevent the substrate or wafer from warping and the semiconductor devices from peeling; can collectively seal a semiconductor device's mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor device's forming surface of a wafer on which semiconductor devices are formed on a wafer level; and can provide a sealant laminated composite that is excellent in the heat resistance and humidity resistance after sealing. | 08-08-2013 |
20130207281 | MICROELECTRONIC SUBSTRATE COMPRISING A LAYER OF BURIED ORGANIC MATERIAL - Microelectronic substrate comprising at least:
| 08-15-2013 |
20130214434 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof. | 08-22-2013 |
20130221544 | MOLDING DIE, MICROCHIP MANUFACTURED BY USING MOLDING DIE, AND MANUFACTURING APPARATUS FOR MANUFACTURING MICROCHIP - A molding die for molding a substrate to be included in a microchip includes a first die and a second die contactable with and separable from the first die. A molding space for molding the substrate and a gate for introducing resin into the molding space are formed between the first die and the second die. A molding surface of the first die includes a first-die substrate molding region which molds the one surface of the substrate, a gate-defining region which defines the gate, and a rising region which is located between the gate-defining region and the first-die substrate molding region and extends from an edge of the first-die substrate molding region toward the second die. The gate-defining region is closer to the second die than the first-die substrate molding region. A microchip and a manufacturing apparatus also are provided. | 08-29-2013 |
20130256922 | Method for Fabricating a Semiconductor Device - In a method for fabricating a semiconductor device, a carrier and at least one semiconductor chip are provided. | 10-03-2013 |
20130256923 | Semiconductor Device and Method of Forming Reconstituted Wafer With Larger Carrier to Achieve More EWLB Packages Per Wafer with Encapsulant Deposited Under Temperature and Pressure - A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer. | 10-03-2013 |
20130264724 | ADHESIVE COMPOUND AND METHOD FOR ENCAPSULATING AN ELECTRONIC ARRANGEMENT - The invention relates to a method for encapsulating an electronic arrangement against permeants, wherein an electronic arrangement is made available on a substrate, wherein, in a vacuum, that area of the substrate which embraces that region of the electronic arrangement which is to be encapsulated, preferably said area and that region of the electronic arrangement which is to be encapsulated, is brought into contact with a sheet material comprising at least one adhesive compound and a composite is produced therefrom. The invention also relates to an apparatus for implementing the method and to an encapsulated electronic arrangement produced thereby. | 10-10-2013 |
20130300002 | RESIN SEALED MODULE - A resin-sealed module is provided which reduces the warpage of a substrate and the detachment between a sealing resin and the substrate which occur during re-reflow, has the excellent flatness of the top and bottom surfaces, and reduces the occurrence of the short failures. A resin layer made of a thermoplastic resin is arranged on top of a substrate, and a resin layer made of a thermosetting resin is arranged on top of this resin layer, thereby reducing the warpage of the substrate and the detachment between the sealing resin and the substrate which occur during re-reflow. | 11-14-2013 |
20130320572 | Isolation Rings for Packages and the Method of Forming the Same - A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface. | 12-05-2013 |
20130328220 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSIST AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming an integrated circuit device having a shaped side; mounting the integrated circuit device on the substrate; forming an encapsulation on the substrate and the integrate circuit device with the shaped side partially exposed from the encapsulation. | 12-12-2013 |
20130334714 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE PREVENTION MECHANISM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes providing a substrate; connecting an integrated circuit die; forming a molding having a temperature-dependent characteristic directly on the top surface of the substrate; and forming a coupling encapsulation having a coupled characteristic different from the temperature-dependent characteristic directly on the molding forms an encapsulation boundary between the coupling encapsulation and the molding. | 12-19-2013 |
20130341807 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a package substrate having a first surface, a second surface opposite to the first surface, and a sidewall surface between the first surface and the second surface. A semiconductor device is mounted on the first surface. A mold cap encapsulates the semiconductor device. The mold cap includes a vertical extension portion covering the sidewall surface and a horizontal extension portion covering a periphery of a solder ball implanting region on the second surface. | 12-26-2013 |
20140001656 | ENCAPSULATING LAYER-COVERED SEMICONDUCTOR ELEMENT, PRODUCING METHOD THEREOF, AND SEMICONDUCTOR DEVICE | 01-02-2014 |
20140001657 | ENCAPSULATING LAYER-COVERED SEMICONDUCTOR ELEMENT, PRODUCING METHOD THEREOF, AND SEMICONDUCTOR DEVICE | 01-02-2014 |
20140027932 | MANUFACTURING AN UNDERFILL IN A SEMICONDUCTOR CHIP PACKAGE - A method for manufacturing an underfill in a semiconductor chip stack having a cavity between a first surface and a second surface includes providing at least one access hole in one of the first or second surface; providing at least one vent hole in the one of the first or second surfaces; and applying a viscous filling material through the at least one access hole into the cavity thereby squeezing out air or gas through the at least one vent hole. | 01-30-2014 |
20140035170 | SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD - The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion. | 02-06-2014 |
20140042645 | RESIN SHEET FOR SEALING ELECTRONIC COMPONENT, RESIN-SEALED TYPE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING RESIN-SEALED TYPE SEMICONDUCTOR DEVICE - An electronic-component-sealing resin sheet capable of restraining the warp amount of a package obtained by use of the sheet, a resin-sealed type semiconductor device high in reliability, and a method for producing the device are provided. The present invention relates to a resin sheet for sealing an electronic component, wherein after the resin sheet is hot-pressed onto an iron nickel alloy plate containing 42% by weight of nickel and having a shape 90 mm square and a thickness of 0.15 mm to give a thickness 0.2 mm and the resultant hot-pressed unit is cured at 150° C., the unit exhibits a warp amount of 5 mm or less. | 02-13-2014 |
20140048960 | PACKAGE SUBSTRATE, MANUFACTURING METHOD THEREOF, AND MOLD THEREFOR - There are provided a package substrate, a manufacturing method thereof, and a mold therefor. The method of manufacturing a package substrate includes: preparing a chip component and a substrate; mounting the chip component on a main surface of the substrate; preparing a mold having a cavity and protrusions formed on a ceiling surface thereof; disposing the substrate on a bottom surface of the mold such that the chip component is positioned within the cavity; and forming a resin sealing body that collectively hermetically seals the chip component and the main surface of the substrate by injecting a pressurized liquid resin into the cavity. | 02-20-2014 |
20140054802 | Semiconductor Device and Method of Forming RDL Using UV-Cured Conductive Ink Over Wafer Level Package - A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench by disposing a stencil over the first insulating layer with an opening aligned with the patterned trench and depositing the conductive ink through the opening in the stencil into the patterned trench. | 02-27-2014 |
20140061955 | THERMOSETTING RESIN SHEET FOR SEALING ELECTRONIC COMPONENT, RESIN-SEALED TYPE SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING RESIN-SEALED TYPE SEMICONDUCTOR DEVICE - A thermosetting resin sheet for sealing an electronic component, that is excellent in adhesiveness, onto the electric component; a resin-sealed type semiconductor device high in reliability; and a method for producing the device are provided. The present invention relates to a thermosetting resin sheet for sealing an electronic component, comprising one or more resin components, one of the components being allowable to be a thermoplastic resin, and having a content by percentage of the thermoplastic resin of 30% or less by weight of all of the entire resin components. | 03-06-2014 |
20140077395 | INTEGRATED CIRCUIT DEVICE - An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer. | 03-20-2014 |
20140091483 | METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS - A method of manufacturing a semiconductor apparatus includes: a charging step of charging the thermosetting resin in excess of an amount necessary for forming the sealing layer to fill the inside of the first cavity with the thermosetting resin and discharging an excess of the thermosetting resin from the first cavity; an integrating step of integrating the substrate on which the semiconductor device is mounted, the substrate on which no semiconductor device is mounted and the sealing layer by molding the thermosetting resin while pressurizing the upper mold and the lower mold; and a dicing step of extracting the integrated substrates from the molding mold and dicing the integrated substrates to obtain an individual semiconductor apparatus. | 04-03-2014 |
20140117568 | STRUCTURE OF WAFER LEVEL CHIP MOLDED PACKAGE - An integrated circuit structure includes a semiconductor chip having a die side and a non-die side, the die side having one or more trenches formed therein. The integrated circuit structure further includes at least one die bonded onto the die side of the semiconductor chip. The integrated circuit structure further includes a protecting material encapsulating the at least one die and substantially filling the one or more trenches. | 05-01-2014 |
20140145353 | TAMPER-RESISTANT COATING FOR AN INTEGRATED CIRCUIT - A system may include an integrated circuit and a coating at least partially encapsulating the integrated circuit. The coating may include an electrically insulating material at least partially encapsulating an analog circuit. The integrated circuit may be electrically connected to the analog circuit. Additionally, the integrated circuit may be configured to generate an analog electrical signal, transmit the analog electrical signal through the analog circuit to generate a modified analog electrical signal, receive the modified analog electrical signal, and in response to determining that the modified analog electrical signal is sufficiently similar to an expected analog electrical signal, use the modified analog electrical signal as an input to an algorithm performed by the integrated circuit. | 05-29-2014 |
20140167294 | FUNCTIONAL FILM, ENVIRONMENTALLY SENSITIVE ELECTRONIC DEVICE PACKAGE, AND MANUFACTURING METHODS THEREOF - An environmentally sensitive electronic device package including a first adhesive, at least one first side wall barrier, a first substrate, and a second substrate is provided. The first adhesive has a first surface and a second surface opposite to the first surface. The first side wall barrier is distributed in the first adhesive. The first substrate is bonded with the first surface. The first substrate has an environmentally sensitive electronic device formed thereon and the environmentally sensitive electronic device is surrounded by the first side wall barrier. The second substrate is bonded with the second surface. A manufacturing method of the environmentally sensitive electronic device package is also provided. | 06-19-2014 |
20140175681 | ABSORBING EXCESS UNDER-FILL FLOW WITH A SOLDER TRENCH - One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication. | 06-26-2014 |
20140183760 | System and Method to Improve Package and 3DIC Yield in Underfill Process - A method embodiment includes forming a packaging unit by attaching a die to a packaging substrate, applying plasma treatment to a first portion of the packaging substrate, wherein the first portion corresponds to a portion of the packaging substrate underneath the die, not applying plasma treatment to a second portion of the packaging substrate, wherein the second portion of the packaging substrate surrounds the first portion of the packaging substrate, and applying an underfill material over the first portion of the packaging substrate. | 07-03-2014 |
20140183761 | Semiconductor Device and Method of Forming Embedded Wafer Level Chip Scale Packages - A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less. | 07-03-2014 |
20140197551 | Method for Fabricating a Semiconductor Chip Panel - The method comprises providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each comprising a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips. | 07-17-2014 |
20140217620 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface. | 08-07-2014 |
20140252660 | MULTILAYER PATTERN TRANSFER FOR CHEMICAL GUIDES - Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a nitride layer and an oxide layer) over a substrate (e.g., silicon (Si)). An orientation control layer (e.g., a neutral layer) is then formed over the etch mask layer, and an ARC layer (e.g., SiARC) is formed over the orientation control layer. In other embodiments, an organic planarization layer (OPL) and/or a protection layer may also be formed between the ARC layer and the orientation control layer. Regardless, a tapered etch profile/pattern may then be formed through the ARC and/or other layers. | 09-11-2014 |
20140264954 | PASSIVATION AND WARPAGE CORRECTION BY NITRIDE FILM FOR MOLDED WAFERS - Embodiments of the invention generally relate to molded wafers having reduced warpage, bowing, and outgassing, and methods for forming the same. The molded wafers include a support layer of silicon nitride disposed on a surface thereof to facilitate rigidity and reduced outgassing. The silicon nitride layer may be formed on the molded wafer, for example, by plasma-enhanced chemical vapor deposition or hot-wire chemical vapor deposition. | 09-18-2014 |
20140264955 | ELECTRONIC DEVICE WITH AN INTERLOCKING MOLD PACKAGE - An electronic device includes a mold package which encapsulates a portion of the electronic device and does not encapsulate another portion of the electronic device to enable a sensing portion of the electronic device to be exposed to a condition to be sensed. In an electronic sensing device having a sensor formed by a substrate such as silicon, a sensor area is not encapsulated, but areas surrounding the sensor area are encapsulated. The area surrounding the sensor area includes one or more trenches or interlock structures formed in the surrounding substrate which receives the mold material to provide an interlock feature. The interlock feature reduces or substantially prevents the mold from delaminating at an interface of the mold and the substrate. | 09-18-2014 |
20140264956 | SEALANT LAMINATED COMPOSITE, SEALED SEMICONDUCTOR DEVICES MOUNTING SUBSTRATE, SEALED SEMICONDUCTOR DEVICES FORMING WAFER, SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - Disclosed is a sealant laminated composite for collectively sealing a semiconductor devices mounting surface of a substrate on which semiconductor devices may be mounted or a semiconductor devices forming surface of a wafer on which semiconductor devices may be formed, including a support wafer that may be composed of silicon and an uncured resin layer that may be constituted of an uncured thermosetting resin formed on one side of the support wafer. | 09-18-2014 |
20140284820 | SUBSTRATE FOR MOUNTING SEMICONDUCTOR, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns. | 09-25-2014 |
20140306356 | ARRANGEMENT HAVING A PLURALITY OF CHIPS AND A CHIP CARRIER, AND A PROCESSING ARRANGEMENT - In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess. | 10-16-2014 |
20140332986 | Semiconductor Device and Method of Forming Adhesive Material to Secure Semiconductor Die to Carrier in WLCSP - A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material. | 11-13-2014 |
20140339713 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes sealing a first surface of a semiconductor wafer with a resin, causing a resin-made warp suppression member to be adhered to a second surface on the opposite side of the first surface of the semiconductor wafer and causing the warp suppression member to shrink, measuring the amount of warp of the semiconductor wafer, and forming cuts in the warp suppression member in accordance with the amount of warp of the semiconductor wafer. | 11-20-2014 |
20140346685 | SILICON-BASED ELECTRONICS WITH DISABLING FEATURE - Silicon-based circuitry is dissolved or otherwise disabled in a controlled manner by reactive materials provided beneath the insulating layer on which the circuitry is formed. Heat and/or light induced acid generating materials are provided for corroding one or more circuitry components. Additionally and/or alternatively, gas-producing materials are deposited in compartments beneath the insulating layer. The gas-producing materials cause pressure to rise within the compartments, damaging the chip. Chemical reactions within the chip may be facilitated by heating elements and/or light generating elements embedded within the chip and actuated by triggering circuits. | 11-27-2014 |
20140346686 | METHODS FOR FORMING COLOR IMAGES ON MEMORY DEVICES AND MEMORY DEVICES FORMED THEREBY - A memory device including graphical content and a method of making the memory device with graphical content are disclosed. The graphical content is formed on a release media. The release media and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the graphical content is transferred from the release media to the encapsulated memory device. | 11-27-2014 |
20150008597 | Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant. | 01-08-2015 |
20150028497 | ENCAPSULANT WITH BASE FOR USE IN SEMICONDUCTOR ENCAPSULATION, SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - The present invention provides an encapsulant with a base for use in semiconductor encapsulation, for collectively encapsulating a device mounting surface of a substrate on which semiconductor devices are mounted, or a device forming surface of a wafer on which semiconductor devices are formed, the encapsulant comprising the base, an encapsulating resin layer composed of an uncured or semi-cured thermosetting resin formed on one surface of the base, and a surface resin layer formed on the other surface of the base. The encapsulant enables a semiconductor apparatus having a good appearance and laser marking property to be manufactured. | 01-29-2015 |
20150061162 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor structure includes several operations. The several operations include placing a plurality of dies on a carrier; defining a first zone and a second zone in a top surface of the carrier; calculating a first coverage ratio in the first zone; calculating a second coverage ratio in the second zone; disposing a dummy block on a specified location of the top surface of the carrier if the difference between the first coverage ratio and the second coverage ratio is greater than a predetermined value; forming a molding compound on the carrier. | 03-05-2015 |
20150069640 | FLEXIBLE CHIP SET ENCAPSULATION STRUCTURE - A flexible chip set encapsulation structure includes a chip set. The chip set comprises a plurality of spaced chips and a fixing film. The fixing film is adapted to wrap and fix the chips. The fixing film has at least one bending portion at a predetermined position for the fixing film to have flexibility in a predetermined direction. Thus, the flexible chip set encapsulation structure is flexible for bending. When the user wears the flexible chip set, the movement of the user won't be confined. Besides, the chip set is completely attached to the body to provide a comfortable wear, and the chips provide a better far infrared radiation effect. | 03-12-2015 |
20150084213 | Semiconductor Device and Method of Controlling Warpage in Reconstituted Wafer - A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced. | 03-26-2015 |
20150091196 | MOLD LOCKS FOR LAMINATE SUBSTRATES - A mechanism is provided by which delamination of a substrate of a system-in-package is prevented. A mold lock feature is provided within the substrate that allows the mold compound forming the encapsulant to flow into the mold lock feature, thereby anchoring the encapsulant to the substrate. The mold lock features can be provided in areas of the substrate where higher stresses due to component configuration are predicted. Aspects of the present invention provide for a method of forming the mold lock features that is compatible with current methods of forming laminate substrates, and thereby do not require an increase in cost for manufacturing the substrate. | 04-02-2015 |
20150108666 | Thinning in package using separation structure as stop - A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop. | 04-23-2015 |
20150108667 | APPARATUS AND METHOD FOR CHIP PLACEMENT AND MOLDING - An approach is provided for placing and securing a chip package portion in an aligned position during a curing process. The approach involves providing an apparatus having a first reservoir configured to receive a first chip package, a second reservoir, and a third reservoir. The approach also involves placing the first chip package portion into the first reservoir, the second chip package portion into the second reservoir, and the third chip package portion into the third reservoir. The approach further involves causing the first chip package portion to be secured in a first curing position, the second chip package portion to be secured in a second curing position and the third chip package portion to be secured in a third curing position. | 04-23-2015 |
20150145149 | Semiconductor Device Packaging - A method of manufacturing a semiconductor device package includes encapsulating at least partially a plurality of semiconductor chips with encapsulating material to form an encapsulation body. The encapsulation body has a first main surface and a second main surface. At least one of a metal layer and an organic layer is formed over the first main surface of the encapsulation body. At least one trace of the at least one of the metal layer and the organic layer is removed by laser ablation. The encapsulation body is then separated into a plurality of semiconductor device packages along the at least one trace. | 05-28-2015 |
20150348860 | SEMICONDUCTOR DEVICE AND TEST SYSTEM FOR THE SEMICONDUCTOR DEVICE - A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member. | 12-03-2015 |
20150371880 | SEMICONDUCTOR DIE ENCAPSULATION OR CARRIER-MOUNTING METHOD, AND CORRESPONDING SEMICONDUCTOR DIE ENCAPSULATION OR CARRIER-MOUNTING APPARATUS - A semiconductor die encapsulation or carrier-mounting method includes the steps of providing a first tool part for holding multiple semiconductor dies and providing the semiconductor dies on the first tool part; providing a second tool part, one of the first and second tool parts including displaceable insert members to allow applying a pressure by each displaceable insert member on a surface area of a semiconductor die; and bringing together the first and second tool parts such as to define a space between the first and second tool parts, the semiconductor products being arranged in the space. The displaceable insert members apply a pressure onto the surface area of the semiconductor dies. The pressure applied by the displaceable insert members is monitored and regulated to a predetermined pressure. Subsequently, the first and second tool parts are separated and the processed semiconductor dies are removed. | 12-24-2015 |
20160013078 | Mould, Carrier with Encapsulated Electronic Components, Separated Encapsulated Electronic Component and Method for Encapsulating Electronic Components | 01-14-2016 |
20160056350 | LED ENCAPSULATION STRUCTURE - An LED encapsulation structure includes a reflective cup, a positive electrode plate, and a negative electrode plate. The reflective cup has a light emitting surface, a bottom surface opposite to the light emitting surface, two parallel first sides, and two parallel second sides. The positive electrode plate includes a first weld, a second weld, and a bent portion interconnecting with the first weld and the second weld. The negative electrode plate includes a third weld, a fourth weld, and a second bent portion interconnecting with the third weld and the fourth weld. The first weld and the third weld are positioned on one first side, and spaced from each other. The second weld and the fourth weld are positioned on the bottom surface. | 02-25-2016 |
20160071779 | SEMICONDUCTOR DEVICE HAVING RECESSED EDGES AND METHOD OF MANUFACTURE - A device and method of manufacture is provided that utilize recessed regions along a package edge. For example, in an integrated fan-out package, the dielectric layers, e.g., the polymer layers, of the redistribution layers are removed along the scribe line such that after singulation the dielectric layers are recessed back from the edges of the die. The corner regions may be recessed further. The recessed regions may be triangular, rounded, or other shape. In some embodiments one or more of the corner regions may be recessed further relative to the remaining corner regions. The redistribution layers may be recessed along one or both of the front side redistribution layers and the backside redistribution layers. | 03-10-2016 |
20160079094 | METHODS OF PROTECTING PERIPHERIES OF IN-PROCESS SEMICONDUCTOR WAFERS AND RELATED IN-PROCESS WAFERS AND SYSTEMS - Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material, a plurality of semiconductor devices located on the active surface of the wafer, an exposed side surface of an adhesive material located on a back side surface of the wafer, and at least a portion of a side surface of a carrier substrate secured to the wafer by the adhesive material in an encapsulation material. At least a portion of the side surface of the adhesive material may be exposed by removing at least a portion of the encapsulation material. The carrier substrate may be detached from the wafer. Processing systems and in-process semiconductor wafers are also disclosed. | 03-17-2016 |
20160118623 | THIN FILM DEPOSITION - A method of preparing a surface for deposition of a thin film thereon, wherein the surface including a plurality of protrusions extending therefrom and having shadowed regions, includes locally treating at least one of the protrusions. | 04-28-2016 |
20160141258 | MULTIPLE BARRIER LAYER ENCAPSULATION STACK - A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying multiple barrier layers to the apparatus and preceding each layer application with a separate cleaning of the presently-exposed apparatus surface, resulting in an apparatus which includes an encapsulation stack, where the encapsulation stack includes a multi-layer stack of barrier layers. Each separate cleaning removes particles from the presently-exposed apparatus surface, exposing gaps in the barrier layer formed by the particles, and the subsequently-applied barrier layer at least partially fills the gaps, so that a permeation pathway through the encapsulation stack via gap spaces is restricted. The quantity of barrier layers applied to form the stack can be based on a determined probability that a stack of the particular quantity of barrier layers is independent of at least a certain quantity of continuous permeation pathways through the stack. | 05-19-2016 |
20160172214 | Molded Electronic Package Geometry To Control Warpage And Die Stress | 06-16-2016 |