Entries |
Document | Title | Date |
20080203586 | Integrated Circuit and Methods of Manufacturing a Contact Arrangement and an Interconnection Arrangement - A contact arrangement is manufactured by providing a substrate that includes first regions that are arranged along a row direction and a second region. An interlayer is provided that covers the first regions and the second region. A buried mask including a first trim opening above the first regions is provided. A top mask including first template openings is provided, where each first template opening is arranged above one of the first regions. A second template opening is provided above the second region. The fill material and the interlayer are etched to form contact trenches above the first regions and the second region. Substrate area efficient chains of evenly spaced contacts are provided. | 08-28-2008 |
20080203587 | SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE LINES WITH FINE LINE WIDTH AND METHOD OF FABRICATING THE SAME - A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process. | 08-28-2008 |
20080224332 | Transistor circuit formation substrate and method of manufacturing transistor - A specially designed mask controls the arrangement of conductive materials that form a source and drain of a transistor. Designing the mask can be costly and time-consuming, which means that the testing of a circuit involving a transistor can also be costly, time consuming and a barrier towards efficient circuit development and testing. Accordingly, the present invention provides a pre-fabricated, general-purpose pattern comprising an array of conductive islands. The pattern is used as a source and a drain terminal for the formation of a thin-film transistor and as a conductive source for the formation of other electrical components upon the array. | 09-18-2008 |
20080246167 | Layout Structure for Chip Coupling - A layout structure disposed on the substrate of the liquid crystal display (LCD) for chip coupling is provided. The first and second orientations that are substantially perpendicular to the first orientation can be defined on the substrate. The layout structure includes a plurality of lines, which extend along the second orientation, and a plurality of conductive pads that are respectively disposed on the lines. The conductive pads are distributed along the first orientation and staggered along the second orientation. Each line can shift away from the adjacent conductive pad on the first orientation. Thus, the LCD chip has a better conductivity and a thinner dimension under the precision of the conventional machines. | 10-09-2008 |
20080246168 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction. | 10-09-2008 |
20080265442 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating film that includes a first opening reaching a substrate and that is provided on the substrate, a second insulating film that includes a second opening reaching the substrate through the first opening of the first insulating film and that covers the first insulating film, and a conductive pattern that is provided on the second insulating film so as to be in contact with the substrate through the second opening of the second insulating film. | 10-30-2008 |
20080277804 | Mask Layout Method, and Semiconductor Device and Method for Fabricating the Same - Provided are a mask layout method and a semiconductor device and a method for fabricating the same. The semiconductor device can include a main pattern, a first dummy pattern, and a second dummy pattern. The main pattern can be disposed on a substrate. The first dummy pattern and the second dummy pattern can be disposed around a side of the main pattern. The first dummy pattern can have an inner open region. The second dummy pattern can be disposed on the inner open region of the first dummy pattern, such that the first dummy pattern surrounds the second dummy pattern. | 11-13-2008 |
20080296785 | Method of forming catalyst nanoparticles for nanowire growth and other applications - Methods for forming a predetermined pattern of catalytic regions having nanoscale dimensions are provided for use in the growth of nanowires. The methods include one or more nanoimprinting steps to produce arrays of catalytic nanoislands or nanoscale regions of catalytic material circumscribed by noncatalytic material. | 12-04-2008 |
20080303177 | BONDING PAD STRUCTURE - A bonding pad structure including a bonding pad and a passivation layer is described. The bonding pad is disposed on a chip. The passivation layer covers the bonding pad. In addition, the passivation layer has a first opening exposing a bonding region of the bonding pad and a second opening exposing a probing region of the bonding pad, respectively. | 12-11-2008 |
20080308954 | Semiconductor device and method of forming the same - A semiconductor device includes conductive lines on a substrate, sidewall spacers on sidewalls of the conductive lines, contacts between the conductive lines, the contacts separated from the conductive lines by the sidewall spacers and electrically connected to active regions of the substrate, contact pads on and electrically connected to corresponding contacts, protection patterns contacting side surfaces of the contact pads, the protection patterns being disposed between the contact pads in a first direction crossing the conductive lines, and storage nodes on and electrically connected to corresponding contact pads. | 12-18-2008 |
20090008803 | LAYOUT OF DUMMY PATTERNS - A layout of dummy patterns on a wafer having a plurality of pads disposed thereon is described. The layout of the dummy patterns includes having a plurality of dummy patterns spaced apart from each other and enclosing the plurality of the pads. The plurality of dummy patterns also include a plurality of peripheral dummy patterns and a plurality of central dummy patterns, wherein a minimum distance between the plurality of the central dummy patterns and the plurality of the pads is greater a minimum distance between the plurality of the peripheral dumpy patterns and the plurality of the pads. | 01-08-2009 |
20090057927 | METHOD FOR FORMING INTERLAYER INSULATING FILM IN SEMICONDUCTOR DEVICE - A method for forming an interlayer insulating film includes providing a semiconductor substrate having a first substrate region with a plurality of metal wiring and a second substrate region having no metal wiring, and then forming an insulating film dummy pattern in the second substrate region, wherein the insulating film dummy pattern has the same thickness as the metal wiring, and then forming an interlayer insulating film over the semiconductor substrate including the insulating film dummy pattern. | 03-05-2009 |
20090065956 | MEMORY CELL - Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the memory cell includes fa first device having a first conductive line extending over a first active region and having a first line end of the first conductive line positioned over an isolation region adjacent to the first active region; and a second device having a second conductive line extending over one of a second active region and a contact element and having a second line end of the second conductive line positioned over the isolation region adjacent to the one of the second active region and the contact element, wherein the first line end and the second line end each include a bulbous end that is distanced from a respective active region or contact element. | 03-12-2009 |
20090079095 | SEMICONDUCTOR WAFER, SEMICONDUCTOR CHIP CUT FROM THE SEMICONDUCTOR WAFER, AND METHOD OF MANUFACTURING SEMICONDUCTOR WAFER - A disclosed semiconductor wafer includes plural semiconductor chip areas each having a color pattern capable of tracing the positional information of the semiconductor chip with respect to the semiconductor wafer. Each of the plural semiconductor chip areas arranged in a matrix manner on the semiconductor wafer includes an underlying insulation film; a wiring pattern and a frame-shaped wiring dummy pattern formed on the underlying insulation film; and plural insulation films formed on the upper side of the underlying insulation film, the wiring pattern, and the wiring dummy pattern. At least one SOG film is included in the plural insulation films, in which a color pattern in accordance with a distance from the center of the semiconductor wafer based on the SOG film is formed on a surface of the insulator film within the wiring dummy pattern in top view. | 03-26-2009 |
20090085230 | SEMICONDUCTOR DEVICE AND LAYOUT METHOD THEREOF - A semiconductor device and a layout method thereof are provided, each of which contributes to a reduction in layout area and appropriately adjusts an inter-wiring capacitance even where wiring widths and intervals in a plurality of wiring layers differ at a bus wiring comprised of the wiring layers. In the semiconductor device, a first functional block and a second functional block are connected to each other, and a plurality of wirings formed over their corresponding wiring layers are provided. The wiring layers have constant wiring widths and wiring intervals for every wiring layer. The number of wirings on each wiring layer is determined, at least in part, by multiplying (a) the total number of required wirings (for all wiring layers) by (b) a ratio of (i) a rate of wirings per unit length on the given layer versus (ii) the sum of the rates of wirings per unit length for each of the plurality of wiring layers. Where the rate of wirings per unit length on a given layer is an inverse of the sum of (x) the desired or predetermined constant wiring width for that layer and (y) the desired or predetermined constant wiring interval for that layer. | 04-02-2009 |
20090127721 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit comprises a first and second common wiring layers common to a plurality of types of products and independent of a user circuit, a customized layer provided between the first common wiring layer and the second common wiring layer and which is configured to form the user circuit. The second common wiring layer is formed above an upper layer of the first common wiring layer, and an universal logic cell is wired to the first and second common wiring layers and the customized layer. A power supply wiring, which is connected to a power supply pad, which is connected to an external power supply, is formed through the second common wiring layer, and the power supply wiring is formed in the same layer as the power supply pad and extends to an internal circuit area in which the universal logic cell is formed. | 05-21-2009 |
20090140443 | Microstructure with Enlarged Mass and Electrode Area for Kinetic to Electrical Energy Conversion - A microstructure has a substrate, a fixed electrode having a plurality of fixed fingers fixed to the substrate, a movable electrode having a body ( | 06-04-2009 |
20090146322 | METHOD OF ELIMINATING A LITHOGRAPHY OPERATION - Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques. According to another embodiment, features for lines and logic device components having a width greater than that of the lines are formed in the spacer material in the same mask layer. | 06-11-2009 |
20090160071 | Die rearrangement package structure using layout process to form a compliant configuration - A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with at least one slit is provided to cover the active surface and the pads is exposed from said slits; one ends of a plurality of metal traces is electrically connected to each pads; a protective layer is provided to cover the active surface of the dies and each metal traces, and the other ends of the metal traces being exposed; a plurality of connecting elements is electrically connected other ends of the metal traces, the characterized in that: the package body is a B-stage material. | 06-25-2009 |
20090166894 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention reduces the congestion of signal wires around an ESD protection circuit resulting from the presence of a connecting wire above the ESD protection circuit. The connecting wire connected to the ESD protection circuit extends in the same direction as a wire preferential direction of a corresponding wiring layer. Therefore, a signal wire extending in the lateral direction may be formed in the wiring layer in which the connecting wire extends in the lateral direction and a signal wire extending in the longitudinal direction may be formed in the wiring layer in which the connecting wire extends in the longitudinal direction. This makes it possible to arrange the signal wire to extend in both of the lateral and longitudinal directions above the ESD protection circuit irrespective of the presence of the connecting wire. | 07-02-2009 |
20090166895 | CIRCUIT SUBSTRATE, CIRCUIT DEVICE AND MANUFACTURING PROCESS THEREOF - A semiconductor device that includes a metal substrate including a top surface, a bottom surface and four side surfaces, a conductive pattern insulated from the metal substrate, and a semiconductor element mounted on and electrically connected to the conductive pattern. The top surface is insulated. Each of the side surfaces of the metal substrate includes a first inclining side surface and a second inclining side surface so as to form a convex shape protruding outwardly between the top surface and the bottom surface of the metal substrate, and the first inclining side surfaces of a pair of two opposing side surfaces are smaller than corresponding first inclining side surfaces of another pair of two opposing side surfaces. | 07-02-2009 |
20090174084 | VIA OFFSETTING TO REDUCE STRESS UNDER THE FIRST LEVEL INTERCONNECT (FLI) IN MICROELECTRONICS PACKAGING - The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip. | 07-09-2009 |
20090174085 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip is provided comprising a semiconductor substrate on which an integrated circuit is formed. The semiconductor chip, which is provided on the semiconductor substrate in an area array, further comprises a plurality of electrodes electrically coupled with the inside of the semiconductor substrate, wherein the electrodes are arranged into a plurality of first groups respectively lined along a plurality of paralleling first straight lines and, further, into a plurality of second groups respectively lined along a plurality of second straight lines which extend so as to intersect with the first straight lines. | 07-09-2009 |
20090194889 | BOND PAD STRUCTURE - A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. In an embodiment, the conductive density of the connective layer is between approximately 20% and 100%. | 08-06-2009 |
20090212445 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit, a second wiring layer includes a ground conductor having at least one opening formed therein. At least one opening is overlapped by at least one patch conductor included in a third wiring layer. At least one patch conductor and the ground conductor are electrically connected to each other by at least one via hole included in a second dielectric layer. A first wiring layer includes a signal line above the ground conductor. | 08-27-2009 |
20090236758 | SEMICONDUCTOR MODULE - A semiconductor module has a plurality of semiconductor devices arranged on a substrate and mutually connected by signal bus wiring lines. Each pair of first semiconductor devices are connected to each other by the signal bus wiring lines, skipping a second semiconductor device located between the pair of first semiconductor devices. | 09-24-2009 |
20090250824 | METHOD AND APPARATUS TO REDUCE PIN VOIDS - A semiconductor package comprises a substrate that utilizes one or more pins to form external interconnects. The pins are bonded to bonding pads on the substrate by solder. The pins may each has a pin head that may have a bonding surface, wherein the bonding surface may comprises a center portion and a side portion that is tapered away relative to the center portion. In some embodiments, the bonding surface may comprise a round shape. In some embodiments, a gas escape path may be provided by the shape of the bonding surface to increase pin pull strength and/or solder strength. The package may further comprise a surface finish that may comprise a palladium layer with a reduced thickness to reduce the amount of palladium based IMC precipitation into the solder. | 10-08-2009 |
20090273099 | SEMICONDUCTOR INTEGRATED CIRCUIT - On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity of an end portion on the first chip side are arranged having a steplike shift in a direction apart from the first chip side with decreasing distance from the center portion to the end portion on the first chip side. | 11-05-2009 |
20090273100 | INTEGRATED CIRCUIT HAVING INTERLEAVED GRIDDED FEATURES, MASK SET AND METHOD FOR PRINTING | 11-05-2009 |
20090273101 | Apparatus and Method for Preventing Configurable System-on-a-Chip Integrated Circuits from Becoming I/O Limited - An integrated circuit containing multiple modules coupled to a pad via a multiplexer. The modules are selectively coupled to the pad by the multiplexer to provide integrated circuit function flexibility with a limited number of pads. A multiplexer select signal determines which module or clock circuit is coupled by the multiplexer. A common buffer may be coupled between the multiplexer and the pad to save substrate space. An analog circuit may be coupled to the pad to provide a signal path minimizing signal distortion. The integrated circuit's clock may be coupled via the multiplexer to an off-substrate circuit. Selective module coupling improves the integrated circuit's testing speed, may salvage an integrated circuit containing a malfunctioning module, and provides for signal loopback during testing. | 11-05-2009 |
20090283921 | CONTACT LAYOUT STRUCTURE - A contact layout structure includes a substrate having at least a first region defined thereon, plural sets of first contact layouts positioned along a predetermined direction in the first region, and a plurality of second contact layouts positioned in the first region. Each set of the first contact layout has two square contact units and two adjacent rectangle contact units positioned between the two square contact units. | 11-19-2009 |
20090309242 | DEVICE PACKAGE STRUCTURE, DEVICE PACKAGING METHOD, DROPLET EJECTION HEAD, CONNECTOR, AND SEMICONDUCTOR DEVICE - A device package structure includes: a base body having a conductive connection portion and a level difference portion; a device arranged on the base body, having a connection terminal electrically connected to the conductive connection portion via the level difference portion on the base body; and a connector electrically connecting the connection terminal and the conductive connection portion, having substantially the same height as a height of the level difference portion. | 12-17-2009 |
20090315191 | Semiconductor integrated circuit - In order to form a semiconductor integrated circuit capable of effectively using a chip area, there is provided a semiconductor integrated circuit ( | 12-24-2009 |
20100013109 | FINE PITCH BOND PAD STRUCTURE - This invention discloses an integrated circuit (IC) chip which comprises a first, second and third bonding pad connected exclusively to a first, second and third probing pad, respectively, wherein the first bonding pad, the second probing pad and the third bonding pad are substantially aligned linearly with the second probing pad being placed between the first and third bonding pad. | 01-21-2010 |
20100019398 | STRUCTURED SEMICONDUCTOR ELEMENT FOR REDUCING CHARGING EFFECTS - A semiconductor circuit element for reducing undesirable charging effects for a connection element of test structures for semiconductor circuits is disclosed. A surface of a semiconductor circuit element has interconnect structures that are electrically insulated from the remainder of the surface of the semiconductor circuit element, where exclusively the interconnect structures are connected to semiconductor circuit elements arranged downstream. | 01-28-2010 |
20100044886 | SEMICONDUCTOR DEVICE HAVING PAIRS OF PADS - An integrated-circuit semiconductor device includes external electrical connection pads on one face and electrical connection vias under said pads. The electrical connection vias are arranged with a defined pitch in a defined direction. Each via is respectively associated with one of a plurality of adjacent zones of the face. These zones extend perpendicularly to the pitch direction. The electrical connection pads are grouped in adjacent pairs. An insulation space is located between the pads of each pair of electrical connection pads. In a direction perpendicular to the pitch direction, the pads in the pair are spaced apart. The pads of each pair of electrical connection pads extend over a pair of adjacent zones and are associated with two adjacent vias. | 02-25-2010 |
20100102460 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and its manufacturing method are offered to increase the number of semiconductor devices obtained from a semiconductor wafer while simplifying a manufacturing process. After forming a plurality of pad electrodes in a predetermined region on a top surface of a semiconductor substrate, a supporter is bonded to the top surface of the semiconductor substrate through an adhesive layer. Next, an opening is formed in the semiconductor substrate in a region overlapping the predetermined region. A wiring layer electrically connected with each of the pad electrodes is formed in the opening. After that, a stacked layer structure including the semiconductor substrate and the supporter is cut by dicing along a dicing line that is outside the opening. | 04-29-2010 |
20100140814 | RF DEVICE AND METHOD WITH TRENCH UNDER BOND PAD FEATURE - Electronic elements ( | 06-10-2010 |
20100207281 | Semiconductor Chip with Reinforcement Layer - Various semiconductor chip reinforcement structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a side and forming a polymer layer on the side. The polymer layer has a central portion and a first frame portion spatially separated from the central portion to define a first channel. | 08-19-2010 |
20100213620 | Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package - A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate. | 08-26-2010 |
20100219538 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction. | 09-02-2010 |
20100225009 | INTEGRATED CIRCUIT ASSEMBLIES WITH ALIGNMENT FEATURES AND DEVICES AND METHODS RELATED THERETO - A method of packaging an integrated circuit die including forming a mask window having a first aperture with a first set of alignment edges and forming an alignment feature on an uppermost surface of the integrated circuit die where the alignment feature has a second set of alignment edges. The alignment feature is inserted into the first aperture. The integrated circuit die is mechanically biased until the first and second set of alignment edges are in physical contact with one another and the alignment feature is secured into the mask window, thus forming an integrated circuit die assembly. | 09-09-2010 |
20100237512 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring. | 09-23-2010 |
20100258956 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package. | 10-14-2010 |
20100327467 | Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device - A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. | 12-30-2010 |
20110006442 | SEMICONDUCTOR CHIP, FILM SUBSTRATE, AND RELATED SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip. | 01-13-2011 |
20110006443 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device composed of a plurality of semiconductor integrated circuits and a plurality of coils. During the production process of the semiconductor device, the plurality of coils are so arranged that the coil surfaces are generally perpendicular to the front surface of a chip of the semiconductor integrated circuits wherein metal films are laminated. A signal is transmitted between a pair of adjacent coils among the plurality of coils. | 01-13-2011 |
20110018145 | MICROELECTRONIC SUBSTRATE INCLUDING EMBEDDED COMPONENTS AND SPACER LAYER AND METHOD OF FORMING SAME - A microelectronic substrate, a method of forming the same, and a system including the same. The microelectronic substrate comprises: a conductive layer; a spacer layer disposed onto the conductive dielectric layer; a dielectric build-up layer disposed onto the spacer layer, the spacer layer being made of a material that has a lower shrinkage than a material of the embedding dielectric-build-up layer during curing, and a higher viscosity than a material of the embedding dielectric build-up layer in its pre-cure form and during curing; and active or passive microelectronic components embedded within the dielectric build-up layer. | 01-27-2011 |
20110024921 | CONTACT LAYOUT STRUCTURE - A contact layout structure includes a substrate having at least a first region defined thereon, plural sets of first contact layouts positioned along a predetermined direction in the first region, and a plurality of second contact layouts positioned in the first region. Each set of the first contact layouts further comprises two square contact units and two adjacent rectangle contact units positioned in between the two square contact units. Each of the rectangle contact units comprises two opposite long sides and two opposite short sides, and a length of the long sides is not equal to the a length of the short sides. | 02-03-2011 |
20110042832 | EXTENDABLE CONNECTOR AND NETWORK - Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled from an initial state in which the first and second connected ends are separated by a first proximate distance and applied in an extended state in which the first and second connected ends are separated by a second distance that is greater than the first proximate distance. | 02-24-2011 |
20110042833 | SEMICONDUCTOR DEVICE - A semiconductor device having a wafer level chip size package may include a semiconductor substrate having an integrated circuit formed thereon; a plurality of electrode pads formed on the semiconductor substrate; at least one rewiring layer which may include rewiring formed adjacent to the plurality of electrode pads; and a plurality of external electrodes formed on the rewiring layer. The plurality of electrodes and plurality of external electrodes may be sectioned and arranged in four areas having the same shapes. Each area may include a first group of N number of external electrodes arranged along an edge of the semiconductor substrate, a second group of (N-2) number of external electrodes arranged inside the first group of external electrodes, and a plurality of (2N-2) number of electrode pads arranged between the first and second groups of external electrodes. | 02-24-2011 |
20110062601 | GENERATING AN INTEGRATED CIRCUIT IDENTIFIER - The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier. | 03-17-2011 |
20110068485 | COMPONENT AND METHOD FOR PRODUCING A COMPONENT - A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device. | 03-24-2011 |
20110079928 | SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI-CHIP MODULE - In a semiconductor integrated circuit requiring a large number of pads, an internal circuit is arranged in the center portion, and a plurality of two kinds of I/O circuits for inputting and outputting signals from and to the outside and many pads are arranged along four sides of the semiconductor integrated circuit. The plurality of I/O circuits that are of one of the foregoing two kinds are one-pad I/O circuits on which one pad is arranged in a direction toward the internal circuit, whereas the plurality of I/O circuits that are of the other of the foregoing two kinds are two-pad I/O circuits on which two pads are arranged in zigzag relationship in a direction toward the internal circuit. The number of arranged pads equals to the number of pads required for the semiconductor integrated circuit. The one-pad I/O circuits and the two-pad I/O circuits are provided with power source wirings for supplying power thereto. The power source wirings extend along the arrangement direction of the one-pad I/O circuits and the second-pad I/O circuits to be ring-shaped. power source wiring migration areas for changing power source wirings between the one-pad I/O circuits and second-pad I/O circuits are disposed in four corner portions of the semiconductor integrated circuit. | 04-07-2011 |
20110089579 | MULTI-CHIP MODULE - A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board. | 04-21-2011 |
20110101545 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BOND PAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor substrate; forming a core region on the semiconductor substrate with the core region having a core side; forming an inner bond pad on the semiconductor substrate with the inner bond pad having an inner core pad and an inner probe pad with the inner probe pad further from the core region than the inner core pad; and forming an outer bond pad on the semiconductor substrate and adjacent the inner bond pad with the outer bond pad having an outer core pad and an outer probe pad with the outer probe pad closer to the core region than the outer core pad, and the inner probe pad and the outer probe pad aligned parallel to the core side. | 05-05-2011 |
20110121467 | SEMICONDUCTOR DEVICE METAL PROGRAMMABLE POOLING AND DIES - A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die designs that incorporate a metal programmable base layer. In some embodiments multi-tile dies are provided with I/O slots configurable for either inter tile communication or inter die communication. | 05-26-2011 |
20110127681 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer. | 06-02-2011 |
20110140288 | Systems and Methods Employing a Physically Asymmetric Semiconductor Device Having Symmetrical Electrical Behavior - An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure. | 06-16-2011 |
20110156282 | Gate Conductor Structure - A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized. | 06-30-2011 |
20110180941 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes. | 07-28-2011 |
20110180942 | INTERCONNECTION STRUCTURE - An interconnection structure includes: first and second differential signal interconnections provided to transmit a differential signal; and first and second voltage interconnections applied with predetermined voltages. The first voltage interconnection, the first differential signal interconnection, the second differential signal interconnection and the second voltage interconnection are arranged in this order. An interval between the first and second differential signal interconnections is longer than an interval between the first voltage interconnection and the first differential signal interconnection and is longer than an interval between the second differential signal interconnection and the second voltage interconnection. When a first connection point and a second connection point nearest to the first connection point are provided on any of the first and second differential signal interconnections and the first and second voltage interconnections, a distance between the first connection point and the second connection point is in a range of 1/16 of a wavelength of the differential signal to ⅛ of the wavelength thereof. | 07-28-2011 |
20110187008 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTER DEVICE - A semiconductor device has a semiconductor chip and a first interconnection tape. The semiconductor chip has a plurality of first electrode pads arranged on a first surface. The first interconnection tape is in contact with each of the plurality of first electrode pads such that the plurality of first electrode pads are electrically connected with each other. | 08-04-2011 |
20110198761 | Methods for Multi-Wire Routing and Apparatus Implementing Same - A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels. | 08-18-2011 |
20110221076 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a power semiconductor element that is a semiconductor element; bonding parts provided for bonding of an upper surface and a lower surface of the semiconductor element; and metal plates bonded to the power semiconductor element from above and below through the bonding parts, wherein the bonding part includes a mesh metal body disposed between the semiconductor element and the metal plate, and a bonding member in which the mesh metal body is embedded. | 09-15-2011 |
20110233796 | Semiconductor Devices and Electronic Systems - A semiconductor device and an electronic system are provided. The semiconductor device includes a lower conductive pattern, and an intermediate conductive pattern on the lower conductive pattern. An upper conductive pattern is provided on the intermediate conductive pattern and is electrically connected to the intermediate conductive pattern. The intermediate conductive pattern includes a first portion and a second portion that extends from a part of the first portion and that is disposed at a higher level from the lower conductive pattern than the first portion. The upper conductive pattern is disposed on the first portion of the intermediate conductive pattern and has a top surface that is disposed at a higher level from the lower conductive pattern than the second portion of the intermediate conductive pattern. | 09-29-2011 |
20110241225 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other. | 10-06-2011 |
20110278743 | LAYOUT STRUCTURE AND VERSION CONTROL CIRCUIT FOR INTEGRATED CIRCUITS - The present invention relates to a layout structure and a version control circuit for integrated circuits. The layout structure for integrated circuits according to the present invention comprises a signal-supplying unit and at least a transfer cell. The signal-supplying unit is used for supplying a first signal and a second signal. The transfer cell has a plurality of metal layers interconnected. One of metal layers receives and transfers the first signal or the second signal. When changing the transfer cell to transfer the second signal instead of the first signal, the metal layers interrupt transferring the first signal but receive and output the second signal. When the circuit is revised and multiple sub-circuits as well as the transferred signal are changed, the fewest metal layers commonly adopted are used. Accordingly, the present invention can reduce effectively the number of masks, and thus reducing costs. | 11-17-2011 |
20110285034 | ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES - Conductive lines are formed on a wafer containing multiple circuits. The conductive lines are isolated from the circuits formed within the wafer. Chips are mounted on the wafer and have their chip pads connected to the conductive lines of the wafer. The wafer may then be protected with a packaging resin and singulated | 11-24-2011 |
20110304060 | METAL THIN FILM CONNECTION STRUCTURE, MANUFACTURING METHOD THEREOF AND ARRAY SUBSTRATE - Embodiments of the invention relates to a metal thin film connection structure, comprising a first metal layer pattern; a second metal layer pattern which is separately disposed with the first metal layer pattern; a first insulating layer formed on the first metal layer pattern and the second metal layer pattern; a plurality of first via holes formed over the first metal layer pattern; a plurality of second via holes formed over the second metal layer pattern; and a plurality of third metal layer patterns formed on the first insulating layer, the third metal layer patterns being filled in the first via holes and the second via holes and electrically connect the first metal layer pattern and the second metal layer pattern through the first and second via holes. The embodiments of the invention also provide an array substrate comprising the metal thin film connection structure and a manufacturing method for the metal thin film connection structure. | 12-15-2011 |
20110304061 | SEMICONDUCTOR DEVICE - A semiconductor device in which it is possible to suppress short-circuiting between pads for chip arising from dicing processing is provided. The semiconductor device includes a semiconductor substrate, multiple first pads, and multiple second pads. The first pads are formed in an element formation region and the second pads are formed in a dicing line region surrounding the element formation region. The dicing line region includes a first region for which second pads are prone to electrically short-circuit to each other and a second region for which second pads are less prone to electrically short-circuit to each other. Some first pads arranged in positions opposite the first region are arranged farther away from one side of the outer edge of the element formation region than the remaining first pads arranged in positions opposite the second region are. | 12-15-2011 |
20110316174 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device, arrangement relationship of power source area I/O pads differs between a peripheral portion and a center portion of a gate region of a chip. That is, in two columns and two rows of the peripheral portion of the gate region, VDD area I/O pads connected to a high-voltage power source VDD and GND area I/O pads connected to a ground power source GND are alternately aligned and arranged both in a row direction and in a column direction. Moreover, in the center portion of the gate region, the same VDD area I/O pads or the same GND area I/O pads are successively aligned in the row direction, and the VDD area I/O pads and the GND area I/O pads are alternately aligned and arranged in the column direction. | 12-29-2011 |
20120025402 | METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A UNIFORM PATTERN OF CONDUCTIVE LINES - Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In one embodiment, a portion of the conductive material is removed from at least one location in each loop of the plurality of loops. Contacts are formed to the conductive material. A semiconductor device structure is also disclosed. | 02-02-2012 |
20120025403 | DESIGN APPARATUS OF SEMICONDUCTOR DEVICE, DESIGN METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A design method of a semiconductor device includes four steps. The first step is of arranging grid wiring which includes a plurality of wiring lines arranged in parallel to each other and a plurality of vias connecting the plurality of wiring lines with each other. The second step is of arranging a plurality of internal circuits connected to the grid wiring. The third step is of calculating a current density of a current flowing in the grid wiring by the plurality of internal circuits. The fourth step is of dividing each of the plurality of wiring lines into portions each having a wiring length such that electromigration corresponding to the current density is suppressed. | 02-02-2012 |
20120043673 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate. | 02-23-2012 |
20120086134 | Method of Forming Patterns of Semiconductor Device - A method of forming patterns of a semiconductor device comprises forming a number of first insulating patterns that define sidewalls by patterning a first insulating layer formed over a semiconductor substrate, forming second insulating patterns, each second insulating pattern comprising a horizontal portion having two ends and being parallel to the semiconductor substrate and spaced protruding portions protruding from both ends of the horizontal portion parallel to the sidewalls of the first insulating patterns, forming third insulating patterns each filling a space between the protruding portions, removing the protruding portions to form trenches, and forming conductive patterns within the respective trenches. | 04-12-2012 |
20120104632 | PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AN ANALOG BLOCK AND A DIGITAL BLOCK, AND CORRESPONDING INTEGRATED CIRCUIT - The integrated circuit comprises an analog block and a digital block in and/or on the same substrate. At least part of a first integrated-circuit portion (BA | 05-03-2012 |
20120104633 | ELECTRONIC DEVICE AND ELECTRONIC APPARATUS - An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion. | 05-03-2012 |
20120104634 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHODS THEREOF - A chip package structure includes a chip module, a plurality of pre-patterned structures, a filling material layer, and a redistribution layer. The chip module includes a chip including an upper surface, a side surface, and an active surface. The pre-patterned structures are disposed around the chip. Each of the pre-patterned structures includes a circuit, a first surface, an upper surface opposite the first surface, and a side surface. The filling material layer encapsulates the chip and the pre-patterned structures. The filling material layer includes a second surface, and encapsulates the upper and side surfaces of the chip, and the upper and side surfaces of each of the pre-patterned structures. The active surface, each first surface, and the second surface are substantially co-planar. The redistribution layer is disposed on the active surface, each first surface, and the second surface. The redistribution layer electrically connects the chip and each circuit. | 05-03-2012 |
20120119393 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLEXIBLE SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a foldable segment, a base segment, and a stack segment; connecting a base substrate connector directly on the base segment; connecting a stack substrate connector directly on the stack segment; mounting a base integrated circuit over the base segment with the base substrate connector outside a perimeter of the base integrated circuit; and folding the package substrate with the stack segment over the base segment and the stack substrate connector directly on the base substrate connector. | 05-17-2012 |
20120133058 | SEMICONDUCTOR DEVICE - The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps. | 05-31-2012 |
20120153511 | HARDMASK COMPOSITION AND METHOD OF FORMING PATTERNS AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE PATTERNS - A hard mask composition includes a solvent and an aromatic ring-containing compound represented by the following Chemical Formula 1: | 06-21-2012 |
20120161337 | WIRING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR-CIRCUIT WIRING APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT - A wiring method for a semiconductor integrated circuit has the steps of, separately from a first layer on which a first signal wiring pattern is mainly formed, laying out a first power-supply wiring pattern on a second layer so that a plurality of rows of the first power-supply wiring pattern are regularly arranged with vacant areas each interposed between the rows and making narrower a width of each vacant area than a narrowest width of a row among the rows of the first power-supply wiring pattern, laying out a second signal wiring pattern electrically conductive to the first layer in two or more rows of the vacant areas on the second layer so that the second signal wiring pattern is not in contact with adjacent rows of the first power-supply wiring pattern on both sides, and laying out a second power-supply wiring pattern further in at least a portion of a pattern-layout allowable area remaining in the vacant areas. | 06-28-2012 |
20120175788 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The heat dissipation capability of a mounted semiconductor element can be improved, and the flexibility of circuit design of the semiconductor element and a circuit board and the productivity of the semiconductor element during a mounting step can be improved. A semiconductor element | 07-12-2012 |
20120256324 | Method for Improving Performance of Etch Stop Layer - A method of forming an interconnect structure includes providing a dielectric layer; forming a metal line in the dielectric layer; and forming a composite etch stop layer (ESL), which includes forming a lower ESL over the metal line and the dielectric layer; and forming an upper ESL over the lower ESL. The upper ESL and the lower ESL have different compositions. The step of forming the lower ESL and the step of forming the upper ESL are in-situ performed. | 10-11-2012 |
20120313265 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed. | 12-13-2012 |
20120326338 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device is provided which includes a substrate in which conductor layers and insulated layers are stacked alternately, a semiconductor element mounted on a first surface side of the substrate, and a reinforcing plate attached to a second surface side that is an opposite side of the first surface of the substrate. | 12-27-2012 |
20130001806 | FABRICATION PROCESS AND DEVICE OF MULTI-CHIP PACKAGE HAVING SPLICED SUBSTRATES - Disclosed are a fabrication process and a device of a multi-chip package having spliced substrates, characterized in utilizing an incomplete substrate and a substrate block with different dimensions to combine as a spliced complete substrate during the fabrication process. Two kinds of chips with different functions, including memory and controller, are disposed on the incomplete substrate and the substrate block, respectively. Then, the incomplete substrate and the substrate block are then spliced together by joining their spliced portions formed on their substrate sidewalls. Finally, an encapsulant is formed on the incomplete substrate and further formed on the substrate block. Accordingly, it is possible to integrate different functional chips into a single multi-chip package by optimizing packaging processing parameters with optimized materials. | 01-03-2013 |
20130015592 | BOND PAD CONFIGURATIONS FOR SEMICONDUCTOR DIES - A semiconductor device is provided and includes a semiconductor die, and a plurality of bond pads having exposed surfaces arranged in an alternating interleaved pattern on the semiconductor die. Each of the surfaces of the bond pads have a first bond placement area that overlaps with a second bond placement area, with the first bond placement area having a major axis that is orthogonal to a major axis of the second bond placement area. A connecting bond is located at an intersection of the major axes of the first bond placement area and the second bond placement area on one or more of the bond pads. | 01-17-2013 |
20130026659 | MICROELECTRONIC COMPONENT - A method for producing a MEMS component including the steps of simultaneously embedding structure elements during producing the multi-level conductive path layer stack which structure elements are to be subsequently exposed, subsequently producing a recess that extends from a substrate backside to the multi-level conductive path layer stack, exposing the micromechanical structure elements in the multi-level conductive path layer stack through the recess. In order to increase process precision a reference mask for defining a lateral position or a lateral extension of the micromechanical structure elements to be exposed is produced, wherein the reference mask is either arranged on the substrate front side between the substrate and the multi-level conductive path layer stack or in a layer of the multi-level conductive path layer stack which layer is more proximal to the substrate than the structure element to be exposed. | 01-31-2013 |
20130043603 | METHOD OF FORMING A CONDUCTIVE IMAGE ON A NON-CONDUCTIVE SURFACE - The present invention relates to a method for forming a raised conductive image on a non-conductive or dielectric surface, the method comprising placing a metal coordination complex on a surface of the substrate, exposing the surface to electromagnetic radiation, reducing the exposed complex. removing unexposed complex leaving an elemental metal image, removing unexposed metal complex and then plating the resulting elemental metal image with a highly conductive material. | 02-21-2013 |
20130043604 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first insulating layer provided in a first area and in a second area, a line-and-space-like second insulating layer formed on the first insulating layer provided in the first area, and a third insulating layer formed on the first insulating layer provided in the second area and which is substantially identical to the second insulating layer in height. | 02-21-2013 |
20130087932 | INTEGRATED CIRCUITS AND METHODS OF DESIGNING THE SAME - A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell. | 04-11-2013 |
20130105996 | LOW ENERGY ETCH PROCESS FOR NITROGEN-CONTAINING DIELECTRIC LAYER | 05-02-2013 |
20130154127 | Microspring Structures Adapted for Target Device Cooling - In a system for providing temporary or permanent connection of an integrated circuit die to a base substrate using electrical microsprings, a thermal element is provided that assists with cooling of the pad structure during use. The thermal element may be formed of the same material and my similar processes as the microsprings. The thermal element may be one or more block structures or one or more thermal microsprings. The thermal element may be provided with channels to contain and/or direct the flow of a thermal transfer fluid. Cooling of components associated with the pad structure (e.g., ICs) may be provided. | 06-20-2013 |
20130154128 | Automatic Place and Route Method for Electromigration Tolerant Power Distribution - The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (J | 06-20-2013 |
20130161839 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the same are provided. The device includes first and second line pattern units configured to extend substantially parallel to one another in a first direction and alternately disposed such that end portions of the first and second line pattern units are arranged in a diagonal direction, third and fourth pattern units configured to respectively extend from the end portions of the first and second line pattern units in a second direction crossing the first direction, first contact pad units respectively formed in the third line pattern units disposed a first distance from the end portions of the first line pattern units, and fourth contact pad units respectively formed in the fourth line pattern units disposed a second distance from the end portions of the second line pattern units. Here, the second distance is different from the first distance. | 06-27-2013 |
20130161840 | STRIPPER SOLUTIONS EFFECTIVE FOR BACK-END-OF-LINE OPERATIONS - Back end of line (BEOL) stripping solutions which can be used in a stripping process that replaces etching resist ashing process are provided. The stripping solutions are useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits with good efficiency and with low and acceptable metal etch rates. Methods for their use are similarly provided. The preferred stripping agents contain a polar aprotic solvent, water, an amine and a quaternary hydroxide that is not tetramethylammonium hydroxide. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods. | 06-27-2013 |
20130187294 | SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 07-25-2013 |
20130193591 | Power Semiconductor Module with Pressed Baseplate and Method for Producing a Power Semiconductor Module with Pressed Baseplate - A power semiconductor module includes a baseplate having a top side, an underside, and a depression formed in the baseplate. The depression extends into the baseplate proceeding from the top side. A thickness of the baseplate is locally reduced in a region of the depression. The power semiconductor module further includes a circuit carrier arranged above the depression on the top side of the baseplate such that the depression is interposed between the circuit carrier and the underside of the baseplate. | 08-01-2013 |
20130214433 | Efficient Non-Integral Multi-Height Standard Cell Placement - An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library. | 08-22-2013 |
20130228938 | HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM - A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias. | 09-05-2013 |
20130228939 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 09-05-2013 |
20130241085 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate configured to include a plurality of active regions that are stretched in parallel to each other, a plurality of first contact plugs and the plurality of active regions, wherein each active region is coupled with a corresponding first contact plug, and a contact pad configured to couple with a given number of first contact plugs among the plurality of first contact plugs. Misalignment occurring at the ends of a series of drain contacts may be prevented, and the size of well-pickup contacts may be decreased by forming contact plugs that are coupled with drain regions with the same distance to a well-pickup contact region without additionally forming well-pickup contact plugs and using the contact plugs as well-pickup contact plugs. Therefore, loss of a substrate may be minimized, and burden of Optical Proximity Correction (OPC) is relieved, reducing Turn-Around Time (TAT). | 09-19-2013 |
20130256921 | Deformable Network Structure - Disclosed herein is a deformable network structure, which includes a first device portion, a second device portion and at least one connector interconnecting between the first device portion and the second device portion. Moreover, the second device portion can be electrically connected to the first device portion through one of the connectors. The first and second device portions respectively have a first and a second center. Each of the connectors may be deformable from an initial state to a final state, such that a first distance between the first and second centers in the final state varies by at least 10% of a second distance between the first and second centers in the initial state. | 10-03-2013 |
20130277866 | Methods for Multi-Wire Routing and Apparatus Implementing Same - A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels. | 10-24-2013 |
20130307166 | METHOD FOR FORMING PATTERNS OF DENSE CONDUCTOR LINES AND THEIR CONTACT PADS, AND MEMORY ARRAY HAVING DENSE CONDUCTOR LINES AND CONTACT PADS - A method for forming patterns of dense conductor lines and their contact pads is described. Parallel base line patterns are formed over a substrate. Each of the base line patterns is trimmed. Derivative line patterns and derivative transverse patterns are formed as spaces on the sidewalls of the trimmed base line patterns, wherein the derivative transverse patterns are formed between the ends of the derivative line patterns and adjacent to the ends of the trimmed base line patterns. The trimmed base line patterns are removed. At least end portions of the derivative line patterns are removed, such that the derivative line patterns are separated from each other and all or portions of the derivative transverse patterns become patterns of contact pads each connected with a derivative line pattern. | 11-21-2013 |
20140054801 | ELECTRONIC DEVICE - An electronic device includes a core circuit and multiple pad units. The core circuit includes multiple core MOS and the multiple pad units are respectively electrically connected to the core circuit. Each pad unit includes at least one pad MOS. A core gate in each core MOS and a pad gate in each pad MOS extend along the same direction or extend parallel with each other. | 02-27-2014 |
20140103545 | SEMICONDUCTOR STRUCTURE AND METHOD OF GENERATING MASKS FOR MAKING INTEGRATED CIRCUIT - A method of generating masks for making an integrated circuit includes determining if a coupling capacitance value of a conductive path of a first and second groups of conductive paths of the integrated circuit is greater than a predetermined threshold value. The determination is performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment. The layout patterns are modified to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value. | 04-17-2014 |
20140131900 | MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL - A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer | 05-15-2014 |
20140167293 | INTEGRATED CIRCUIT WITH BUMP CONNECTION SCHEME - An integrated circuit includes first and second bump pads spaced from each other with a first space, configured to receive differential signals for a normal operation, and at least one redundant bump pad spaced from the first bump pad with a second space smaller than the first space, configured to receive a signal for a repair to the differential signals. | 06-19-2014 |
20140175680 | ELECTRICAL CHARACTERISTICS OF PACKAGE SUBSTRATES AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME - Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided. | 06-26-2014 |
20140246791 | 14 LPM CONTACT POWER RAIL - A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active layer of a semiconductor substrate using a first color mask; forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail, wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches. | 09-04-2014 |
20140252659 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad. | 09-11-2014 |
20140264953 | WIRING STRUCTURES, METHODS OF MANUFACTURING THE SAME, AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING THE SAME - A method of manufacturing a wiring structure may include forming a first conductive pattern on a substrate, forming a hardmask on the first conductive pattern, forming a first spacer on sidewalls of the first conductive pattern and the hardmask, forming a first sacrificial layer pattern on a sidewall of the first spacer, forming a second spacer on a sidewall of the first sacrificial layer pattern, removing the first sacrificial layer pattern, and forming a third spacer on the second spacer, may be provided. The third spacer may contact an upper portion of the sidewall of the first spacer and define an air gap in association with the first and second spacers. The first spacer has a top surface substantially higher than a top surface of the first conductive pattern. The second spacer has a top surface substantially lower than the top surface of the first spacer. | 09-18-2014 |
20140339712 | SEMICONDUCTOR DEVICE COMPRISING MOLD FOR TOP SIDE AND SIDEWALL PROTECTION - Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer. | 11-20-2014 |
20140374926 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having an electrode, a connector having a chip contact surface, an interconnecting portion, and an external electrode terminal contact surface, the chip contact surface being electrically connected to the electrode, and a first connection material disposed between the chip contact surface and the electrode, the first connecting material having a surface area that is greater than a surface area of the chip contact surface. | 12-25-2014 |
20150054179 | ARC RESIDUE-FREE ETCHING - Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer. | 02-26-2015 |
20150076715 | SEMICONDUCTOR DEVICE - Provided is a downsized semiconductor device having high reliability. A plurality of recessed portions ( | 03-19-2015 |
20150084212 | CLOCK SKEW ADJUSTING METHOD AND STRUCTURE - A clock transmission adjusting method applied to integrated circuit design is provided. The clock transmission adjusting method includes the following steps. At first, a timing path including a clock source and a sequential logic cell is provided. Then, at least one non-active wire delay module is inserted in the timing path to approach a predetermined clock arrival time. An integrated circuit structure utilizing the clock transmission adjusting method is also provided. | 03-26-2015 |
20150348772 | Metallization Of The Wafer Edge For Optimized Electroplating Performance On Resistive Substrates - A method for electroplating a substrate is provided, including: providing a substrate having a conductive layer disposed on a top surface of the substrate, the top surface of the substrate having an edge exclusion region and a process region; directing a flow of an electroless deposition solution toward the edge exclusion region while the substrate is rotated, to plate metallic material over the conductive layer at the edge exclusion region; continuing the flow of the electroless deposition solution for a period of time to produce an increased thickness of the metallic material at the edge exclusion region, wherein the increased thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; applying electrical contacts over the metallic material, and applying electrical current to the metallic material via the electrical contacts while an electroplating solution is applied over the process region of the substrate. | 12-03-2015 |
20160035715 | SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM - A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other. | 02-04-2016 |
20160111328 | MULTILEVEL MASK CIRCUIT FABRICATION AND MULTILAYER CIRCUIT - Circuit fabrication uses a multilevel mask to pattern a first conductor layer of a multilayer circuit. The first conductor patterning is to provide electrical isolation between the first conductor layer and a second conductor layer that one of overlies the multilevel mask and underlies the multilevel mask. With the second conductor layer overlying the multilevel mask, the electrical isolation is provided by undercutting the multilevel mask. Alternatively, with the second conductor underlying the multilevel mask, the first conductor includes a bridged gapped conductor and the electrical isolation may be provided by both the bridged gapped conductor and an insulating layer between the second conductor layer and the first conductor layer. | 04-21-2016 |
20160172300 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | 06-16-2016 |
20190148297 | SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME | 05-16-2019 |