Entries |
Document | Title | Date |
20080197511 | Bonding pad structure, electronic device having a bonding pad structure and methods of fabricating the same - An electronic device having a bonding pad structure and a method of fabricating the same is provided. The electronic device may include a first bonding pads formed on the substrate. A second bonding pad may be formed on the lower insulating layer. The second bonding pads may be spaced apart from the first bonding pads. The second bonding pads may have a top surface formed at a higher level than the first bonding pads. | 08-21-2008 |
20080211113 | WAFER LEVEL PACKAGING - Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die. | 09-04-2008 |
20080224327 | Microelectronic substrate including bumping sites with nanostructures - A microelectronic substrate and a package including the substrate. The substrate comprises: a wafer; circuitry disposed within the wafer and including a plurality of bonding pads; and a plurality of bumping sites disposed on respective ones of the bonding pads, each of the bumping sites comprising a nanolayer including columnar nanostructures. | 09-18-2008 |
20080224328 | TEMPORARY CHIP ATTACH USING INJECTION MOLDED SOLDER - An improved method for performing an improved Temporary Chip Attach utilizing an Injection Molded Solder (IMS) process to allow efficient testing of die for creating a Known Good Die Bank. The IMS is applied to the testing substrate to form a column on the substrate. The die to be tested can then be attached to the IMS column with C4 solder. A slight reflow is then applied to the die, allowing some of the C4 to melt, and form an electrical connection with the corresponding IMS column. After testing, the die can be removed along with the C4 from the IMS column or permanently attached the substrate by performing a full reflow of the C4. | 09-18-2008 |
20080230927 | Fully tested wafers having bond pads undamaged by probing and applications thereof - Methods and apparatus for producing fully tested unsingulated integrated circuits without probe scrub damage to bond pads includes forming a wafer/wafer translator pair removably attached to each other wherein the wafer translator includes contact structures formed from a soft crushable electrically conductive material and these contact structures are brought into contact with the bond pads in the presence of an inert gas; and subsequently a vacuum is drawn between the wafer and the wafer translator. In one aspect of the present invention, the unsingulated integrated circuits are exercised by a plurality of test systems wherein the bond pads are never physically touched by the test system and electrical access to the wafer is only provided through the inquiry-side of the wafer translator. In a further aspect of the present invention, known good die having bond pads without probe scrub marks are provided for incorporation into products. | 09-25-2008 |
20080246164 | Soldering Method, Solder Pellet for Die Bonding, Method for Manufacturing a Solder Pellet for Die Bonding, and Electronic Component - A pellet for use in die bonding of an electronic chip and a substrate in an electronic component generates minimized voids in spite of the pellet being made of a lead-free solder. The pellet forms a colorless transparent protective film comprising Sn-(30-50 at % 0)-(5-15 at % P) or Sn-(10-30 at % In)-(40-60 at % O)-(5-15 at % P) when heated for soldering, has a thickness of 0.05-1 mm, and has generally the same shape as the semiconductor chip to be bonded to the substrate. | 10-09-2008 |
20080251946 | Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus - A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin. | 10-16-2008 |
20080265439 | Die bonding agent and a semiconductor device made by using the same - A die bonding agent comprising (A) an epoxy resin, (B) a curing agent, and (C) an inorganic filler, the die bonding agent having a viscosity ratio, V | 10-30-2008 |
20080272500 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention has a semiconductor chip provided with an insulating layer formed so as to be thinner in a first secondary-wire-free area than in a first secondary-wire-containing area. Further, the semiconductor chip has an edge extending further outward than a side wall, which severs as an edge of an upper insulating layer, in an extending direction of a circuit-forming surface of the semiconductor chip on which electrode pads are provided. This makes it possible to provide a semiconductor device capable of suppressing electromagnetic interference between a secondary wire and an electronic circuit of a semiconductor chip and the curvature of a wafer even in the case of overlap between the secondary wire and the electronic circuit, and of reducing the risk of occurrence of chipping in a dicing step. | 11-06-2008 |
20080272501 | SEMICONDUCTOR PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package. | 11-06-2008 |
20080296781 | REDUCED-DIMENSION MICROELECTRONIC COMPONENT ASSEMBLIES WITH WIRE BONDS AND METHODS OF MAKING SAME - The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component mounted to a substrate. The substrate carries a plurality of bond pads at a location substantially coplanar with a terminal surface of the microelectronic component. This enables a smaller package to be produced by moving the bond pads laterally inwardly toward the periphery of the microelectronic component. | 12-04-2008 |
20080308952 | Method for Reliably Positioning Solder on a Die Pad for Attaching a Semiconductor Chip to the Die Pad and Molding Die for Solder Dispensing Apparatus - The rotational orientation of a die pad about its longitudinal axis is determined. The desired rotational orientation of a semiconductor chip to be attached to the die pad is determined. A molding die is provided which comprises a body with a cavity disposed in a bottom surface. The rotational orientation of the body of the molding die about its longitudinal axis is determined. The cavity is positioned in the body of the molding die with a rotational orientation such that the cavity is rotated with respect to the molding die by an angle corresponding to the desired rotational orientation of the semiconductor chip with respect to the die pad. | 12-18-2008 |
20080315438 | SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER - An integrated circuit includes a first surface configured for mounting to a carrier, an active area of the integrated circuit spaced from the first surface, a bond pad disposed over and in electrical communication with the active area, and a ceramic inorganic stress-buffering layer disposed between the active area and the bond pad. | 12-25-2008 |
20090001609 | Semiconductor Device and Method of Assembly - An encapsulated leadless semiconductor package comprises a first semiconductor die and a second semiconductor die which are electrically connected by a bond wire. The lower surface of the first semiconductor die and the lower surface of the second semiconductor die are essentially coplanar with the lower surface of the encapsulation material. | 01-01-2009 |
20090008801 | Semiconductor device and method for fabricating the same - This invention discloses a semiconductor device and a method for fabricating the same. The method includes providing a flexible carrier board having a first surface and a second surface opposite thereto; forming a metal lead layer and a first heat dissipating metal layer on the first surface of the flexible carrier board, and forming a second heat dissipating metal layer on the second surface of the flexible carrier board; providing a chip having an active surface and an opposed non-active surface, wherein a plurality of solder pads are formed on the active surface of the chip, each of the solder pads has a metal bump formed thereon and corresponding in position to the metal lead layer, and heat dissipating bumps are formed between the metal bumps corresponding in position to the first heat dissipating metal layer. | 01-08-2009 |
20090026635 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device comprises: a step of forming an inter-layer insulating film on a semiconductor substrate; a step of forming a first metal film on the inter-layer insulating film; a step of forming a first resist on the first metal film and patterning the first resist; a step of performing anisotropic etching on the first metal film using the first resist as a mask; a step of removing the first resist; a step of forming a second metal film on the inter-layer insulating film so as to cover the remaining first metal film; a step of forming a second resist on the second metal film in an area where the first metal film exists on the inter-layer insulating film and part of an area where the first metal film does not exist; a step of performing anisotropic etching on the second metal film using the second resist as a mask and forming a bonding pad having the first metal film and the second metal film and an upper layer wiring which has the second metal film, yet not the first metal film; a step of removing the second resist; a step of forming a surface protection film so as to cover the bonding pad; and a step of forming a pad opening in the surface protection film on the bonding pad. | 01-29-2009 |
20090026636 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark. | 01-29-2009 |
20090051049 | Semiconductor device, substrate and semiconductor device manufacturing method - The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane. | 02-26-2009 |
20090108472 | WAFER-LEVEL UNDERFILL PROCESS USING OVER-BUMP-APPLIED RESIN - A process of fabricating wafer-level underfilled microelectronic packages using over-bump application of a self-fluxing resin to a wafer, b-staging of the resin, dicing of the coated wafer, and joining the diced chips to substrates producing wafer-level underfilled microelectronic flip-chip packages. Moreover, provided are microelectronic packages, which are produced in accordance with the inventive process. | 04-30-2009 |
20090121362 | SEMICONDUCTOR PACKAGE AND MOUNTING METHOD THEREOF - A semiconductor package and mounting method of improving reliability by strengthening adhesive strength of both a printed circuit board and a surface mounting package, includes a chip pad on which a semiconductor device is disposed, and lead terminals, wherein at least one of the chip pad and the lead terminals have a plurality of grooves. Accordingly, in comparison with a typical package, since a plurality of grooves are formed on both a chip pad and lead terminals of a package adhering to a printed circuit, an adhesive area of both the package and the cream solder is widened so that the shearing strength may be improved and greater solder joint reliability can be acquired. | 05-14-2009 |
20090127719 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE SUBSTRATE HAVING CORNER CONTACTS - A integrated circuit package system includes: forming a package substrate with a top substrate side and a bottom substrate side; forming a corner contact in a first corner of the bottom substrate side, the corner contact extending to a substrate edge of the package substrate; mounting an integrated circuit device over the top substrate side; connecting an electrical interconnect between the integrated circuit device and the top substrate side; and forming a package encapsulation over the top substrate side, the integrated circuit device, and the electrical interconnect. | 05-21-2009 |
20090146319 | SEMICONDUCTOR DEVICE - A semiconductor device which can prevent damage to an ESD protection device by pressure when bonding is carried out, while having a pad configuration that can ensure bonding reliability, with the semiconductor device being made as small as possible. A bonding area that is an area for wire bonding with respect to an external electrode pad and a probing area that is an area in which a probe needle is applied when probing, are provided, and the ESD protection device and a discharge path therefor are arranged below the probing area. Arranged below the bonding area are a support via that is a little smaller than the bonding pad, and a support pattern having a size corresponding to the bonding pad and joined to the bonding pad by the support via. | 06-11-2009 |
20090152743 | ROUTING LAYER FOR A MICROELECTRONIC DEVICE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF FORMING A MULTI-THICKNESS CONDUCTOR IN SAME FOR A MICROELECTRONIC DEVICE - A routing layer for a microelectronic device includes a first region ( | 06-18-2009 |
20090166891 | Cutting and molding in small windows to fabricate semiconductor packages - A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate strip has a plurality of small windows disposed at the sides or at the corners of the substrate strip. The external surface of the substrate strip includes a plurality of window molding areas surrounding the small windows and extending to the scribe lines. A plurality of chips are disposed on the substrate strip. Then, an encapsulant is formed in the small windows to encapsulate the electrical connecting components and formed on the window molding areas so that the encapsulant extends to the scribe lines. Therefore, the mold flashes at the small windows can be effectively reduced. Additionally, the encapsulnat on the window molding areas is cut when singulating the substrate units so that the adhesion area of the encapsulant to the substrate strip is increased to prevent the delamination of traces and solder mask of the substrate units. | 07-02-2009 |
20090179334 | APPARATUS FOR FACILITATING PROXIMITY COMMUNICATION BETWEEN CHIPS - One embodiment of the present invention provides a system for facilitating proximity communication between semiconductor chips. The system includes a base chip and a bridge chip, each of which includes an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip. Then, an identified portion of the active face of the bridge chip is thinned via etching and is removed by planarizing the back face of the bridge chip, thereby creating an opening in the bridge chip that exposes a portion of the active face of the base chip. | 07-16-2009 |
20090189298 | Bonding pad structure and debug method thereof - The bonding pad structure includes a main bonding pad and a blank path. The blank path crosses through the main bonding pad for dividing the main bonding pad into a first sub-bonding pad and a second sub-bonding pad. The bonding pad structure may further include a solder covered on the blank path and the main bonding pad selectively. The main bonding pad is regarded as a closed circuit when the solder is covered on the blank path and the main bonding pad. The main bonding pad is regarded as a open circuit when the solder is not covered on the blank path and the main bonding pad. A debug method with the bonding pad structure is also disclosed. | 07-30-2009 |
20090189299 | METHOD OF FORMING A PROBE PAD LAYOUT/DESIGN, AND RELATED DEVICE - A method of forming a probe pad layout/design, and related device. At least some of the illustrative embodiments are methods comprising testing a semiconductor device by electrically contacting a first portion of a semiconductor die by way of a first pad within a scribe street adjacent to the semiconductor die, and electrically contacting a second portion of the semiconductor die by way of a first bond pad within the semiconductor die. | 07-30-2009 |
20090200685 | Electronic packaging method and apparatus - The present invention utilizes a panel substrate as the packaging substrate carried by a working susceptor. Packaging devices are hung in the nearby of the working susceptor and moved by robot arms to the working susceptor, whereby the problems of substrate warpage and substrate transportation are overcome. Further, identical or different packaging steps can be simultaneously performed in different areas of a panel substrate, whereby the cost is reduced and the product yield is promoted. | 08-13-2009 |
20090206493 | Flip Chip Interconnection Pad Layout - A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint. | 08-20-2009 |
20090309240 | RETURN LOSS TECHNIQUES IN WIREBOND PACKAGES FOR HIGH-SPEED DATA COMMUNICATIONS - A wirebond package configured to reduce wirebond return loss is presented. An integrated circuit of interest with rows of bonding pads is bonded to a surface of the wirebond package. The surface of wirebond package has columns of bonding pads, which are configured to transmit or receive signals, power, and ground to and/or from the wirebond package to the integrated circuit. Corresponding die pads on the integrated circuit and bonding pads of the wirebond package are coupled using conductive lines. The conductive lines carrying the active signal has coplanar adjacent ground lines on opposing sides of active signal line and the distance between active signal line and the coplanar adjacent ground lines is tapered. | 12-17-2009 |
20100001412 | BOND PAD STRUCTURE - A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a first via plug formed in the first dielectric layer, and an electrically floating first conductive plate situated under the conductive pad. | 01-07-2010 |
20100019395 | METHOD AND APPARATUS FOR IMPROVEMENTS IN CHIP MANUFACTURE AND DESIGN - A method of securing a bond pad in to a semiconductor chip having an upper top metal surface which includes one or more holes, the method comprising the steps of forming a passivation layer over the upper metal surface, which passivation layer has holes therein substantially corresponding to the or each hole in the upper metal layer and being substantially the same size or smaller than the holes in the upper metal layer; forming the bond pad over the passivation layer; characterised in that the step of forming the bond pad comprises introducing some of the material from the bond pad into the holes in the passivation layer and upper metal layer when forming the bond pad, securing the bond pad to the passivation layer by allowing said material to flow under the surface thereof and attach thereto without attaching to the upper metal layer to thereby form a securing means. | 01-28-2010 |
20100084772 | Package and fabricating method thereof - A package and a fabricating method thereof are provided. The package includes a conductive layer, a chip, a plurality of first pads, a plurality of bonding wires and a sealant. The conductive layer has a die pad and includes a plurality of wires. A path of each wire is substantially parallel to a supporting surface of the die pad. Each wire has an upper surface and a lower surface. The chip disposed on the supporting surface has a plurality of pads. The first pads are correspondingly formed on the upper surfaces of the wires. The bonding wires electrically connect the pads of the chip to the first pads. The sealant seals up the conductive layer, the first pads, the chip and the bonding wires, and exposes the lower surface of the conductive layer. The conductive layer projects from a bottom surface of the sealant. | 04-08-2010 |
20100090353 | PAD STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS - A pad structure of a semiconductor integrated circuit apparatus includes a semiconductor substrate upon which circuit patterns forming a device are disposed, a pad disposed on an uppermost part of the semiconductor substrate, and a plurality of fixing parts, each disposed along opposing edge portions of the pad to fix the pad and the semiconductor substrate to each other. | 04-15-2010 |
20100133705 | APPARATUS AND METHOD FOR REDUCING PITCH IN AN INTEGRATED CIRCUIT - An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first and a second contact pad formed thereon, a first dielectric layer coupled to the electronic chip, a second dielectric layer coupled to the first dielectric layer such that a dielectric boundary lies therebetween, a first and a second cover pad positioned along the dielectric boundary, a metal interconnect formed along a first multi-layer via and coupled to the first cover pad and contact pad, and a metal interconnect formed along a second multi-layer via and coupled to the second cover pad and contact pad. The first multi-layer via extends through the second dielectric layer, the first cover pad, and the first dielectric layer to the first contact pad. The second multi-layer via extends through the second dielectric layer, the second cover pad, and the first dielectric layer to the second contact pad. | 06-03-2010 |
20100140813 | INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent. | 06-10-2010 |
20100237509 | IO CELL WITH MULTIPLE IO PORTS AND RELATED TECHNIQUES FOR LAYOUT AREA SAVING - An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plural predetermined regions of the plural IO ports partially overlaps with active circuit layout region of the IO cell. In a chip, if a given IO cell has a predetermined region of an IO port overlapping an IO pad location of another adjacent IO cell, then a predetermined region of another IO port is selected for implementing an IO pad of the given IO cell, such that the IO cells can be arranged more compactly for chip layout area saving. | 09-23-2010 |
20100258953 | SUBSTRATE AND SEMICONDUCTOR DEVICE - A substrate has a plurality of pads formed over one surface of a base, and an insulating film which is formed thereon and has a plurality of openings formed therein so as to expose each of the pads, wherein the openings of the insulating film are formed so that, in each pad formed at the corner of the base, among the plurality of pads, a first peripheral portion which composes a portion of the pad more closer to the corner and more distant away from the center of the base is covered by the insulating film, and so that a second peripheral portion which composes a portion of the pad more closer to the center as compared with the first peripheral portion is exposed in the opening. | 10-14-2010 |
20100276816 | SEPARATE PROBE AND BOND REGIONS OF AN INTEGRATED CIRCUIT - Disclosed are a system and method of separate probe and bond regions of an integrated circuit (IC). An IC, an I/O region adjacent to the core region to enable the core region, and a die metal interconnect separating a bond pad area in the I/O region from a probe pad area outside the I/O region of the IC are disclosed. The die metal interconnect may have a length that is greater than the bond pad area length and/or the probe pad area length, and a width that is less than the bond pad area width and/or the probe pad area width. An in-front staggering technique may be used at a die corner of the IC to maintain the bond pad area in the I/O region, and a side staggering technique may be used at the die corner of the IC to maintain the bond pad area in the I/O region. | 11-04-2010 |
20110018143 | WAFER LEVEL PACKAGING - Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die. | 01-27-2011 |
20110024919 | WIRING SUBSTRATE FOR A SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE HAVING THE WIRING SUBSTRATE - A wiring substrate for a semiconductor chip includes a substrate having a first face and a second face opposite to the first face. The substrate has a window from the first face to the second face that exposes chip pads of a semiconductor chip adherable to the first face. A first bonding pad is arranged on the second face along a side portion of the window. The first bonding pad is connected to a bonding wire drawn from the chip pad through the window at a predetermined angle with respect to the side portion. A second bonding pad is adjacent to the first bonding pad on the second face. The second bonding pad includes an end portion having an inclined side portion at an angle corresponding to the drawn angle of the first bonding wire for avoiding an overlap of the second bonding pad with the first bonding wire. | 02-03-2011 |
20110068484 | DEVICE AND MANUFACTURING METHOD - A description is given of a device, including a semiconductor chip, a first metal layer laterally extending over the semiconductor chip, the first metal layer having a first thickness. A dielectric layer laterally extends over the first metal layer, and a second metal layer laterally extends over the dielectric layer, the second metal layer having a second thickness that is at least four times larger than the first thickness. | 03-24-2011 |
20110074047 | Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die - A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. | 03-31-2011 |
20110084407 | SYSTEM AND METHOD FOR PREVENTING METAL CORROSION ON BOND PADS - A system and method are disclosed for preventing metal corrosion on bond pads. During manufacture of an integrated circuit device an anti-reflective coating (ARC) layer is applied to a metal stack of a bond pad. A mask and etch process is applied to etch an aperture through the ARC layer down to the metal stack. Then a passivation layer is applied to cover the ARC layer and the aperture through the ARC layer. Then another mask and etch process is applied to etch a bond pad opening through the passivation layer inside the ARC layer aperture down to the metal stack. Interior edge portions of the passivation layer seal the interior edge portions of the ARC layer aperture to prevent corrosion of the ARC layer due to high temperatures, high humidity and corrosive materials encountered in subsequent assembly operations of the integrated circuit device. | 04-14-2011 |
20110089578 | WAFER STRUCTURE - A wafer structure includes a plurality of dies, an edge portion, a passivation layer, and a UV-blocking metal layer. Each of the dies having an integrated circuit formed thereon, and the circuit includes an upmost metal layer that includes bonding pads. A composite dielectric layer corresponding to dielectric layers of the integrated circuit is disposed on the edge portion, and a cavity is formed in the composite dielectric layer over the edge portion. The passivation layer is located over the whole wafer and covers the upmost metal layer. The UV-blocking metal layer is located on the passivation layer and covers the edge portion and at least a portion of each of the dies. The cavity, the passivation layer, and the UV-blocking metal layer result in an alignment mark. | 04-21-2011 |
20110095441 | MICROELECTRONIC ASSEMBLIES HAVING COMPLIANT LAYERS - A compliant semiconductor chip package assembly includes a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip. | 04-28-2011 |
20110101543 | CONNECTING MATERIAL AND SEMICONDUCTOR DEVICE - The invention provides a connecting material comprising metallic particles with an oxygen state ratio of less than 15% as measured by X-ray photoelectron spectroscopy, and especially a connecting material comprising metallic particles that have been subjected to treatment for removal of the surface oxide film and to surface treatment with a surface protective material, for the purpose of providing a connecting material having a high coefficient of thermal conductivity even when joined at a curing temperature of up to 200° C. without application of a load, and that has sufficient bonding strength even when the cured product has been heated at 260° C., as well as a semiconductor device employing it. | 05-05-2011 |
20110108997 | MOUNTING METHOD AND MOUNTING STRUCTURE FOR SEMICONDUCTOR PACKAGE COMPONENT - A semiconductor package component ( | 05-12-2011 |
20110108998 | USE OF DISCRETE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE TO RE-ROUTE BONDING WIRES FOR SEMICONDUCTOR DEVICE PACKAGE - A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length. | 05-12-2011 |
20110115100 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a base, a memory chip, a controller chip, and a plurality of passive components. The base includes a bonding pad. The memory chip is provided above the base and connected to the bonding pad by a wire. Data can be electrically stored in the memory chip. The controller chip is provided in a memory area including the memory chip in a direction from the memory chip toward the base and controls an operation of the memory chip. The passive components are provided in the memory area. | 05-19-2011 |
20110156281 | Quad Flat No Lead (QFN) Package - The present invention relates to a quad flat no lead (QFN) package is provided. In the invention, a plurality of first pads are disposed outside an extension area of a conductive circuit layer, and a plurality of second pads are disposed inside a die bonding area of the conductive circuit layer, wherein the extension area surrounds the die bonding area. First ends of a plurality of traces are connected to the second pads, and second ends of the traces are located in the extension area. An insulating layer fills at least the die bonding area and the extension area, and exposes top surfaces and bottom surfaces of the second pads. A chip is mounted at the die bonding area and a plurality of wires electrically connect the chip to the first pads and the second ends of the traces respectively. An encapsulation material is used to cover the conductive circuit layer, the chip and the wires. Whereby, the package of the invention can have more inputs/outputs terminals, and the insulating layer can prevent moisture permeation from corroding the joints between the wires and the first pads and the second ends of the traces, thus increasing the reliability of the package of the invention. | 06-30-2011 |
20110175238 | Method for Producing Semiconductor Chips and Corresponding Semiconductor Chip - A method for producing a plurality of semiconductor chips is specified. A plurality of semiconductor bodies is provided on a substrate, wherein the semiconductor bodies are spaced apart from one another by interspaces. A structured carrier is provided, having a plurality of elevations. The structured carrier is positioned relative to the substrate in such a way that the elevations of the structured carrier extend into the interspaces between the semiconductor bodies A mechanically stable assemblage is produced, comprising the substrate and the structured carrier. The assemblage is singulated into a plurality of semiconductor chips. | 07-21-2011 |
20110175239 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device, including: a mount body having a first principal surface on which a wiring pattern is formed; a semiconductor chip mounted above the principal surface of the mount body on which the wiring pattern is formed; an underfill material filled between the mount body and the semiconductor chip, thereby forming a fillet in an outer peripheral portion of the semiconductor chip; and an introduction portion formed outside a side portion, along which the fillet is formed so as to be longest, of four side portions which measure a chip mounting area, on the mount body, onto which the semiconductor chip is mounted, the introduction portion serving to introduce the underfill material between the mount body and the semiconductor chip. | 07-21-2011 |
20110210453 | METHOD FOR DESIGNING ELECTRONIC SYSTEM - When an electronic system is designed, then if an integrated circuit chip (LSI), a package (PKG), and a printed circuit board (PCB) are designed separately and in parallel, it will be found near the end of the design process that a satisfactory electrical characteristic is not achieved. Therefore, a design procedure of each part (e.g., an LSI, a PKG, a PCB, etc.) is decided, and allocation of resources to a part which is designed with a higher priority is decided, and thereafter, the other parts start to be designed. Therefore, a basic interconnect distribution for a circuit board is calculated based on a prediction function for predicting an interconnect distribution for the circuit board using design information of the circuit board as input data, and is output. | 09-01-2011 |
20110233794 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device at a good manufacturing efficiency and at a low cost while suppressing the occurrence of voids in the sealing region, the method including the steps of (A) bonding external connection terminals of a semiconductor chip to wirings of a film substrate by hot press bonding, and (B) resin sealing the periphery of the bonded portion of the semiconductor chip and the film substrate, in which the bonding step (A) is performed in a state of adsorbing a portion of the film substrate facing the semiconductor chip from the side opposite the bonding side of the semiconductor chip, and the resin sealing step (B) is performed in a state where the temperature of the semiconductor chip and the film substrate is lowered press is no thermal expansion of the film substrate. | 09-29-2011 |
20110233795 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 09-29-2011 |
20110241222 | Semiconductor Package and Manufacturing Method - A polymer layer is generated on a wafer. The wafer is then separated into semiconductor chips. At least two semiconductor chips are placed on a carrier with the polymer layer facing the carrier. The at least two semiconductor chips are covered with an encapsulating material to form an encapsulant. The carrier is removed from the encapsulant, and the encapsulant and the polymer layer are thinned. | 10-06-2011 |
20110254177 | POWER ELECTRONIC PACKAGE HAVING TWO SUBSTRATES WITH MULTIPLE SEMICONDUCTOR CHIPS AND ELECTRONIC COMPONENTS - A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates. | 10-20-2011 |
20110260340 | CIRCUIT BOARD STRUCTURE, PACKAGING STRUCTURE AND METHOD FOR MAKING THE SAME - A method for making a circuit board structure is disclosed. First, a substrate is provided. The substrate includes a carrier, a copper film and a release film disposed between them. Next, the copper film is patterned to form a connecting pattern and a die pad. Later, a passivation layer is formed to cover the connecting pattern and the die pad. | 10-27-2011 |
20110266699 | METHOD FOR MANUFACTURING A MICROELECTRONIC DEVICE AND A MICROELECTRONIC DEVICE THUS MANUFACTURED - The invention pertains to a method for manufacturing a microelectronic device on a substrate comprising at least one first electrical component and one second electrical component distributed respectively in first and second levels stacked one on top of the other on the substrate, this method comprising:
| 11-03-2011 |
20110266700 | WIRE BOND INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal. | 11-03-2011 |
20110266701 | NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body. | 11-03-2011 |
20110272826 | METHOD FOR PRODUCING AN ELECTRIC FUNCTIONAL LAYER ON A SURFACE OF A SUBSTRATE - An electric functional layer is produced on a surface of a substrate, having at least an electronic component, particularly a semiconductor chip, provided thereof. The electric functional layer is formed using particles in powder of an electrically conductive material. The functional layer is blown on the surface of the substrate to form a thick and strong adhesive layer on impact with the substrate. | 11-10-2011 |
20110291300 | DICING SHEET-ATTACHED FILM FOR FORMING SEMICONDUCTOR PROTECTION FILM, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE USING THE SAME, AND SEMICONDUCTOR DEVICE - The present invention includes a dicing sheet-attached film for forming a semiconductor protection film ( | 12-01-2011 |
20110309527 | INSULATING MEMBER, METAL BASE SUBSTRATE, AND SEMICONDUCTOR MODULE, AND MANUFACTURING METHODS THEREOF - An insulating member of the invention can include an epoxy resin, a first inorganic filler diffused in the epoxy resin and having an average particle diameter of 1 to 99 nm, and a second inorganic filler diffused in the epoxy resin and having an average particle diameter of 0.1 to 100 μm. The first and second inorganic fillers can be independent of each other, and can be selected from a group including Al | 12-22-2011 |
20110309528 | Electronic Modules and Methods for Forming the Same - Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate. | 12-22-2011 |
20120001349 | METHOD OF MANUFACTURING SEMICONDUCTOR MODULES AND SEMICONDUCTOR MODULE - A semiconductor module having an integrated structure is manufactured by mounting a semiconductor chip on the side of a surface of a cooling plate via an insulating material, and by molding the semiconductor chip and the cooling plate by a resin-molded member. This method includes the steps of: (a) forming a sprayed insulating film as the insulating material on a surface of the cooling plate; (b) forming a sprayed conductive film on a face of the sprayed insulating film opposite to a face where the cooling plate is provided; (c) checking whether the sprayed conductive film is insulated from the cooling plate by using the sprayed conductive film and the cooling plate as electrodes and applying voltage therebetween; and (d) mounting the semiconductor chip on the upper side of the sprayed conductive film when the sprayed conductive film is insulated, and then resin-molding the semiconductor chip and the cooling plate. | 01-05-2012 |
20120013029 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A METALLISATION LAYER - A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness. | 01-19-2012 |
20120018904 | Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis - A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer. | 01-26-2012 |
20120018905 | ELECTRONIC COMPONENT ASSEMBLY HAVING PROFILED ENCAPSULATED BONDS - An electronic component assembly is provided having an integrated circuit supported on a first mounting area such that a first surface of the integrated circuit contacts the first mounting area, electrical conductors supported on a second mounting area, and a series of wire bonds extending from contact pads on a second surface of the integrated circuit, opposite the first surface, to the electrical conductors. The first and second mounting areas are stepped relative to one another and the wire bonds are covered in a bead of encapsulant. The bead of encapsulant has a profiled surface that is flat and inclined relative to the second surface. | 01-26-2012 |
20120025401 | INTEGRATED CIRCUIT PACKAGE WITH VOLTAGE DISTRIBUTOR - An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor. | 02-02-2012 |
20120032350 | Systems and Methods for Heat Dissipation Using Thermal Conduits - The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader. | 02-09-2012 |
20120032351 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor device, a plurality of element contacts, a molding compound and a plurality of substrate contacts. The substrate has opposite to the first surface the first surface and the second surface. The semiconductor device is disposed on the first surface. The element contacts electrically connect the substrate and the semiconductor device. The molding compound encapsulates the semiconductor device and a portion of the molding compound is located between the semiconductor device and the first surface, wherein the molding compound includes a plurality of fillers, the fillers amount to 85-89% of the molding compound and the sizes of the fillers range between 18 and 23 micrometers. The substrate contacts are formed on the second surface. | 02-09-2012 |
20120032352 | SIDE WETTABLE PLATING FOR SEMICONDUCTOR CHIP PACKAGE - A method for providing a semiconductor chip package with side wettable plating includes singulating a semiconductor chip package from an array of packages formed in a block format, immersing the semiconductor chip package in a bath of plating solution, contacting a lead land of the semiconductor chip package with conductive contact material within the bath of plating solution, connecting the conductive contact material to a cathode electrical potential, connecting an anode within the bath of plating solution to an anode electrical potential, and plating the lead land of the semiconductor chip package. | 02-09-2012 |
20120032353 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring board having connection pads thereon and a semiconductor chip mounted on the wiring board. The wiring board and the semiconductor chip are covered with a sealing portion. Conductive members are extended upward from the connection pads and are exposed from the sealing portion. Rewiring lines are connected to the exposed conductive members. Land portions are arranged on the sealing portion and are electrically connected to the conductive members through the rewiring lines. | 02-09-2012 |
20120056337 | RFIC CHIP MOUNTING STRUCTURE - An RFIC module includes an RFIC chip that is mounted on a mounting substrate and that is encapsulated with an encapsulation resin layer. The mounting substrate includes a flexible base and electrodes provided on the flexible base. External terminals are disposed near four corners of a mounting surface of the RFIC chip. One of a plurality of mounting lands located on the surface of the flexible base is a shared mounting land and defines an integrated mounting land that is shared by an RF terminal and an NC terminal of the RFIC chip. The shared mounting land is arranged to cover one side of the RFIC chip when viewed from above. | 03-08-2012 |
20120061856 | Apparatus and Methods for High-Density Chip Connectivity - An electronic circuit and method may include a first chip including first electronics and a first connector including multiple self-alignment features and conductive pads. A second chip may include second electronics and a second connector including multiple self-alignment features and conductive pads. The first chip and second chip may be indirectly horizontally aligned with one another and in electrical communication with one another via the first and second connectors. | 03-15-2012 |
20120068362 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR MEMBER AND MOUNTING MEMBER - A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased. | 03-22-2012 |
20120086133 | Semiconductor Device And Semiconductor Device Manufacturing Method - A semiconductor device includes: a semiconductor chip with a plurality of electrode pads disposed at a top surface thereof; a plurality of thin film terminals set apart from one another via respective separator portions, which are located below a bottom surface of the semiconductor chip; an insulating layer disposed between the semiconductor chip and the thin-film terminals; connecting members that connect the electrode pads at the semiconductor chip with the thin-film terminals respectively and a resin layer disposed so as to cover the semiconductor chip, the plurality of thin-film terminals exposed at the semiconductor chip, the separator portions and the connecting members. | 04-12-2012 |
20120112368 | MEMS SENSOR PACKAGE - An MEMS sensor package includes an MEMS sensor and a driving IC that controls driving of the MEMS sensor, which are fixed onto the same mounting surface made of a given package material, wherein an MEMS sensor mounting area and a driving IC mounting area are set on the mounting surface, a die attach metalized layer is formed on a package material of the driving IC mounting area, the driving IC is mounted on the die attach metalized layer, and the MEMS sensor is mounted on a package material of the MEMS sensor mounting area. | 05-10-2012 |
20120119389 | Method for Fabricating a Semiconductor Chip and Semiconductor Chip - A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces. | 05-17-2012 |
20120119390 | SEMICONDUCTOR STRUCTURE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE - According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure includes a first support structure, a plurality of chips formed on the first support structure and a reinforcing structure formed on the first support structure, the reinforcing structure including an outer surrounding element which surrounds the plurality of chips and extends from a surface of the first support structure to a height higher than each of the plurality of chips. A method of manufacturing a semiconductor structure is also provided. | 05-17-2012 |
20120119391 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a support member having a concave portion formed in one surface thereof. A semiconductor chip is accommodated in the concave portion so that a circuit formation surface of the semiconductor chip is exposed on a side of the one surface of the support member. A wiring structure including a wiring layer electrically connected to the semiconductor chip is formed on the circuit formation surface of the semiconductor chip and the one surface of the support member. A portion of the support member including the one surface is made of silicon or borosilicate glass. | 05-17-2012 |
20120119392 | LEAD-FREE HIGH TEMPERATURE COMPOUND - A simple method is provided for firmly-bonded connection of an electronic component to a substrate, which dispenses with the use of lead-containing paste solders and leads to a contact layer featuring sufficiently high resistance to heat fatigue in an environment characterized by incessant periodical temperature variations, and featuring high thermal and electrical conductivity. The method for firmly-bonded connection of an electronic component to a substrate includes the steps of: (a) providing an electronic component having a first surface to be connected and a substrate having a second surface to be connected; (b) applying a paste solder to at least one of the surfaces to be connected; (c) arranging the electronic component and the substrate such that the first electronic component surface to be connected and the second substrate surface to be connected contact each other through the paste solder; and (d) soldering the arrangement from (c) in order to generate a firmly-bonded connection between the electronic component and the substrate, wherein the paste solder contains (i) 10-30% by weight copper particles, (ii) 60-80% by weight particles of at least one substance selected from the group consisting of tin and tin-copper alloys, and (iii) 3-30% by weight solder flux, wherein the mean particle diameter of the particles (i) and of the particles (ii) is no more than 15 μm, and wherein the thickness of the applied layer of paste solder is at least 20 μm. | 05-17-2012 |
20120126432 | SEMICONDUCTOR DEVICE HAVING POWER SUPPLY-SIDE AND GROUND-SIDE METAL REINFORCING MEMBERS INSULATED FROM EACH OTHER - Provided is a semiconductor device which includes a wiring substrate; a semiconductor chip fixedly attached to a first surface of the wiring substrate; a power supply pad that is provided on a second surface opposite to the first surface of the wiring substrate, and supplies electric power to the wiring substrate; a ground pad that is provided on the second surface of the wiring substrate and grounds the wiring substrate; a power supply-side reinforcing member that is connected to the power supply pad and made of metal; a ground-side reinforcing member that is connected to the ground pad and made of metal; and an insulating part that insulates the power supply-side reinforcing member and the ground-side reinforcing member from each other. | 05-24-2012 |
20120146246 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DIELECTRIC SUPPORT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having an outer pad at a substrate top side; forming a resist layer directly on the substrate top side, the resist layer having a resist top side with a channel array adjacent the outer pad exposed from the resist layer; mounting an integrated circuit having an active side facing the resist top side, the integrated circuit having a non-horizontal side adjacent the outer pad; and forming a dielectric between the active side and the resist top side, the dielectric having a fillet extended from the non-horizontal side to the substrate top side inside an inner extent of the channel array. | 06-14-2012 |
20120153507 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method include disposing a semiconductor chip having an electrode pad formed on a circuit forming surface on one surface of a support so that the electrode pad contacts with the one surface of the support, forming a first insulating layer on the one surface of the support so that the first insulating layer covers at least a side surface of the semiconductor chip, removing the support and forming an interconnection terminal on the electrode pad, forming a second insulating layer on the circuit forming surface of the semiconductor chip and the first insulating layer so that the second insulating layer covers the interconnection terminal, exposing an end portion of the interconnection terminal from a top surface of the second insulating layer, and forming a wiring pattern that is electrically connected to the end portion of the interconnection terminal, on the top surface of the second insulating layer. | 06-21-2012 |
20120161336 | SEMICONDUCTOR DEVICE AND ASSEMBLING METHOD THEREOF - A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements. | 06-28-2012 |
20120175787 | SEMICONDUCTOR PACKAGE - A semiconductor package including a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying locations of specific leads. | 07-12-2012 |
20120187580 | Semiconductor Device and Method of Forming B-Stage Conductive Polymer over Contact Pads of Semiconductor Die in Fo-WLCSP - A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. A b-stage conductive polymer is deposited over the contact pads on the semiconductor wafer. The semiconductor wafer is singulated to separate the die. An insulating layer is formed over a carrier with openings formed in the insulating layer. The die is mounted to the carrier with the conductive polymer disposed in the openings of the insulating layer. The conductive polymer is heated to a glass transition temperature to liquefy the conductive polymer to an electrically conductive state. An encapsulant is deposited over the die and insulating layer. The carrier is removed to expose the conductive polymer. An interconnect structure is formed over the die, encapsulant, and conductive polymer. The interconnect structure is electrically connected through the conductive polymer to the contact pads on the die. | 07-26-2012 |
20120199989 | CIRCUIT ARRANGEMENT AND MANUFACTURING METHOD THEREOF - Exemplary embodiments of the disclosure are directed to a circuit arrangement in which a power functional device and a conductor element are mounted and a method of manufacturing the same. The arrangement includes a substrate, a wiring layer provided on the substrate and electrically connected to the functional device and to the conductor element and an intermediate electric contact device. The intermediate electric contact device is mounted on the wiring layer to provide on the side opposite to the wiring layer a contact region for contacting the conductor element. The conductor element is contacting the intermediate electric contact device in the contact region which is opposite to an area, in which the electric contact device is fixed to the wiring layer. | 08-09-2012 |
20120211900 | Semiconductor Device and Method of Forming Multi-Layered UBM with Intermediate Insulating Buffer Layer to Reduce Stress for Semiconductor Wafer - A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers. | 08-23-2012 |
20120228783 | MIXED WIRE BONDING PROFILE AND PAD-LAYOUT CONFIGURATIONS IN IC PACKAGING PROCESSES FOR HIGH-SPEED ELECTRONIC DEVICES - A method and apparatus for mixed wire bonding and staggered bonding pad placement. A first plurality of bonding pads is arranged on a semiconductor device. A second plurality of bonding pads is also arranged on the semiconductor device. The bonding pads of the second plurality of bonding pads are arranged in a staggered pattern, such that the first and second pluralities of bonding pads form one of a plurality of double rows of bonding pads on the semiconductor device. | 09-13-2012 |
20120235309 | Semiconductor Package with Embedded Die and Manufacturing Methods Thereof - A semiconductor package includes a conductive base, a die disposed adjacent to an upper surface of the conductive base, a patterned conductive layer, and a dielectric layer encapsulating the die. The dielectric layer defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base. The conductive base has a lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to a lower surface of the conductive base, where the second portion is sloped inwardly with respect to the lower surface of the conductive base. | 09-20-2012 |
20120235310 | SEMICONDUCTOR PACKAGES - The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon nanostructures (such as, for example, carbon nanotubes) as thermally conductive interface materials. The invention also includes methods of cooling a semiconductor die in which coolant is forced through grooves in a backside of the die, and includes methods of making semiconductor packages. | 09-20-2012 |
20120241984 | Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die - A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. | 09-27-2012 |
20120241985 | SEMICONDUCTOR CHIP WITH SUPPORTIVE TERMINAL PAD - Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure. | 09-27-2012 |
20120248630 | HYBRID INTEGRATED CIRCUIT DEVICE, AND METHOD FOR FABRICATING THE SAME, AND ELECTRONIC DEVICE - A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include ones which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals. | 10-04-2012 |
20120256323 | METHOD FOR PROCESSING A SEMICONDUCTOR WAFER OR DIE, AND PARTICLE DEPOSITION DEVICE - According to various embodiments, a method for processing a semiconductor wafer or die is provided including supplying particles to a plasma such that the particles are activated by the plasma and spraying the activated particles on the semiconductor wafer or die to generate a particle layer on the semiconductor wafer or die. | 10-11-2012 |
20120261840 | SEMICONDUCTOR DEVICE - A semiconductor device includes an interposer, a semiconductor chip mounted on the interposer, a first wiring pattern formed on the interposer, the first wiring pattern including a first contact coupled to a bonding wire from the semiconductor chip and a second contact coupled to an external terminal of the interposer, and a second wiring pattern formed adjacent to the first wiring pattern on the interposer, the second wiring pattern including a third contact coupled to another bonding wire from the semiconductor chip and a fourth contact coupled to another external terminal of the interposer. The first contact is closer to the semiconductor chip than the third contact. | 10-18-2012 |
20120280408 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a die paddle having an internal portion with a trench along a perimeter of the die paddle; forming an interconnect having a concave indentation and an upper portion, the upper portion, opposite the concave indentation, aligned horizontally to the internal portion; | 11-08-2012 |
20120280409 | Micromechanical Method and Corresponding Assembly for Bonding Semiconductor Substrates and Correspondingly Bonded Semiconductor Chip - A micromechanical assembly for bonding semiconductor substrates includes a semiconductor substrate having a chip pattern having a plurality of semiconductor chips, each having a functional region and an edge region surrounding the functional region. There is a bonding frame made of a bonding alloy made from at least two alloy components in the edge region, spaced apart from the functional region. Within the part of the edge region surrounding the bonding frame between the bonding frame and the functional region, there is at least one stop frame made of at least one of the alloy components, which is configured such that when a melt of the bond alloy contacts the stop frame during bonding, the bonding alloy solidifies. | 11-08-2012 |
20120306104 | Semiconductor Device and Method of Forming Interconnect Structure With Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties - A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate. | 12-06-2012 |
20120319301 | Monolithic Darlington with Intermediate Base Contact - In one embodiment, a method includes forming a first pad for coupling to a first terminal of a first transistor of a monolithic darlington transistor configuration and forming a second pad for coupling to a first terminal of a second transistor of the monolithic darlington transistor configuration. The method then forms a third pad for coupling to an external component for the monolithic darlington transistor configuration. The third pad is coupled to a second terminal of the first transistor and a second terminal of the second transistor of the monolithic darlington transistor configuration. | 12-20-2012 |
20120326337 | Semiconductor Device and Method of Forming EWLB Package With Standoff Conductive Layer Over Encapsulant Bumps - A semiconductor device has a carrier with a die attach area. Recesses are formed partially through the carrier outside the die attach area. A first conductive layer is conformally applied over a surface of the carrier and into the recesses. A semiconductor die is mounted to the die attach area of the carrier. An encapsulant is deposited over the carrier and semiconductor die. The encapsulant extends into the recesses over the first conductive layer to form encapsulant bumps. The carrier is removed to expose the first conductive layer over the encapsulant bumps. A first insulating layer is formed over the semiconductor die with openings to expose contact pads of the semiconductor die. A second conductive layer is formed between the first conductive layer and the contact pads on the semiconductor die. A second insulating layer is formed over the second conductive layer and semiconductor die. | 12-27-2012 |
20130001803 | METHOD FOR ATTACHING A METAL SURFACE TO A CARRIER, A METHOD FOR ATTACHING A CHIP TO A CHIP CARRIER, A CHIP-PACKAGING MODULE AND A PACKAGING MODULE - A method for attaching a metal surface to a carrier is provided, the method including: depositing a porous layer over at least one of a metal surface and a side of a carrier; and attaching the at least one of a metal surface and a side of a carrier to the porous layer by bringing a material into pores of the porous layer, resulting in the material forming an interconnection between the metal surface and the carrier. | 01-03-2013 |
20130001804 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There are constituted by a tab on which a semiconductor chip is mounted, a sealing portion formed by resin-sealing the semiconductor chip, a plurality of leads each having a mounted surface exposed to a peripheral portion of a rear surface of the sealing portion and a sealing-portion forming surface disposed on an opposite side thereto, and a wire for connecting a pad of the semiconductor chip and a lead, wherein the length between inner ends of the sealing-portion forming surfaces of the leads disposed so as to oppose to each other is formed to be larger than the length between inner ends of the mounted surfaces. Thereby, a chip mounting region surrounded by the inner end of the sealing-portion forming surface of each lead can be expanded and the size of the mountable chip is increased. | 01-03-2013 |
20130037966 | SEMICONDUCTOR DEVICE DIE BONDING - A semiconductor device includes a semiconductor die having first and second opposing faces and an edge surface. The edge surface has an undercut under the first face. The second face of the semiconductor die is bonded to a bonding surface of a die support member, such as a thermally conductive flag of a lead frame, with a die attach material. A fillet of the bonding material is formed within the undercut. | 02-14-2013 |
20130056883 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a base board, a mounting substrate, a semiconductor element, a holder, a holder terminal, a case, a first sealing layer, and a second sealing layer. The mounting substrate is provided on the base board. The semiconductor element is provided on the mounting substrate. The holder is provided above the mounting substrate. The holder terminal is held by the holder and electrically connected to the semiconductor element. The case surrounds the mounting substrate along a side face of the mounting substrate and surrounds the holder along a side face of the holder. The first sealing layer covers the mounting substrate and the semiconductor element inside a space surrounded by the case. The second sealing layer is provided on the first sealing layer inside the space surrounded by the case and has a higher hardness than the first sealing layer. | 03-07-2013 |
20130056884 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes at least 4 conductive line groups arranged in parallel over one memory cell block and each configured to include conductive lines. First contact pads may be coupled to the respective ends of the conductive lines of two of the 4 conductive line groups in a first direction, and second contact pads may be coupled to the respective ends of the conductive lines of the remaining 2 of the 4 conductive line groups in a second direction opposite to the first direction. | 03-07-2013 |
20130062786 | SOLDER MASK WITH ANCHOR STRUCTURES - Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site. | 03-14-2013 |
20130075937 | Apparatus and Methods for Molding Die on Wafer Interposers - Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits. | 03-28-2013 |
20130087930 | Semiconductor structure and method for making same - One or more embodiments relate to a semiconductor structure, comprising: a conductive pad, the conductive pad including a plurality of laterally spaced apart gaps diposed at least partially through the conductive pad. | 04-11-2013 |
20130087931 | Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure - A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer. | 04-11-2013 |
20130093104 | BOND PAD STRUCTURE AND FABRICATING METHOD THEREOF - A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening. | 04-18-2013 |
20130105993 | SEMICONDUCTOR DEVICE INTERCONNECT | 05-02-2013 |
20130105994 | HEATSINK ATTACHMENT MODULE | 05-02-2013 |
20130113118 | Semiconductor Device and Method of Forming Sloped Surface in Patterning Layer to Separate Bumps of Semiconductor Die from Patterning Layer - A semiconductor device has a semiconductor die with bumps formed over a surface of the semiconductor die. A conductive layer is formed over a substrate. A patterning layer is formed over the substrate and conductive layer. A masking layer having an opaque portion and linear gradient contrast portion is formed over the patterning layer. The linear gradient contrast portion transitions from near transparent to near opaque. The patterning layer is exposed to ultraviolet light through the masking layer. The masking layer is removed and a portion of the patterning layer is removed to form an opening having a sloped surface to expose the conductive layer. The sloped surface in patterning layer can be formed by laser direct ablation. The semiconductor die is mounted to the substrate with the bumps electrically connected to the conductive layer and physically separated from the patterning layer. | 05-09-2013 |
20130119562 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor package includes a semiconductor chip, a first insulating layer formed to cover the semiconductor chip, a wiring structure formed on the first insulating layer. The wiring structure has an alternately layered configuration including wiring layers electrically connected to the semiconductor chip and interlayer insulating layers each located between one of the wiring layers and another. The interlayer insulating layers include an outermost interlayer insulating layer located farthest from a surface of the first insulating layer. A groove formed in the outermost interlayer insulating layer passes through the outermost interlayer insulating layer in a thickness direction. | 05-16-2013 |
20130134607 | INTERPOSER FOR STACKED SEMICONDUCTOR DEVICES - A semiconductor device is disclosed, comprising a substrate having at least one substrate bonding pad. A plurality of semiconductor dies are stacked on the substrate. Each semiconductor die has at least one die bonding pad located on an active surface of the die. A plurality of interposers are each mounted on a corresponding one of the semiconductor dies. Each interposer has an aperture formed therethrough in alignment with the at least one die bonding pad. An electrical connection between the at least one die bonding pad and the at least one substrate bonding pad is formed at least in part by the interposer. The electrical connection includes at least one wire bond. | 05-30-2013 |
20130140713 | Interposer Wafer Bonding Method and Apparatus - The present disclosure relates to a method for fast and precise alignment and mounting of a top die onto an interposer wafer. The method is performed by applying a hydrophobic self assembled monolayer to a carrier wafer in a pattern defining a top die placement region correlating to an arrangement of a top die on an interposer wafer. A liquid is provided into the top die placement region and a top die is placed into contact with the liquid. The surface tension of the liquid automatically aligns the top die by generating a force causing the top die to overlap with the top die placement region. The liquid is then eliminated and the top die is affixed to the carrier wafer. The carrier wafer is bonded to the interposer wafer, bringing the top die into contact with an interposer. | 06-06-2013 |
20130140714 | SEMICONDUCTOR DEVICE - In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing member sealing the semiconductor chip and the plurality of wires, first and second step portions are formed at shifted positions on the left and right sides of each of the leads to make the positions of the first and second step portions shifted between the adjacent leads. As a result, the gap between the leads is narrowed, thereby achieving the miniaturization or the increase in the number of pins of the QFN. | 06-06-2013 |
20130140715 | Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same - Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component. | 06-06-2013 |
20130154123 | Semiconductor Device and Fabrication Method - In various embodiments, a semiconductor device may include: a carrier; a semiconductor chip disposed over a first side of the carrier; a layer stack disposed between the carrier and the semiconductor chip or over a second side of the carrier opposite the semiconductor chip, or both, the layer stack including at least a first electrically insulating layer, the first electrically insulating layer having a laminate having a first electrically insulating matrix material and a first mechanically stabilizing material embedded in the first electrically insulating matrix material. | 06-20-2013 |
20130154124 | METHOD FOR PACKAGING SEMICONDUCTORS AT A WAFER LEVEL - A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices. | 06-20-2013 |
20130168874 | DIE UP FULLY MOLDED FAN-OUT WAFER LEVEL PACKAGING - A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to a redistribution layer. | 07-04-2013 |
20130168875 | SEMICONDUCTOR DEVICE AND PACKAGE - A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate. | 07-04-2013 |
20130214432 | STACKED DIE ASSEMBLY - Embodiments of stacked die assemblies for an IC are disclosed. One embodiment includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components, avoiding the interconnect restricted area of the first interposer and the second interposer. | 08-22-2013 |
20130249118 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A GRID ARRAY WITH A LEADFRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a conductive trace having a terminal end and a circuit end; forming a terminal on the terminal end; connecting an integrated circuit die directly on the circuit end of the conductive trace, the integrated circuit die laterally offset from the terminal, the active side of the integrated circuit die facing the circuit end; and forming an insulation layer on the terminal and the integrated circuit die, the integrated circuit die covered by the insulation layer. | 09-26-2013 |
20130277864 | METHOD FOR PRODUCING A COMPONENT AND DEVICE COMPRISING A COMPONENT - A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit. | 10-24-2013 |
20130277865 | MULTI DIE PACKAGE STRUCTURES - Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies. | 10-24-2013 |
20130307165 | METHOD FOR LOW TEMPERATURE WAFER BONDING AND BONDED STRUCTURE - A low temperature wafer bonding method and a bonded structure are provided. The method includes: providing a first substrate having a plurality of metal pads and a first dielectric layer close to the metal pads, where the metal pads and the first dielectric layer are on a top surface of the first substrate; providing a second substrate having a plurality of semiconductor pads and a second dielectric layer close to the semiconductor pads, where the semiconductor pads and the second dielectric layer are on a top surface of the second substrate; disposing at least one of the metal pads in direct contact with at least one of the semiconductor pads, and disposing the first dielectric layer in direct contact with the second dielectric layer; and bonding the metal pads with the semiconductor pads, and bonding the first dielectric layer with the second dielectric layer. | 11-21-2013 |
20130320570 | ELECTRONIC DEVICE FOR POWER APPLICATIONS - An electronic device for power applications and configured for being mounted on a printed circuit board is disclosed. The electronic device includes a semiconductor chip integrating a power component, and a package. The package comprises an insulating body embedding the semiconductor chip, and exposed electrodes for electrically connecting conductive terminals of the semiconductor chip to external circuitry in the printed circuit board. The electronic device is further configured to be fastened to a heatsink with a back surface of the insulating body in contact with a main surface of the heatsink for removing heat produced by the electronic device during the operation thereof. The insulating body lacks of a fixing portion in which a hole for receiving an insertable fastener element for the fastening of the electronic device to the heatsink is located. | 12-05-2013 |
20140035167 | METHOD FOR PRODUCING A BONDING PAD FOR THERMOCOMPRESSION BONDING, AND BONDING PAD - A method produces a bonding pad for thermocompression bonding. The method includes providing a carrier material having semiconductor structures, wherein an outermost edge layer of the carrier material is a wiring metal layer configured to make electrical contact with the semiconductor structures. The method also includes depositing a single-layered bonding metal layer directly on a surface of the wiring metal layer to produce the bonding pad. | 02-06-2014 |
20140035168 | BONDING PAD FOR THERMOCOMPRESSION BONDING, PROCESS FOR PRODUCING A BONDING PAD AND COMPONENT - A bonding pad for thermocompression bonding of a carrier material to a further carrier material includes a base layer and a top layer. The base layer is made of metal, is deformable, and is connected to the carrier material. The metal is nickel-based. The top layer is metallic and is connected directly to the base layer. The top layer is arranged at least on a side of the base layer which faces away from the carrier material. The top layer has a smaller layer thickness than the base layer. In at least one embodiment, the top layer has a greater oxidation resistance than the base layer. | 02-06-2014 |
20140048958 | Pad Sidewall Spacers and Method of Making Pad Sidewall Spacers - A method of making contact pad sidewall spacer and pad sidewall spacers are disclosed. An embodiment includes forming a plurality of contact pads on a substrate, each contact pad having sidewalls, forming a first photoresist over the substrate, and removing the first photoresist from the substrate thereby forming sidewall spacers along the sidewalls of the plurality of the contact pads. | 02-20-2014 |
20140048959 | MICROELECTRONIC PACKAGE HAVING NON-COPLANAR, ENCAPSULATED MICROELECTRONIC DEVICES AND A BUMPLESS BUILD-UP LAYER - A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material, wherein the encapsulated structure may have an active surface proximate the active surfaces of the plurality of microelectronic devices, and wherein at least one of the plurality of microelectronic devices may have a height greater than another of the plurality of microelectronic devices (e.g. non-coplanar), The microelectronic package further includes a bumpless build-up layer structure formed proximate the encapsulated structure active surface. The microelectronic package may also have an active surface microelectronic device positioned proximate the encapsulated structure active surface and in electrical contact with at least one of the plurality of microelectronic devices of the encapsulated substrate. | 02-20-2014 |
20140054800 | METHOD FOR MANUFACTURING A METAL PAD STRUCTURE OF A DIE, A METHOD FOR MANUFACTURING A BOND PAD OF A CHIP, A DIE ARRANGEMENT AND A CHIP ARRANGEMENT - A method for manufacturing a metal pad structure of a die is provided, the method including: forming a metal pad between encapsulation material of the die, wherein the metal pad and the encapsulation material are separated from each other by a gap; and forming additional material in the gap to narrow at least a part of the gap. | 02-27-2014 |
20140061952 | IDENTIFICATION MECHANISM FOR SEMICONDUCTOR DEVICE DIE - A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads. | 03-06-2014 |
20140061953 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - To provide a semiconductor device having suspension leads with less distortion. In QFN having a plurality of external terminal portions at the periphery of the bottom surface of a sealing body, a plurality of leads is linked to a plurality of long suspension leads of the QFN at an intermediate portion thereof or at between the intermediate portion and a position near the die pad. These long suspension leads are each supported by these leads, making it possible to suppress distortion of each of the suspension leads in a wire bonding step or molding step in the fabrication of the QFN. | 03-06-2014 |
20140077394 | Wafer Level Embedded Heat Spreader - Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads. | 03-20-2014 |
20140091482 | Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP - A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. | 04-03-2014 |
20140131896 | Exposing Connectors in Packages Through Selective Treatment - A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed. | 05-15-2014 |
20140138854 | THERMAL INTERFACE MATERIAL FOR INTEGRATED CIRCUIT PACKAGE ASSEMBLY AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure are directed towards a thermal interface material for integrated circuit package assembly and associated techniques and configurations. In one embodiment, an apparatus includes a die and a layer of thermal interface material (TIM) thermally coupled with the die, the TIM including a polymer matrix and carbon filler having anisotropic thermal conductivity disposed in the polymer matrix, the polymer matrix being configured for deposition on the die in liquid form. Other embodiments may be described and/or claimed. | 05-22-2014 |
20140159255 | CONTACT PAD STRUCTURE - A contact pad structure disposed on a peripheral region of a substrate is provided. The contact pad structure includes a transparent conductive pattern, a metal conductive pattern, and a protection layer. The transparent conductive pattern has a bonding region, a first side region, a second side region, a third side region and a fourth side region. The first, the second, the third, and the fourth side regions sequentially surround the bonding region. The metal conductive pattern without overlapping the bonding region has a first contact region, a second contact region and a first connection region. The first contact region contacts the first side region. The second contact region contact the third side region. The first connection region is connected between the first contact region and the second contact region. The protection layer covering the metal conductive pattern has a protection layer opening exposing the bonding region. | 06-12-2014 |
20140191420 | EMBEDDED PACKAGE IN PCB BUILD UP - An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device. | 07-10-2014 |
20140197549 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a package substrate, a semiconductor chip, a die attach film, a molding member, and a dummy finger. A bond finger is arranged on an upper surface of the package substrate. The semiconductor chip is arranged on the upper surface of the package substrate, and electrically connected to the bond finger. The die attach film is interposed between the semiconductor chip and the package substrate such that the semiconductor chip is attached to the package substrate. The molding member is formed on the upper surface of the package substrate to cover the semiconductor chip. The dummy finger is formed between the upper surface of the package substrate and the molding member. Moisture in the void formed in the die attach film may be released through the discharge passageway. Thus, the package substrate is prevented from being swollen during a subsequent thermal process such as a reflow process. | 07-17-2014 |
20140210111 | EMBEDDED PACKAGE ON PACKAGE SYSTEMS - In some embodiments, a semiconductor device package assembly may include a substrate. The substrate may include a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the substrate. The second surface may include a die electrically coupled to the second surface. In some embodiments, the semiconductor device package may include an electrically insulating material covering at least a portion of the second surface and the die. The electrically insulating material may include a dielectric polymer. The dielectric polymer may function to inhibit deformation of the package during use. The dielectric polymer may include a coefficient of thermal expansion of between about 5 to about 15 ppm/° C. The dielectric polymer may include a modulus of between about 15 to about 25 Gpa. | 07-31-2014 |
20140232017 | IDENTIFICATION MECHANISM FOR SEMICONDUCTOR DEVICE DIE - A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads. | 08-21-2014 |
20140246790 | FLOATING BOND PAD FOR POWER SEMICONDUCTOR DEVICES - Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size. | 09-04-2014 |
20140252657 | Package Alignment Structure and Method of Forming Same - An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line. | 09-11-2014 |
20140264949 | GOLD DIE BOND SHEET PREFORM - The amount of gold required for bonding a semiconductor die to an electronic package is reduced by using a sheet preform tack welded to the package prior to mounting the die. The preform, only slightly larger than a semiconductor die to be attached to the package, is placed in the die bond location and tack welded to the package at two spaced locations. | 09-18-2014 |
20140284819 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES HAVING A METALLISATION LAYER - A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness. | 09-25-2014 |
20140312513 | SEMICONDUCTOR DEVICE, SUBSTRATE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane. | 10-23-2014 |
20140312514 | SEMICONDUCTOR DEVICE - [Object] A semiconductor device is configured to release heat from semiconductor chips more efficiently. [Means for Solution] A semiconductor device includes: a die pad | 10-23-2014 |
20140361445 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - When a conductive post is bonded to a bonding target member such as a semiconductor chip or an insulating substrate with conductive patterns by using metal nanoparticles, a strong bonding layer can be obtained by forming a bottom surface of the distal end of the conductive post in a concave shape. | 12-11-2014 |
20150008595 | SEMICONDUCTOR DEVICE WITH PRE-MOLDING CHIP BONDING - This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact. | 01-08-2015 |
20150041993 | METHOD FOR MANUFACTURING A CHIP ARRANGEMENT, AND A CHIP ARRANGEMENT - A method for manufacturing a chip arrangement may include: disposing a stabilizing structure and a chip including at least one contact next to each other and over a carrier; encapsulating the chip and the stabilizing structure by means of an encapsulating structure; and forming an electrically conductive connection to the at least one contact of the chip. | 02-12-2015 |
20150041994 | SEMICONDUCTOR PACKAGE HAVING RECESSED SOLDER TERMINALS - A semiconductor device ( | 02-12-2015 |
20150041995 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a chip package includes the following steps. A wafer structure having a wafer and a protection layer is provided. The first opening of the wafer is aligned with and communicated with the second opening of the protection layer. A first insulating layer having a first thickness is formed on a conductive pad exposed from the second opening, and a second insulating layer having a second thickness is formed on a first sidewall of the protection layer surrounding the second opening and a second sidewall of the wafer surrounding the first opening. The first and second insulating layers are etched, such that the first insulating layer is completely removed, and the second thickness of the second insulating layer is reduced. | 02-12-2015 |
20150076713 | Integrated Fan-Out Package Structures with Recesses in Molding Compound - A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface. | 03-19-2015 |
20150108664 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device which includes a bonding wire, one end of which is connected to a bipolar device, the other end of which is connected to a conductive member, and the center of which is connected to a unipolar device, said semiconductor device being capable of improving the reliability of wire bonding. A package ( | 04-23-2015 |
20150130085 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device according to the present invention includes the steps of (a) preparing an insulating or conductive substrate; (b) arranging a bonding material having sinterability in at least one bonding region of a principal surface of the substrate (i.e., insulating substrate); and (c) sintering the bonding material while a bonding surface to be subjected to bonding of at least one semiconductor element is brought into pressurized contact with the bonding material, and bonding the substrate (i.e., insulating substrate) and the semiconductor element together through the bonding material. The bonding region in the step (b) is inwardly positioned from the bonding surface (i.e., region) of the semiconductor element in plan view, and the bonding material is not protruded outwardly from the bonding surface of the semiconductor element in plan view even after the step (c). | 05-14-2015 |
20160079170 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced. | 03-17-2016 |
20160086899 | ROOM TEMPERATURE METAL DIRECT BONDING - A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed. | 03-24-2016 |
20160086913 | METHOD FOR LOW TEMPERATURE BONDING AND BONDED STRUCTURE - A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO | 03-24-2016 |
20160126216 | Method of forming an interconnection and arrangement for a direct interconnect chip assembly - Various embodiments provide a method of forming an interconnection between an electric component and an electronic component, wherein the method comprises forming a first interconnection sublayer on an electric component, wherein the first interconnection sublayer comprises a metal and has a main surface opposite to the electric component, wherein the main surface has a first surface roughness; forming a second interconnection sublayer on an electronic component, wherein the second interconnection sublayer comprises the metal and has a surface opposite to the electronic component, wherein the surface has a second surface roughness, wherein the first surface roughness and the second surface roughness are in the same order of magnitude; and interconnecting the first interconnection sublayer and the second interconnection sublayer by contacting the same and applying pressure and heat to the contacted first and second interconnection sublayers. | 05-05-2016 |
20160181213 | WAFER STRUCTURE AND METHOD FOR WAFER DICING | 06-23-2016 |
20160190093 | THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE - A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. | 06-30-2016 |
20160197034 | PACKAGE CARRIER | 07-07-2016 |
20190148264 | Wafer Level Embedded Heat Spreader | 05-16-2019 |
20190148283 | ELEMENT PLACE ON LAMINATES | 05-16-2019 |