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Flip chip

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257734000 - COMBINED WITH ELECTRICAL CONTACT OR LEAD

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DocumentTitleDate
20090032974METHOD AND STRUCTURE TO REDUCE CRACKING IN FLIP CHIP UNDERFILL - A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.02-05-2009
20100019394IC CHIP MOUNTING PACKAGE - In one embodiment of the present invention, an IC chip mounting package includes a film base member and an IC chip connected via an interposer. Connecting terminals on the film base member side of the interposer are provided so as to have a pitch larger than that of connecting terminals of the IC. A device hole is opened to the film base member, and the IC chip is provided in the device hole. A distance between an inner lead leading end and a periphery of the device hole is set as not less than 10 μm.01-28-2010
20090194887EMBEDDED DIE PACKAGE ON PACKAGE (POP) WITH PRE-MOLDED LEADFRAME - A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.08-06-2009
20110193243Unique Package Structure - A system in a package comprising a flip chip semiconductor die on a package substrate, a spacer on the package substrate, and a wire bond semiconductor die supported by the spacer and the flip chip semiconductor die.08-11-2011
20100148375Vertically Tapered Transmission Line for Optimal Signal Transition in High-Speed Multi-Layer Ball Grid Array Packages - Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.06-17-2010
20100148373Stacked Die Parallel Plate Capacitor - A stacked integrated circuit having a first die with a first surface and a second die with a second surface facing the first surface, the stacked integrated circuit includes a capacitor. The capacitor is formed by a first conducting plate on a region of the first surface, a second conducting plate on a region of the second surface substantially aligned with the first conducting plate, and a dielectric between the first conducting electrode and the second conducting electrode.06-17-2010
20090146316FLIP-CHIP ASSEMBLY WITH ORGANIC CHIP CARRIER HAVING MUSHROOM-PLATED SOLDER RESIST OPENING - Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility.06-11-2009
20090189295STACK CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A stack chip package structure and a manufacturing method thereof are disclosed. The method comprises: providing a first substrate; disposing a first chip on the first substrate; disposing a second chip and at least one second substrate on the first chip, wherein the second substrate is electrically connected to the first chip; bonding at least one first connecting wire connected between the second chip and the second substrate; bonding at least one second connecting wire connected between the first substrate and the second substrate; and forming a package body on the first substrate to encapsulate the first chip, the second chip, the second substrate, the first connecting wire and the second connecting wire.07-30-2009
20100044883Plastic Semiconductor Package Having Improved Control of Dimensions - A device with a semiconductor chip assembled on a planar substrate and encapsulation compound surrounding the assembled chip and a portion of the substrate near the chip; the compound has a planar top area. The encapsulation compound has a plurality of side areas reaching from the substrate to the top area; these side areas form edge lines with the top area, where the top area plane intersects with the respective plane of each side area. The encapsulation compound is recessed along the edge lines so that the material is caved-in along the lines; this feature causes the recess to prevent any compound from the side area planes to reach the top area plane, whereby the planarity of the top area is preserved.02-25-2010
20100044882INTEGRATED CIRCUIT PACKAGE SYSTEM FLIP CHIP - An integrated circuit package system includes: providing a substrate having a top side with a trace conductor connected to a bottom side with a system interconnect; forming a bump ring on the substrate, the bump ring having an inner cavity area over the trace conductor and an outer bump area; applying a substrate mask layer adjacent a perimeter of the outer bump area; connecting a device to the trace conductor below the bump ring; and applying a compound between the device and the substrate.02-25-2010
20090160068FLIP-CHIP PACKAGE AND METHOD OF FORMING THEREOF - A flip-chip package is disclosed. The flip-chip package includes a substrate comprising at least one build-up layer. At least one longitudinal trench is formed in at least one build-up layer of the substrate. The at least one longitudinal trench filled with a conductive material. A conductive plane may be disposed at least partially on the at least one longitudinal trench. An insulating layer may cover the conductive plane and, at least in part, at least one build-up layer of the substrate. The solder resist layer may include a plurality of openings partially exposing the conductive plane. A plurality of conductive pads may be disposed on the conductive plane through the plurality of openings. A method for fabricating the flip-chip package is also disclosed.06-25-2009
20090160067INTEGRATED CIRCUIT PACKAGE - An integrated circuit package is described that includes two dice. The active surface of each die includes a plurality of I/O pads. The active surface of the first die is positioned adjacent first surfaces of the leads of a leadframe such that I/O pads from the first die are arranged adjacent corresponding solder pad surfaces on the first surfaces. Similarly, the active surface of the second die is positioned adjacent second surfaces of the leads opposite the first surfaces such that I/O pads from the second die are arranged adjacent corresponding solder pad surfaces on the second surfaces. A plurality of solder joints are arranged to physically and electrically connect I/O pads from the first or second die to associated adjacent solder pad surfaces on the leads. In this way, a single leadframe can be utilized to package two dice, one on either side of the leads of the leadframe.06-25-2009
20130082406Method for producing a two-chip assembly and corresponding two-chip assembly - A method for producing a two-chip assembly includes: providing a wafer having a first thickness, which wafer has a front side and a back side, a first plurality of first chips being provided on the front side of the wafer; attaching a second plurality of second chips on the front side of the wafer, so that every first chip is joined in each instance to a second chip and forms a corresponding two-chip pair; forming a cohesive mold package on the front side of the wafer, so that the second chips are packaged; thinning the wafer from the back side to a second thickness which is less than the first thickness; forming vias from the back side to the second chips; and separating the two-chip pairs into corresponding two-chip assemblies.04-04-2013
20130082405Semiconductor Package - A semiconductor package including a first package having a first semiconductor chip, a plurality of first inner leads electrically connected to the first semiconductor chip, and a plurality of first outer leads extending from the first inner leads and electrically connected to an external apparatus; and a second package having a second semiconductor chip and a plurality of second inner leads electrically connected to the second semiconductor chip, wherein an inactive surface of the first semiconductor chip and an inactive surface of the second semiconductor chip face each other, and the first inner leads contact the second inner leads to be electrically connected to each other.04-04-2013
20090115073WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a wiring substrate of a semiconductor device, a hollow portion is provided under a pad wiring portion including a connection pad, and thus a wiring layer has a cantilever structure in which the pad wiring portion is formed as an aerial wiring, and a semiconductor chip is flip-chip connected to the connection pad. The pad wiring portion including the connection pad is formed on a sacrifice layer which is filled in a recess portion in an interlayer insulating layer of the wiring substrate, then the semiconductor chip is flip-chip connected to the connection pad, and then the hollow portion is provided by removing the sacrifice layer.05-07-2009
20120217659INTEGRATED CIRCUIT PACKAGE WITH MOLDED CAVITY - An integrated circuit package system includes a base substrate, attaching a base die over the base substrate, attaching an integrated interposer having interposer circuit devices, over the base die, and forming a package system encapsulant having an encapsulant cavity over the integrated interposer.08-30-2012
20120112367CHIP CARD, AND METHOD FOR THE PRODUCTION THEREOF - A chip card in the form of an ID-1 card, a plug-in SIM or a USB token has a layered compound (05-10-2012
20090065951STACKED DIE PACKAGE - The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.03-12-2009
20130062785TRANSISTOR STRUCTURE AND RELATED TRANSISTOR PACKAGING METHOD THEREOF - A transistor structure includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die. One of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.03-14-2013
20090236756FLIP CHIP INTERCONNECTION SYSTEM - A flip chip interconnection system includes: providing a conductive lead coated with a protective coating; forming a groove through the protective coating to the conductive lead for controlling solder position on a portion of the conductive lead; and attaching a flip chip having a solderable conductive interconnect to the portion of the conductive lead.09-24-2009
20090008800FLIP CHIP MOUNTING BODY, FLIP CHIP MOUNTING METHOD AND FLIP CHIP MOUNTING APPARATUS - The flip chip mounted body of the present invention includes: a circuit board (01-08-2009
20110068483METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device of the present invention includes a coating process in which a pasty thermosetting resin composition having a flux activity is coated on at least either one of a substrate and a semiconductor chip; a bonding process in which the substrate and the semiconductor chip are electrically bonded while placing the pasty thermosetting resin composition in between; a curing process in which the pasty thermosetting resin composition is cured under heating; and a cooling process, succeeding to the curing process, in which cooling is performed at a cooling rate between 10[° C./hour] or above and 50[° C./hour] or below.03-24-2011
20110037179SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed. In one aspect, the package includes a base frame and a wiring substrate mounted on the base frame. The base frame has two pieces made of a material with respectively a first and a second coefficient of thermal expansion and connected to each other via resilient connecting structures. The wiring substrate has electric wiring tracks providing the electric connection between first and second bond pads, provided for being electrically connected to bond pads on respectively a die and a printed wiring board. The electrical wiring tracks have flexible parts provided to expand and contract along with the resilient connecting structures.02-17-2011
20130161836SEMICONDUCTOR PACKAGE HAVING INTERPOSER COMPRISING A PLURALITY OF SEGMENTS - Provided is a semiconductor package comprising a substrate, a semiconductor chip formed on the substrate, and an interposer including a plurality of segments which are separated from each other and arranged on the substrate to surround the semiconductor chip. And a stacked package for multiple chips including the semiconductor package with a plurality of segments of an interposer is provided.06-27-2013
20090166890Flip-chip package - A flip-chip package is described. The package has an integrated circuit (IC) die positioned within an epoxy layer on the top surface of a package substrate. Cooling of the IC die is facilitated by a heat spreader having two contact surfaces separated by a pedestal, the first contact surface for attachment to the epoxy layer the second contact surface for thermal attachment to the exposed backside surface of the IC die, the pedestal thickness is selected so as to create a gap between the first contact surface and the epoxy layer.07-02-2009
20110291299Stress Reduction in Chip Packaging by a Stress Compensation Region Formed Around the Chip - A stress compensation region that may be appropriately positioned on a package substrate may compensate for or at least significantly reduce the thermally induced mechanical stress in a sensitive metallization system of a semiconductor die, in particular during the critical reflow process. For example, a stressor ring may be formed so as to laterally surround the chip receiving portion of the package substrate, wherein the stressor ring may efficiently compensate for the thermally induced deformation in the chip receiving portion.12-01-2011
20110291298Chip Package Including Multiple Sections for Reducing Chip Package Interaction - Thermally induced stress in a semiconductor die, i.e., in a complex metallization system thereof, may be reduced by “dividing” a package substrate into two or more substrate sections, which may have formed therebetween an appropriate stress buffer region, for instance a region of superior resiliency. In this case, the total deformation of the package substrate may be reduced, thereby also reducing the thermally induced stress forces in the complex metallization system of the semiconductor die. Hence, for a given size and complexity of a metallization system, an increased production yield and superior reliability may be achieved.12-01-2011
20080308950Semiconductor package and method for manufacturing thereof - A semiconductor package, which includes: a first substrate, on which a pre-designed pattern is formed; a first chip, mounted by a flip chip method on one side of the first substrate; a first molding, covering the first substrate and the first chip; a first via, which penetrates the first molding, and which is electrically connected with the pattern formed on the first substrate; an interposer, which is placed on the first molding, and on both sides of which a pre-designed pattern is formed respectively; a second via, penetrating the interposer and electrically connecting both sides of the interposer; a second substrate, placed on the interposer with at least one conductive ball positioned in-between, such that the second substrate is electrically connected with the pattern formed on the interposer; and a second chip mounted on the second substrate, can be used to improve heat release and increase the degree of integration.12-18-2008
20090189296FLIP CHIP QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE - A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads.07-30-2009
20090189297SEMICONDUCTOR DEVICE - To provide a semiconductor device having high reliability by reducing the bending of a semiconductor device and mitigating stress exerted on external terminals. In a semiconductor device 07-30-2009
20090102062WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - A wiring substrate of the present invention includes such a structure that a plurality of connection pads and leading wiring portions connected to the plurality of connection pads respectively are arranged to an insulating layer of a surface layer side, and the leading wiring portions are arranged to be bended from the connection pads, and a solder layer to protrude upward is provided on the connection pads respectively. A solder on the leading wiring portions moves to the bend portion side, and thus the solder layer to protrude upward is formed on the connection pads.04-23-2009
20090152741CHIP STRUCTURE AND FABRICATION PROCESS THEREOF AND FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF - A chip structure including a chip, a first dielectric layer and at least one first conductive layer is provided. The chip has an active surface, a backside and at least one bonding pad disposed on the active surface. The first dielectric layer is disposed on the active surface and has at least one first opening, wherein the first opening correspondingly exposes the bonding pad. The first conductive layer covers an inner wall of the first opening and the bonding pad so as to form a concave structure in the first opening. When the chip structure is bonded to a substrate, the solder bump of the substrate is inlaid into the concave structure of the chip. Moreover, a fabrication process of the chip structure, a flip chip package structure and a fabrication process thereof, a package structure of a light emitting/receiving device and a chip stacked structure are also provided.06-18-2009
20090152739METHOD AND SYSTEM FOR FILTERS EMBEDDED IN AN INTEGRATED CIRCUIT PACKAGE - Methods and systems for filters embedded in an integrated circuit package are disclosed and may include controlling filtering of signals within an integrated circuit via one or more filter components embedded within a multi-layer package bonded to the integrated circuit. The one or more filter components may be electrically coupled to one or more switchable capacitors within the integrated circuit. The filter components may include transmission line devices, microstrip filters, transformers, surface mount devices, inductors, and/or coplanar waveguide filters. The filter components may be fabricated utilizing metal conductive layers and/or ferromagnetic layers deposited on and/or embedded within the multi-layer package. The integrated circuit may be electrically coupled to the multi-layer package utilizing a flip-chip bonding technique.06-18-2009
20090152740INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLIP CHIP - An integrated circuit package system includes: mounting a flip chip over a carrier with a non-active side of the flip chip facing the carrier; mounting a substrate over the flip chip; connecting an internal interconnect between the flip chip and the carrier; and encapsulating the flip chip and the internal interconnect over the carrier with the substrate exposed.06-18-2009
20090315190WIRING BOARD, SEMICONDUCTOR DEVICE USING WIRING BOARD AND THEIR MANUFACTURING METHODS - A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.12-24-2009
20090140442Wafer Level Package Integration and Method - In a wafer level chip scale package, a wafer level interconnect structure is formed on a dummy substrate with temperatures in excess of 200° C. First semiconductor die are mounted on the wafer level interconnect structure. The wafer level interconnect structure provides a complete electrical interconnect between the semiconductor die and one or more of the solder bumps according to the function of the semiconductor device. A second semiconductor die can be mounted to the first semiconductor die. A first encapsulant is formed over the semiconductor die. A second encapsulant is formed over the first encapsulant. The dummy substrate is removed. A first UBM is formed in electrical contact with the first conductive layer. Solder bumps are made in electrical contact with the first UBM. A second UBM is formed to electrically connect the semiconductor die to the wafer level interconnect structure.06-04-2009
20080265437Package Equipped with Semiconductor Chip and Method for Producing Same - A highly reliable, high-productivity package equipped with a semiconductor chip, and a method for producing the same. In a package (10-30-2008
20080265436Semiconductor for Device and Its Manufacturing Method - An object of the present invention is to provide a semiconductor device by packaging a plurality of semiconductor chips three-dimensionally in a smaller thickness, with a smaller footprint, at the lower cost without using any other components and through a simpler manufacturing process of the semiconductor device than with the conventional methods.10-30-2008
20080265435STRUCTURE AND METHOD FOR STRESS REDUCTION IN FLIP CHIP MICROELECTRONIC PACKAGES USING UNDERFILL MATERIALS WITH SPATIALLY VARYING PROPERTIES - A structure for a flip chip package assembly includes: a flip chip die with solder attach bumps; a substrate for receiving and solder attaching the flip chip die; an underfill material with spatially varying curing properties applied to fill voids between the flip chip die and the substrate, and for forming a fillet around the perimeter of the flip chip die and extending to the surface of the substrate; and wherein the portion of the underfill material forming the fillets is cured prior to curing the portion of the underfill material that fills the voids between the flip chip die and the substrate.10-30-2008
20090309239SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes a supporting board, a first semiconductor element mounted on a main surface of the supporting board; and an electronic component provided between the supporting board and the first semiconductor element; wherein the supporting board includes a concave part formed in a direction separated from the first semiconductor element; and at least a part of the electronic component is accommodated in the concave part.12-17-2009
20100007033METHOD FOR CONNECTING BETWEEN SUBSTRATES, FLIP-CHIP MOUNTING STRUCTURE, AND CONNECTION STRUCTURE BETWEEN SUBSTRATES - A resin containing a conductive particle and a gas bubble generating agent is supplied in a space between the substrates each having a plurality of electrodes. The resin is then heated to melt the conductive particle contained in the resin and generate gas bubbles from the gas bubble generating agent. A step portion is formed on at least one of the substrates. In the process of heating the resin, the resin is pushed aside by the growing gas bubbles, and as a result of that, the conductive particle contained in the resin is led to a space between the electrodes, and a connector is formed in the space. At the same time, the resin is led to a space between parts of the substrates at which the step portion is formed, and cured to fix the distance between the substrates.01-14-2010
20110062599INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base package substrate; mounting a flip chip integrated circuit die on the base package substrate; applying a flip chip protective layer on the flip chip integrated circuit die including covering only a back side of the flip chip integrated circuit die; and mounting an upper package on the base package substrate including positioning an upper package substrate adjacent to the flip chip protective layer.03-17-2011
20090174083WIRING BOARD AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC COMPONENT DEVICE USING THE WIRING BOARD AND METHOD OF MANUFACTURING THE SAME - A wiring board is provided with an external connection terminal to which an electrode terminal of an electronic component is to be connected. The external connection terminal is formed so that a portion thereof is electrically connected to a pad portion exposed from an outermost insulating layer on an electronic component mounting surface of a wiring board body and so that an air gap is kept between a portion of the external connection terminal, to which the electrode terminal of the electronic component is to be connected, and the insulating layer.07-09-2009
20090146318MULTILAYER WIRING BOARD AND SEMICONDUCTOR DEVICE - A multilayer wiring board includes: a substrate; connection pads arranged in a square grid fashion; and wiring patterns. Relationship between the connection pads and the wiring patterns satisfies: {(Ndl+1)P−d−s}/(w+s)>2Ndr+Ndl(a+1)+2a, wherein P is a pitch of the connection pads, d is a diameter of the connection pads, s is a minimum interval between the wiring patterns and is a minimum interval between the wiring pattern and the connection pad that are adjacent to each other, w is a minimum width of the wiring patterns, Ndl is the number of non-pad rows in each of the non-pad regions, Ndr is the number of non-pad columns in each of non-pad region, and a is an integer of (P−d−s)/(w+s).06-11-2009
20090273098Enhanced Architectural Interconnect Options Enabled With Flipped Die on a Multi-Chip Package - A particular chip is designed having a first variant (front side connected chip) of the chip and a second variant (back side connected chip). The first variant of the chip is attached to a carrier. The second variant of the chip is attached to the carrier inverted relative to the first variant of the chip. The first and second variants of the chip are attached to the carrier such that a vertical surface (side) of the first variant of the chip faces a corresponding vertical surface of the second variant of the chip. A circuit on the first variant of the chip is electrically connected to a corresponding circuit on the second variant of the chip.11-05-2009
20080211111INTEGRATED CIRCUIT PACKAGE SYSTEM WITH UNDERFILL - An integrated circuit package system includes: providing a package carrier; forming a first channel in the package carrier; mounting a first integrated circuit device over the package carrier and adjacent to the first channel; mounting a second integrated circuit device over the package carrier and adjacent to the first channel; and forming a contiguous underfill fillet with the first channel and under both the first integrated circuit device and the second integrated circuit device.09-04-2008
20090273097Semiconductor Component with Contact Pad - A structure and method of forming low cost bond pads is described. In one embodiment, the invention includes depositing an insulating layer over a last metal line of a substrate and forming an opening in the insulating layer. A colloid is printed over the insulating layer and fills the opening in the insulating layer. A conductive via and bond pads are formed by heating the colloid.11-05-2009
20090294992EMBEDDING DEVICE IN SUBSTRATE CAVITY - An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.12-03-2009
20090294991FLIP-CHIP INTERCONNECTION WITH FORMED COUPLINGS - A flip-chip electrical coupling between first and second electrical components (12-03-2009
20100102458SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE AND MANUFACTURING METHOD THEREFOR - A method of manufacturing a semiconductor package system includes: providing a first substrate; providing a second substrate having a cavity, the second substrate being attached to the first substrate; connecting the first substrate to the second substrate using an interconnect, the interconnect being in the cavity; and attaching a semiconductor device to the first substrate or the second substrate.04-29-2010
20080237891SEMICONDUCTOR DEVICE - A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.10-02-2008
20080237892Semiconductor device - A semiconductor device having a first rectangular chip on which wires, electrode pads and chip mounting area are provided, a first dame formed on the first rectangular chip around the electrode pads and the chip mounting area so as to cover the wires and an under fill formed by filling liquid resin between a second rectangular chip mounted on the chip mounting area in a flip-chip manner and the first rectangular chip.10-02-2008
20090283919SEMICONDUCTOR PACKAGE FEATURING FLIP-CHIP DIE SANDWICHED BETWEEN METAL LAYERS - Embodiments in accordance with the present invention relate to flip-chip packages for semiconductor devices, which feature a die sandwiched between metal layers. One metal layer comprises portions of the lead frame configured to be in electrical and thermal communication with various pads on a first surface of the die (e.g. IC pads or MOSFET gate or source pads) through a solder ball contact. The other metal layer is configured to be in at least thermal communication with the opposite side of the die. Embodiments of packages in accordance with the present invention exhibit superior heat dissipation qualities, while avoiding the expense of wire bonding. Embodiments of the present invention are particularly suited for packaging of power devices.11-19-2009
20080277803SEMICONDUCTOR DEVICE - A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.11-13-2008
20080277802Flip-chip semiconductor package and package substrate applicable thereto - A flip-chip semiconductor package structure and a package substrate applicable thereto are disclosed. The package substrate includes a body having at least a chip-attach area disposed thereon; a plurality of solder pads disposed in the chip-attach area and arranged at different intervals; and a fluid-disturbing portion disposed in the chip-attach area at a position where the solder pads are loosely arranged. A flip-chip semiconductor chip is mounted on the solder pads via conductive bumps and an underfill material is filled between the package substrate and the flip-chip semiconductor chip, the underfill material encapsulating the conductive bumps and the fluid-disturbing portion. By protrudingly disposing the fluid-disturbing portion at a position where the conductive bumps are loosely arranged, that is, the conductive bumps having bigger intervals therebetween, gap between the package substrate and the flip-chip semiconductor chip can be reduced so as to increase capillary attraction generated by capillary phenomenon, thereby balancing flow rate of the underfill material between the conductive bumps that are arranged at different intervals and thus avoiding problems of void formation, subsequent popcorn effect or delamination as encountered in the prior art.11-13-2008
20080284046Flip chip mounting method and bump forming method - A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a bump forming method are provided. After a resin 11-20-2008
20080246163Semiconductor Device - A semiconductor device (10-09-2008
20090014896Flip-chip package structure, and the substrate and the chip thereof - A flip-chip package structure is disclosed, which comprises: a packaging substrate having an upper surface and a plurality of conductive pads formed on the upper surface; a semiconductor chip having an active surface and a plurality of electrode pads formed on the active surface; and a plurality of first solder bumps; wherein each first solder bump connects to an electrode pad and a conductive pad, and each first solder bump contains a solid grain.01-15-2009
20090014897Semiconductor chip package and method of manufacturing the same - A semiconductor chip (01-15-2009
20100140812SEMICONDUCTOR DEVICE - Semiconductor device 06-10-2010
20090020890SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of the first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same.01-22-2009
20090160069Leadless alignment of a semiconductor chip - There is disclosed a mounting technique for mounting a semiconductor chip of the leadless or so-called flip chip type to a header. The header has an insert made of glass or other suitable non-conductive material within the header hollow. Mounted into the glass insert are a series of conductive metal pins which are placed in areas so that when a chip is mounted in the header, the chip makes contact with these conductive pins and allows one to make outside connections. Also positioned in the header are a series of nonconductive guide pins. These pins are placed in suitable positions in the header to enable one to contact the outside surfaces of the chip when the chip is placed in the header. In this manner, the chip is constrained from movement from side to side or from rotation. However, due to the positioning of the nonconductive pins within the header, it is possible to move the chip up and down while mounting.06-25-2009
20090140441Wafer Level Die Integration and Method - In a wafer level chip scale package (WLSCP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLSCP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs.06-04-2009
20090051047Semiconductor apparatus and method of manufacturing the same - There is provided a semiconductor apparatus which includes a substrate, a semiconductor chip mounted above the substrate, a first resin filled between the substrate and the semiconductor chip, and a second resin formed on the substrate and extending from a side surface of the semiconductor chip toward an outer edge of the substrate. The second resin extends from an intersection of an extension of the side surface of the semiconductor chip and the substrate toward the outer edge of the substrate so that a first stress generated on a contact surface between the first resin and the semiconductor chip and a second stress generated on a contact surface between the first resin or the second resin and the substrate balance out each other.02-26-2009
20090051048Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a carrier, a chip-bonding structure and a chip. The chip-bonding structure is formed on a first surface of the carrier. The chip-bonding structure includes a cavity, a dam, several via holes and several solder bumps. The solder bumps are received in the via holes and are correspond to the first connecting pads located on the carrier. The chip is embedded in the cavity of the chip-bonding structure. An active surface of the chip is tightly pasted on the first surface of the chip-bonding structure, and the first solder pads form electrical contact with the corresponding solder bumps. The chip of the package structure is precisely disposed on the carrier, not only simplifying the manufacturing process but also forming stable electrical connection between the chip and the carrier of the package structure.02-26-2009
20090065952Semiconductor Chip with Crack Stop - Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner.03-12-2009
20090102063Semiconductor package and method for fabricating the same - This invention provides a semiconductor package and a method for fabricating the same. The method includes: forming a first resist layer on a metal carrier; forming a plurality of openings penetrating the first resist layer; forming a conductive metal layer in the openings; removing the first resist layer; covering the metal carrier having the conductive metal layer with a dielectric layer; forming blind vias in the dielectric layer to expose a portion of the conductive metal layer; forming conductive circuit on the dielectric layer and conductive posts in the blind vias, such that the conductive circuit is electrically connected to the conductive metal layer via the conductive posts; electrically connecting at least one chip to the conductive circuit; forming an encapsulant for encapsulating the chip and the conductive circuit; and removing the metal carrier, thereby allowing a semiconductor package to be formed without a chip carrier. Given the conductive posts, both the conductive circuit and conductive metal layer are efficiently coupled to the dielectric layer to prevent delamination. Further, downsizing the blind vias facilitates the fabrication process and cuts the fabrication cost.04-23-2009
20090102064CONNECTION STRUCTURE AND METHOD OF PRODUCING THE SAME - A connection structure (package 04-23-2009
20110221074Board on chip package - A board on chip package including a photo solder resist having a cavity and a pattern on one side, the pattern corresponding to a circuit wire; a solder ball pad accommodated in the cavity; a circuit wire electrically connected with the solder ball pad, and formed on the other side of the photo solder resist; a semiconductor chip mounted on the solder ball pad by a flip chip bonding; and a passivation material to mold the semiconductor chip.09-15-2011
20090200684FLIP CHIP PACKAGE WITH SHELF AND METHOD OF MANUFACTGURING THERE OF - The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.08-13-2009
20090230566Method of underfill air vent for flipchip BGA - This invention relates to ejecting an underfill resin at multiple semiconductor die edges such that vacuum suction provided at a laminate through hole located beneath a stage enables spread of underfill resin from each edge simultaneously for quicker spread and reduction of voids. The excess underfill resin intentionally suctioned through the through hole air vent on the underside of the laminate is attracted to re-usable tape. The attracted underfill resin is cleaned from a rotating head mechanism by a cleaning pad positioned beneath a lower surface of the head.09-17-2009
20090218702METHODS FOR BONDING AND MICRO-ELECTRONIC DEVICES PRODUCED ACCORDING TO SUCH METHODS - One inventive aspect is related to a method of bonding two elements and micro-electronic devices produced according to such methods. In one aspect, a micro-electronic device includes a first and a second element, bonded together by a joining structure. The joining structure has a first micropattern portion, a second micropattern portion, and a joining portion in between the first and second micropattern portions. The first and second micropattern portions are made of cobalt. The joining portion includes intermetallic compounds of cobalt and tin (Sn).09-03-2009
20090212443INTEGRATED CIRCUIT PACKAGE SUBSTRATE HAVING CONFIGURABLE BOND PADS - Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate.08-27-2009
20080315437Tape wiring substrate and chip-on-film package using the same - A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.12-25-2008
20100264552CIRCUIT DEVICE, METHOD OF MANUFACTURING THE CIRCUIT DEVICE, DEVICE MOUNTING BOARD AND SEMICONDUCTOR MODULE - A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base. By allowing the fibrous filler projecting through the top surface of the resin layer to be in contact with the underfill, strength of adhesion between the underfill and the insulating base is improved.10-21-2010
20090250823Electronic Modules and Methods for Forming the Same - Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.10-08-2009
20090256268PARTIALLY UNDERFILLED SOLDER GRID ARRAYS - An electronic device and a method of forming the device. The device including a module having opposite top surface and bottom surfaces; a first set of pads on the top surface of the module and a second set of pads on the bottom surface of the module substrate, wires within the module electrically connecting the first set of pads to the second set of pads; a set of solder interconnects in electrical and physical contact with a the second set of module pads; and a dielectric underfill layer formed on the bottom surface of the module, the underfill layer filling the space between lower regions of the solder interconnects of the set of solder interconnects, upper regions of the solder interconnects of the set of solder interconnects extending past a top surface of the underfill layer.10-15-2009
20080230924SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE FOR USE THEREIN, AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate opening. The electrode of the semiconductor chip is electrically connected to the connecting pattern via wires through the elongate opening. The elongate opening and the wires are sealed with resin.09-25-2008
20090079094Solder Bump with Inner Core Pillar in Semiconductor Package - A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.03-26-2009
20100258952Interconnection of IC Chips by Flex Circuit Superstructure - Integrated circuit chips have top and bottom surfaces. The bottom surfaces comprise a plurality of IC die terminals in flip-chip assembly with fine-pitch terminals formed on the top surface of corresponding interconnection substrate. Each IC chip includes one or more through-silicon vias and/or edge wrap connectors that extend to the top surface, terminating in IC die terminals. Flexible connectors are coupled between the IC die terminals on the top surfaces of corresponding first and second integrated circuit chips. The flexible connectors are preferably controlled impedance, and may include differential pairs, including twisted pairs, coaxial pairs, and broadside pairs. Conductive vias within the interconnection substrates couple the fine-pitch terminals to corresponding next-level terminals on the bottom surface of the respective interconnection substrates. The next level terminals of the interconnection substrates are interconnected with terminals of a printed circuit board.10-14-2010
20100176516Substrate having optional circuits and structure of flip chip bonding - The present invention relates to a substrate having optional circuits and a structure of flip chip bonding. The substrate includes a substrate body, at least one substrate pad, a first conductive trace and a second conductive trace. The substrate body has a surface. The substrate pad is disposed on the surface of the substrate body. The first conductive trace is connected to a first circuit, and has a first breaking area so it forms a discontinuous line. The second conductive trace is connected to a second circuit, and has a second breaking area so tit forms a discontinuous line. The second conductive trace and the first conductive trace are connected to the same substrate pad. Thus, the substrate can choose to connect different circuits, so the substrate can be applied to different products by connecting the desired circuit, thus reducing the manufacturing cost.07-15-2010
20100001411METHOD FOR MUTUALLY CONNECTING SUBSTRATES, FLIP CHIP MOUNTING BODY, AND MUTUAL CONNECTION STRUCTURE BETWEEN SUBSTRATES - A resin containing conductive particles and a gas bubble generating agent is supplied between a first substrate and a second substrate, and then the resin is heated to generate gas bubbles from the gas bubble generating agent contained in the resin so that the resin is self-assembled between electrodes. Then, the resin is further heated to melt the conductive particles contained in the resin, thereby forming connectors between electrodes. A partition member sealing the gap between the substrates is provided near a peripheral portion of the resin, and gas bubbles in the resin are discharged to the outside through the peripheral portion of the resin where the partition member is absent.01-07-2010
20100193969DICING TAPE-INTEGRATED WAFER BACK SURFACE PROTECTIVE FILM - The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored with a dye contained therein. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.08-05-2010
20100225007INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED DIE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a flip chip die, having a backside protrusion; mounting a wire bond die on the flip chip die, adjacent to the backside protrusion; and mounting an internal stacking module over the backside protrusion and the wire bond die.09-09-2010
20100001410FLIP CHIP OVERMOLD PACKAGE - An integrated circuit (IC) package having a packaging substrate, an IC disposed onto the packaging substrate, and a rigid support member attached to the substrate layer through an adhesive spacer is provided. The packaging substrate includes multiple decoupling capacitors positioned thereon around the IC. A heat sink is placed over the IC. The rigid support member provides enhanced structural support for the IC packaging and there is ample space between a bottom surface of the rigid support member and the packaging substrate to allow the placement of the decoupling capacitors underneath the rigid support member.01-07-2010
20080230925SOLDER-BUMPING STRUCTURES PRODUCED BY A SOLDER BUMPING METHOD - A method for solder bumping provides a substrate and forms a film on the substrate. The film has openings therethrough. A stencil is aligned on the film. The stencil has openings therethrough over the openings through the film. Solder paste is printed onto the substrate and into the openings through the stencil and the openings through the film. The solder paste is reflowed to form solder balls therefrom. The stencil and the film are then removed.09-25-2008
20100252938SEMICONDUCTOR PACKAGE - A semiconductor package includes: a semiconductor element mounted on a one-sided plane of a wiring board; an underfill agent dropped so as to be filled between the semiconductor element and the wiring board; and a pad group constituted by a plurality of pads which are formed in the vicinity of a circumference of the wiring board and along the circumference, the pad group being formed on a bottom plane of a groove portion formed in a solder resist which covers the one-sided plane of the wiring board, wherein a corner edge of the groove portion located in the vicinity of a dropping starting portion to which dropping of the underfill agent is started is formed at an obtuse angle or in an arc shape in order to avoid the dropped underfill agent from entering into an inner portion of the groove portion.10-07-2010
20090127718FLIP CHIP WAFER, FLIP CHIP DIE AND MANUFACTURING PROCESSES THEREOF - The invention relates to a flip chip wafer comprising an active surface having a plurality of bumps (05-21-2009
20090146317PACKAGE SUBSTRATE HAVING ELECTRICALLY CONNECTING STRUCTURE - A package substrate having an electrically connecting structure are provided. The package substrate include: a package substrate substance with at least a surface having a plurality of electrically connecting pads formed thereon, allowing an insulating protective layer to be formed on the surface of the package substrate substance and the electrically connecting pads and formed with a plurality of openings corresponding in position to the electrically connecting pads so as to expose a portion of the electrically connecting pads, respectively; and a metal layer provided on an exposed portion of the electrically connecting pads, walls of the openings of the insulating protective layer, and a circular portion of the insulating protective layer encircling each of the openings thereof, and provided with a slope corresponding in position to a bottom rim of each of the openings. Accordingly, solder bleeding and short circuits are prevented.06-11-2009
20090039530NEAR CHIP SCALE PACKAGE INTEGRATION PROCESS - Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.02-12-2009
20090039531Flip-chip package covered with tape - A manufacturing method of a semiconductor device includes arranging a melted resin on a substrate, arranging a semiconductor chip on the melted resin, pressing the semiconductor chip and flip-chip mounting the semiconductor chip on the substrate, and hardening the melted resin with the melted resin being subjected to a fluid pressure and forming a resin portion.02-12-2009
20090039529Integrated Circuit Having a Plurality of Connection Pads and Integrated Circuit Package - In accordance with an embodiment of the invention, an integrated circuit including a plurality of connection pads is provided, wherein a first connection pad is configured in accordance with a first contacting technology, and wherein a second connection pad is configured in accordance with a second contacting technology. The second contacting technology is different from the first contacting technology.02-12-2009
20080308951Semiconductor package and fabrication method thereof - A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes providing a carrier board; forming a plurality of metal bumps on the carrier board; covering on the carrier board a resist layer having openings for exposure of the metal bumps, the openings being smaller than the metal bumps in width such that a metal layer is formed in the openings, the metal layer having extension circuits and extension pads and bonding pads formed on respective ends of the extension circuits; removing the resist layer; electrically connecting at least one semiconductor chip to the bonding pads; forming an encapsulant on the carrier board to encapsulate the semiconductor chip; and removing the carrier board and the metal bumps to expose the metal layer. Therefore, the extension pads of the exposed metal layer can be electrically connected to an external device through a conductive material in subsequent processes, and the extension circuits can be disposed flexibly in accordance with the degree of integration of the chip, so as to reduce the electrical connection path between the chip and the extension circuits.12-18-2008
20090115072BGA Package with Traces for Plating Pads Under the Chip - A semiconductor flip-chip ball grid array package (05-07-2009
20090115071FLIP CHIP MOUNTING METHOD AND METHOD FOR CONNECTING SUBSTRATES - A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a method for connecting substrates are provided. A circuit board 10 having a plurality of connecting terminals 11 and a semiconductor chip 20 having a plurality of electrode terminals 21 are disposed in mutually facing relation and a resin 13 containing conductive particles 12 and a gas bubble generating agent is supplied into the space therebetween. In this state, the resin 13 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the resin 13. The resin 13 is pushed toward the outside of the generated gas bubbles 30 by the growth thereof. The resin 13 pushed to the outside is self-assembled in the form of columns between the respective terminals of the circuit board 10 and the semiconductor chip 20. In this state, by pressing the semiconductor chip 20 against the circuit board 10, the conductive particles 12 contained in the resin 13 self-assembled between the facing terminals are brought into contact with each other to provide electrical connection between the terminals.05-07-2009
20100301497DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE - The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface has a multilayered structure including a wafer adhesion layer and a laser mark layer, the wafer adhesion layer is formed of a resin composition containing a thermosetting resin component and, as an optional component, a thermoplastic resin component in an amount of less than 30% by weight relative to the whole amount of resin components, and the laser mark layer is formed of a resin composition containing a thermoplastic resin component in an amount of 30% by weight or more relative to the whole amount of resin components and, as an optional component, a thermosetting resin component.12-02-2010
20110001250METHOD AND STRUCTURE FOR ADHESION OF INTERMETALLIC COMPOUND (IMC) ON CU PILLAR BUMP - A method and structure for good adhesion of Intermetallic Compounds (IMC) on Cu pillar bumps are provided. The method includes depositing Cu to form a Cu pillar layer, depositing a diffusion barrier layer on top of the Cu pillar layer, and depositing a Cu cap layer on top of the diffusion barrier layer, where an intermetallic compound (IMC) is formed among the diffusion barrier layer, the Cu cap layer, and a solder layer placed on top of the Cu cap layer. The IMC has good adhesion on the Cu pillar structure, the thickness of the IMC is controllable by the thickness of the Cu cap layer, and the diffusion barrier layer limits diffusion of Cu from the Cu pillar layer to the solder layer. The method can further include depositing a thin layer for wettability on top of the diffusion barrier layer prior to depositing the Cu cap layer.01-06-2011
20100133704Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias - A semiconductor device is fabricated by providing a carrier for supporting the semiconductor device. A first semiconductor die is mounted to the carrier. The first semiconductor die has a contact pad. A first dummy die is mounted to the carrier. The first dummy die has a through-silicon via (TSV). The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. A first interconnect structure is formed over the first semiconductor die and the first dummy die. The first interconnect structure is connected to the contact pad of the first semiconductor die and the TSV of the first dummy die. The carrier is removed and a second interconnect structure is formed over the first semiconductor die and the first dummy die. The second interconnect structure is connected to the TSV of the first dummy die. A semiconductor package is connected to the second interconnect structure.06-03-2010
20110115099Flip-chip underfill - A method for flip-chip interconnection includes applying a dielectric film onto the active side of the die, or onto the die mount side of the substrate, or both onto the die and onto the substrate; then orienting and aligning the die in relation to the substrate, and moving the die toward the substrate so that interconnect contact is made; then treating the assembly (for example by heating or by heating and pressing) to complete the electrical connections and to cause the film to soften and to adhere. Also, a method for flip-chip assembly includes completing electrical connection of the flip-chip interconnects on a die with bond pads on a substrate and thereafter exposing the assembly to a CVD process to fill the headspace between the die and the substrate with a dielectric material. Also, a flip-chip assembly is made by the method. Also, a die or a substrate is prepared for flip-chip interconnection by applying a dielectric film on a surface thereof.05-19-2011
20110241221SEMICONDUCTOR DEVICE WITH IMPROVED RESIN CONFIGURATION - A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.10-06-2011
20100193968DICING TAPE-INTEGRATED WAFER BACK SURFACE PROTECTIVE FILM - The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.08-05-2010
20110084406DEVICE AND INTERCONNECT IN FLIP CHIP ARCHITECTURE - The present invention discloses a device in flip chip architecture. The device comprises at least two integrated circuits, which are interconnected by a passive device. The integrated circuits are mounted on a base ground plate, and are each connected to the passive device via conductive elements.04-14-2011
20090085227FLIP-CHIP MOUNTING BODY AND FLIP-CHIP MOUNTING METHOD - A flip chip mounting body in which a circuit substrate having a plurality of connection terminals and an electronic part (semiconductor chip) having a plurality of electrode terminals are aligned face to face with each other, with a resin composition composed of solder powder, a resin and a convection additive being sandwiched in between, while a means such as spacers is interposed in between so as to provide a uniform gap between the two parts, or the electronic part (semiconductor chip) is placed inside a plate-shaped member having two or more protruding portions, so that the solder powder is allowed to move through boiling of the convection additive and to be self-aggregated to form a solder layer, thereby electrically connecting the connection terminals and the electrode terminals; and a mounting method for such a mounting body.04-02-2009
20110147951WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate includes a wiring layer, an insulating layer formed on the wiring layer, a connection pad formed on the insulating layer, and a via conductor formed to penetrate the insulating layer, and connecting the wiring layer and the connection pad, wherein the wiring layer located under the connection pad is formed to have via receiving electrode portion whose area is smaller than an area of the connection pad, and a wiring portion separated from the via receiving electrode portion, in an area corresponding to the connection pad, and the via receiving electrode portion is connected to the connection pad via the via conductor.06-23-2011
20110147950METALLIZATION LAYER STRUCTURE FOR FLIP CHIP PACKAGE - The present invention discloses a metallization layer structure for flip chip package, which comprises an UBM layer formed on a metal pad, whereby a fine-quality tin-based solder ball can be formed on the metal pad. The UBM layer is a NiZnP layer formed via the reduction and oxidization of a solution containing nickel sulfate (Ni06-23-2011
20090218701INDUCTIVELY COUPLED INTEGRATED CIRCUIT WITH MAGNETIC COMMUNICATION PATH AND METHODS FOR USE THEREWITH - An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit.09-03-2009
20100025863Integrated Circuit Interconnect Method and Apparatus - Techniques for interconnecting an IC chip and a receiving substrate are provided. A method includes the steps of: providing the IC chip, the IC chip including at least a first connection site formed thereon; providing the receiving substrate, the receiving substrate including at least a second connection site formed thereon; forming an alloy structure on at least a portion of an upper surface of the second connection site; orienting the IC chip relative to the receiving substrate so that the at least first connection site is aligned with the alloy deposit formed on the at least second connection site; and forming an electrical connection between the first and second connection sites, the electrical connection comprising a volume of electrically conductive fusible material, wherein a majority of the volume of electrically conductive fusible material is supplied from the alloy structure.02-04-2010
20090321961Method of Packaging a Die - A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads.12-31-2009
20110101542INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.05-05-2011
20090152742Method of manufacturing semiconductor package and semiconductor plastic package using the same - A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.06-18-2009
20110068482SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor chip includes a plurality of electrode terminals having a fixed terminal which is supplied with a signal, an outside terminal for the signal being fixed when the semiconductor chip is mounted in both a face-up configuration and a face-down configuration on a package substrate that has the outside terminal, and which is arranged within 50% of the width of the semiconductor chip with a symmetric line of the semiconductor chip as a center. According to the present invention, it is possible to reduce the variation of the wiring delays of the fixed terminal and to keep the wiring routes from being complicated, when the semiconductor chip is mounted in both the face-up configuration and the face-down configuration.03-24-2011
20090026634ELECTRONIC PART MOUNTING STRUCTURE AND ITS MANUFACTURING METHOD - An electronic part mounting structure includes electronic part (01-29-2009
20090026633Flip chip package structure and method for manufacturing the same - A flip chip package structure and a method for manufacturing the same are disclosed. The method for manufacturing a flip chip package structure comprises following steps: (a) providing a semiconductor chip including a plurality of electrode pads and a plurality of first solders, and providing a packaging substrate having a plurality of conductive pads and a plurality of second solders (b) forming a resin adhesive layer on the active surface of the semiconductor chip, and the first solders are exposed from the resin adhesive layer; (c) assembling the packaging substrate and the semiconductor chip with the resin adhesive layer formed thereon to form an assembly unit; and (d) reflow soldering the assembly unit to fuse the first solders of the semiconductor chip with the second solders of the packaging substrate to form fused solders, and the packaging substrate is adhered with the resin adhesive layer.01-29-2009
20110042830CHIP CARD, AND METHOD FOR THE PRODUCTION THEREOF - A chip card in the form of an ID-1 card, a plug-in SIM or a USB token comprises a layered compound (02-24-2011
20100308474SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A substrate (12-09-2010
20090001606SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor package 01-01-2009
20090001604Semiconductor Package and Method for Producing Same - An oxide layer and a metal layer composed of a gold- or platinum-group metal are formed in the stated order on a substrate. A wiring body having a wiring layer, insulating layer, via, and electrode is formed on the metal layer. A semiconductor element is then connected as a flip chip via solder balls on the wiring body electrode, and underfill is introduced between the semiconductor element and the wiring body. Subsequently, a sealing resin layer is formed so as to cover the semiconductor element and the surface of the wiring body on which the semiconductor element is mounted, thus producing a semiconductor package. A high-density, detailed, thin semiconductor package can thereby be realized.01-01-2009
20090001605SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same. The semiconductor package includes a substrate having connection pads formed on one surface thereof, a semiconductor chip having bonding pads formed on one surface thereof to correspond to the connection pads; bumps for electrically connecting the connection pads and the bonding pads with each other, a coating layer located on exposed surface portions of the bonding pads and the connection pads to prevent voids from being formed in spaces between the substrate and the semiconductor chip, and an underfill member filled in the spaces over the coating layer.01-01-2009
20090001603High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line structure mainly includes: two boards with similar structures and a dielectric film for combing the two boards. Semiconductor devices respectively in two boards are opposite to each other after the two boards are combined. The two boards each include a fine line circuit, an insulated layer on the same surface, and the semiconductor device installed above the fine line circuit. The surface of the circuit, which is not covered by a solder mask, is made into a pad. The pad is filled with the tin balls for electrically connecting with another semiconductor device. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density.01-01-2009
20100244279Liquid resin composition for underfill, flip-chip mounted body and method for manufacturing the same - The invention relates to a liquid resin composition for underfill comprising (A) an epoxy resin, (B) an amine-based curing agent, and (C) an inorganic filler, a viscosity at a temperature of 25° C. being 1 to 150 Pa·s, and a time required for the viscosity to become 1 Pa·s at a temperature of 100° C. being 40 to 180 minutes.09-30-2010
20100244278STACKED MULTICHIP PACKAGE - A stacked multichip package comprises a first chip having a first active surface and a first rear surface, a first chip carrier having a first opening and being configured to carrier the first active surface, a plurality of first conductive leads passing through the first opening and being configured to electrically connect the first active surface and the first chip carrier, a second chip having a second active surface and a second rear surface, an adhesive layer configured to enclose the first conductive leads and to electrically couple the first chip carrier to the second rear surface, a second chip carrier having a second opening and being electrically connected to the second active surface, and a plurality of conductive leads passing through the second opening and being configured to electrically connect the second active surface and the second chip carrier.09-30-2010
20100244277INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a sacrificial carrier assembly having a stack interconnector thereover; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit with the underfill material substantially free of a void; encapsulating the integrated circuit over the sacrificial carrier assembly and the underfill material; exposing the stack interconnector by removing the sacrificial carrier assembly; and forming a base array over the underfill material and the stack interconnector.09-30-2010
20080308949FLIP CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A flip chip package realizes a fine pitch and improves the reliability of a bump joint and a method for manufacturing the same. The flip chip package includes a printed circuit board having a plurality of electrode terminals on one surface thereof; a semiconductor chip located on the printed circuit board in a face-down type and having a plurality of bonding pads; conductive polymers for electrically and mechanically connecting the bonding pads of the semiconductor chip and the electrode terminals of the printed circuit board with each other; and an encapsulant for molding one surface of the printed circuit board including the conductive polymers and the semiconductor chip.12-18-2008
20090085226METHOD AND ARRANGEMENT FOR CONTACT-CONNECTING SEMICONDUCTOR CHIPS ON A METALLIC SUBSTRATE - The method comprises the following steps: the substrate in the form of a one-piece basic substrate (04-02-2009
20110175237SEMICONDUCTOR DEVICE, FLIP-CHIP MOUNTING METHOD AND FLIP-CHIP MOUNTING APPARATUS - A semiconductor chip (07-21-2011
20110254176DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE - The present invention provides a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer on the base material; and a film for flip chip type semiconductor back surface, which is provided on the pressure-sensitive adhesive layer, in which at least a part of the pressure-sensitive adhesive layer has been cured beforehand by irradiation with a radiation ray.10-20-2011
20080251942Semiconductor Device and Manufacturing Method Thereof - Electrode pads (10-16-2008
20080251943FLIP CHIP WITH INTERPOSER, AND METHODS OF MAKING SAME - A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material.10-16-2008
20080251944SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor chip bonded to external connection pads or external connection terminals by flip-chip bonding and an underfill resin, and provides a semiconductor device which enables to lessen the warpage attributable to the underfill without involvement of an increase in the size of the semiconductor device. A low elastic resin member is disposed opposite to a surface of a semiconductor chip on which a plurality of electrode pads are formed, and an underfill resin is filled between the semiconductor chip and the low elastic resin member and between electrode pads and external connection pads.10-16-2008
20100320622ELECTRONIC COMPONENT BUILT-IN WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - In an electronic component built-in wiring substrate, an electronic component is mounted on a first wiring substrate. A second wiring substrate is stacked on the first wiring substrate and is connected electrically to the first wiring substrate by connection terminals. The second wiring substrate has an opening portion of a size larger than a planar area of the electronic component. An underfill resin is filled in a first space between the first wiring substrate and the electronic component, and has a raised portion which is raised along an outer peripheral side surface of the electronic component, seals a clearance between an inner peripheral edge of the opening portion and an outer peripheral edge of the electronic component and supports the second wiring substrate. A sealing resin is filled in a second space between the first and second wiring substrates.12-23-2010
20100148374METHOD FOR LOW STRESS FLIP-CHIP ASSEMBLY OF FINE-PITCH SEMICONDUCTOR DEVICES - A device including a first body (06-17-2010
20100148376FLIP CHIP MOUNTING PROCESS AND FLIP CHIP ASSEMBLY - A flip chip mounting process includes the steps of supplying a resin (06-17-2010
20100117245INTEGRATED CIRCUIT PACKAGE SUBSTRATE HAVING CONFIGURABLE BOND PADS - Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate.05-13-2010
20100117244Semiconductor device and manufacturing method therefor - The present invention can avoid spaces not filled with resin by using simplified procedures and configuration even when multiple semiconductor chips are stacked, creating an overhanging portion. A semiconductor device 05-13-2010
20110079926Method of manufacturing substrate for flip chip and substrate for flip chip manufactured using the same - There is provided a method of manufacturing a substrate for flip chip, and a substrate for flip chip manufactured using the same. The method includes providing a base substrate including at least one conductive pad, forming a solder resist layer on the base substrate, the solder resist layer including a first opening exposing the conductive pad, forming a dry film on the solder resist layer, the dry film including a second opening connected with the first opening, forming a metal post in the first opening and a part of the second opening, filling the second opening above the metal post with solder paste, forming a solder cap by performing a reflow process on the filled solder paste, planarizing a surface of the solder cap, and removing the dry film. Accordingly, fine pitches and improve reliability can be achieved.04-07-2011
20110079925Flip Chip Interconnect Method and Design For GaAs MMIC Applications - A monolithic microwave integrated circuit (MMIC) flip chip interconnect is formed by coating an active side of the chip with a dielectric coating, such as benzocyclobutene (BCB), that inhibits deposition of metal plating materials. A portion of the dielectric coating is removed to expose bond pads on the active side of the chip, stud bumps are bonded to the bond pads, and the active side is then plated with first and second consecutive metal plating materials, such as nickel and gold, respectively, that do not adhere to the dielectric coating. The chip is then oriented such that the plated stud bumps on the active side of the chip face bond pads on a substrate, and the stud bumps on the chip are bonded to the bond pads on the substrate.04-07-2011
20100155965SEMICONDUCTOR DEVICE - A semiconductor device includes: the mounting surface of the wiring substrate exposed from the semiconductor element is covered by a solder-resist layer, a part of the solder-resist layer covering the mounting surface of the wiring substrate at a dropping-commencing point at which dropping of a liquid-state under-filling agent filled in a gap between the semiconductor element and the mounting surface of the wiring substrate is commenced is extended in an area of the wiring substrate covered by the semiconductor element, and a gap between the semi conductor element at the dropping-commencing point and the vicinity thereof and an extension portion of the solder-resist layer is formed to be narrower than the gap between the semi conductor element and the mounting surface of the wiring substrate so that liquid drops of the under-filling agent dropped at the dropping-commencing point are sucked into the gap by a capillary phenomenon.06-24-2010
20110260338Semiconductor Device and Method of Forming Adjacent Channel and DAM Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material - A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel.10-27-2011
20080217793METHOD AND DEVICE INCLUDING REWORKABLE ALPHA PARTICLE BARRIER AND CORROSION BARRIER - A method and device comprising an easily reworkable alpha particle barrier is provided. The easily reworkable alpha particle barrier is applied in the space between the surface of the chip and the surface of the substrate, and reduces soft error rate (SER). Further, the easily reworkable alpha particle barrier material is chosen from the group of an organic material, a hydrocarbon, more specifically a polyalphaolefin (PAO) oil, and a polymer or filled polymer; wherein the polyalphaolefin oil has a viscosity below 1000 cSt (at 100° C.). The easily reworkable alpha particle barrier material can be used with multichip modules (MCM's) allowing easy device rework of one or more dies without affecting other dies on the same substrate.09-11-2008
20100025862Integrated Circuit Interconnect Method and Apparatus - Techniques for interconnecting an IC chip and a receiving substrate are provided. A method includes the steps of: providing the IC chip, the IC chip including at least a first connection site formed thereon; providing the receiving substrate, the receiving substrate including at least a second connection site formed thereon; forming an alloy structure on at least a portion of an upper surface of the second connection site; orienting the IC chip relative to the receiving substrate so that the at least first connection site is aligned with the alloy deposit formed on the at least second connection site; and forming an electrical connection between the first and second connection sites, the electrical connection comprising a volume of electrically conductive fusible material, wherein a majority of the volume of electrically conductive fusible material is supplied from the alloy structure.02-04-2010
20080265438LIQUID EPOXY RESIN COMPOSITION AND SEMICONDUCTOR DEVICE - A liquid epoxy resin composition comprising (A) a liquid epoxy resin, (B) a curing agent, (C) an inorganic filler, (D) a hygroscopic agent, and optionally, (E) a fluxing agent has the advantages of void-free fill, shelf stability and solder connection, and is thus advantageously used in the fabrication of flip chip semiconductor devices by the no-flow method.10-30-2008
20100193967DICING TAPE-INTEGRATED WAFER BACK SURFACE PROTECTIVE FILM - The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored, and the colored wafer back surface protective film has an elastic modulus (23° C.) of 3 GPa or more. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.08-05-2010
20110074046PRINTED WIRING BOARD AND MANUFACTURING METHOD THEREOF - A printed wiring board is configured to be connected to an organic substrate in a state where a semiconductor chip is mounted thereon. A plurality of first layers are formed of a material having the same coefficient of thermal expansion as the semiconductor chip. A plurality of second layers are formed of a material having the same coefficient of thermal expansion as the organic substrate. The first layers have different thicknesses from each other and the second layers have different thicknesses from each other. The first layers and the second layers form a lamination by being laminated alternately one on another. The thicknesses of the first layers decrease from a side where the semiconductor chip is mounted toward a side where the organic substrate is connected. The thicknesses of the second layers decrease from the side where the organic substrate is connected toward the side where the semiconductor chip is mounted.03-31-2011
20100193970MICRO PIN GRID ARRAY WITH PIN MOTION ISOLATION - A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.08-05-2010
20110304059CIRCUIT BOARD, CIRCUIT BOARD ASSEMBLY, AND SEMICONDUCTOR DEVICE - A disclosed circuit board includes a substrate, a plurality of electrode pads formed on the substrate, and a groove formed between adjacent electrode pads on the substrate. Further, the electrode pads are surrounded by the groove to have an air space between the adjacent electrode pads.12-15-2011
20110304058Semiconductor Device and Method of Forming Flipchip Interconnection Structure with Bump on Partial Pad - A semiconductor device has a semiconductor die having a plurality of bumps formed over a surface of the semiconductor die. The bumps can include a fusible portion and non-fusible portion. Conductive traces are formed over the substrate with interconnect sites having an exposed sidewall and sized according to a design rule defined by SRO+2*SRR−2X, where SRO is an opening over the interconnect site, SRR is a registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The bumps are misaligned with the interconnect sites by a maximum distance of X which ranges from 5 to 20 microns. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.12-15-2011
20090278263RELIABILITY WCSP LAYOUTS - An integrated circuit device includes a functional circuit die with a patterned rewiring layer defining a first rewiring pad and one or more second rewiring pads on opposite sides of a neutral point of the die. The device also includes at least one dielectric layer having bump opening features over the rewiring pads. The device further includes electrically conductive bump pad features formed on the dielectric layer over the bump opening features. The bump pad features make contact with the rewiring pads via the bump opening features. In the device, a center of the bump opening features are laterally offset from a center of the bump pad feature towards a neutral point of the die.11-12-2009
20120043672Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate - A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.02-23-2012
20090079093FLIP CHIP STRUCTURE AND METHOD OF MANUFACTURE - A flip chip structure includes glass stand-offs formed overlying a substrate surface. A conductive layer is formed overlying the glass stand-offs and configured for attaching to a next level of assembly. In one embodiment, photo glass processing is used to form the glass stand-offs.03-26-2009
20110156280DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE - The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which a peel force (temperature: 23° C., peeling angle: 180°, tensile rate: 300 mm/min) between the pressure-sensitive adhesive layer of the dicing tape and the film for flip chip type semiconductor back surface is from 0.05 N/20 mm to 1.5 N/20 mm.06-30-2011
20110156277DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE - The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface contains a black pigment.06-30-2011
20110156279FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE - The present invention provides a film for flip chip type semiconductor back surface, which is to be formed on a back surface of a semiconductor element flip-chip connected on an adherend, the film including a wafer adhesion layer and a laser marking layer, in which the wafer adhesion layer has a light transmittance of 40% or more in terms of a light having a wavelength of 532 nm and the laser marking layer has a light transmittance of less than 40% in terms of a light having a wavelength of 532 nm.06-30-2011
20110156276Patch on interposer assembly and structures formed thereby - Methods of forming microelectronic structures are described. Embodiments of those methods include attaching a patch structure to an interposer by thermal compression bonding, forming an underfill around an array of interconnect structures disposed on a top surface of the interposer, curing the underfill, and then attaching a die to the patch structure.06-30-2011
20110156278FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE - The present invention provides a film for flip chip type semiconductor back surface, which is to be formed on a back surface of a semiconductor element flip-chip connected on an adherend, the film including a wafer adhesion layer and a laser marking layer, in which the wafer adhesion layer has an elastic modulus (at 50° C.) of 10 MPa or less and the laser marking layer has an elastic modulus (at 50° C.) of 100 MPa or more.06-30-2011
20120007259LATENT HARDENER WITH IMPROVED BARRIER PROPERTIES AND COMPATIBILITY - A curing agent for epoxy resins that is comprised of the reaction product of an amine, an epoxy resin, and an elastomer-epoxy adduct; compositions containing the curing agent and an epoxy resin; the compositions are useful in electronic displays, circuit boards, semi conductor devices, flip chips and other applications.01-12-2012
20120056336SEMICONDUCTOR PACKAGE FOR CONTROLLING WARPAGE - A semiconductor structure having a ring. The semiconductor structure includes a substrate, at least one chip, and the ring. The substrate has a first surface. The chip is located on the first surface of the substrate and electrically connected to the substrate. The ring has a first portion and a second portion. In various embodiments, the first and second portions different coefficients of thermal expansion (CTE), and or different cross-sectional widths. In another embodiment, the ring includes a third portion having a CTE different from both the first and second CTEs.03-08-2012
20120153506WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A wiring substrate includes a plurality of connection pads, and a protection insulating layer in which opening portion exposing said plurality of connection pads collectively is provided, wherein a notched opening portion is provided to a sidewall of the opening portion of the protection insulating layer in area between said plurality of connection pads. When a semiconductor chip is flip-chip connected to the connection pads by the prior sealing technology, a void occurring in the sealing resin is trapped in the notched opening portion.06-21-2012
20120205820ENCAPSULATING RESIN SHEET AND SEMICONDUCTOR DEVICE USING THE SAME, AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR DEVICE - Provided are an encapsulating resin sheet having improved a connection reliability by improving a connection failure, and by suppressing intrusion of an inorganic filler between terminals of the semiconductor element and the interconnection circuit substrate, a semiconductor device using the same, and a fabricating method for the semiconductor device. The encapsulating resin sheet is an epoxy resin composition sheet having a two-layer structure of an inorganic filler containing layer and an inorganic filler non-containing layer, in which a melt viscosity of the inorganic filler containing layer is 1.0×1008-16-2012
20120025399FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE, AND ITS USE - The present invention relates to a film for flip chip type semiconductor back surface, which is to be disposed on the back surface of a semiconductor element to be flip chip-connected onto an adherend, the film containing a resin and a thermoconductive filler, in which the content of the thermoconductive filler is at least 50% by volume of the film, and the thermoconductive filler has an average particle size relative to the thickness of the film of at most 30% and has a maximum particle size relative to the thickness of the film of at most 80%.02-02-2012
20120025400FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE, DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, AND FLIP CHIP TYPE SEMICONDUCTOR DEVICE - The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.02-02-2012
20120061855INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a substrate bottom side and a substrate top side opposite the substrate bottom side; mounting an integrated circuit over the package substrate, the integrated circuit having an inactive side and an active side opposite the inactive side; connecting stack connectors to the substrate top side; applying a multi-layer film over the substrate top side, the integrated circuit, and the stack connectors, the multi-layer film having a base film layer, a penetrable film layer, and a penetrable adhesive; removing the base film layer and the penetrable film layer to expose the penetrable adhesive and exposed portions of the stack connectors; and forming an adhesive film layer by hardening the penetrable adhesive.03-15-2012
20120061853SEMICONDUCTOR CHIP DEVICE WITH UNDERFILL - A method of manufacturing is provided that includes placing a removable cover on a surface of a substrate. The substrate includes a first semiconductor chip positioned on the surface. The first semiconductor chip includes a first sidewall. The removable cover includes a second sidewall positioned opposite the first sidewall. A first underfill is placed between the first semiconductor chip and the surface wherein the second sidewall provides a barrier to flow of the first underfill. Various apparatus are also disclosed.03-15-2012
20110089577METHOD AND STRUCTURE FOR BONDING FLIP CHIP - Provided is a method and structure for bonding a flip chip while increasing the manufacturing yield. In the method, solder bumps are formed on first electrodes and/or second electrodes disposed on first and second substrates, respectively. In addition, the first and second electrodes are arranged to face each other with a second resin including spacer balls being disposed between the first and second substrates. In addition, while flowing the second resin, the first and second substrates are pressed until the distance between the first and second substrates is decreased smaller than diameter of the spacer balls so as to connect the solder bumps between the first and second electrodes.04-21-2011
20120119388Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die - A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.05-17-2012
20100207279SEMICONDUCTOR PACKAGE WITH RIBBON WITH METAL LAYERS - A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a ribbon. The ribbon includes a first metal layer and a second metal layer. The first metal layer is welded to the first chip and the second metal layer is attached to the second chip.08-19-2010
20110180938ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - In an electronic device, a silicone adhesive bonding first and second members is made from a composition comprising: (A) 100 parts by mass of an organopolysiloxane containing in one molecule at least two alkenyl groups and being free of silicon-bonded hydroxyl and alkoxy groups wherein the content of cyclic siloxanes having 4 to 20 siloxane units is at most 0.1 mass %; (B) an organopolysiloxane containing in one molecule at least two silicon-bonded hydrogen atoms and being free of an alkenyl group, and silicon-bonded hydroxyl and alkoxy groups; (C) at least 0.05 parts by mass of an adhesion promoter; (D) 100 to 2000 parts by mass of a thermally conductive filler; and (E) a hydrosilylation-reaction catalyst. (B) is contained such that the silicon-bonded hydrogen atoms is in the range of 0.5 to 10 mol per 1 mol of the alkenyl groups of (A), and the sum of (B) and (C) is 0.5 to 10 mass % of the sum of (A), (B) and (C).07-28-2011
20090057922Semiconductor device, method of manufacturing the semiconductor device, flip chip package having the semiconductor device and method of manufacturing the flip chip package - A semiconductor device can include a semiconductor chip, a protective layer pattern, an under bump metallurgy (UBM) layer, and conductive bumps. The semiconductor chip can include a pad and a guard ring. The protective layer pattern can be formed on the semiconductor chip to expose the pad and the guard ring. The UBM layer can be formed on the protective layer and can directly make contact with the pad and the guard ring. The conductive bumps can be formed on a portion of the UBM layer on the pad. Thus, the UBM layer and the guard ring can directly make contact with each other, so that a uniform current can be provided to the UBM layer on the pad regardless of a thick difference of different portions of the UBM layer.03-05-2009
20090057921FLIP CHIP FOR ELECTRICAL FUNCTION TEST AND MANUFACTURING METHOD THEREOF - Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.03-05-2009
20090057920LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit.03-05-2009
20120168967THREE DIMENSIONAL STACKED CHIP PACKAGE STRUCTURE - This disclosure related to a stacked chip package structure having a sloped dam structure located on the substrate and beside the chip stack. The dam structure can facilitate the dispensing process of the underfill.07-05-2012
20100052188Semiconductor Chip with Solder Joint Protection Ring - Various semiconductor chip arrangements and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip that has an external peripheral wall to a first side of a substrate. A first metallic ring is coupled to the first side of the substrate. The first metallic ring has an internal peripheral wall that frames the semiconductor chip and is separated from the external peripheral wall by a gap. The first metallic ring has a coefficient of thermal expansion less than about 6.0 1003-04-2010
20100052189ELECTRONIC COMPONENT MOUNTING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - Electronic component mounting structure (03-04-2010
20090096113SOI on Package Hypersensitive Sensor - A hypersensitive semiconductor die structure is disclosed, in which flip-chip packaging is used in conjunction with a modified SOI die in which a thick silicon support substrate has been removed to increase sensitivity of the sensing device. Rather than being located beneath layers of interconnects and dielectric, the disclosed structure places the sensing devices close to the surface, more closely exposed to the environment in which sensing is to occur. The structure also allows for the placement of sensing films on nearer to the sensing devices and/or an oxide layer overlying the sensing devices.04-16-2009
20120175786METHOD OF POST-MOLD GRINDING A SEMICONDUCTOR PACKAGE - A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB.07-12-2012
20120074596SET OF RESIN COMPOSITIONS FOR PREPARING SYSTEM-IN-PACKAGE TYPE SEMICONDUCTOR DEVICE - Set of compositions for preparing system-in-package type semiconductor device. The composition set consists of underfill composition for preparing underfill part and encapsulation resin composition for preparing resin encapsulation part. 1) A cured product of the underfill composition has a glass transition temperature, Tg, ≧100° C. and is the same with or differs from a Tg of a cured product of the encapsulation resin composition by ≦20° C. 2) Total linear expansion coefficient of the cured product of the underfill composition at a temperature not higher than (Tg−30)° C. and a linear expansion coefficient of the cured product of the encapsulation resin composition at a temperature not higher than (Tg−30)° C. is ≦42 ppm/° C. 3) A ratio of the linear expansion coefficient of the cured product of the encapsulation resin composition to the linear expansion coefficient of the cured product of the underfill composition ranges from 0.3 to 1.0.03-29-2012
20120256322SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.10-11-2012
20120187579LOW NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A flip chip comprises first and second circuitry portions formed in a substrate. The first and second circuitry portions are spaced apart from one another in a separation direction. A substrate-contact boundary is formed in the substrate between the first and second circuitry portions.07-26-2012
20120187578PACKAGED SEMICONDUCTOR DEVICE FOR HIGH PERFORMANCE MEMORY AND LOGIC - A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.07-26-2012
20090020891Methods to Achieve Precision Alignment for Wafter Scale Packages - Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.01-22-2009
20120261839DICING TAPE-INTEGRATED WAFER BACK SURFACE PROTECTIVE FILM - The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device.10-18-2012
20110121465PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer.05-26-2011
20100327465PACKAGE PROCESS AND PACKAGE STRUCTURE - A package process is provided. First, a semiconductor substrate is disposed on a carrier, in which a surface of the carrier has an adhesive layer and the semiconductor substrate is bonded to the carrier by the adhesive layer. Next, a chip is bonded on the semiconductor substrate by flip chip technique and a first underfill is formed between the chip and the semiconductor substrate to encapsulate a plurality of first conductive bumps at the bottom of the chip. Then, a first molding compound is formed on the semiconductor substrate. The first molding compound at least encapsulates the side surface of the chip and the first underfill. Finally, the semiconductor substrate together with the chip and the first molding compound located thereon are separated from the adhesive layer of the carrier to form an array package structure.12-30-2010
20120299201Use of a Local Constraint to Enhance Attachment of an IC Device to a Mounting Platform - An embodiment is directed to an IC mounting assembly that comprises an IC device having a first planar surface, wherein multiple electrically conductive first terminals are located at the first surface. The assembly further comprises an IC device mounting platform having a second planar surface in closely spaced relationship with the first surface, wherein multiple electrically conductive second terminals are located at the second surface, each second terminal corresponding to one of the first terminals. A solder element extends between each first terminal and its corresponding second terminal, and a constraining element is fixably joined to the second surface, wherein the constraining element has a CTE which is selectively less than the CTE of the mounting platform at the second surface. The constraining element is provided with a number of holes or apertures, and each hole is traversed by a solder element that extends between a first terminal and its corresponding second terminal.11-29-2012
20080284045Method for Fabricating Array-Molded Package-On-Package - A method and apparatus for fabricating a semiconductor device are disclosed. The method attaches semiconductor chips (11-20-2008
20120326334INTERPOSER, ITS MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE - At least one embodiment provides an interposer including: a lower wiring substrate; an upper wiring substrate disposed over the lower wiring substrate via a gap; and through-electrodes which penetrate through the upper wiring substrate and the lower wiring substrate across the gap to thereby link the upper wiring substrate and the lower wiring substrate, portions of the through-electrodes being exposed in the gap.12-27-2012
20120280407INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ELECTRICAL INTERFACE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die.11-08-2012
20120326335LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit.12-27-2012
20130015590MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.01-17-2013
20130015591MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, first, second, third, and fourth microelectronic elements, and a plurality of terminals exposed at the second surface. Each microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. The front surfaces of the microelectronic elements can be arranged in a single plane parallel to the first surface. Each microelectronic element can have a column of contacts exposed at the front surface and arranged along respective first, second, third, and fourth axes. The first and third axes can be parallel to one another. The second and fourth axes can be transverse to the first and third axes. The microelectronic package can also include electrical connections extending from at least some of the contacts of each microelectronic element to at least some of the terminals.01-17-2013
20120241983INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A FLIP CHIP AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead; placing an integrated circuit device, having an external connector, adjacent to and electrically isolated from the lead; mounting an integrated circuit over the lead and the integrated circuit device with the integrated circuit electrically isolated from the integrated circuit device; and forming a package encapsulation, having an encapsulation base, over the lead, the integrated circuit, and the integrated circuit device with the lead and the external connector exposed from the encapsulation base.09-27-2012
20100090352FLIP-CHIP SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - There is provided a flip-chip substrate which is flip-chip connected to electrode terminals provided on one surface of an electronic component. The flip-chip substrate includes: mounting pads which are exposed to a surface of the flip-chip substrate on which the electronic component is mounted and each of which comprises a pad surface which is flip-chip connected to a corresponding one of the electrode terminals; wiring patterns which are electrically connected to the mounting pads; an insulating layer which covers the wiring patterns; and a solder resist formed on an entire surface of the insulating layer such that each pad surface of the mounting pads is exposed from the solder resist.04-15-2010
20080237890Semiconductor Device and Wiring Board - A wiring board (10-02-2008
20080224325WIRING BOARD, MOUNTING STRUCTURE FOR ELECTRONIC COMPONENTS, AND SEMICONDUCTOR DEVICE - A wiring board includes a main surface where an electronic component is mounted in a face-down manner so that a surface of the electronic component having plurality of external connecting terminals faces the main surface of the wiring board, the electronic component being fixed to the wiring board by an adhesive; an insulating layer formed on the main surface where the electronic component is mounted; an opening part formed in the insulating layer so that a plurality of adjacent wiring patterns are commonly and partially opened, the adjacent wiring patterns having electrodes where electrodes of the electronic component are connected; wherein an outer periphery of the opening part situated at a center side of the wiring board is formed in an oblique direction against extending directions of the wiring patters.09-18-2008
20080224324SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of one embodiment has a substrate, a semiconductor chip mounted over the substrate by flip-chip bonding, and a semiconductor chip provided over the semiconductor chip, wherein a space resides between the substrate and the semiconductor chip.09-18-2008
20080224323Semiconductor Module With Semiconductor Chips And Method For Producing It - A semiconductor module (09-18-2008
20080217792SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A manufacturing method of a semiconductor device includes: forming a columnar electrode on a semiconductor wafer; flip-chip bonding a second semiconductor chip onto the semiconductor wafer; forming a molding portion on the semiconductor wafer, the molding portion covering and molding the columnar electrode and the second semiconductor chip; grinding or polishing the molding portion and the second semiconductor chip so that an upper face of the columnar electrode and an upper face of the semiconductor chip are exposed; and cutting the molding portion and the semiconductor wafer so that a first semiconductor chip, where the second semiconductor chip is flip-chip bonded and the columnar electrode is formed, is formed.09-11-2008
20130099394FILM FOR BACK SURFACE OF FLIP-CHIP SEMICONDUCTOR - The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented.04-25-2013
20130134606SEMICONDUCTOR PACKAGES - A semiconductor package may include a substrate including a substrate pad on a top surface thereof; at least one semiconductor chip including a connection terminal electrically connected to the substrate on an active surface thereof, and mounted on the substrate; a heat release pattern formed between the substrate and the at least one semiconductor chip and configured to generate heat; and underfill resin underfilled between the substrate and the at least one semiconductor chip and comprising fillers. A semiconductor package may include a substrate including a substrate pad on a top surface thereof and a first heat release pattern configured to generate heat, and a semiconductor chip including a bonding pad formed on an active surface facing the substrate and a second heat release pattern configured to generate heat.05-30-2013
20080203585INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS - An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.08-28-2008
20130175708SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR CHIP CONNECTED IN A FLIP CHIP MANNER - A semiconductor device (07-11-2013
20130175707SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE - A substrate structure, a semiconductor package and a manufacturing method of semiconductor package are provided. The substrate structure comprises a conductive structure, an electrical component, a package body and a ring-shaped conductive structure. The conductive structure comprises a first conductive layer and a second conductive layer. The first conductive layer has a lower surface. The second conductive layer and the electrical component are formed on the lower surface of the first conductive layer. The package body encapsulates the conductive structure and the electrical component and has an upper surface. The ring-shaped conductive structure surrounds the conductive structure and the electrical component and is disposed at the edge of the upper surface of the package body to expose the conductive structure.07-11-2013
20130147065Semiconductor Device and Method of Forming Adjacent Channel and Dam Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material - A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel.06-13-2013
20090309238Molded flip chip package with enhanced mold-die adhesion - A molded flip chip package with enhanced adhesion between mold and die backside interface and the method of fabricating the package are described. The package is less prone to mold-die delamination. In an embodiment of the invention, the package has a die with a die frontside (die bottom side) attached to a substrate and a die backside (die top side). A first material is disposed on a portion of the die backside. A second material encapsulates the first material and the die backside.12-17-2009
20120273973SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE DESIGN METHOD, SEMICONDUCTOR DESIGN APPARATUS, AND PROGRAM - A potential-supply connection interconnect is provided in a multilayer interconnect layer. The potential supply connection interconnect overlaps some cell of I/O cells in the outer peripheral cell column and some cell of I/O cells in the inner peripheral cell column in a plan view. The potential-supply connection interconnect connects a power potential supply interconnect located below the outer peripheral cell column to a power potential supply interconnect located below the inner peripheral cell column and also connects a ground potential supply interconnect located below the outer peripheral cell column to a ground potential supply interconnect located below the inner peripheral cell column.11-01-2012
20130154118INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONTACTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion; forming a die paddle, adjacent to the isolated contact, having a die paddle contour; depositing a contact pad on the contact protrusion; coupling an integrated circuit die to the contact protrusion; molding an encapsulation on the integrated circuit die; and depositing an organic filler on and between the isolated contact and the die paddle, the contact protrusion extended past the organic filler.06-20-2013
20110233792METHODS AND SYSTEMS FOR MATERIAL BONDING - A device and a method for realizing reliable electrical contacts at low temperature and low pressure between conducting materials on, for example, different substrates are disclosed. In one aspect, a rough and brittle intermetallic layer is formed on a conducting material on a first substrate. A soft solder material layer on the other substrate is used for contacting the brittle and rough intermetallic layer that will break. As the solder material is relatively soft, contact between the broken intermetallic layer and the solder material can be realized over a large portion of the surface area. At that stage, a second intermetallic layer is formed between the solder material and the first intermetallic layer realizing electrical contact.09-29-2011
20100314782DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE - The present invention provides a dicing tape-integrated film for semiconductor back surface, including: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface is formed of a resin composition containing a thermosetting resin component and, as an optional component, a thermoplastic resin component in an amount of less than 50% by weight relative to the whole amount of resin components.12-16-2010
20100314781DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE - The present invention provides a dicing tape-integrated film for semiconductor back surface, including: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface has a storage elastic modulus (at 60° C.) of from 0.9 MPa to 15 MPa.12-16-2010
20130154120INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead; forming an interior conductive layer directly on the peripheral lead; forming a vertical connector directly on the interior conductive layer, the vertical connector having a connector top side; connecting an integrated circuit to the interior conductive layer; and forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation top side coplanar with the connector top side.06-20-2013
20130154121INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSISTANCE MOLD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side; mounting a mold chase having a buffer layer over the integrated circuit; forming an encapsulation between the substrate and the buffer; and removing the mold chase, leaving the encapsulation having a recess exposing a portion of the non-horizontal side.06-20-2013
20130154122SEMICONDUCTOR CHIP WITH UNDERFILL ANCHORS - Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.06-20-2013
20130154119INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead top side; forming a lower interior conductive layer directly on the lead top side; forming an interior insulation layer directly on the lower interior conductive layer; forming an upper interior conductive layer directly on the interior insulation layer; and mounting an integrated circuit over the upper interior conductive layer.06-20-2013
20080315436SEMICONDUCTOR WAFER THAT SUPPORTS MULTIPLE PACKAGING TECHNIQUES - Methods, systems, and apparatuses for semiconductor wafers and integrated circuit chip packaging techniques are provided. A wafer is fabricated that supports multiple different packaging techniques. The wafer is formed to have a plurality of integrated circuit regions. A first plurality of terminals is formed on a surface of the wafer in a central region of each integrated circuit region. A second plurality of terminals is formed on the surface of the wafer in a peripheral region of each integrated circuit region. For each integrated circuit region, each terminal of the second plurality of terminals is electrically coupled through the wafer to at least one terminal of the first plurality of terminals. The integrated circuit regions can be separated into chips that can be packaged in multiple ways. In an aspect, a wafer may be fabricated that supports wire-bond packaging or wafer level ball grid array (WLBGA) packaging for a common chip/die configuration of the wafer.12-25-2008
20130187293ELECTRONIC DEVICE, METHOD OF MANUFACTURING, AND ELECTRONIC DEVICE MANUFACTURING APPARATUS - According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first electronic component to organic acid, irradiating the top surface of the first electrode exposed to the organic acid with ultraviolet light, and bonding the first electrode and a second electrode of a second electronic component by heating and pressing the first electrode and the second electrode each other.07-25-2013
20090184431Liquid epoxy resin composition and flip chip semiconductor device - A liquid epoxy resin composition comprising (A) a liquid epoxy resin, (B) an aromatic amine curing agent comprising at least 5% by weight of a specific aromatic amine compound, and (C) an inorganic filler has a low viscosity for ease of working, cures into a cured product which has improved adhesion to the surface of silicon chips, and offers an encapsulated semiconductor device that does not suffer a failure even at a reflow temperature of 260-270° C., does not deteriorate under hot humid conditions, and does not peel or crack on thermal cycling.07-23-2009
20120018903FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE, DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, AND FLIP CHIP TYPE SEMICONDUCTOR DEVICE - The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film having a light transmittance at a wavelength of 532 nm or 1064 nm of 20% or less, and having a contrast between a marking part and a part other than the marking part after laser marking of 20% or more.01-26-2012
20120018902FILM FOR FLIP CHIP TYPE SEMICONDUCTOR BACK SURFACE, DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, AND FLIP CHIP TYPE SEMICONDUCTOR DEVICE - The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected to an adherend, the film for flip chip type semiconductor back surface containing an inorganic filler in an amount within a range of 70% by weight to 95% by weight based on the whole of the film for flip chip type semiconductor back surface.01-26-2012
20120018901FLIP-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME USING ABLATION - A method of manufacturing a flip-chip package and a flip-chip package manufactured by such method. In one embodiment, the method includes: (1) mounting a die to a first die, (2) encapsulating the second die with a molding compound and (3) selectively ablating the molding compound based on an expected heat generation of portions of the second die to reduce a thickness of the molding compound proximate the portions.01-26-2012
20130200531Circuit Board, Method for Fabricating the Same and Semiconductor Package Using the Same - A circuit board is provided including a core insulation film having a thickness and including a first surface and an opposite second surface, an upper stack structure and a lower stack structure. The upper stack structure has a thickness and has an upper conductive pattern having a thickness and an overlying upper insulation film stacked on the first surface of the core insulation film. The lower stack structure has a thickness and has a lower conductive pattern having a thickness and an overlying lower insulation film stacked on the second surface of the core insulation film. A ratio P of a sum of the thicknesses of the upper conductive pattern and the lower conductive pattern to a sum of the thicknesses of the core insulation film, the upper stack structure and the lower stack structure is in a range from about 0.05 to about 0.2.08-08-2013
20120061854INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; mounting a bottom integrated circuit over the bottom substrate; mounting a top substrate over a side of the bottom integrated circuit opposite the bottom substrate; connecting a top interconnect between the bottom substrate and the top substrate; and forming an underfill layer between the bottom substrate and the top substrate, the underfill layer encapsulating the top interconnect outside a perimeter of the bottom integrated circuit.03-15-2012

Patent applications in class Flip chip