Entries |
Document | Title | Date |
20080237871 | Method of Manufacturing a Semiconductor Device and Semiconductor Device Obtained With Such a Method - The invention relates to a method of manufacturing a semiconductor device ( | 10-02-2008 |
20090051037 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A semiconductor device relating to the present invention has multiple gate electrodes arranged on a semiconductor substrate at a narrow spacing and an interlayer insulating film covering the gate electrodes. The interlayer insulating film consists of a hygroscopic insulating film filling gate electrode spacing with a thinner thickness on the gate electrodes than the film thickness on the flat surface of the semiconductor substrate and low-hygroscopic insulating film formed on the hygroscopic insulating film. This structure enables suppressing an increase of contact resistance due to H | 02-26-2009 |
20090146309 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon. | 06-11-2009 |
20090166875 | METHODS FOR PREPARING AND DEVICES WITH TREATED DUMMY MOATS - Devices and methods are presented to fabricate dummy moats in an isolation region on a substrate. Presently, dummy moats are prone to losing impedance after the silicidation process. In high-voltage devices, silicided dummy moats reduce the breakdown voltage between active regions, particularly when the dummy moat overlaps or is in close proximity to a junction. The present devices and methods disclose a dummy moat covered with an oxide layer. During the silicidation process, the dummy moat and other designated isolation regions remain non-silicided. Thus, high and stable breakdown voltages are maintained. | 07-02-2009 |
20090174078 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device and method of manufacturing the same. The semiconductor device may include a base material and a compound layer on the base material including a mixture of a non-adhesive organic material and a non-oxidizing metal material. | 07-09-2009 |
20090289370 | LOW CONTACT RESISTANCE SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - Low contact resistance semiconductor devices and methods for fabricating such semiconductor devices are provided. In accordance with one exemplary embodiment, a method comprises depositing an insulating material overlying a metal silicide region and etching a contact opening within the insulating material and exposing the metal silicide region. The contact opening is at least partially bottom-filled with substantially pure cobalt. A conductor is deposited in the contact opening if, after the step of at least partially bottom-filling, the contact opening is not filled with the substantially pure cobalt. | 11-26-2009 |
20090315185 | SELECTIVE ELECTROLESS METAL DEPOSITION FOR DUAL SALICIDE PROCESS - A method for forming dual salicide contacts includes depositing a low or mid-gap work function metal selectively on an NMOS source/drain (S/D) region of a semiconductor device via electroless deposition; depositing a high work function metal selectively over the low work function metal and a PMOS source/drain (S/D) region of a semiconductor device via electroless deposition; annealing the semiconductor device to form a silicide of the low work function metal over the NMOS source/drain (S/D) region and a silicide of the high work function metal over the PMOS source/drain (S/D) region; and performing a SALICIDE etch to remove the unreacted metals from all regions of the substrate. | 12-24-2009 |
20100155955 | METHOD FOR MANUFACTURING SYSTEM-IN-PACKAGE - A method of manufacturing a System In Package (SIP) and devices thereof. A method of manufacturing a SIP may include providing a first chip having a first substrate region and/or a first metal connection portion. A method of manufacturing a SIP may include providing a second chip having a second substrate region and/or a second metal connection portion. A method of manufacturing a SIP may include bonding a first metal connection portion with a second metal connection portion, which may stack a second chip with a first chip. A method of manufacturing a SIP may include subjecting a second substrate region to reactive ion etching to expose a portion of a second metal connection portion and/or to form a deep contact hole. A method of manufacturing a SIP may include treating a surface of a deep contact hole with tetra-methyl ammonium hydroxide and/or nitric acid. | 06-24-2010 |
20100264544 | Device including contact structure and method of forming the same - A device includes an insulating layer on a substrate having a lower conductive pattern, the insulating layer having a contact hole that penetrates the insulating layer and exposes a portion of the lower conductive pattern, a catalytic pattern having a first portion on the exposed portion of the lower conductive pattern and a second portion on a sidewall of the contact hole, a spacer on the sidewall of the contact hole, wherein the second portion of the catalytic pattern is disposed between the spacer and the sidewall, and a contact plug in the contact hole and contacting the catalytic pattern, the contact plug being a carbon nanotube material. | 10-21-2010 |
20100320608 | Semiconductor Substrate Contact VIA - Edges of a first conductive layer ( | 12-23-2010 |
20110101533 | INTEGRATED (MULTILAYER) CIRCUITS AND PROCESS OF PRODUCING THE SAME - A process of forming a semiconductor integrated circuit that includes the steps of: forming at least a first element having a first pattern of conductive material and including a polymer layer surrounding the conductive material, forming at least a second element having a second pattern of conductive material and including a polymer layer surrounding the conductive material, positioning the first element relative to the second element, and bonding the polymer layer of the first and second elements at a temperature below a melting temperature of the conductive materials of the first and second elements wherein the conductive material of the first element contacts the conductive material of the second element and is maintained in position by the bonded polymer layers. | 05-05-2011 |
20110175228 | MOLECULAR SELF-ASSEMBLY IN SUBSTRATE PROCESSING - Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming. | 07-21-2011 |
20120025385 | Low Resistance Peripheral Local Interconnect Contacts with Selective Wet Strip of Titanium - Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided. | 02-02-2012 |
20120241962 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME ETCHING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad. | 09-27-2012 |
20130147048 | INTEGRATED CIRCUIT DEVICES INCLUDING ELECTRODE SUPPORT STRUCTURES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed. | 06-13-2013 |
20130234335 | HNO3 SINGLE WAFER CLEAN PROCESS TO STRIP NICKEL AND FOR MOL POST ETCH - Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO | 09-12-2013 |
20140021620 | POWER DEVICE AND POWER DEVICE MODULE - According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni. | 01-23-2014 |
20140197540 | Extended Redistribution Layers Bumped Wafer - A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad. | 07-17-2014 |
20140332965 | High Performance Refractory Metal / Copper Interconnects To Eliminate Electromigration - An interconnect structure and method of making the same. A preferred interconnect structure has a first interconnect including a first dual damascene via and narrow line and a second interconnect at the same level as the first including a second dual damascene via and wider line. The first and second interconnects may have different aspect ratio and may have different line heights while being co-planar with each other. The second line of the second interconnect may abut or partially surround the first line of the first interconnect. The first interconnect includes a refractory metal material as the main conductor, whereas the second interconnect includes a lower resistivity material as its main conductor. | 11-13-2014 |
20150097292 | INTERCONNECTS HAVING SEALING STRUCTURES TO ENABLE SELECTIVE METAL CAPPING LAYERS - Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect. | 04-09-2015 |
20160111382 | VERTICAL BREAKDOWN PROTECTION LAYER - The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line. | 04-21-2016 |