Class / Patent application number | Description | Number of patent applications / Date published |
257766000 | At least one layer containing chromium or nickel | 20 |
20090057909 | UNDER BUMP METALLIZATION STRUCTURE HAVING A SEED LAYER FOR ELECTROLESS NICKEL DEPOSITION - Structures and methods for fabrication of an under bump metallization (UBM) structure having a metal seed layer and electroless nickel deposition layer are disclosed involving a UBM structure comprising a semiconductor substrate, at least one final metal layer, a passivation layer, a metal seed layer, and a metallization layer. The at least one final metal layer is formed over at least a portion of the semiconductor substrate. Also, the passivation layer is formed over at least a portion of the semiconductor substrate. In addition, the passivation layer includes a plurality of openings. Additionally, the passivation layer is formed of a non-conductive material. The at least one final metal layer is exposed through the plurality of openings. The metal seed layer is formed over the passivation layer and covers the plurality of openings. The metallization layer is formed over the metal seed layer. The metallization layer is formed from electroless deposition. | 03-05-2009 |
20090206487 | WIRE BONDING SUBSTRATE AND FABRICATION THEREOF - A method for forming a wire bonding substrate is disclosed. A substrate comprising a first surface and a second surface is provided. A through hole is formed in the substrate. A conductive layer is formed on the first surface and the second surface of the substrate and covers a sidewall of the through hole. The conductive layer on the first surface of the substrate is patterned to form at least a first conductive pad, and the conductive layer on the second surface of the substrate is patterned to form at least a second conductive pad. An insulating layer is formed on the first surface and the second surface of the substrate and covers the first conductive pad and the second conductive pad. The insulating layer is recessed until top surfaces of the first conductive pad and the second conductive pad are exposed. A first metal layer is electroplated on the first conductive pad by applying current from the second conductive pad to the first conductive pad through the conductive layer passing the through hole. | 08-20-2009 |
20090261476 | Semiconductor device and manufacturing method thereof - A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface. | 10-22-2009 |
20100301484 | LGA SUBSTRATE AND METHOD OF MAKING SAME - An LGA substrate includes a core ( | 12-02-2010 |
20110042816 | SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF - A semiconductor apparatus includes an aluminum electrode film formed on a semiconductor chip; and a nickel plated layer formed on the aluminum electrode film, wherein a concentration of sodium and potassium present in the nickel plated layer and at an interface between the nickel plated layer and the aluminum electrode film is 3.20×10 | 02-24-2011 |
20110163454 | ELECTROLESS PLATING A NICKLE LAYER AND A GOLD LAYER IN A SEMICONDUCTOR DEVICE - A method and resulting device for maintaining non-porous nickel layer at a nickel/passivation interface of a semiconductor device in a nickel/gold electroless plating process. The method can include determining a thickness of a gold layer of the semiconductor device; determining an electroless plating rate and plating time of the gold layer to reach the determined thickness; determining a thickness of nickel under the gold layer to maintain the non-porous nickel layer at the nickel/passivation interface at a termination of an electroless gold plating process; and following the determinations, sequentially electroless plating of each of the nickel layer and gold layer on the device layer to the determined thicknesses. | 07-07-2011 |
20110169167 | GRID ARRAY CONNECTION DEVICE AND METHOD - A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results. | 07-14-2011 |
20120098135 | INTEGRATED CIRCUITS WITH BACKSIDE METALIZATION AND PRODUCTION METHOD THEREOF - An embodiment of an integrated device, including a chip of semiconductor material wherein an integrated circuit is integrated, is proposed; the integrated device includes a set of contact terminals for contacting the integrated circuit. At least one contact terminal of said set of contact terminals includes a contact layer of metal material being suitable to be directly coupled mechanically to an element external to the chip, and a coupling element for improving an electrical and/or mechanical coupling between the contact layer and the chip. The coupling element includes a coupling layer being formed by a combination between the metal material of the contact layer and the semiconductor material of the chip, with the coupling layer that is directly coupled to the chip and to the contact layer. | 04-26-2012 |
20120168954 | SUBSTRATE BONDING METHOD AND SEMICONDUCTOR DEVICE - A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other. | 07-05-2012 |
20130075914 | SEMICONDUCTOR ELEMENT - There is provided a semiconductor element including a semiconductor layer, a translucent electrode which is formed on the semiconductor layer, and a pad electrode which is formed on the translucent electrode, wherein the translucent electrode includes a recessed part on which the pad electrode is mounted, and wherein a thickness of a bottom surface of the recessed part of the translucent electrode is more than 0% of and equal to or less than 70% of a thickness of a part of the translucent electrode other than the recessed part. | 03-28-2013 |
20130320547 | ENABLING PACKAGE-ON-PACKAGE (POP) PAD SURFACE FINISHES ON BUMPLESS BUILD-UP LAYER (BBUL) PACKAGE - A bumpless build-up layer (BBUL) integrated circuit package and method of manufacturing are presented. In some embodiments, the package-on-package (PoP) pads of the BBUL integrated circuit package has a surface finish that can be palladium, nickel-palladium, nickel-gold, nickel-palladium-gold, or palladium-nickel-palladium-gold. In some embodiments, the PoP pad surface finish can be formed using either an electroless or electrolytic process. | 12-05-2013 |
20130334692 | Bonding Package components Through Plating - A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector. | 12-19-2013 |
20140001637 | WIRING BOARD | 01-02-2014 |
20140110848 | STRONG, HEAT STABLE JUNCTION - Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is an electrical conductor; and a strong, heat stable junction there between including an intermetallic bond formed of: substantially (a) indium (In), tin (Sn) or a mixture thereof, and (b) substantially nickel (Ni). The junction can have an electrical contact resistance that is small compared to the resistance of the electrical device. | 04-24-2014 |
20140138836 | SEMICONDUCTOR DEVICE - In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively. | 05-22-2014 |
20150054162 | METHOD OF MANUFACTURING CHIP PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING CHIP PACKAGE - A chip package substrate includes a base substrate including via holes. A circuit pattern layer is formed in an area of the base substrate corresponding to the via holes, and a first plated layer formed on the other surface opposite to one surface of the circuit pattern layer in contact with the via holes. | 02-26-2015 |
20150069613 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one exemplary embodiment, a semiconductor device includes a chip main body; a first layer that is provided on the chip main body and contains nickel and phosphorus; and a second layer that is provided on the first layer and contains nickel and phosphorus and has a higher phosphorus concentration than that of the first layer. | 03-12-2015 |
20150069614 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first metal layer disposed on a first surface of a semiconductor layer, or a portion thereof. The first metal layer is made of a first metal. At least a portion of the first metal layer is crystallized. A second metal layer is disposed on a second surface of the semiconductor layer. The second surface is opposite the first surface. The second metal layer is also made of the first metal and has at least a portion that is crystallized. In some embodiments, the first metal may be nickel. In some embodiments, the semiconductor device may be a power semiconductor device, such as an insulated gate bipolar transistor and a fast recovery diode. | 03-12-2015 |
20150333023 | Semiconductor Device Having Solderable and Bondable Electrical Contact Pads - A semiconductor device includes a semiconductor chip and a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein the electrical contact pads each include a layer stack, each layer stack having one and the same order of layers, and wherein the electrical contact pads are both solderable and bondable. | 11-19-2015 |
20160133533 | SUBSTRATE STRUCTURES AND METHODS OF MANUFACTURE - A semiconductor package. Implementations may include a substrate including a metallic baseplate coupled with an electrically insulative layer and a plurality of metallic traces coupled to the electrically insulative layer on a surface of the electrically insulative layer opposing a surface of the electrically insulative layer coupled to the metallic baseplate. The plurality of metallic traces may include at least two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the surface of the electrically insulative layer coupled with the metallic baseplate. The package may include at least one semiconductor device coupled to the substrate, a mold compound that encapsulates the power electronic device and at least a portion of the substrate, and at least one package electrical connector coupled with the substrate. | 05-12-2016 |