Class / Patent application number | Description | Number of patent applications / Date published |
257759000 | Including organic insulating material between metal levels | 20 |
20080203574 | INSULATING FILM MATERIAL, MULTILAYER INTERCONNECTION STRUCTURE, METHOD FOR MANUFACTURING SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide an insulating film material that can be advantageously used for forming an insulating film having a low dielectric constant and excellent resistance to damage, such as etching resistance and resistance to liquid reagents, a multilayer interconnection structure in which a parasitic capacitance between the interconnections can be reduced, efficient methods for manufacturing the multilayer interconnection structure, and an efficient method for manufacturing a semiconductor device with a high speed and reliability. The insulating film material contains at least a silicon compound having a steric structure represented by Structural Formula (1) below. | 08-28-2008 |
20080246153 | ORGANIC SILICA-BASED FILM, METHOD OF FORMING THE SAME, COMPOSITION FOR FORMING INSULATING FILM FOR SEMICONDUCTOR DEVICE, INTERCONNECT STRUCTURE, AND SEMICONDUCTOR DEVICE - A method of forming an organic silica-based film, including: applying a composition for forming an insulating film for a semiconductor device, which is cured by using heat and ultraviolet radiation, to a substrate to form a coating; heating the coating; and applying heat and ultraviolet radiation to the coating to effect a curing treatment, wherein the composition includes organic silica sol having a carbon content of 11.8 to 16.7 mol %, and an organic solvent, the organic silica sol being a hydrolysis-condensation product produced by hydrolysis and condensation of a silane compound selected from compounds shown by the general formulae (1): R | 10-09-2008 |
20080246154 | Top layers of metal for high performance IC's - The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill. | 10-09-2008 |
20080251926 | Method of Fabricating Organic Silicon Film, Semiconductor Device Including the Same, and Method of Fabricating the Semiconductor Device - An organic silicon film is formed by carrying out chemical vapor deposition with organic silicon compound being used as a raw material gas. The organic silicon compound contains at least silicon, hydrogen and carbon as a constituent thereof, and contains two or more groups having unsaturated bond, per a molecule thereof. The organic silicon compound is used in mixture with a silicon hydride gas. | 10-16-2008 |
20080277796 | ELECTRONIC STRUCTURES UTILIZING ETCH RESISTANT BORON AND PHOSPHORUS MATERIALS AND METHODS TO FORM SAME - A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric comprised of phosphorus and nitrogen. The present invention also provides electronic structures containing the dense boron-based or phosphorus-based dielectric as an etch stop, a dielectric Cu capping material, a CMP stop layer, and/or a reactive ion etching mask in a ULSI back-end-of-the-line (BEOL) interconnect structure. A method of forming the inventive boron-based or phosphorus-based dielectric as well as the electronic structure containing the same are also described in the present invention. | 11-13-2008 |
20080284032 | High performance system-on-chip using post passivation process - The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface. | 11-20-2008 |
20080290521 | FILM-FORMING COMPOSITION, INSULATING FILM WITH LOW DIELECTRIC CONSTANT, FORMATION METHOD THEREOF, AND SEMICONDUCTOR DEVICE - In the invention, a silica sol prepared by hydrolyzing and condensing a silane compound represented by the following formula: Si(OR | 11-27-2008 |
20080290522 | CARBON CONTAINING SILICON OXIDE FILM HAVING HIGH ASHING TOLERANCE AND ADHESION - A semiconductor device includes an interlayer insulating film formed on or over a semiconductor substrate. An opening is formed in the interlayer insulating film and reaches a lower layer metal wiring conductor. A metal plug is formed by filling the opening with Cu containing metal via a barrier metal. The interlayer insulating film includes the insulating film which includes a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond in the carbon containing silicon oxide film. The proportion of Si—CH2 bond (1360 cm-1) to Si—CH3 bond (1270 cm-1) in the insulating film is in a range from 0.03 to 0.05 measured as a peak height ratio of FTIR spectrum. | 11-27-2008 |
20090096106 | ANTIREFLECTIVE COATINGS - A method of forming a feature in a substrate comprising the steps of: forming a dielectric layer on a substrate; forming an antireflective coating over the dielectric layer; forming a photoresist pattern over the antireflective coating; etching the dielectric layer through the patterned photoresist; and removing the antireflective coating and the photoresist, wherein the antireflective coating is a film represented by the formula Si | 04-16-2009 |
20090206486 | WIREBOND OVER POST PASSIVATION THICK METAL - A chip assembly includes a semiconductor chip and a wirebonded wire. The semiconductor chip includes a passivation layer over a silicon substrate and over a thin metal structure, a first thick metal layer over the passivation layer and on a contact point of the thin metal structure exposed by an opening in the passivation layer, a polymer layer over the passivation layer and on the first thick metal layer, and a second thick metal layer on the polymer layer and on the first thick metal layer exposed by an opening in the polymer layer. The first thick metal layer includes a copper layer with a thickness between 3 and 25 micrometers. The wirebonded wire is bonded to the second thick metal layer. | 08-20-2009 |
20090212435 | POWER SEMICONDUCTOR DEVICE INCLUDING A DOUBLE METAL CONTACT - A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof. | 08-27-2009 |
20090309225 | Top layers of metal for high performance IC's - The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill. | 12-17-2009 |
20100007025 | ORGANIC SILICA FILM AND METHOD FOR FORMING SAME, COMPOSITION FOR FORMING INSULATING FILM OF SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME, WIRING STRUCTURE AND SEMICONDUCTOR DEVICE - An insulating-film-forming composition for a semiconductor device comprising an organic silica sol with a carbon atom content of 11 to 17 atom % and an organic solvent is disclosed. The organic silica sol comprises a hydrolysis-condensation product P1 and a hydrolysis-condensation product P2. The hydrolysis-condensation product P1 is obtained by hydrolyzing and condensing (A) a silane monomer comprising a hydrolyzable group and (B) a polycarbosilane comprising a hydrolyzable group in the presence of (C) a basic catalyst, and the hydrolysis-condensation product P2 is obtained by hydrolyzing and condensing (D) a silane monomer comprising a hydrolyzable group. | 01-14-2010 |
20100230820 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the steps of: forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap. | 09-16-2010 |
20100314767 | SELF-ALIGNED DUAL DAMASCENE BEOL STRUCTURES WITH PATTERNABLE LOW- K MATERIAL AND METHODS OF FORMING SAME - A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided. | 12-16-2010 |
20110278727 | CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME - A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers. | 11-17-2011 |
20150364404 | PAD DESIGN FOR RELIABILITY ENHANCEMENT IN PACKAGES - A package includes a corner, a device die having a front side and a backside, and a molding material molding the device die therein. A plurality of redistribution lines is on the backside of the device die. The plurality of redistribution lines includes a plurality of metal pads. A polymer layer contacts the plurality of metal pads. A plurality of openings is formed in the polymer layer, with the plurality of metal pads aligned to and exposed to the plurality of openings. The plurality of openings includes a corner opening that is elongated and an additional opening farther away from the corner than the corner opening. The additional opening is non-elongated. | 12-17-2015 |
20160020176 | INTERCONNECT HAVING AIR GAPS AND POLYMER WRAPPED CONDUCTIVE LINES - A device includes a first conductive line in a first metallization layer over a dielectric layer, wherein the first conductive line is wrapped by a first polymer layer on three sides and the first conductive line and the dielectric layer are separated by a bottom portion of the first polymer layer, a second conductive line over the dielectric layer, wherein the second conductive line is wrapped by a second polymer layer on three sides and the second conductive line and the dielectric layer are separated by a bottom portion of the second polymer layer and an air gap between the first conductive line and the second conductive line. | 01-21-2016 |
20160099197 | SEMICONDUCTOR PACKAGE AND CIRCUIT SUBSTRATE FOR THE SEMICONDUCTOR PACKAGE - Provided is a circuit substrate for a semiconductor package used for mounting a plurality of semiconductor devices. The circuit substrate including: a first circuit substrate unit; and a second circuit substrate unit that is formed on the first circuit substrate unit, wherein Young's modulus of a first dielectric material composing the dielectric layer of the first circuit substrate unit is higher than Young's modulus of a second dielectric material composing the dielectric layer of the second circuit substrate unit, and a coefficient of thermal expansion of the first dielectric material composing the dielectric layer of the first circuit substrate unit is smaller than a coefficient of thermal expansion of the second dielectric material composing the dielectric layer of the second circuit substrate unit. | 04-07-2016 |
20190148136 | CELL CONTACT | 05-16-2019 |