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Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257734000 - COMBINED WITH ELECTRICAL CONTACT OR LEAD

257741000 - Of specified material other than unalloyed aluminum

257750000 - Layered

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257760000 Separating insulating layer is laminate or composite of plural insulating materials (e.g., silicon oxide on silicon nitride, silicon oxynitride) 16
257759000 Including organic insulating material between metal levels 16
Entries
DocumentTitleDate
20090194879SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique, and a second interconnection layer which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer. A space between the second interconnection layer and each of first interconnection layers adjacent to both sides of the second interconnection layer equals the space between the first interconnection layers.08-06-2009
20130026633Multilayer Metallization with Stress-Reducing Interlayer - A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 μm and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer adjoining a different layer of the multilayer metallization. The interlayer includes at least one of W, WTi, Ta, TaN, TiW, and TiN or other suitable compound metal or a metal silicide such as WSi, MoSi, TiSi, and TaSi.01-31-2013
20130037955SUBSTRATE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE HAVING THE SUBSTRATE, AND MANUFACTURING METHOD THEREOF - A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part. The first metal line is electrically connected to a first electrode of the semiconductor device. The second metal line is electrically connected to a second electrode of the semiconductor device and spaced apart from the first metal line. The metal support part is disposed between the first metal line and the second metal line. The first insulating part is disposed between the first metal line and the metal support part and configured to electrically insulate the first metal line from the metal support part. The second insulating part is disposed between the second metal line and the metal support part and configured to electrically insulate the second metal line from the metal support part.02-14-2013
20090001589NOR FLASH DEVICE AND METHOD FOR FABRICATING THE DEVICE - An NOR flash memory device having a back end of line (BEOL) structure, the BEOL structure including a substrate having a conductive region, a first intermetal dielectric layer formed on the substrate, a first metal line formed on the conductive region, a second intermetal dielectric layer formed on the first metal line and the first inter metal dielectric, a first contact extending through the second intermetal dielectric layer, and a second metal line connected to the first metal line through the first contact. At least one of the first contact and the first and second metal lines is composed of copper and at least one of the first and second intermetal dielectric layers is composed of a low diectrice material. The use of copper metal lines and intermetal dielectric layers composed of a low-k (k=3.0) material makes it possible to improve 40% or more in the time constant delay.01-01-2009
20100117239INTERCONNECTION STRUCTURE OF ELECTRONIC DEVICE AND METHOD OF MANUFACTURING PACKAGE THEREOF - An interconnection is formed on an object having a step by a screen printing method. The interconnection is formed by printing it on a substrate having an upper stage surface and a lower stage surface. A multilayer interconnection structure having a plurality of layers which are stacked is formed by repeatedly performing a process of printing and drying an interconnection pattern on the lower stage surface. Then, when the height of the multilayer interconnection structure approaches the height of the upper stage surface, an interconnection pattern of the uppermost layer is printed on the multilayer interconnection structure to extend onto the upper stage surface. Because the interconnection pattern of the uppermost layer is printed in a smaller step, the print characteristic is good. Thus, by the printing, the interconnection structure is formed which has a narrow interconnection width and surely connects the upper surface and the lower surface in a larger step than the interconnection width.05-13-2010
20130075913STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION - A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.03-28-2013
20090121357DESIGN STRUCTURE FOR BRIDGE OF A SEMINCONDUCTOR INTERNAL NODE - A design structure for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a lower end in electrical contact with first and second transistor elements, respectively; one or more intermediate metal pillars disposed between and in electrical contact with an upper end of the metal pillars; and one or more separation regions of dielectric disposed below the intermediate metal pillar and between the lower ends of the first and second metal pillars.05-14-2009
20130043593Semiconductor Arrangement - A semiconductor arrangement includes a circuit carrier, a bonding wire and at least N half bridge circuits. N is an integer that amounts to at least 1. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each of the half bridge circuits includes a first circuit node, a second circuit node and a third circuit node, a controllable first semiconductor switch and a controllable second semiconductor switch. The controllable first semiconductor switch has a first main contact electrically connected to the first circuit node, a second main contact electrically connected to the third circuit node, and a gate contact for controlling an electric current between the first main contact and the second main contact. Accordingly, the controllable second semiconductor switch has a first main contact electrically connected to the second circuit node, a second main contact electrically connected to the third circuit node, and a gate contact for controlling an electric current between the first main contact and the second main contact. The first semiconductor switch and the second semiconductor switch of each of the half bridge circuits are arranged on that side of the first metallization layer facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer at a first bonding location.02-21-2013
20100044868SEMICONDUCTOR DEVICE - A semiconductor device includes an external terminal, a plurality of first interconnections, an electrode, a conductor, and a second interconnection. The first interconnections are positioned below the external terminal. The electrode is positioned at the same level as the first interconnections and is electrically connected to the external terminal through the conductor. The second interconnection is positioned below the first interconnections and the electrode. The semiconductor device has a region where the shortest distance between an edge surface of the electrode and an edge surface of one of the first interconnections positioned most adjacent to the electrode is less than 0.11 times the total thickness of the conductor and the electrode. The second interconnection is positioned at a position different from that of the region in a thickness direction of the semiconductor device.02-25-2010
20120181696PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF - A manufacturing method of a package carrier is provided. A substrate having an upper and lower surface is provided. A first opening communicating the upper and lower surface of the substrate is formed. A heat conducting element is disposed inside the first opening, wherein the heat conducting element is fixed in the first opening via an insulating material. At least a through hole passing through the substrate is formed. A metal layer is formed on the upper and lower surface of the substrate and inside the through hole. The metal layer covers the upper and lower surface of the substrate, the heat conducting element and the insulating material. A portion of the metal layer is removed. A solder mask is formed on the metal layer. A surface passivation layer is formed and covers the metal layer exposed by the solder mask and the metal layer located inside the through hole.07-19-2012
20090045516TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC's - A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.02-19-2009
20130069235BONDING PAD STRUCTURE FOR SEMICONDUCTOR DEVICES - A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; anda plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.03-21-2013
20130069236EFFICIENT SEMICONDUCTOR DEVICE CELL LAYOUT UTILIZING UNDERLYING LOCAL CONNECTIVE FEATURES - Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.03-21-2013
20090283912DAMASCENE WIRING FABRICATION METHODS INCORPORATING DIELECTRIC CAP ETCH PROCESS WITH HARD MASK RETENTION - Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected by the buffer oxide layer.11-19-2009
20110140277SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.06-16-2011
20110074033Crack Stop Trenches - Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.03-31-2011
20110291280SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.12-01-2011
20110291279SEMICONDUCTOR ARTICLE HAVING A THROUGH SILICON VIA AND GUARD RING - Disclosed is a semiconductor article which includes a semiconductor base portion, a back end of the line (BEOL) wiring portion on the semiconductor base portion, a through silicon via and a guard ring. The semiconductor base portion is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having metallic wiring and insulating material. The BEOL wiring portion does not include a semiconductor material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor base portion. The guard ring surrounds the through silicon via in the BEOL wiring portion.12-01-2011
20090096104Semiconductor device having crack stop structure - Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.04-16-2009
20090121358DUAL DEPTH TRENCH TERMINATION METHOD FOR IMPROVING CU-BASED INTERCONNECT INTEGRITY - A trench is formed in a low K dielectric (05-14-2009
20090121359SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a semiconductor substrate; a first insulating film (third insulating film 05-14-2009
20090051035SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit includes: a first wiring layer including a plurality of first interconnects formed to run in a first direction; a second wiring layer formed above the first wiring layer, the second wiring layer including a plurality of second interconnects formed to run in a second direction vertical to the first direction; and a third wiring layer formed above the second wiring layer, the third wiring layer including a plurality of third interconnects formed to run in the same direction as the second direction.02-26-2009
20080265421Structure for Electrostatic Discharge in Embedded Wafer Level Packages - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.10-30-2008
20080272492METHOD OF BLOCKING A VOID DURING CONTACT FORMATION PROCESS AND DEVICE HAVING THE SAME - An electronic device can include conductive regions. A void can extend between different portions of an insulating layer. Different openings can intersect the void. A liner layer can substantially block the void, substantially preventing subsequently forming an electrical leakage path along the void. In one aspect, a stressor layer can be deposited over the conductive regions prior to forming the insulating layer. The liner layer can be formed over the stressor layer within the different openings through the insulating layer. In another aspect, an etch-stop layer can be formed over a silicide layer prior to forming the insulating layer. After removing a portion of the liner layer, a portion of the etch-stop layer can be removed to expose the silicide layer within the different openings. In yet another aspect, a nitride layer can lie between a substrate and the insulating layer and include a section of the openings.11-06-2008
20090160058Structure and process for the formation of TSVs - An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.06-25-2009
20090309224CIRCUITRY COMPONENT AND METHOD FOR FORMING THE SAME - A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.12-17-2009
20110147939METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS - A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.06-23-2011
20100007024SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.01-14-2010
20090243110Voltage controlled oscillator - A semiconductor device includes a semiconductor substrate having an element region on a surface thereof, an active element being formed in the element region. An insulating layer is formed on the semiconductor substrate and covers the active element. An inductor is formed on the insulating layer and overlaps with the active element.10-01-2009
20090273086METHOD OF REDUCING EROSION OF A METAL CAP LAYER DURING VIA PATTERNING IN SEMICONDUCTOR DEVICES - During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.11-05-2009
20080303158SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.12-11-2008
20090091035Highly integrated and reliable DRAM and its manufacture - A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.04-09-2009
20080211102LATERALLY GROWN NANOTUBES AND METHOD OF FORMATION - A semiconductor device has lateral conductors or traces that are formed of nanotubes such as carbon. A sacrificial layer is formed overlying the substrate. A dielectric layer is formed overlying the sacrificial layer. A lateral opening is formed by removing a portion of the dielectric layer and the sacrificial layer which is located between two columns of metallic catalysts. The lateral opening includes a neck portion and a cavity portion which is used as a constrained space to grow a nanotube. A plasma is used to apply electric charge that forms an electric field which controls the direction of formation of the nanotubes. Nanotubes from each column of metallic catalyst are laterally grown and either abut or merge into one nanotube. Contact to the nanotube may be made from either the neck portion or the columns of metallic catalysts.09-04-2008
20090289369MEMORY DEVICE PERIPHERAL INTERCONNECTS AND METHOD OF MANUFACTURING - An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.11-26-2009
20090267232METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit (10-29-2009
20090261475METHOD FOR FABRICATING A METAL INTERCONNECTION USING A DUAL DAMASCENE PROCESS AND RESULTING SEMICONDUCTOR DEVICE - A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.10-22-2009
20120292772SHIELDED ELECTRONIC COMPONENTS AND METHOD OF MANUFACTURING THE SAME - A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO11-22-2012
20110266679SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M11-03-2011
20110266680CARBON NANOTUBE CIRCUIT COMPONENT STRUCTURE - The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.11-03-2011
20090096105CONTACT STRUCTURE OF A WIRES AND METHOD MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT STRUCTURE AND METHOD MANUFACTURING THE SAME - In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.04-16-2009
20080237868METHOD AND STRUCTURE FOR ULTRA NARROW CRACK STOP FOR MULTILEVEL SEMICONDUCTOR DEVICE - An integrated circuit design and a method of fabrication and, more particularly, a semiconductor structure having an ultra narrow crack stop for use in multilevel level devices and a method of making the same. The structure includes a first dielectric layer having a first connection connecting to an underlying interconnect and a second dielectric layer having a second connection connecting to the first connection. A stop gap structure extends through the first dielectric layer and the second dielectric layer, and has a width of about less than 1 um.10-02-2008
20080237869STRUCTURE AND METHOD FOR LOW RESISTANCE INTERCONNECTIONS - A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface.10-02-2008
20080265422STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF - A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.10-30-2008
20090283911Backend Interconnect Scheme with Middle Dielectric Layer Having Improved Strength - An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a second dielectric layer having a second k value greater than the first k value; and second metal lines in the second dielectric layer. The third metallization layer is over the second metallization layer, and includes a third dielectric layer having a third k value; and third metal lines in the third dielectric layer. The integrated circuit structure further includes a bottom passivation layer over the third metallization layer.11-19-2009
20080277794 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.11-13-2008
20080277793Semiconductor Device and Manufacturing Method Thereof - A semiconductor device with improved moisture resistance and its manufacturing method as well as a manufacturing method of a semiconductor device which simplifies a manufacturing process and improves productivity are offered. This invention offers a CSP type semiconductor device and its manufacturing method that can prevent moisture and the like from infiltrating into it to attain high reliability by covering a side surface of a semiconductor chip with a thick protection layer. This invention also offers a highly productive manufacturing method of semiconductor devices by which a supporter bonded to semiconductor dice is etched from a back surface-side of the supporter so that the semiconductor devices can be separated without dicing.11-13-2008
20080284029Contact structures and semiconductor devices including the same and methods of forming the same - Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer dielectric layer is formed on the semiconductor substrate. Direct contact plugs are formed extending through the first interlayer dielectric layer to contact selected ones of the active regions. Bit line structures are formed on the first interlayer dielectric layer and crossing the word lines that are coupled to the selected ones of the active regions by the direct contact plugs. A second interlayer dielectric layer is formed on the semiconductor substrate including the bit line structures. Barrier patterns are formed extending in parallel with bit line structures and into the second interlayer dielectric layer. Mask patterns are formed overlying an entirety of top surfaces of the direct contact plugs on the second interlayer dielectric layer and the bit line structures. The second and first interlayer dielectric layers are etched using the mask patterns, the barrier patterns and the bit line structures as an etching mask to form buried contact holes and buried contact plugs are formed in the buried contact holes.11-20-2008
20080284031METHOD FOR IMPROVED PROCESS LATITUDE BY ELONGATED VIA INTEGRATION - Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.11-20-2008
20080284028INTEGRATED DEVICE FABRICATED USING ONE OR MORE EMBEDDED MASKS - A device fabricated using a multi-layered wafer that has an embedded etch mask adapted to map a desired device structure onto an adjacent (poly)silicon layer. Due to the presence of the embedded mask, it becomes possible to delay the etching that forms the mapped structure in the (poly)silicon layer until a relatively late fabrication stage. As a result, flatness of the (poly)silicon layer is preserved for the deposition of any necessary over-layers, which substantially obviates the need for filling the voids created by the structure formation with silicon oxide.11-20-2008
20080284027METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.11-20-2008
20080284026Semiconductor device and method for fabricating the same - A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulating film, and a third metal pattern formed in the second insulating film and connecting between the first metal pattern and the second metal pattern. The third metal pattern is a single continuous structure, and the principal orientation axes of crystals of a metal constituting the third metal pattern are parallel to the principal surface of the semiconductor substrate.11-20-2008
20080308940LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES - A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.12-18-2008
20080308939SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of first group wiring layers laminated on a substrate, and each of the first group wiring layers having a wire formed with a first minimum wire width and a main dielectric film portion; and a plurality of second group wiring layers laminated on a top layer of the plurality of first group wiring layers and each of the second group wiring layers having a wire formed with a second minimum wire width greater than the first minimum wire width and a main dielectric film portion, wherein a main dielectric film portion in a bottom layer of the plurality of second group wiring layers has a relative dielectric constant which is substantially identical to a relative dielectric constant of main dielectric film portions of the other second group wiring layers, and Young's modulus of the main dielectric film portion in the bottom layer of the plurality of second group wiring layers is smaller than those of the main dielectric film portions of the other second group wiring layers and larger than those of main dielectric film portions of the first group wiring layers.12-18-2008
20080203573SEMICONDUCTOR DEVICE - Provided is a semiconductor device including first and second wiring layers, and dummy and conductive patterns. The first and second wiring layers each have a hollow structure, and are stacked vertically adjacent to each other on a semiconductor substrate. The dummy pattern is formed in the first wiring layer, and does not function as a signal line. The conductive pattern is formed in the second wiring layer. The dummy and conductive patterns have an overlapping portion where these patterns overlap each other, and a non-overlapping portion where these patterns overlap each other, as viewed from above the semiconductor substrate.08-28-2008
20080303159Thin Silicon based substrate - Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.12-11-2008
20090014881SEMICONDUCTOR DEVICE, AND METHOD AND APPARATUS FOR MANUFACTURING SAME - For the purpose of removing an oxide film on the surface of a varying metal electroconductive material used for wiring in a semiconductor device without inflicting damage on a peripheral structure, the oxide film formed on the surface of a metal electroconductive region 01-15-2009
20080246152SEMICONDUCTOR DEVICE WITH BONDING PAD - A semiconductor device with a bonding pad is provided. The semiconductor device includes a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are disposed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is disposed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and the first substrate is exposed through an opening in the lowermost metal pattern.10-09-2008
20090146307Top layers of metal for high performance IC's - The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.06-11-2009
20080258305Low fabrication cost, fine pitch and high reliability solder bump - A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.10-23-2008
20100200992Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced - A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.08-12-2010
20090127711INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - A highly reliable copper interconnect structure and method of fabricating the same is provided. The interconnect structure comprises a metal layer buried between an adjacent upper copper layer and an adjacent lower copper layer structure. More specifically, the interconnect structure comprises a recess formed in a dielectric layer; a barrier metal lining sidewalls of the recess; a first copper layer within the recess; a second copper layer within the recess; and a metal layer buried between the first copper layer and the second copper layer. The method comprises forming a recess in an interlayer dielectric; forming a first copper layer, a metal layer over the first copper layer and a second copper layer over the metal layer, all within the recess. The metal layer is sandwiched between the first copper layer and the second copper layer within the recess.05-21-2009
20090001590WIRING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A wiring structure includes a first wiring, a first interlayer dielectric film having a first opening, a second wiring formed with a first recess portion on a region corresponding to the first opening, a second interlayer dielectric film having a second opening and a third wiring so formed as to cover the second interlayer dielectric film, wherein an inner side surface of the second opening is arranged on a region corresponding to the first recess portion and formed such that an opening width of a portion in the vicinity of an upper end increases from a lower portion toward an upper portion.01-01-2009
20120068345LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS - In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process.03-22-2012
20120104615MICROELECTRONIC DEVICE PROVIDED WITH AN ARRAY OF ELEMENTS MADE FROM A CONDUCTIVE POLYMER WITH A POSITIVE TEMPERATURE COEFFICIENT - Production of a device including: a substrate; multiple components forming an electronic circuit on the substrate; multiple superimposed metal levels of interconnections of the components, wherein the metal levels are located in at least one insulating layer resting on the substrate; and multiple elements made from a positive temperature coefficient conductive polymer material, wherein the elements traverse the insulating layer to a given depth, and are connected to at least one conductive line of a given interconnection level.05-03-2012
20090200674STRUCTURE AND METHOD OF FORMING TRANSITIONAL CONTACTS BETWEEN WIDE AND THIN BEOL WIRINGS - A structure and method of forming a conducting via for connecting two back end of the line (BEOL) metal wiring levels is described. The method includes forming a first interconnect structure having a first dimensional width in a first dielectric layer; depositing a second dielectric layer over said first dielectric layer; etching an interconnect trench in the said second dielectric layer; etching a interconnect via using a photo resist mask to form a first portion of the transitional via; reacting the photo resist to expand the photo resist at least in the lateral direction; etching the said dielectric layer using the reacted photo resist to form the second portion of the transitional via; and filling the said interconnect trench and the said interconnect via with metal.08-13-2009
20090014882SEMICONDUCTOR DEVICE - A semiconductor device includes an effective wire formed above a substrate in a multilayer interconnection structure and having a first electrode pad in a top layer; a first reinforcing material formed in the multilayer interconnection structure like surrounding the effective wire; a protective film configured to protect a final surface of the multilayer interconnection structure; and a second reinforcing material formed at a position in contact with the protective film and also between an area in which the effective wire is formed and a chip area end, the second reinforcing material being constituted by a film pattern whose Young's modulus is larger than that of a conductor constituting the first electrode pad and that of a conductor constituting the first reinforcing material.01-15-2009
20090200675Passivated Copper Chip Pads - A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.08-13-2009
20090230556NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory apparatus 09-17-2009
20090194878SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method of manufacture thereof, particularly, to the technology capable of preventing the overlap failure between the metal line and the bit line pad, since the size of the bit line pad can be increased and the height between the bit line pad and the metal line can be reduced, by designing the semiconductor device to form the bit line and the bit line pad with the stacking structure08-06-2009
20090200677SEMICONDUCTOR DEVICE - A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.08-13-2009
20080277795SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING UPPER PATTERN ALIGNED WITH LOWER PATTERN MOLDED BY SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING THE SAME - Provided are semiconductor integrated circuit (IC) devices having an upper pattern aligned with a lower pattern molded by a semiconductor substrate and methods of forming the same. In the semiconductor IC devices, the lower pattern contacts the upper pattern using an active region and/or an isolation layer. The methods include preparing a semiconductor substrate having an active region. A lower pattern is formed on the active region. The lower pattern is surrounded by the active region and protrudes from a top surface of the active region. An upper pattern is disposed on the lower pattern. The upper pattern contacts the lower pattern.11-13-2008
20090250820CONFIGURABLE NON-VOLATILE LOGIC STRUCTURE FOR CHARACTERIZING AN INTEGRATED CIRCUIT DEVICE - An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.10-08-2009
20080315421Die backside metallization and surface activated bonding for stacked die packages - Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be coupled to an active metal layer of a second die through silicon vias and/or a die backside metallization layer of the second die. Other embodiments are also described.12-25-2008
20080315420Metal pad formation method and metal pad structure using the same - A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.12-25-2008
20090243108CONTROL OF LOCALIZED AIR GAP FORMATION IN AN INTERCONNECT STACK - The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect levels. The method comprises forming local etch vias (10-01-2009
20090250819METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - The invention relates to a metal line of a semiconductor device and a method of forming the same. According to a method of forming a metal line of a semiconductor device in accordance with an aspect of the invention, a semiconductor substrate in which contact plugs are formed within contact holes of a first dielectric layer is first provided. An etch-stop layer and a hard mask pattern are formed over the first dielectric layer and the contact plugs. The etch-stop layer is patterned along the hard mask pattern. The exposed first dielectric layer and the contact plugs are etched to thereby form trenches in the first dielectric layer over the contact plugs. A metal layer is formed to gap-fill the trenches. A polishing process is performed to expose the etch-stop layer.10-08-2009
20090256260SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor element and a functional member fixed thereto with an adhesive film is provided, where the performance or reliability degradation due to moisture entered by way of the adhesive film itself or the interfaces between the adhesive film and members adjacent thereto can be suppressed with a simple structure. The semiconductor element has an active region for realizing a predetermined function, formed on a surface of the element. The functional member has a predetermined function and is fixed on a surface side of the semiconductor element with the adhesive film. A metal film covers a region including at least all outer side faces of the semiconductor element, all outer side faces of the adhesive film, an interface between the adhesive film and the semiconductor element, and an interface between the adhesive film and the functional member.10-15-2009
20110101532DEVICE FABRICATED USING AN ELECTROPLATING PROCESS - A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.05-05-2011
20090085214SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member, a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.04-02-2009
20100176513STRUCTURE AND METHOD OF FORMING METAL INTERCONNECT STRUCTURES IN ULTRA LOW-K DIELECTRICS - A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element.07-15-2010
20100237504Methods of Fabricating Semiconductor Devices Having Conductive Wirings and Related Flash Memory Devices - A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is provided that electrically insulates the plurality of lower conductive structures from one another. A first insulation interlayer pattern is provided on the insulation layer. The first insulation interlayer pattern includes a contact plug that contacts the substrate through the insulation layer. An etch-stop layer is provided on the contact plug and the first insulation interlayer pattern. A second insulation interlayer pattern is provided on the etch-stop layer. The second insulation interlayer pattern includes a conductive line that is electrically connected to the contact plug. Related methods and flash memory devices are also provided.09-23-2010
20100224997SEMICONDUCTOR DEVICE - A semiconductor device includes a first metal layer disposed on a semiconductor substrate; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer and having an electrode pad surface exposed to the outside, wherein a recess is disposed in the insulating layer and the second metal layer; and at least the second metal layer is disposed in the recess of the insulating layer.09-09-2010
20100237503ELECTROMIGRATION RESISTANT ALUMINUM-BASED METAL INTERCONNECT STRUCTURE - A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl09-23-2010
20090321940Method for Manufacturing Contact Openings, Method for Manufacturing an Integrated Circuit, an Integrated Circuit - An integrated circuit is described including a first and a second plurality of conductor lines, each of the lines being separated from an adjacent line by a spacer dielectric and capped with a first and second dielectric cap material, respectively. A contact element is embedded in a covering dielectric layer with electrical contact to one of the first plurality of conductor lines in a contact portion, while being separated from a line adjacent to the contacted line only by the second cap material.12-31-2009
20090166873INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF THE SAME - The interconnecting structure for a semiconductor die includes a die having bonding pads on an active surface; a core attached the side wall (edge) of the die by adhesion material; an isolating base adhered on the active surface of the die by adhesion glue; a through silicon via (TSV) open from the back side of the die to expose the bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via; solder balls melted on terminal pads, wherein the terminal pads located on the core and/or the die.07-02-2009
20090184424SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - The production of a crack in an insulating film under an external terminal of a semiconductor device due to external force applied to the external terminal is suppressed or prevented. Over the principal surface of a semiconductor substrate, there are formed multiple wiring layers. In the fifth wiring layer directly under the uppermost wiring layer of the wiring layers, the following measure is taken: a conductor pattern (fifth wiring, dummy wiring, and plug) is not formed directly under the probe contact area of each bonding pad PD in the uppermost wiring layer. In the fifth wiring layer, conductor patterns (fifth wiring, dummy wirings, and plugs) are formed in the areas other than directly under the probe contact area of each bonding pad in the uppermost wiring layer.07-23-2009
20090115063SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.05-07-2009
20090115062Semiconductor device - A semiconductor device according to the present invention includes: a lower layer wiring made of a conductive material; an etching stopper film laminated on the lower layer wiring; an interlayer insulating film laminated on the etching stopper film; an intermediate film laminated on the interlayer insulating film and made of a material having an etching selectivity with respect to a material of the etching stopper film; an upper wiring layer laminated on the intermediate film; an upper layer wiring made of a metal material having Cu as a main component and embedded in an upper groove formed by digging in from a top surface of the upper wiring layer; and a via for electrically connecting the lower layer wiring and the upper layer wiring made of the same material as the material of the upper layer wiring and disposed in a via hole penetrating through the interlayer insulating film and the intermediate film.05-07-2009
20090072405Semiconductor device - The semiconductor device according to the present invention includes: a first wire made of a material mainly composed of Cu; a second wire made of a material mainly composed of Cu; an interlayer dielectric film formed between the first wire and the second wire; a via, made of a material mainly composed of Cu, penetrating through the intermediate dielectric film to be connected to the first wire and the second wire; and a dummy via, made of a material mainly composed of Cu, smaller in via diameter than the via and connected to the first wire while not contributing to electrical connection between the first wire and the second wire.03-19-2009
20080296771METHODS OF FABRICATING SILICON CARBIDE POWER DEVICES BY AT LEAST PARTIALLY REMOVING AN N-TYPE SILICON CARBIDE SUBSTRATE, AND SILICON CARBIDE POWER DEVICES SO FABRICATED - A silicon carbide power device is fabricated by forming a p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate, and forming a silicon carbide power device structure on the p-type silicon carbide epitaxial layer. The n-type silicon carbide substrate is at least partially removed, so as to expose the p-type silicon carbide epitaxial layer. An ohmic contact is formed on at least some of the p-type silicon carbide epitaxial layer that is exposed. By at least partially removing the n-type silicon carbide substrate and forming an ohmic contact on the p-type silicon carbide epitaxial layer, the disadvantages of using a p-type substrate may be reduced or eliminated. Related structures are also described.12-04-2008
20090152728SEMICONDUCTOR APPARATUS - A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.06-18-2009
20090108453CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.04-30-2009
20090108454METAL LINE IN SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A metal line in a semiconductor device and fabricating method thereof includes a first contact plug on a substrate, a first insulating interlayer over the substrate including the first contact plug, a first etch stop layer formed over the first insulating interlayer; a trench in the first insulating interlayer and the first etch stopper layer, a metal line in the trench, the metal line including a second contact plug projecting from the trench, wherein the metal line and the trench are formed as a single body, and a second insulating interlayer over the substrate including the metal line and the second contact plug.04-30-2009
20110042814SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE - A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.02-24-2011
20100164111INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME - Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.07-01-2010
20090321939Through Silicon via Bridge Interconnect - An integrated circuit bridge interconnect system includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The bridge die includes through silicon vias (TSVs) to connect conductive interconnect lines on the bridge die to the first die and the second die. Active circuitry, other than interconnect lines, may be provided on the bridge die. At least one or more additional die may be stacked on the bridge die and interconnected to the bridge die.12-31-2009
20090321941Phase memorization for low leakage dielectric films - Embodiments of a phase-stable amorphous high-κ dielectric layer in a device and methods for forming the phase-stable amorphous high-κ dielectric layer in a device are generally described herein. Other embodiments may be described and claimed.12-31-2009
20090039514SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor constituent provided with a semiconductor substrate and a plurality of electrodes for external connection provided under the semiconductor substrate. A lower-layer insulating film is provided under and around the semiconductor constituent. A plurality of lower-layer wirings are electrically connected to the electrodes for external connection of the semiconductor constituent, and provided under the lower-layer insulating film. An insulation layer is provided on the lower-layer insulating film in the periphery of the semiconductor constituent. An upper-layer insulating film is provided on the semiconductor constituent and the Insulation layer. A plurality of upper-layer wirings are provided on the upper-layer insulating film. A base plate on which the semiconductor constituent and the insulation layer are mounted is removed.02-12-2009
20100032841Semiconductor Devices and Structures Thereof - A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.02-11-2010
20100038791RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME - A resistive random access memory and a method for fabricating the same are provided. The method includes providing a bottom electrode formed on a substrate. A metal oxide layer is formed on the bottom electrode. An oxygen atom gettering layer is formed on the metal oxide layer. A top electrode is formed on the oxygen atom gettering layer. The previous mentioned structure is subjected to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, thus leaving a plurality of oxygen vacancies of the metal oxide layer.02-18-2010
20100038792SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.02-18-2010
20100038790 RELIABILITY OF WIDE INTERCONNECTS - An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the first metal wiring level which includes a via interconnect within an interlevel dielectric, a second metal wiring level on the interconnect wiring level which includes metal wiring lines, at least one metal wiring line having a plurality of dielectric fill shapes that reduces the cross sectional area of the at least one metal wiring line, and wherein the via interconnect makes electrical contact between a metal line in the first wiring level and the at least one metal wiring line in the second wiring level, the via interconnect being adjacent to and spaced from the plurality of dielectric fill shapes. Also disclosed is a method in which a plurality of dielectric fill shapes are placed adjacent to and spaced from a via contact area in a wiring line in a second wiring level.02-18-2010
20090032955SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD AND DISPLAY APPARATUS - A semiconductor device including n, where notation n denotes a positive integer at least equal to three, conductive layers created as stacked layers on a substrate and connected to each other through a contact pattern, a manufacturing method thereof and a display apparatus thereof are provided.02-05-2009
20120241961SEMICONDUCTOR APPARATUS, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - Disclosed herein is a semiconductor apparatus including: a first semiconductor part including a first wiring; a second semiconductor part which is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring; and a metallic oxide formed by a reaction between oxygen and a metallic material which reacts with oxygen more easily than hydrogen does, the metallic oxide having been diffused into a region which includes a joint interface between the first wiring and the second wiring and the inside of at least one of the first wiring and the second wiring.09-27-2012
20110175227POST PASSIVATION INTERCONNECTION SCHEMES ON TOP OF THE IC CHIPS - A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.07-21-2011
20090026620METHOD FOR CUTTING MULTILAYER SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, LIGHT EMITTING DEVICE, AND BACKLIGHT DEVICE - In order to cut off, without causing any burr, a multilayer substrate having a metal layer on a front surface and a second metal layer on a back surface, a method for cutting the multilayer substrate is a method for cutting the multilayer substrate having a metal layer on the front surface and a backside electrode on the back surface, the method including the step of cutting the multilayer substrate into certain depth respectively from a metal layer side and from a backside electrode side, width of a notch on the metal layer side and width of a notch on the backside electrode side being different from each other.01-29-2009
20080230912WAFER-LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME - A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.09-25-2008
20100244265SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Wiring grooves are formed on a first interlayer insulating film 09-30-2010
20100244264Semiconductor device - A semiconductor device including a first wire made of a material mainly composed of Cu, two second wires made of a material mainly composed of Cu, an interlayer dielectric film formed between the first wire and the two second wires, two vias made of a material mainly composed of Cu and each penetrating through the interlayer dielectric film and connecting the first wire and a respective one of the two second wires, and a dummy via formed between the two second wires. The dummy via is made of a material mainly composed of Cu, has a diameter smaller than a diameter of each of the two vias, and is connected to the first wire while not contributing to electrical connection between the first wire and the two second wires.09-30-2010
20100244263CHIP PACKAGES - Chip assemblies are disclosed that include a semiconductor substrate, multiple devices in and on the semiconductor substrate, a first metallization structure over the semiconductor substrate, and a passivation layer over the first metallization structure. First and second openings in the passivation layer expose first and second contact pads of the first metallization structure. A first metal post is positioned over the passivation layer and over the first contact pad. A second metal post is positioned over the passivation layer and over the second contact pad. A polymer layer is positioned over the passivation layer and encloses the first and second metal posts. A second metallization structure is positioned on the polymer layer, on the top surface of the first metal post and on the top surface of second metal post. The second metallization structure includes an electroplated metal. Related fabrication methods are also described.09-30-2010
20100244262DEPOSITION METHOD AND A DEPOSITION APPARATUS OF FINE PARTICLES, A FORMING METHOD AND A FORMING APPARATUS OF CARBON NANOTUBES, AND A SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - A deposition method of fine particles, includes the steps of irradiating a fine particle beam formed by size-classified fine particles to an irradiated subject under a vacuum state, and depositing the fine particles on a bottom part of a groove structure formed at the irradiated subject.09-30-2010
20080284030ENHANCED MECHANICAL STRENGTH VIA CONTACTS - The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.11-20-2008
20080290520Reliable metal bumps on top of I/O pads after removal of test probe marks - A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.11-27-2008
20080251925TOP LAYERS OF METAL FOR INTEGRATED CIRCUITS - The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.10-16-2008
20080251923Seal ring structures with reduced moisture-induced reliability degradation - A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening.10-16-2008
20110163453Semiconductor device and method for manufacturing the same - The present invention provides a semiconductor device having a low-k film including an interconnect layer and a highly-reliable through-substrate contact plug. The semiconductor device includes: 07-07-2011
20110163452SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SUBSTRATE PROCESSING APPARATUS - Provided is a semiconductor device including a metal film which can be formed with lower costs but still mange to have a necessary work function and oxidation resistance. The semiconductor device includes an insulating film disposed on a substrate; and a metal film disposed adjacent to the insulating film. The metal film includes a stacked structure of a first metal film and a second metal film. The oxidation resistance of the first metal film is greater than that of the second metal film. The second metal film has a work function greater than 4.8 eV and is different from the first metal film in material. The first metal film is disposed between the second metal film and the insulating film.07-07-2011
20110074032Semiconductor device - A semiconductor device which is capable of preventing interface peeling and a crack from occurring in the vicinity of the edge part of a rewiring layer is provided. The semiconductor device includes a semiconductor substrate, an electrode pad formed on the semiconductor substrate, a first insulation film formed on the semiconductor substrate having a first aperture which exposes the electrode pad, a first conductor film formed on the electrode pad and the first insulation film, an external electrode electrically connected to the first conductor film, and a sealing resin which covers the first conductor film and the first insulation film. The first conductor film includes a plurality of copper layers which are stacked so that an outer edge portion of the first conductor film has a stepped portion.03-31-2011
20100078821METAL CAP LAYER WITH ENHANCED ETCH RESISTIVITY FOR COPPER-BASED METAL REGIONS IN SEMICONDUCTOR DEVICES - During the fabrication of sophisticated metallization systems of semiconductor devices, material deterioration of conductive cap layers may be significantly reduced by providing a noble metal on exposed surface areas after the patterning of the corresponding via openings. Hence, well-established wet chemical etch chemistries may be used while not unduly contributing to process complexity.04-01-2010
20090267233BONDED SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING THE SAME - A bonded semiconductor structure static random access memory circuit includes a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a conductive line. The memory circuit includes a donor substrate which includes a semiconductor layer stack coupled to a donor substrate body region through a detach region, wherein the semiconductor layer stack is coupled to the interconnect region through a bonding interface, and wherein the semiconductor layer stack includes a pn junction.10-29-2009
20090200676SEMICONDUCTOR DEVICE - A semiconductor device which includes a first wiring with a via connected to the first wiring, a second wiring connected to the via and a dummy via disposed adjacent to the via at a distance of 100 nm or less and formed on the same layer as the via.08-13-2009
20110215475MULTI-SURFACE IC PACKAGING STRUCTURES - An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.09-08-2011
20110108989PROCESS FOR REVERSING TONE OF PATTERNS ON INTEGERATED CIRCUIT AND STRUCTURAL PROCESS FOR NANOSCALE FABRICATION - A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.05-12-2011
20110115091SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films 05-19-2011
20080303160Method for fabricating dual damascene structures using photo-imprint lithography, methods for fabricating imprint lithography molds for dual damascene structures, materials for imprintable dielectrics and equipment for photo-imprint lithography used in dual damascene patterning - The process of producing a dual damascene structure used for the interconnect architecture of semiconductor chips. More specifically the use of imprint lithography to fabricate dual damascene structures in a dielectric and the fabrication of dual damascene structured molds.12-11-2008
20120306083SEMICONDUCTOR INTEGRATED CIRCUIT WITH MULTI-CUT VIA AND AUTOMATED LAYOUT METHOD FOR THE SAME - A semiconductor integrated circuit includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first overlap area, a second overlap area, a multi-cut via, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring in the second overlap area. A width of the second portion of the second wiring corresponding to a first direction is longer than a width of the first portion of the second wiring corresponding to the first direction. A distance between the center of the first via and the center of the second via is longer than the width of the first portion of second wiring.12-06-2012
20120306082SEMICONDUCTOR DEVICE AND STRUCTURE FOR HEAT REMOVAL - A device, including: a first layer of first transistors, overlaid by at least one interconnection layer, wherein the interconnection layer includes metals such as copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, wherein the second layer is less than about 0.4 micron thick; and a connection path connecting the second transistors to the interconnection layer, wherein the connection path includes at least one through-layer via, and the through-layer via includes material whose co-efficient of thermal expansion is within about 50 percent of the second layer coefficient of thermal expansion.12-06-2012
20080303157HIGH THERMAL CONDUCTIVITY SUBSTRATE FOR A SEMICONDUCTOR DEVICE - A method and apparatus for packaging semiconductor dies for increased thermal conductivity and simpler fabrication when compared to conventional semiconductor packaging techniques are provided. The packaging techniques described herein may be suitable for various semiconductor devices, such as light-emitting diodes (LEDs), central processing units (CPUs), graphics processing units (GPUs), microcontroller units (MCUs), and digital signal processors (DSPs). For some embodiments, the package includes a ceramic substrate having an upper cavity with one or more semiconductor dies disposed therein and having a lower cavity with one or more metal layers deposited therein to dissipate heat away from the semiconductor dies. For other embodiments, the package includes a ceramic substrate having an upper cavity with one or more semiconductor dies disposed therein and having a lower surface with one or more metal layers deposited thereon for efficient heat dissipation.12-11-2008
20110316161METHOD OF PRODUCING A DUAL DAMASCENE MULTILAYER INTERCONNECTION AND MULTILAYER INTERCONNECTION STRUCTURE - In an insulating film structure having a barrier insulating film, a via interlayer insulating film, a wiring interlayer insulating film, and a hard mask film stacked in this order on an underlayer wiring, a via hole pattern is formed in the insulating film structure, then a groove pattern is formed in the hard mask film, and a grove is formed in the insulating film structure using this as a mask. According to the prior art, the via side wall is oxidized equally severely in the both processes. The trench side wall is oxidized severely in the via first process according to the prior art, whereas, according to the present invention, the oxidation thereof is suppressed to such an extent that an almost non-oxidized state can be created.12-29-2011
20110049719SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes a first interconnect layer insulating film, first copper interconnects that are embedded in the first interconnect layer insulating film, and an interlayer insulating film that is formed on the first copper interconnects and the first interconnect layer insulating film. The semiconductor device includes a second interconnect layer insulating film that is formed on the interlayer insulating film and second copper interconnects that are embedded in the second interconnect layer insulating film. The first and second interconnect layer insulating films include first and second low dielectric constant films, respectively. The interlayer insulating film has higher mechanical strength than the first and second interconnect layer insulating films.03-03-2011
20090032956DUMMY METAL FILL SHAPES FOR IMPROVED RELIABILITY OF HYBRID OXIDE/LOW-K DIELECTRICS - A semiconductor structure including a first rigid dielectric layer and a second rigid dielectric layer. A first non-rigid low-k dielectric layer is formed between the first and second rigid dielectric layer. A plurality of dummy fill shapes is formed in the first non-rigid layer which replace portions of the first non-rigid low-k dielectric layer with lower coefficient of thermal expansion (CTE) metal such that an overall CTE of the first non-rigid low-k dielectric layer and the plurality of dummy fill shapes matches a CTE of the first and second rigid dielectric layers more closely than that of the first non-rigid low-k dielectric layer alone.02-05-2009
20120153483BARRIERLESS SINGLE-PHASE INTERCONNECT - A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an opening in the dielectric layer to expose the conductive layer; forming a barrierless single-phase interconnect comprising a metal or compound having a melting point between a melting point of copper and a melting point of tungsten. Forming includes depositing a layer of metal or compound within the opening and on an upper surface of the dielectric layer Preferably, the barrierless single-phase interconnect comprises cobalt or a cobalt containing compound. Thus, an interconnect structure, including a via and associated line, is made up of a single-phase metal or compound without the use of a different material between the interconnect and the underlying dielectric, thus improving electrical performance and reliability and further simplifying the interconnect formation process.06-21-2012
20100230819Semiconductor Constructions - Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.09-16-2010
20090140431HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE - By forming the first metallization layer of a semiconductor device as a dual damascene structure, the contact elements may be formed on the basis of a significantly reduced aspect ratio, thereby enhancing process robustness and also improving electrical performance of the contact structure.06-04-2009
20120313245SEMICONDUCTOR DEVICE - One embodiment provides a semiconductor device having: a core substrate having first and second surfaces and an accommodation hole penetrating therethrough; a semiconductor element accommodated in the accommodation hole so that a front surface thereof is on the first surface side; a first metal film formed on a back surface of the semiconductor element; a second metal film formed on the second surface of the core substrate; an insulating layer covering the first and second metal films; and a third metal film formed on the insulating layer, via parts thereof penetrating through the insulating layer to respectively reach the first and second metal films.12-13-2012
20100289145WAFER CHIP SCALE PACKAGE WITH CENTER CONDUCTIVE MASS - A method and structure for an unencapsulated wafer section such as a wafer chip scale package (WCSP) includes a plurality of interconnect terminals and a pad metallization structure on an active surface of a WCSP chip. An area of the pad metallization structure is larger than an area of one of the interconnect terminals and, in an embodiment, larger than an area of two interconnect terminals. A plurality of conductive interconnects are attached to the plurality of interconnect terminals. The conductive interconnects are placed in contact with first lands of a supporting substrate, which can be a printed circuit board. Subsequently, a conductive mass is electrically coupled with a second land of the receiving substrate, with the second land being connected to at least one via of the supporting substrate which can, in turn, be connected to a plane of the supporting substrate. Improved thermal characteristics can result.11-18-2010
20120126410Contact Array for Substrate Contacting - The present invention relates to a contact arrangement (05-24-2012
20100052173SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A first impurity diffusion layer in a memory cell portion and a second impurity diffusion layer in a peripheral circuit portion are provided in a surface of a semiconductor substrate and having upper faces substantially flush with each other. First and second insulating films are formed to cover the upper faces of the impurity diffusion layers, and having substantially uniform film thicknesses. A first metal plug is formed in the insulating films, and connected to the first impurity diffusion layer. A second metal plug is formed in the first insulating film, to have a lower height than the first metal plug, and is connected to the second impurity diffusion layer. A first metal interconnection is connected to an upper end portion of the first metal plug, and having an upper face embedded in and flush with the second insulating film. A second metal interconnection is connected to an upper end portion of the second metal plug, and having an upper face embedded in and flush with the second insulating film.03-04-2010
20100270675SEMICONDUCTOR DEVICE HAVING DAMASCENE INTERCONNECTION STRUCTURE THAT PREVENTS VOID FORMATION BETWEEN INTERCONNECTIONS HAVING TRANSPARENT DIELECTRIC SUBSTRATE - A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which includes a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem where the material of the first main interconnection transfers from a portion connected to the second interconnection due to electromigration to form a void, with the result that the first interconnection is disconnected from the second interconnection.10-28-2010
20100270674High quality electrical contacts between integrated circuit chips - Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive chain, acting as a spring or self-adaptive contact structure (SACS) in a wafer bonding process, is designed to reduce bonding interface stress, to increase bonding interface reliability, and to have an adjustable height to close or eliminate undesirable opens or voids between two integrated circuits.10-28-2010
20090079079SEMICONDUCTOR DEVICE WITH AN AIR GAP BETWEEN LOWER INTERCONNECTIONS AND A CONNECTION PORTION TO THE LOWER INTERCONNECTIONS NOT FORMED ADJACENT TO THE AIR GAP - A method for fabricating a semiconductor device includes the steps of: forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap.03-26-2009
20110121460SEMICONDUCTOR DEVICE HAVING A MULTILAYER INTERCONNECTION STRUCTURE - A semiconductor device has a multilayer interconnection structure, wherein the multilayer interconnection structure comprises at least a first interconnection layer and a second interconnection layer formed over the first interconnection layer, the first interconnection layer comprises a first conductor pattern embedded in a first interlayer insulation film and constituting a part of an interconnection pattern and a second, another interconnection pattern embedded in the first interlayer insulation film, the second interconnection layer comprises a third conductor pattern embedded in a second interlayer insulation film and constituting a part of said interconnection pattern, the third conductor pattern has an extension part in a part thereof so as to extend in a layer identical to the third conductor pattern, the third conductor pattern being electrically connected to the first conductor pattern at a first region of the extension part via a first via plug, the extension part making a contact with the second conductor pattern at a second region further away from, or closer to the third conductor pattern with regard to the first region via a second via-plug of a diameter smaller than the first via-plug, the extension part of the third conductor pattern, the first via-plug and the second via-plug form, together with the second interlayer insulation film, a dual damascene structure.05-26-2011
20090315184Semiconductor Device - Disclosed is a semiconductor device that is capable of preventing impurities such as moisture from being introduced into an active region at the time of dicing and at the time of bonding and that is capable of being easily miniaturized. The semiconductor device includes a cylindrical dummy wire having an opening for allowing a wire interconnecting a semiconductor element and an external connection terminal to pass therethrough, extending in an insulation film provided on a semiconductor layer having the semiconductor element to surround the semiconductor element, and disposed inside the external connection terminal.12-24-2009
20120319281SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films 12-20-2012
20100193958Semiconductor Device and a Method of Manufacturing the Same - A technique is provided for improving the security of information stored in a semiconductor device. Multilayer wiring layers are formed over a semiconductor substrate. Wirings are formed on the uppermost wiring layer among those multilayer wiring layers. On the wirings, there is formed, in the following order, a silicon oxide film, a colored thin film, and a silicon oxide film, over which, a silicon nitride film serving as a surface protective film is formed. In other words, the invention is characterized by that the colored thin film is formed between the wiring constituting the uppermost wiring layer and the silicon nitride film serving as the surface protective film. The colored thin film has a function of attenuating visible light and laser light in the specific wavelength region, and is formed of, for example, a silicon oxide film containing cobalt oxide.08-05-2010
20080251924Post Passivation Interconnection Schemes On Top Of The IC Chips - A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.10-16-2008
20080237870Semiconductor device - The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.10-02-2008
20130168865SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films 07-04-2013
20080224319Micro electro-mechanical system and method of manufacturing the same - A micro electro-mechanical system, which can be stably formed so as to prevent sticking of a movable part and which has a narrow gap, and a method of manufacturing the same are provided. The micro electro-mechanical system includes at least one fixed electrode formed above a principal surface of a semiconductor substrate and at least one movable electrode formed on the principal surface. The at least one movable electrode includes the movable part separated from the principal surface and the at least one fixed electrode. The movable part is movable with respect to the principal surface and the at least one fixed electrode. The method of manufacturing the micro electromechanical system includes a sacrifical film formation step for forming a sacrifical film above the principal surface, an electrode layer formation step for forming an electrode layer above the principal surface so as to cover over the sacrifical film, an etching step for partially etching the electrode layer via a pattern so as to form the at least one electrode and the at least one fixed electrode, a sacrifical film removal step for removing the sacrifical film, and a conducting film formation step for forming a conducting film on surfaces of the at least one electrode and the at least one fixed electrode.09-18-2008
20080224318System and method for integrated circuit arrangement having a plurality of conductive structure levels - An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.09-18-2008
20130093092ELECTRONIC DEVICE AND METHOD FOR PRODUCING SAME - An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench being filled with the interconnection pattern; a metal film on a surface of the interconnection pattern, the metal film having a higher elastic modulus than Cu; a second insulating film on the first insulating film; and a via plug composed of Cu and arranged in the second insulating film, the via plug being in contact with the metal film.04-18-2013
20110272813SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a cap insulating film, including Si and C, on a substrate; forming an organic silica film, having a composition ratio of the number of carbon atoms to the number of silicon atoms higher than that of the cap insulating film, on the cap insulating film; and forming two or more concave portions, having different opening diameters, in the organic silica film, by plasma processing in which mixed gas including inert gas, N-containing gas, fluorocarbon gas and oxidant gas is used.11-10-2011
20110272812STRUCTURE AND METHOD FOR MANUFACTURING INTERCONNECT STRUCTURES HAVING SELF-ALIGNED DIELECTRIC CAPS - Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.11-10-2011
20130175692SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films 07-11-2013
20130175691SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films 07-11-2013
20080197502SEMICONDUCTOR DEVICE HAVING METAL WIRINGS OF LAMINATED STRUCTURE - A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material.08-21-2008
20080197501INTERCONNECTION SUBSTRATE AND SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF INTERCONNECTION SUBSTRATE - An interconnection substrate including therein one or more resin layers, each of the resin layers including therein a via-hole penetrating from a top surface to a bottom surface of the resin layer. A via-plug of metal particles is formed in the via-hole. Each of the metal particles has a flat shape generally parallel to a plane of the resin layer.08-21-2008
20080197500INTERCONNECT STRUCTURE WITH BI-LAYER METAL CAP - A structure and method of fabricating an interconnect structures with bi-layer metal cap is provided. In one embodiment, the method includes forming an interconnect feature in a dielectric material layer; and forming a bi-layer metallic cap on a top surface of the interconnect feature. The method further includes depositing a blanket layer of a dielectric capping layer, wherein the depositing covers an exposed surface of the dielectric material layer and a surface of the bi-layer metallic cap. The bi-layer metallic cap includes a metal capping layer formed on a conductive surface of the interconnect feature; and a metal nitride formed on a top portion of the metal capping layer. An interconnect structure is also described having an interconnect feature formed in a dielectric layer; a bi-layer metallic cap formed on a top portion of the interconnect feature; and a dielectric capping layer formed over the bi-layer metallic cap.08-21-2008
20080197499STRUCTURE FOR METAL CAP APPLICATIONS - An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.08-21-2008
20110221064ELECTROMIGRATION RESISTANT ALUMINUM-BASED METAL INTERCONNECT STRUCTURE - A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl09-15-2011
20110241212STRESS LAYER STRUCTURE - A stress layer structure includes an active stress portion and a dummy stress portion, both formed of a stress material and disposed on the substrate. The active stress portion includes first and second active stress patterns in a region where active devices are formed. The first and second active stress patterns coverrespective active regions, and are separated from each other. The dummy stress portion includes a first dummy stress pattern formed directly on the substrate and disposed between and separated from the first and second active stress patterns.10-06-2011
20100301483LIGHT-BLOCKING LAYER SEQUENCE HAVING ONE OR MORE METAL LAYERS FOR AN INTEGRATED CIRCUIT AND METHOD FOR THE PRODUCTION OF THE LAYER SEQUENCE - In an integrated circuit, a light sensitive area is protected against radiation by arranging a light blocking layer sequence (12-02-2010
20100301482SRAM BIT CELL WITH SELF-ALIGNED BIDIRECTIONAL LOCAL INTERCONNECTS - Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.12-02-2010
20100308464SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.12-09-2010
20130187276MICROELECTRONIC DEVICE HAVING METAL INTERCONNECTION LEVELS CONNECTED BY PROGRAMMABLE VIAS - A microelectronic device, including: a substrate and a plurality of metal interconnection levels stacked on the substrate; a first metal line of a given metal interconnection level; a second metal line of another metal interconnection level located above the given metal interconnection level, the first and second lines are interconnected via at least one semiconductor connection element extending in a direction forming a nonzero angle with the first metal lines and the second metal line; and a gate electrode capable of controlling conduction of the semiconductor connection element.07-25-2013
20130187275SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF - A three dimensional semiconductor integrated circuit device includes a stacking of a plurality of semiconductor chips each including a plurality of through via-plugs, in each of the semiconductor chips, a plurality of through via-plugs are connected commonly with each other by a connection pad provided on a top surface or bottom surface of the semiconductor chip, the connection pad on a top surface of a first semiconductor chip being joined directly to a corresponding connection pad on a bottom surface of a second semiconductor chip stacked thereon.07-25-2013
20120018889PROCESS FOR PRODUCING A METALLIZATION LEVEL AND A VIA LEVEL AND CORRESPONDING INTEGRATED CIRCUIT - A process for producing an upper metallization level and a via level connecting this upper metallization level to a lower metallization level includes: producing an insulating region on the lower metallization level; producing a hard mask on the insulating region (01-26-2012
20090243109METAL CAP LAYER OF INCREASED ELECTRODE POTENTIAL FOR COPPER-BASED METAL REGIONS IN SEMICONDUCTOR DEVICES - A conductive cap material for a copper region may be provided with enhanced etch resistivity by taking into consideration the standard electrode potential of one or more of the species contained therein. For example, instead of a conventionally used CoWP alloy, a modified alloy may be used, by substituting the cobalt species by a metallic species having a less negative standard electrode potential, such as nickel. Consequently, device performance may be enhanced, while at the same time the overall process complexity may be reduced.10-01-2009
20130200521INDUCTORS AND WIRING STRUCTURES FABRICATED WITH LIMITED WIRING MATERIAL - Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature, which may be a trench or a wire, is formed that includes a sidewall intersecting a top surface of a dielectric layer. A surface layer is formed on the sidewall of the feature. The surface layer is comprised of a conductor and has a thickness selected to provide a low resistance path for the conduction of a high frequency signal.08-08-2013

Patent applications in class Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)

Patent applications in all subclasses Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)