Entries |
Document | Title | Date |
20080224314 | Method and Apparatus for Forming a Noble Metal Layer, Notably on Inlaid Metal Features - A cap layer for a metal feature such as a copper interconnect on a semiconductor wafer is formed by immersion plating a more noble metal (e.g. Pd) onto the copper interconnect and breaking up, preferably by mechanical abrasion, loose nodules of the noble metal that form on the copper interconnect surface. The mechanical abrasion removes plated noble metal which is only loosely attached to the copper surface, and then continued exposure of the copper surface to immersion plating chemicals leads to plating at new sites on the surface until a continuous, well-bonded noble metal layer has formed. The method can be implemented conveniently by supplying immersion plating chemicals to the surface of a wafer undergoing CMP or undergoing scrubbing in a wafer-scrubber apparatus. | 09-18-2008 |
20080224315 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device having a bonding wireless structure, a preform material is used for electrically connecting a metal plate serving as a connection with an electrode layer of a semiconductor chip. Thus, a multilayered metal layer needs to be provided in a junction part between the preform material and a first electrode layer, but has a problem of a variation in electrical characteristics and characteristic fluctuations in a temperature cycling test and the like. A metal layer mainly made of titanium is formed with a thickness of 1000 Å, as a bottom layer (a first metal layer in contact with an electrode layer of a semiconductor chip) in a multilayered metal layer with an electron impact heating deposition method. Thus, the film quality of the Ti layer is improved compared with the conventional structure, which minimizes variations in electrical characteristics and characteristic fluctuations in the multilayered metal layer. | 09-18-2008 |
20080258301 | Semiconductor device and manufacturing method of the same - A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced. | 10-23-2008 |
20080265415 | Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same - A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method. | 10-30-2008 |
20080296767 | Composition for cleaning semiconductor device - A sulfur-containing detergent composition for cleaning a semiconductor device having an aluminum wire, wherein the sulfur-containing detergent composition is capable of forming a protective film containing a sulfur atom on a surface of an aluminum film in a protective film-forming test; a semiconductor device comprising a protective film containing a sulfur atom on a surface of an aluminum wire, wherein sulfur atom is contained within a region of at least 5 nm in its thickness direction from the surface of the protective film; and method for manufacturing a semiconductor device, comprising the step of contacting an aluminum wire of the semiconductor device with the sulfur-containing detergent composition as defined above, thereby forming a sulfur-containing protective film on the surface of the aluminum wire. The semiconductor device can be suitably used in the manufacture of electronic parts such as LCD, memory and CPU. Especially, the semiconductor device is suitably used in the manufacture of a highly integrated semiconductor with advanced scale-down. | 12-04-2008 |
20080308936 | METHOD AND STURCTURE FOR SELF-ALIGNED DEVICE CONTACTS - Disclosed are embodiments of a semiconductor structure with a partially self-aligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole. | 12-18-2008 |
20090001576 | INTERCONNECT USING LIQUID METAL - A semiconductor package comprises a substrate that has a first protruding interconnect and a semiconductor die that has a second protruding interconnect that faces the first protruding interconnect. The package further comprises a spacer provided between the substrate and the die, wherein the spacer comprises a hole filled with liquid metal to couple the first protruding interconnect to the second protruding interconnect. | 01-01-2009 |
20090065938 | Semiconductor Element and Method for Manufacturing Same - The object of the present invention is to provide a semiconductor element containing an n-type gallium nitride based compound semiconductor and a novel electrode that makes an ohmic contact with the semiconductor. | 03-12-2009 |
20090091034 | Driving circuit of a liquid crystal display panel - A driving circuit of a liquid crystal display panel includes a substrate, a plurality of driver IC chips located on the substrate, a current supplier, and a first conductive wire set. The first conductive wire set has a plurality of conductive wire segments for connecting the driver IC chips in parallel to the current supplier. Furthermore, the conductive wire segments each have a form, such that paths formed of the conductive wire segments from the current supplier to the respective driver IC chips have an equal resistance, and, accordingly, each of the driver IC chips obtain the same input voltage. Hence, a problem of band mura is avoided. | 04-09-2009 |
20090115060 | INTEGRATED CIRCUIT DEVICE AND METHOD - An integrated circuit device includes a semiconductor chip with a metallization layer on the chip. A gas-phase deposited insulation layer is disposed on the metallization layer. | 05-07-2009 |
20090146304 | CARBON NANOTUBE INTEGRATED CIRCUIT DEVICES AND METHODS OF FABRICATION THEREFOR USING PROTECTED CATALYST LAYERS - A method of fabricating an integrated circuit device is provided. The method includes sequentially forming a lower interconnection layer, a catalyst layer, and a buffer layer on a semiconductor substrate, forming an interlayer dielectric layer to cover the buffer layer, forming a contact hole through the interlayer dielectric layer so that a top surface of the buffer layer may be partially exposed, removing a portion of the buffer layer exposed by the contact hole so that a top surface of the catalyst layer may be exposed, and growing carbon nanotubes from a portion of the catalyst layer exposed by the contact hole so that the contact hole may be filled with the carbon nanotubes. | 06-11-2009 |
20090200667 | OHMIC CONTACT FILM IN SEMICONDUCTOR DEVICE - The invention provides an ohmic contact film formed between a doped semiconductor material layer and a conductive material layer of a semiconductor device. The composition of the ohmic contact film according to a preferred embodiment of the invention is represented by the general formula M | 08-13-2009 |
20090212431 | THERMALLY PROGRAMMABLE ANTI-REVERSE ENGINEERING INTERCONNECTS AND METHODS OF FABRICATING SAME - An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires. | 08-27-2009 |
20090250815 | SURFACE TREATMENT FOR SELECTIVE METAL CAP APPLICATIONS - Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal cap formation provides a means for controlling the selective formation of the metal cap directly on the non-recessed surface of a conductive material. That is, the selective formation of the metal cap directly on the non-recessed surface of a conductive material is enhanced since the formation rate of the metal cap on the non-recessed surface of a conductive material is greater than on the hydrophobic surface of the low k dielectric material. It is observed that the hydrophobic surface may be a result of treating a damaged surface of the dielectric material with a silylating agent prior to the selective formation of the noble metal cap or, as a result of forming a hydrophobic polymeric layer on the surface of the dielectric material prior to the selective deposition of the noble metal cap. The hydrophobic polymeric layer typically includes atoms of Si, C and O. | 10-08-2009 |
20090294967 | Diodes, And Methods Of Forming Diodes - Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes. | 12-03-2009 |
20090302471 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - There is provided a semiconductor device including a semiconductor substrate on which a plurality of semiconductor chips having electrode pads is formed, an internal connection terminal provided on each of the electrode pads, an insulating layer provided to cover the plurality of semiconductor chips and the internal connection terminals, and a wiring pattern connected to the internal connection terminals across the insulating layer. This semiconductor device is characterized in that the insulating layer is configured to contain an alpha ray blocking material including polyimide and/or a polyimide-based compound. | 12-10-2009 |
20090321932 | Coreless substrate package with symmetric external dielectric layers - A thin die Package Substrate is described that may be produced using existing chemistry. In one example, a package substrate is built over a support material. A dry film photoresist layer is formed over the package substrate. The support material is removed from the package substrate. The dry film photoresist layer is removed from the substrate and the substrate is finished for use with a package. | 12-31-2009 |
20100052167 | METAL LINE HAVING A MOxSiy/Mo DIFFUSION BARRIER OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A metal line having a Mo | 03-04-2010 |
20100072620 | Semiconductor Chip with Backside Conductor Structure - Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway. | 03-25-2010 |
20100078816 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a metal conductive layer formed on a substrate, a transparent electrode film formed on the substrate and joined to the metal conductive layer and an interlayer insulating film isolating the metal conductive layer and the transparent conductive film. The metal conductive layer has a lower aluminum layer made of aluminum or aluminum alloy, an intermediate impurity containing layer made of aluminum or aluminum alloy containing impurities and formed on a substantially entire upper surface of the lower aluminum layer and an upper aluminum layer made of aluminum or aluminum alloy and formed on the intermediate impurity containing layer. In the interlayer insulating film and the upper aluminum layer, a contact hole penetrates therethrough and locally exposes the intermediate impurity containing layer, and the transparent electrode film is joined to the metal conductive layer in the intermediate impurity containing layer exposed from the contact hole. | 04-01-2010 |
20100181669 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In order to improve a bonding reliability of a semiconductor device, in the semiconductor device, the wiring patterns on the substrate surface and the connection electrodes are electrically connected by face-down mounting. The connection electrodes are formed on the connecting surface of the semiconductor element and made from a conductive material, and a part of the wiring patterns has such a width that allows the connection electrodes formed on the part of said wiring patterns to have a fillet shape. | 07-22-2010 |
20100237500 | Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site - A semiconductor substrate includes a first conductive layer formed over the semiconductor substrate. The first conductive layer has first and second portions which are electrically isolated during formation of the first conductive layer. A solder resist layer is formed over the first conductive layer and semiconductor substrate. An opening is formed in the solder resist layer to expose the first conductive layer. A seed layer is formed over the semiconductor substrate and first conductive layer within the opening. A second conductive layer is formed over the seed layer within the opening. The opening may expose the second portion of the first conductive layer due to solder resist registration shifting causing a defect condition. The second conductive layer electrically contacts the first and second portions of the first conductive layer. By testing the first and second portions of the first conductive layer, the defect condition can be identified. | 09-23-2010 |
20100237501 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming an insulating film including silicon, oxygen, carbon and hydrogen above a semiconductor substrate, forming a wiring trench in the insulating film, forming a metal film to be a metal wiring on the insulating film such that the metal film is provided in the wiring trench, forming the metal wiring by removing the metal film outside the wiring trench, performing a hydrophobic treatment to the surface of the insulating film after the forming the metal wiring, and forming a metal cap selectively on an upper surface of the metal wiring by plating after the performing the hydrophobic treatment. | 09-23-2010 |
20100289144 | 3D INTEGRATION STRUCTURE AND METHOD USING BONDED METAL PLANES - A method of making 3D integrated circuits and a 3D integrated circuit structure. There is a first semiconductor structure joined to a second semiconductor structure. Each semiconductor structure includes a semiconductor wafer, a front end of the line (FEOL) wiring on the semiconductor wafer, a back end of the line (BEOL) wiring on the FEOL wiring, an insulator layer on the BEOL wiring and a metallic layer on the insulator layer. The first semiconductor structure is aligned with the second semiconductor structure such that the metallic layers of each of the semiconductor structures face each other. The metallic layers of each of the semiconductor structures are in contact with and bonded to each other by a metal to metal bond wherein the bonded metallic layers form an electrically isolated layer. | 11-18-2010 |
20110006425 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate and containing a wiring trench; a first catalyst layer provided directly or via another member on side and bottom surfaces of the wiring trench; and a first graphene layer provided in the wiring trench so as to be along the side and bottom surface of the wiring trench, the first graphene layer being provided on the first catalyst layer so as to be in contact with the first catalyst layer. | 01-13-2011 |
20110057315 | MEMORY DEVICE PERIPHERAL INTERCONNECTS - An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias. | 03-10-2011 |
20110115090 | INTERCONNECT STRUCTURE INCLUDING A MODIFIED PHOTORESIST AS A PERMANENT INTERCONNECT DIELECTRIC AND METHOD OF FABRICATING SAME - A photoresist conversion that changes a patterned photoresist into a permanent patterned interconnect dielectric is described. The photoresist conversion process includes adding a dielectric enabling element into a patterned photoresist. The dielectric enabling element-containing photoresist is converted into a permanent patterned dielectric material by performing a curing step. In one embodiment, a method is described that includes providing at least one photoresist to an upper surface of a substrate. At least one interconnect pattern is formed into the at least one photoresist. A dielectric enabling element is added to the patterned photoresist and thereafter the patterned photoresist including the dielectric enabling element is cured into a cured permanent patterned dielectric material. The cured permanent patterned dielectric material includes the dielectric enabling therein. | 05-19-2011 |
20110140274 | FORMING THICK METAL INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS - Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed. | 06-16-2011 |
20110163449 | SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES - In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region. | 07-07-2011 |
20110175225 | METHOD OF FORMING AN EM PROTECTED SEMICONDUCTOR DIE - In one embodiment, a semiconductor die is formed to have sloped sidewalls. A conductor is formed on the sloped sidewalls. | 07-21-2011 |
20110193231 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - An electronic device package includes a substrate assembly, an electronic device disposed to face the substrate assembly, and a sealing ring or rings including a sealing layer and a bonding layer that is disposed between the substrate assembly and the electronic device, wherein the sealing ring(s) has a closed loop shape surrounding a sealing region of the electronic device, and the bonding layer is formed through a reaction of the sealing layer and sealing layer pad with a low-melting-point material layer whose melting point is lower than that of the sealing layer and sealing ring pad. The bonding layer is formed of an intermetallic compound of the sealing layer, sealing ring pad and low-melting-point material that melts at a temperature greater than the melting temperature of the low-melting-point material. The device package also includes electrical connections in the form of joints between the substrate assembly and electronic device. | 08-11-2011 |
20110215473 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first contact, a second contact, and an intermediate interconnection. The first contact is made of a first conductive material. The second contact is made of a second conductive material. A lower end portion of the second contact is connected to an upper end portion of the first contact. The intermediate interconnection is made of a third conductive material and isolated from the first contact and the second contact. A lower face of the intermediate interconnection is positioned higher than a lower face of the first contact. An upper face of the intermediate interconnection is positioned lower than an upper face of the second contact. A diffusion coefficient of the first conductive material with respect to the second conductive material is lower than a diffusion coefficient of the third conductive material with respect to the second conductive material. | 09-08-2011 |
20110221062 | METHODS FOR FABRICATION OF AN AIR GAP-CONTAINING INTERCONNECT STRUCTURE - Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures. | 09-15-2011 |
20120025379 | FRONT-END PROCESSING OF NICKEL PLATED BOND PADS - A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. | 02-02-2012 |
20120032331 | CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF AND PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer. | 02-09-2012 |
20120080790 | APPARATUS AND METHOD FOR UNIFORM METAL PLATING - Apparatus and methods for uniform metal plating onto a semiconductor wafer, such as GaAs wafer, are disclosed. One such apparatus can include an anode and a showerhead body. The anode can include an anode post and a showerhead anode plate. The showerhead anode plate can include holes sized to dispense a particular plating solution, such as plating solution that includes gold, onto a wafer. The showerhead body can be coupled to the anode post and the showerhead anode plate. The showerhead body can be configured to create a seal sufficient to substantially prevent a reduction of pressure in the plating solution flowing from the anode post to holes of the showerhead anode plate. | 04-05-2012 |
20120104610 | INTERCONNECT STRUCTURE WITH ENHANCED RELIABILITY - An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided. | 05-03-2012 |
20120104611 | SEMICONDUCTOR STRUCTURE WITH INSULATED THROUGH SILICON VIA - Techniques described herein generally relate to laminated semiconductor structures. In some examples, method of forming a polyimide film are described. An example method may include forming a through hole in a laminated semiconductor structure that includes multiple stacked semiconductor layers. An inner wall of the laminated semiconductor structure can define the through hole. The inner wall can be exposed to a solution including a salt of polyamic acid and/or a polyamic acid that can be precipitated on the inner wall. The precipitated polyamic acid on the inner wall can be transformed into a polyimide film substantially coating the inner wall. | 05-03-2012 |
20120119364 | ADDING CAP TO COPPER PASSIVATION FLOW FOR ELECTROLESS PLATING - An integrated circuit includes a metal seed layer contacting a metal element of a top interconnect layer, a plated copper pad over the seed layer, a plated metal cap layer on the top surface of the copper pad, an upper protective overcoat covering a lateral surface of the copper pad and overlapping a top surface of the cap layer with a bond pad opening exposing the cap layer, and a bond pad of electroless plated metal in the bond pad opening. | 05-17-2012 |
20120119365 | INTEGRATED CIRCUIT DEVICES HAVING CONDUCTIVE STRUCTURES WITH DIFFERENT CROSS SECTIONS - A semiconductor device includes a first conductive structure and a second conductive structure. The first conductive structure is formed in a first region of a substrate, and includes a first polysilicon layer pattern, a first conductive layer pattern having a resistance smaller than that of the first polysilicon layer pattern, and a first hard mask. The second conductive structure is formed in a second region of the substrate and has a thickness substantially the same as that of the first conductive structure. The second conductive structure includes a second polysilicon layer pattern, a second conductive layer pattern having a resistance smaller than that of the second polysilicon layer pattern and having a thickness different from that of the first conductive layer pattern, and a second hard mask. | 05-17-2012 |
20120139112 | Selective Seed Layer Treatment for Feature Plating - Conventional metallization processes fail at high density or small feature size patterns. For example, during patterning dry films may collapse or lift-off resulting in short circuits or open circuits in the metallization pattern. An exemplary method for metallization of integrated circuits includes forming features such as trenches, pads, and planes in a dielectric layer and depositing and selectively treating a seed layer in desired features of the dielectric layer. The treated regions of the seed layer may be used as a seed for electroless deposition of conductive material, such as copper, into the features. When the seed layer is a catalytic ink, the seed layer may be treated by curing the catalytic ink with a laser. | 06-07-2012 |
20120153476 | ETCHED WAFERS AND METHODS OF FORMING THE SAME - Etched wafers and methods of forming the same are disclosed. In one embodiment, a method of etching a wafer is provided. The method includes forming a metal hard mask on the wafer using electroless plating, patterning the metal hard mask, and etching a plurality of features on the wafer using an etcher. The plurality of featured are defined by the metal hard mask. | 06-21-2012 |
20120228770 | METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE - A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous. | 09-13-2012 |
20120267784 | Semiconductor Device and Bonding Wire - A semiconductor device includes a semiconductor chip, a contact pad of the semiconductor chip and a first layer arranged over the contact pad. The first layer includes niobium, tantalum or an alloy including niobium and tantalum. | 10-25-2012 |
20130026631 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor apparatus and a manufacturing method thereof. The manufacturing method of the semiconductor apparatus includes: forming a semiconductor chip on a semiconductor substrate; adhering a carrier wafer with a plurality of through holes onto the semiconductor chip; polishing the semiconductor substrate; forming a first via hole at the rear side of the polished semiconductor substrate; forming a first metal layer below the polished semiconductor substrate and at the first via hole; and removing the carrier wafer from the polished semiconductor substrate. | 01-31-2013 |
20130062768 | METHOD FOR THE PRODUCTION OF A SUBSTRATE HAVING A COATING COMPRISING COPPER, AND COATED SUBSTRATE AND DEVICE PREPARED BY THIS METHOD - A method for producing a substrate with a copper or a copper-containing coating is disclosed. The method comprises a first step wherein a first precursor, a second precursor and a substrate are provided. The first precursor is a copper complex that contains no fluorine and the second precursor is selected from a ruthenium complex, a nickel complex, a palladium complex or mixtures thereof. In the second step, a layer is deposited at least on partial regions of a surface of the substrate by using the first precursor and the second precursor by means of atomic layer deposition (ALD). The molar ratio of the first precursor:second precursor used for the ALD extends from 90:10 to 99.99:0.01. The obtained layer contains copper and at least one of ruthenium, nickel and palladium. Finally, a reduction is performed step in which a reducing agent acts on the substrate obtained after depositing the copper-containing layer. | 03-14-2013 |
20130200518 | Devices Including Metal-Silicon Contacts Using Indium Arsenide Films and Apparatus and Methods - Described are apparatus and methods for forming films comprise indium and arsenic. In particular, these films may be formed in a configuration of two or more chambers under “load lock” conditions. These films may include additional components as dopants, such as aluminum and/or gallium. Such films can be used in metal/silicon contacts having low contact resistances. Also disclosed are devices including the films comprising indium arsenide. | 08-08-2013 |
20130221526 | System in Package and Method for Manufacturing The Same - A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by help of a sintered bonding layer, which is made from a sinter paste. Lamination of the substrate and further layers providing the laminate body and sintering of the sinter paste may be performed in a single and common curing step. | 08-29-2013 |
20130228922 | SEMICONDUCTOR DEVICE STRUCTURES AND PRINTED CIRCUIT BOARDS COMPRISING SEMICONDUCTOR DEVICES - The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed. | 09-05-2013 |
20130256890 | SHALLOW VIA FORMATION BY OXIDATION - A method, and an apparatus formed thereby, to construct shallow recessed wells on top of exposed conductive vias on the surface of a semiconductor. The shallow recessed wells are subsequently filled with a conductive cap layer, such as a tantalum nitride (TaN) layer, to prevent or reduce oxidation which may otherwise occur naturally when exposed to air, or possibly occur during an under-bump metallization process. | 10-03-2013 |
20130307151 | METHOD TO RESOLVE HOLLOW METAL DEFECTS IN INTERCONNECTS - A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer. | 11-21-2013 |
20130307152 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield. | 11-21-2013 |
20140035139 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To prevent cracking in a passivation film by oxidation of an antireflection film, a semiconductor device includes a metal wiring layer for a pad, an insulating layer which is provided so as to cover the metal wiring layer and which includes an opening portion from which a part of a surface of the metal wiring layer is exposed. The metal wiring layer includes a first metal layer, and a second metal layer which is provided over the first metal layer except for the opening portion and which is thinner than the first metal layer. The metal wiring layer has a groove portion in a predetermined region except for the opening portion. The first metal layer protrudes, in an eaves shape, to the groove portion. The second metal layer on a side wall inside the groove portion is thinner than the second metal layer outside the groove portion. | 02-06-2014 |
20140035140 | Semiconductor Structure and Method for Manufacturing the Same - A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer. | 02-06-2014 |
20140048936 | HIGH TEMPERATURE INTERCONNECT ASSEMBLIES FOR HIGH TEMPERATURE ELECTRONICS UTILIZING TRANSITION PADS - An interconnect assembly that operates in environments well exceeding 200° C. without degradation and/or failure. The interconnect assembly of the present invention eliminates the incompatible metal interfaces of the prior art and relies on aluminum first-metal wire to electrically connect to first-metal pads on a chip and a second-metal wire to electrically connect to second-metal plated contacts on a package. Both wire types are then electrically connected together utilizing a high temperature transition pad disposed between the chip and contacts on the package, therefore eliminating incompatible metal interfaces of the prior art. | 02-20-2014 |
20140131871 | INTERCONNECTION STRUCTURE AND FABRICATION THEREOF - A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad. | 05-15-2014 |
20140138830 | METAL INTERCONNECTION STRUCTURE - A metal interconnection structure includes a substrate and a protective laver. The substrate includes at least a first conductive layer. The protective layer is a single-layered structure disposed on the substrate, and a quantity of oxygen (O) in an upper part of the protective layer is more than a quantity of oxygen (O) in a lower part of the protective layer. A material of the upper part of the protective layer includes silicon oxycarbide (SiCO) or silicon oxycarbonitride (SiCNO), and a material of the lower part of the protective layer includes silicon carbide (SiC) or silicon carbonitride (SiCN). | 05-22-2014 |
20140138831 | SURFACE FINISH ON TRACE FOR A THERMAL COMPRESSION FLIP CHIP (TCFC) - Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is | 05-22-2014 |
20140159240 | Thermal Management Structure with Integrated Heat Sink - A thermal management structure for a device is provided. The thermal management structure includes electroplated metal, which connects multiple contact regions for a first contact of a first type located on a first side of the device. The electroplated metal can form a bridge structure over a contact region for a second contact of a second type without contacting the second contact. The thermal management structure also can include a layer of insulating material located on the contact region of the second type, below the bridge structure. | 06-12-2014 |
20140231997 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device concerning the embodiment includes a semiconductor layer which has a first surface and a second surface which is opposite to the first surface, an interlayer which is provided on the first surface and which consists of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency, and an electrode provided on the interlayer. The semiconductor device further includes an electrical conductive layer which covers an inside of a hole which is formed in the semiconductor layer so as to reach the interlayer the interlayer from the second surface, and which is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole. | 08-21-2014 |
20140284798 | GRAPHENE WIRING AND METHOD OF MANUFACTURING THE SAME - A graphene wiring has a substrate a catalyst layer on the substrate a first graphene sheet layer on the catalyst layer and a second graphene sheet layer on the first graphene layer. The second graphene layer comprises multilayer graphene sheets. The multilayer graphene sheets are intercalated with an atomic or molecular species. | 09-25-2014 |
20140284799 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a substrate a lower layer wiring on the substrate, an interlayer dielectric on the lower layer wiring having a contact hole, a catalyst metal layer at the bottom of the contact hole having catalyst metal particles, multi-walled carbon nanotubes on the catalyst metal layer passing through the contact hole, and an upper layer wiring on the multi-walled carbon nanotubes. The multi-walled carbon nanotubes are intercalated with an atomic or molecular species. | 09-25-2014 |
20140284800 | GRAPHENE WIRING - A graphene wiring has a substrate, a catalyst layer on the substrate, a graphene layer on the catalyst layer, and a dopant layer on a side surface of the graphene layer. An atomic or molecular species is intercalated in the graphene layer or disposed on the graphene layer. | 09-25-2014 |
20150115446 | METHODS OF FORMING SEMICONDUCTOR DEVICES, INCLUDING FORMING A CONTACT INCLUDING AN ALKALINE EARTH METAL ON A SEMICONDUCTOR LAYER, AND RELATED DEVICES - Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a metal contact that includes a heavy alkaline earth metal on an n-type semiconductor layer. The heavy alkaline earth metal may underlie a metal layer and/or a capping layer. Related semiconductor devices are also provided. | 04-30-2015 |
20150303140 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING THE SAME - One or more semiconductor arrangements are provided. A semiconductor arrangement includes a first dielectric layer defining a first recess, a first contact in the first dielectric layer, a first metal cap over at least part of the first contact and a second dielectric layer over the first dielectric layer within the first recess and defining an air gap proximate the first contact. One or more methods of forming a semiconductor arrangement are also provided. Such a method includes forming a first metal cap on a first exposed surface of a first contact, the first metal cap having an extension region that extends into a first recess defined in a first dielectric layer and forming a second dielectric layer over the first dielectric layer within the first recess such that an air gap is defined within the second dielectric layer proximate the first contact due to the extension region. | 10-22-2015 |
20150325524 | SEMICONDUCTOR DEVICE COMPRISING A GRAPHENE WIRE - According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer. | 11-12-2015 |
20150364441 | MICRO-PILLAR ASSISTED SEMICONDUCTOR BONDING - Micro pillars are formed in silicon. The micro pillars are used in boding the silicon to hetero-material such as III-V material, ceramics, or metals. In bonding the silicon to the hetero-material, indium is used as a bonding material and attached to the hetero-material. The bonding material is heated and the silicon and the hetero-material are pressed together. As the silicon and the hetero-material are pressed together, the micro pillars puncture the bonding material. In some embodiments, pedestals are used in the silicon as hard stops to align the hetero-material with the silicon. | 12-17-2015 |
20150371940 | INSULATOR VOID ASPECT RATIO TUNING BY SELECTIVE DEPOSITION - Disclosed herein is a structure conductive lines disposed in a base layer and separated by a first region. Pillars are each disposed over a respective one of the conductive lines. A dielectric fill layer is disposed over the pillars and extending between the pillars into the first region, and a void is disposed in the dielectric fill layer in the first region between the conductive lines. | 12-24-2015 |
20160035674 | AUTOBAHN INTERCONNECT IN IC WITH MULTIPLE CONDUCTION LANES - A topological insulator is grown on an IC wafer in a vacuum chamber as a thin film interconnect between two circuits in the IC communicating with each other. As the TI is being grown, magnetic doping of the various TI sub-layers is varied to create different edge states in the stack of sub-layers. The sub-edges conduct in parallel with virtually zero power dissipation. Conventional metal electrodes are formed on the IC wafer that electrically contact the four corners of the TI layer (including the side edges) to electrically connect a first circuit to a second circuit via the TI interconnect. The TI interconnect thus forms two independent conducting paths between the two circuits, with each path being formed of a plurality of sub-edges. This allows bi-direction communications without collisions. Since each electrode contacts many sub-edges in parallel, the overall contact resistance is extremely low. | 02-04-2016 |
20160079169 | POLYMER MEMBER BASED INTERCONNECT - An interconnect ( | 03-17-2016 |
20160086890 | WIRING AND METHOD FOR MANUFACTURING THE SAME - Wiring comprises a multilayer graphene including graphene sheets, an interlayer substance disposed between layers of the multilayer graphene, and an organic compound layer connected to a side surface of the multilayer graphene. The organic compound layer contains a photoisomerizable organic group connected to the multilayer graphene. | 03-24-2016 |
20160086891 | GRAPHENE WIRING AND METHOD FOR MANUFACTURING THE SAME - Graphene wiring of an embodiment has a graphene intercalation compound including a multilayer graphene having graphene sheets stacked therein and an interlayer substance disposed between layers of the multilayer graphene, and an interlayer cross-linked layer connected to a side surface of the multilayer graphene. The interlayer cross-linked layer has a cross-linked molecular structure including multiple bonded molecules cross-linking the graphene sheets included in the multilayer graphene. | 03-24-2016 |
20160141246 | SEMICONDUCTOR DEVICE - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench. | 05-19-2016 |