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Of specified material other than unalloyed aluminum

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257734000 - COMBINED WITH ELECTRICAL CONTACT OR LEAD

Patent class list (only not empty are listed)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
257750000 Layered 1140
257768000 Refractory or platinum group metal or alloy or silicide thereof 108
257772000 Solder composition 42
257746000 Composite material (e.g., fibers or strands embedded in solid matrix) 30
257771000 Alloy containing aluminum 19
257744000 For compound semiconductor material 13
257767000 Resistive to electromigration or diffusion of the contact or lead material 8
257749000 At least portion of which is transparent to ultraviolet, visible or infrared light 6
257742000 With a semiconductor conductivity substitution type dopant (e.g., germanium in the case of a gallium arsenide semiconductor) in a contact metal) 2
20090108449Microelectronic device - A microelectronic device includes a non-polymeric substrate, an organic interlayer, and a indium tin oxide layer formed on the organic interlayer.04-30-2009
20090152722Synergy Effect of Alloying Materials in Interconnect Structures - A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line comprises an alloying material; and forming an etch stop layer on the copper line.06-18-2009
257747000 With thermal expansion matching of contact or lead material to semiconductor active device 1
20090218690Reduced-Stress Through-Chip Feature and Method of Making the Same - A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.09-03-2009
Entries
DocumentTitleDate
20130043589Methods of Forming a Non-Planar Cap Layer Above Conductive Lines on a Semiconductor Device - Disclosed herein are various methods of forming methods of forming a non-planar cap layer above a conductive line on a semiconductor device, and to devices incorporating such a non-planar cap layer. In one illustrative example, the method includes forming a conductive structure in a layer of insulating material, recessing an upper surface of the conductive structure relative to an upper surface of the layer of insulating material such that the recessed upper surface of the conductive structure and the upper surface of the layer of insulating material are positioned in different planes and, after recessing the upper surface of the conductive structure, forming a first cap layer on the conductive structure and the layer of insulating material. In another example, the device includes a conductive structure positioned in a layer of insulating material and a first cap layer formed on the layer of insulating material and the conductive structure, wherein a first interface between the first cap layer and the layer of insulating material is located in a first plane and a second interface between the first cap layer and the conductive structure is located in a second plane that is different from the first plane.02-21-2013
20130043590SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING - The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.02-21-2013
20110193230FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES - A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask. Material can be removed from the dielectric layer where exposed to the etchant by the holes in the cap layer. At such time, the mask can protect the first portion of the cap layer and the metal lines from being attacked by the etchant.08-11-2011
20130075907Interconnection Between Integrated Circuit and Package - In order to achieve finer bump interconnect pitch for integrated circuit packaging, while relieving pressure-induced delamination of upper layer dielectric films, the under bump metallurgy of the present invention provides a pressure distribution pedestal upon which a narrower copper pillar is disposed. A solder mini-bump is disposed on the upper exposed portion of the copper pillar, wherein the solder is softer than the copper pillar. The radius of the copper pillars is selected such that lateral deformation of the solder mini-bumps during final assembly does not form undesired conductive bridges between adjacent pillars.03-28-2013
20100133689COPPER (I) COMPOUNDS USEFUL AS DEPOSITION PRECURSORS OF COPPER THIN FILMS - Copper (I) amidinate precursors for forming copper thin films in the manufacture of semiconductor devices, and a method of depositing the copper (I) amidinate precursors on substrates using chemical vapor deposition or atomic layer deposition processes.06-03-2010
20090096100SEMICONDUCTOR APPARATUS, MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS, AND JOINT MATERIAL - A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 μm to 200 μm and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.04-16-2009
20120217638WIRING CONNECTION METHOD AND FUNCTIONAL DEVICE - By forming a metal layer 08-30-2012
20130069232DAMASCENE PROCESS FOR ALIGNING AND BONDING THROUGH-SILICON-VIA BASED 3D INTEGRATED CIRCUIT STACKS - Through-silicon-via (TSV) based 3D integrated circuit (3D IC) stacks are aligned, bonded and electrically interconnected using a transparent alignment material in the TSVs until the wafers are bonded. Embodiments include providing a first wafer having a first device layer and at least one first TSV filled with a conductive material, providing a second wafer having a second device layer, forming at least one second TSV in the second wafer, filling each second TSV with an alignment material, thinning the second wafer until the transparent material extends all the way through the wafer, aligning the first and second wafers, bonding the first and second wafers, removing the alignment material from the second wafer, and filling each second TSV in the second wafer with a conductive material.03-21-2013
20110057314CONDUCTORS FOR PHOTOVOLTAIC CELLS - The invention relates to conductive pastes including one or more acids, or acid-forming components for silicon semiconductor devices and photovoltaic cells.03-10-2011
20110266673INTEGRATED CIRCUIT PACKAGE STRUCTURE AND METHOD - An integrated circuit package structure includes an integrated circuit (IC) module, a plastic encapsulation, and input/output pins. The IC includes a substrate configured with signal lines and input/output ports disposed at edges of the substrate, chips, and wires. The chips are mounted on surfaces of the substrate, and the wires connect the chips to the signals lines and the input/output ports. The plastic encapsulation encapsulates the IC module to form an encapsulation body including an upper surface, a lower surface, and side surfaces, and the input/output ports are exposed out of the encapsulation body. The input/output pins are disposed on the side surfaces and at least one of the upper surface and the lower surface of the encapsulation body, and correspondingly leads the input/output ports to the at least one of the upper surface and the lower surface of the encapsulation body.11-03-2011
20130062767VIA STRUCTURE AND VIA ETCHING PROCESS OF FORMING THE SAME - An integrated circuit structure includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. The integrated circuit structure further includes at least a conductive layer formed in the hard mask layer and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall.03-14-2013
20110012262SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device wherein a semiconductor element made of Si or Si group material mounted on a substrate, the semiconductor element is mounted on the substrate and the semiconductor element is bonded to a silver bonding material via a oxide film formed on the semiconductor element. The bonding material comprising silver oxide particles having an average particle size of 1 nm to 50 nm and an organic reducing agent is used for bonding in air, which gives a high bonding strength to the oxide on the semiconductor element.01-20-2011
20090236743Programmable Resistive RAM and Manufacturing Method - Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.09-24-2009
20130214413CONDUCTIVE LINE STRUCTURES AND METHODS OF FORMING THE SAME - Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns.08-22-2013
20130161817TECHNIQUES FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES - Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.06-27-2013
20110018134Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride - By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.01-27-2011
20110068470Apparatus For Making Interconnect Seed Layers And Products - An apparatus for depositing seed layers over a substrate, which substrate includes a patterned insulating layer with at least one opening surrounded by a field, and which opening has sidewalls, bottom surfaces and top corners, includes: a CVD chamber adapted to deposit one or more CVD seed layers over the substrate; a PVD chamber adapted to deposit one or more PVD seed layers over the substrate; and a controller which includes recipe information. The recipe information includes deposition sequence and process parameters for operation of the deposition chambers. The controller, in response to the recipe information, causes the CVD chamber to deposit a continuous CVD seed layer over the substrate, and causes the PVD chamber to deposit a PVD seed layer over the substrate, wherein: (a) the continuous CVD seed layer is continuous over the sidewalls and bottom surfaces of the at least one opening, (b) the continuous CVD seed layer has a thickness from about 20 Å to about 250 Å over the field, and (c) the controller causes the stopping of the deposition of the seed layers so as to leave room for electroplating inside the at least one opening.03-24-2011
20120098131Nickel Silicide Film - A nickel alloy sputtering target and a nickel silicide film formed with such a target are provided and enable the formation of a thermally stable silicide (NiSi) film, scarcely causing the aggregation of films or excessive formation of silicides, having low generation of particles upon forming the sputtered film, having favorable uniformity and superior plastic workability to the target, and which is particularly effective for the manufacture of a gate electrode material (thin film). The nickel alloy sputtering target contains 22 to 46 wt % of platinum and 5 to 100 wtppm of one or more components selected from iridium, palladium, and ruthenium, and remainder is nickel and inevitable impurities.04-26-2012
20090206482TOOLING METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FABRICATED THEREOF - A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first block pattern corresponding to the first region on a photomask when the device-to-device spacing width is equal to a predetermined value, and transferring the first block pattern to the substrate.08-20-2009
20110285020MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact.11-24-2011
20110285019TRANSPARENT CONDUCTORS COMPRISING METAL NANOWIRES - A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates.11-24-2011
20110298131Yttrium contacts for germanium semiconductor radiation detectors - A germanium semiconductor radiation detector contact made of yttrium metal. A thin (˜1000 Å) deposited layer of yttrium metal forms a thin hole-barrier and/or electron-barrier contact on both p- and n-type germanium semiconductor radiation detectors. Yttrium contacts provide a sufficiently high hole barrier to prevent measurable contact leakage current below ˜120 K. The yttrium contacts can be conveniently segmented into multiple electrically independent electrodes having inter-electrode resistances greater than 10 GΩ. Germanium semiconductor radiation detector diodes fabricated with yttrium contacts provide good gamma-ray spectroscopy data.12-08-2011
20110291276MAGNETICALLY SINTERED CONDUCTIVE VIA - The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic components of the microelectronic packages may have sintered conductive vias comprising sintered metal and magnetic particles.12-01-2011
20100078815Ruthenium interconnect with high aspect ratio and method of fabrication thereof - An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.04-01-2010
20130009309CONDUCTIVE CHIP DISPOSED ON LEAD SEMICONDUCTOR PACKAGE AND METHODS OF MAKING THE SAME - In one implementation, an apparatus includes a semiconductor die, a lead, a non-conductive epoxy, and a conductive epoxy. The semiconductor die includes an upper surface and a lower surface opposite the upper surface. The lead is electrically coupled to the upper surface of the semiconductor die. The non-conductive epoxy is disposed on a first portion of the lower surface of the semiconductor die. The conductive epoxy is disposed on a second portion of the lower surface of the semiconductor die. In some implementations, a conductive wire extends from the lead to the upper surface of the semiconductor die to electrically couple the lead to the upper surface of the semiconductor die.01-10-2013
20090294963MODULE INCLUDING A SINTERED JOINT - A method comprises applying a paste comprising metal grains, a solvent, and a sintering inhibitor to one of a die and a metal layer. The method comprises evaporating the solvent in the paste and placing the one of the die and the metal layer on the other of the die and the metal layer such that the paste contacts the die and the metal layer. The method comprises applying a force to the one of the die and the metal layer and decomposing the sintering inhibitors to form a sintered joint joining the die to the metal layer.12-03-2009
20090189280Method of Forming a Non Volatile Memory Device - In one embodiment, a method of forming a semiconductor device is disclosed. A high-k dielectric is deposited of over a semiconductor body, and a portion of the high-k dielectric is wet etched an etchant selected from the group consisting of hot phos, piranha, and SC1.07-30-2009
20090189281 SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same capable of supplying power easily without an increase in the number of pads for power supply. The semiconductor package includes a semiconductor chip having a plurality of pads including pads for power supply disposed in a center portion and an internal wiring disposed to be exposed to outside; an insulating film formed on the semiconductor to expose the pads for power supply and the internal wirings; and re-distribution lines formed on the insulating film to connect between the exposed portions of the pads for power supply and the internal wiring.07-30-2009
20090146302METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Embodiments relate to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device capable of simplifying a silicide manufacturing process using a photo resist overhang structure. According to embodiments, a surface is subjected to a monochlorobenzene coating processing to cure the surface of the exposed photo resist so as not to react with developing solution and such a processed photo resist is developed to make the lower of the photo resist in the overhang structure so as to form an accurate pattern according to the clear removal of the oxide film, making it possible to simply manufacture the silicide and the non-silicide without performing an etching process by a subsequent cobalt deposition process.06-11-2009
20090309220ADHESIVE COMPOSITION, CIRCUIT CONNECTING MATERIAL, CONNECTION STRUCTURE OF CIRCUIT MEMBER, AND SEMICONDUCTOR DEVICE - The adhesive composition of the invention comprises a radical generator, a thermoplastic resin and a urethane (meth)acrylate having two or more radical-polymerizing groups in the molecule and a weight-average molecular weight of 3000-30,000.12-17-2009
20100123248SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an electrode pad; a wiring line electrically coupled to the electrode pad, the wiring line being formed by disposing and drying a droplet of a conductive ink in which metal fine particles are dispersed in a dispersion medium; an intermediate layer of an bonded layer of the metal fine particles on a surface of the electrode pad; and a liquid repellent layer that includes a liquid repellent material repelling the dispersion medium and is layered on the intermediate layer to cover the intermediate layer. In the device, the wiring line is physically coupled to the electrode pad with the liquid repellent layer and the intermediate layer interposed between the wiring line and the electrode pad.05-20-2010
20090309221SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device of this invention has a copper wiring layer, of which a layer, to which a composition including at least one substance selected from the group consisting of ammonia and organic bases is applied, and a silicon-containing insulating film are sequentially superimposed on the copper wiring layer. Accordingly, semiconductor devices having insulating layers which adheres well to the copper serving as the wiring material can be obtained.12-17-2009
20110147935METHOD AND SYSTEM FOR BINDING HALIDE-BASED CONTAMINANTS - A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to remove halides, such as chlorine and chlorides, during the deposition process so that contamination of the titanium-based film is minimized. A method for regenerating the halide adsorbing material is also provided.06-23-2011
20100078814SYSTEM AND METHOD FOR USING POROUS LOW DIELECTRIC FILMS - A system and method for manufacturing a semiconductor device including a low dielectric constant porous material layer. Ions are implanted into the low dielectric constant porous material layer which thereby provides the porous material layer with sufficient mechanical strength for withstanding semiconductor manufacturing processes. The ions implanted in the porous material layer further facilitate disposition of a conductive layer on the porous material layer.04-01-2010
20100007020SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: an insulating film including a porous insulating material and formed above a substrate; an interconnection wire including copper and buried in a groove formed at least in an obverse surface of the insulating film; and a barrier insulating film including an insulating material containing a nitrogen heterocyclic compound and formed over the insulating film and the interconnection wire.01-14-2010
20100090340Drawn Dummy FeCAP, Via and Metal Structures - An integrated circuit containing hydrogen permeable dummy vias configured in a linear or rectangular array and symmetrically positioned over a component in the integrated circuit. An integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.04-15-2010
20080211094SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an electrode pad formed on a pad forming surface of a semiconductor integrated circuit chip, and a step formed on the pad forming surface to surround the electrode pad. A method of manufacturing the semiconductor device is also disclosed.09-04-2008
20110198754Semiconductor device including porous layer covered by poreseal layer - A method of forming a semiconductor device includes forming a trench on a porous insulating film, placing a chemical material including a structure comprising —Si—O— including vinyl group on a surface of the porous insulating film or in the porous insulating film, and performing polymerization of the chemical material to provide a dielectric film having a density higher than that of porous insulating film on the surface of the trench. The structure may be a structure defined by a formula 1.08-18-2011
20090294964ELECTRICALLY-CONDUCTIVE INORGANIC COATING, METHOD FOR PRODUCING THE COATING, CIRCUIT BOARD, AND SEMICONDUCTOR APPARATUS - A method for producing an electrically-conductive inorganic coating includes depositing, on a substrate, a coating-precursor containing a plurality of inorganic particles and at least one kind of organic component by a liquid-phase method by using a material-liquid containing the inorganic particles and an organic solvent. The inorganic particles are coated with a dispersant binding to the surfaces of the inorganic particles by chemical bonds that can be broken by oxidation. Further, the method includes oxidizing the coating-precursor at a temperature exceeding 100° C., and that is less than or equal to the pyrolysis initiation temperature of an organic component that has the highest pyrolysis initiation temperature among the at least one kind of organic component and less than or equal to the heat-resistance temperature of the substrate, thereby breaking the chemical bonds to eliminate the dispersant from the surfaces, and decomposing the at least one kind of organic component.12-03-2009
20090278257METHOD TO ASSEMBLE STRUCTURES FROM NANO-MATERIALS - Numerous embodiments of a method to assemble nano-materials on a platform are described. In one embodiment, a nano-material is functionalized with a first bondable group. The functionalized nano-material is disposed on an assembly platform having an electrode to form a first layer. Additional layers of the nano-material may be formed above the first layer to form a semiconductor device. In one embodiment, the nano-material may be a carbon nanotube.11-12-2009
20090294965Method of Manufacturing A Semiconductor Device - Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.12-03-2009
20120292765SEMICONDUCTOR DEVICE HAVING WIRING LAYER - Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 μm; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 μm from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 μm from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential.11-22-2012
20080284019CONDUCTOR-DIELECTRIC STRUCTURE AND METHOD FOR FABRICATING - A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.11-20-2008
20110204516SINGLE CHIP SEMICONDUCTOR COATING STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a single chip semiconductor coating structure includes following steps. Step 1 is providing a single chip semiconductor which has a plurality of surfaces, and two opposite surfaces selected from the plurality of surfaces are manufacturing surfaces and have a conductive area with a pad thereon, respectively. Step 2 is providing a tool to cover one of the conductive areas with the pad. Step 3 is providing a coating step to form an insulating layer on the single chip semiconductor. Step 4 is providing a removing step to remove the insulating layer for exposing the covered conductive area and the pad. Step 5 is forming two electrodes and each of the two electrodes covers the conductive area with the pad.08-25-2011
20120292764METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.11-22-2012
20130119544MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME - A microelectronic package includes a substrate (05-16-2013
20110006424Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.01-13-2011
20100200990MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCED THEREWITH - A semiconductor device (having an interlayer insulating film) which is sufficiently low in the dielectric constant and high in the mechanical strength is provided.08-12-2010
20100200989LINER MATERIALS AND RELATED PROCESSES FOR 3-D INTEGRATION - In some embodiments, a low-k dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of through-silicon vias used in three-dimensional (3-D) integration of integrated circuits. A semiconductor workpiece having a via is provided. A dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of the via by chemical vapor deposition. Following the deposition of the dielectric film liner, conductive material is deposited into the via. The conductive material on the bottom of the via can be exposed by thinning the back of the semiconductor workpiece, thereby forming a through-silicon via. The semiconductor workpiece can form a stack with one or more additional semiconductor workpieces having vias filled with conductive material to form a 3-D integrated circuit. The conductive material electrically interconnects the integrated circuits at different levels of the stack.08-12-2010
20100140802FILM FORMING METHOD AND FILM FORMING APPARATUS - On a surface of an object to be treated, a Mn-containing thin film or CuMn-containing alloy thin film is formed by heat treatment (CVD or ALD) by using a Mn-containing source gas (or Mn-containing source gas and a Cu-containing gas) and an oxygen-containing gas (for instance, water vapor) as a processing gas. The Mn-containing thin film or the CuMn-containing alloy thin film can be formed with high step coverage in a fine recess formed on the surface of the object to be treated.06-10-2010
20090184421SEMICONDUCTOR DEVICE WITH HIGH RELIABILITY AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.07-23-2009
20120104609DISCRETE CIRCUIT COMPONENT HAVING COPPER BLOCK ELECTRODES AND METHOD OF FABRICATION - A discrete circuit component has copper block electrodes and that utilizes a simple copper substrate as the basis for the component. The component is made by providing an electrode separation hole preformed in the main substrate. The electrode separation hole results in a simple fabrication for the construction of the discrete component product. With the presence of the electrode separation hole, two solid blocks of copper automatically come into shape for each fabricated device at the final phase of production when each device is cut loose from the main production matrix.05-03-2012
20080265414Electrically Conductive Composite - The present invention provides a conductive composite comprising: suspension matrix, metal nanoparticles suspended within the suspension matrix, wherein the conductive composite has a conductivity greater than 104 S cm10-30-2008
20090212430CARBON NANOTUBE-BASED CONDUCTIVE CONNECTIONS FOR INTEGRATED CIRCUIT DEVICES - Electrical connection in an integrated circuit arrangement is facilitated with carbon nanotubes. According to various example embodiments, a carbon nanotube material (08-27-2009
20090243102METHOD OF ALIGNING DEPOSITED NANOTUBES ONTO AN ETCHED FEATURE USING A SPACER - A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.10-01-2009
20090243101METHOD FOR FORMING INTERCONNECTION LEVELS OF AN INTEGRATED CIRCUIT - A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.10-01-2009
20090140427Metal foil interconnection of electrical devices - An electrical assembly (06-04-2009
20090256258SEMICONDUCTOR CHIP WITH INTEGRATED VIA - An integrated circuit with a substrate with a lower and an upper surface is described. A via extends between the upper and the lower surface of the substrate. The via contains a conductive filling material that comprises carbon.10-15-2009
20100155948TOOLING METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FABRICATED THEREOF - A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first block pattern corresponding to the first region on a photomask when the device-to-device spacing width is equal to a predetermined value, and transferring the first block pattern to the substrate.06-24-2010
20130214411METAL INTERCONNECT OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a metal interconnect of a semiconductor device including: forming a interconnect hole by patterning an interlayer insulating film formed on a substrate; performing a nitriding treatment on a surface of the interlayer insulating film by injecting a gas including nitrogen into a deposition apparatus in which the substrate is disposed; forming a diffusion preventing film by injecting the gas including nitrogen and a metal source gas into the deposition apparatus together; filling the interconnect hole with a metal; and removing the metal formed on a part other than the interconnect hole by a chemical mechanical polishing (CMP) process. Accordingly, the mechanical strength of the interlayer insulating film is increased, thereby preventing scratches or defects that are generated during the chemical mechanical polishing process.08-22-2013
20130214412METHOD OF FORMING THIN FILM INTERCONNECT AND THIN FILM INTERCONNECT - A method of forming a thin film interconnect in which a film is formed by sputtering method using a Cu—Ca alloy target and a thin film interconnect formed by the method, the method comprising: forming a Cu—Ca alloy film by sputtering method using a Cu—Ca alloy target that contains 0.5 atomic % or more and less than 5 atomic % of Ca, and the balance consisting of Cu and unavoidable impurities; and performing heat treatment of the Cu—Ca alloy film at a temperature of 300 to 700° C. in an inert gas atmosphere containing trace amount of oxygen defined by oxygen partial pressure in the range of 1008-22-2013
20100013096Cu-Mn Alloy Sputtering Target and Semiconductor Wiring - Proposed is a Cu—Mn alloy sputtering target, wherein the Mn content is 0.05 to 20 wt %, the total amount of Be, B, Mg, Al, Si, Ca, Ba, La, and Ce is 500 wtppm or less, and the remainder is Cu and unavoidable impurities. Specifically, provided are a copper alloy wiring for semiconductor application, a sputtering target for forming this wiring, and a manufacturing method of a copper alloy wiring for semiconductor application. The copper alloy wiring itself for semiconductor application is equipped with a self-diffusion suppression function for effectively preventing the contamination around the wiring caused by the diffusion of active Cu, improving electromigration (EM) resistance, corrosion resistance and the like, enabling and facilitating the arbitrary formation of a barrier layer, and simplifying the deposition process of the copper alloy wiring for semiconductor application.01-21-2010
20100019385Implementing Reduced Hot-Spot Thermal Effects for SOI Circuits - Methods and structures are provided for implementing reduced hot spot thermal effects for silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, an active layer carried by the thin BOX layer, and a pad oxide layer carried by the active layer. A thermal conductive path is built to reduce thermal effects of a hotspot area in the active layer and extends from the active layer to the backside of the SOI structure. A trench etched from the topside to the active layer, and is filled with a thermal connection material. A thermal connection from a backside of the SOI structure includes an opening etched into the silicon substrate layer from the backside and filled with a thermal connection material.01-28-2010
20100224994Low Temperature Metal to Silicon Diffusion and Silicide Wafer Bonding - A method of bonding two members includes forming a metal pad on a first member and a silicon pad on the second member, and coupling the pads at a temperature and pressure that will not damage features of the members, such as integrated circuitry or MEMS devices, but is sufficient to form a silicide bond. In various embodiments, the metal may be nickel and the silicon may be polysilicon.09-09-2010
20120139111ELECTRONIC COMPONENT - An electronic component has a substrate, a die bonding pad provided on an upper surface of the substrate, a semiconductor element bonded onto the die bonding pad by a die bonding resin, a conductive pattern disposed adjacent to the die bonding pad, and a coating member covering the conductive pattern. At least an outer peripheral portion of a surface of the die bonding pad is made of an inorganic material. The inorganic material of the outer peripheral portion is exposed. The die bonding pad and the conductive pattern are separated by an air gap such that the coating member does not come into contact with the die bonding pad.06-07-2012
20120193792SEMICONDUCTOR DEVICE CONDUCTIVE PATTERN STRUCTURES INCLUDING DUMMY CONDUCTIVE PATTERNS, AND METHODS OF MANUFACTURING THE SAME - Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.08-02-2012
20090020875Semiconductor Device and Manufacturing Method Thereof - A semiconductor device is provided. The semiconductor device includes a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed. The semiconductor device also includes a first via plug and a first metal line respectively formed by filling the first via hole and the first trench with a first metal, a predetermined scratch being formed on the first metal line; and a second via plug a second metal line respectively formed by filling a second via hole and a second trench with a second metal, the second metal lines being separated.01-22-2009
20090273083ELECTRICALLY CONDUCTIVE FLUID INTERCONNECTS FOR INTEGRATED CIRCUIT DEVICES - Disclosed are embodiments of an electrically conductive fluid interconnect for coupling an integrated circuit (IC) device to a substrate. The IC device may be coupled to the substrate in a socketless manner or using a socket. The electrically conductive fluid interconnect may include, for example, a metal, an electrically conductive paste, or an electrically conductive polymer material. The fluid may be in a liquid or paste state over at least part of an operating temperature range of the IC device, and in other embodiments the fluid may be in the liquid or paste state at room temperature. Other embodiments are described and claimed.11-05-2009
20090039511SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same that includes a drain contact that can prevent bridging between contact metals in metal contact line (M1C) processes. The method includes forming a contact hole extending through an interlayer dielectric film in a space between respective gate electrodes to expose an undercut region, filling the contact hole and the undercut region with a photosensitive material, removing the photosensitive material from the contact hole and then forming a drain contact in the contact hole.02-12-2009
20090115059GOLD WIRE FOR SEMICONDUCTOR ELEMENT CONNECTION - A gold wire for semiconductor element connection having high strength and bondability. The connection has a limited amount of at least one element selected from calcium and rare earth elements, and a limited amount of at least one element selected from a group consisting of titanium, vanadium, chromium, hafnium, niobium, tungsten, and zirconium. The incorporation of a suitable amount of palladium or beryllium is preferred. The incorporation of calcium and rare earth element can improve the strength and young's modulus of a gold wire, and the incorporation of titanium and the like can reduce a deterioration in the roundness of press-bonded shape of press-bonded balls in the first bonding caused by the incorporation of calcium and rare earth elements. The bonding wire can simultaneously realize mechanical properties and bondability capable of meeting a demand for a size reduction in semiconductor and a reduction in electrode pad pitch.05-07-2009
20090072399 SEMICONDUCTOR MOUNTING BONDING WIRE - There is provided a bonding wire which does not cause a leaning failure or the like. A semiconductor mounting bonding wire has a breaking elongation of 7 to 20%, and stress at 1% elongation is greater than or equal to 90% of a tensile strength and is less than or equal to 100% thereof.03-19-2009
20090072398INTEGRATED CIRCUIT, CIRCUIT SYSTEM, AND METHOD OF MANUFACTURING - An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material.03-19-2009
20090146303Flip Chip Interconnection with double post - A packaged microelectronic assembly includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. Each of the first posts has a width in a direction of the front surface and a height extending from the front surface, wherein the height is at least half of the width. There is also a substrate having a top surface and a plurality of second solid metal posts extending from the top surface and joined to the first solid metal posts.06-11-2009
20110121457Process for Reversing Tone of Patterns on Integrated Circuit and Structural Process for Nanoscale Production - A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.05-26-2011
20110042812Electronic device and method of manufacturing the same - An electronic device includes a power element on a first substrate and an electronic component on a second substrate. The first and second substrates are stacked so that the power element and the electronic component can be located between the first and second substrates. A first end of a first wire is connected to the power element. A second end of the first wire is connected to the first substrate. A middle portion of the first wire projects toward the second substrate. A first end of a second wire is connected to the power element. A second end of the wire extends above a top of the middle portion of the first conductive member and is connected to the second substrate.02-24-2011
20120241959MAGNETIC INTEGRATION DOUBLE-ENDED CONVERTER - The present invention relates to a method of bonding a chip to an external electric circuit. The conductors of the external electric circuit for connection to the chip are formed with physical extensions and the chip is directly bonded to these extensions. The invention also relates to an electric device comprising at least one chip and an external electric circuit. The chip is directly bonded to physical extensions of conductors of the external electric circuit.09-27-2012
20100171218SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first substrate formed with a through silicon via reaching the back surface thereof, and a second substrate electrically connected to the first substrate via the through silicon via, and bonded to the back surface of the first substrate. A taper angle of a sidewall of a tip end portion of the through silicon via connected to the second substrate is larger than a taper angle of a sidewall of the other portion thereof.07-08-2010
20090032949Method of depositing Tungsten using plasma-treated tungsten nitride - Devices structures utilizing, and methods of forming, tungsten interconnects in semiconductor fabrication are disclosed. Tungsten deposition is accomplished by a three-step process that does not require a resistive nucleation material to be deposited prior to bulk tungsten deposition. By treating a tungsten nitride material with a hydrogen plasma, thereby reducing the tungsten nitride to tungsten, the necessity of a resistive nucleation layer is eliminated. Other embodiments describe methods of tungsten deposition requiring a thinner resistive nucleation material (<10 angstroms) than currently known.02-05-2009
20100164102Isolated germanium nanowire on silicon fin - The present invention describes a method of and an apparatus for providing a wafer, the wafer including Silicon; etching trenches in the wafer to form Silicon fins; filling Silicon Oxide in the trenches; planarizing the Silicon Oxide; recessing the Silicon Oxide to a first thickness to form exposed Silicon pedestals from the Silicon fins; depositing SiGe over the exposed Silicon pedestal; recessing the Silicon Oxide to a second thickness; undercutting the exposed Silicon pedestals to form necked-in Silicon pedestals; oxidizing thermally and annealing the SiGe; and forming Germanium nanowires.07-01-2010
20100237499SEMICONDUCTOR DEVICE, AND STACKED STRUCTURE, PACKAGE, MODULE, AND ELECTRONIC APPARATUS INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME - Semiconductor devices, as well as stacked structures, packages, modules, and electronic apparatus including the semiconductor device, and methods of fabricating the same. The semiconductor device includes a circuit layer on a substrate, a metal interconnection layer on the circuit layer, the metal interconnection layer having a copper interconnection and a protection layer, a first and a second through silicon via plugs vertically penetrating the circuit layer, a first via pad on the first through silicon via plug, and a second via pad on the second through silicon via plug, wherein the first via pad is electrically connected to the copper interconnection, and wherein the second via pad is electrically insulated from the copper interconnection.09-23-2010
20110241208MICROELECTRONIC PACKAGE CONTAINING SILICON CONNECTING REGION FOR HIGH DENSITY INTERCONNECTS, AND METHOD OF MANUFACTURING SAME - A microelectronic package comprises a substrate (10-06-2011
20090321930SEMICONDUCTOR WITH BOTTOM-SIDE WRAP-AROUND FLANGE CONTACT - A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.12-31-2009
20100193951METAL PRECURSORS FOR DEPOSITION OF METAL-CONTAINING FILMS - Compositions and methods for forming a metal-containing thin film on a substrate. A reactor and at least one substrate in the reactor are provided. A metal-containing bis-β-diketiminate precursor is introduced into the reactor. The reactor is maintained at a set temperature and pressure, and the precursor is contacted with the substrate to form a metal-containing film on the substrate.08-05-2010
20090321931Semiconductor device and method of manufacturing the same - A semiconductor device and a method of manufacturing the semiconductor device maintain an insulating distance between contact plugs and wiring lines formed on the contact plugs by using an etch mask pattern for forming contact holes. The device comprises a substrate comprising a plurality of conductive areas; an inter-layer insulating layer on the substrate having a plurality of contact holes through which the conductive areas are exposed; a first insulating layer covering the top surface of the inter-layer insulating layer; a plurality of contact plugs respectively connected to the plurality of conductive areas through the plurality of contact holes, the plurality of contact plugs having top surfaces a distance from each of which to a top surface of the substrate is less than a distance from the top surface of the inter-layer insulating layer to the top surface of the substrate; a plurality of ring-shaped insulating spacers covering inner sidewalls of the inter-layer insulating layer, inner sidewalls of the first insulating layer, and outer edge areas of top surfaces of the contact plugs so as to expose center areas of the top surfaces of the contact plugs in the contact holes; and a plurality of wiring lines above the first insulating layer and on the insulating spacers and respectively electrically connected to the plurality of contact plugs.12-31-2009
20100013095SEMICONDUCTOR DEVICE, PRODUCTION METHOD FOR THE SAME, AND SUBSTRATE - A semiconductor device is provided in which a semiconductor chip is bonded to a substrate with a sufficiently increased bonding strength and cracking is assuredly prevented which may otherwise occur due to heat shock, heat cycle and the like. The semiconductor device includes a semiconductor chip and a substrate having a bonding area to which the semiconductor chip is bonded via a metal layer. The metal layer includes an Au—Sn—Ni alloy layer and a solder layer provided on the Au—Sn—Ni alloy layer. Undulations are formed in an interface between the Au—Sn—Ni alloy layer and the solder layer.01-21-2010
20120241958Increasing reliability of copper-based metallization structures in a microstructure device by using aluminum nitride - By forming an aluminum nitride layer by a self-limiting process sequence, the interface characteristics of a copper-based metallization layer may be significantly enhanced while nevertheless maintaining the overall permittivity of the layer stack at a lower level.09-27-2012
20100059888Mask ROM and method of fabricating the same - A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.03-11-2010
20110175224BONDED STRUCTURE AND MANUFACTURING METHOD FOR BONDED STRUCTURE - A manufacturing method for a bonded structure, in which a semiconductor device is bonded to an electrode by a bonding portion, the method including: first mounting a solder ball, in which a surface of a Bi ball is coated with Ni plating, on the electrode that is heated to a temperature equal to or more than a melting point of Bi; second pressing the solder ball against the heated electrode, cracking the Ni plating, spreading molten Bi on a surface of the heated electrode, and forming a bonding material containing Bi-based intermetallic compound of Bi and Ni; and third mounting the semiconductor device on the bonding material.07-21-2011
20120199975ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN - The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.08-09-2012
20110163446METHOD TO GENERATE AIRGAPS WITH A TEMPLATE FIRST SCHEME AND A SELF ALIGNED BLOCKOUT MASK AND STRUCTURE - A structure and method to produce an airgap on a substrate having a dielectric layer and copper interconnects with sublithographic perforations therein which are ordered throughout the wafer structure in a macro level and a micro level with no change in order orientation and the top layer of the copper interconnects are not exposed.07-07-2011
20110254163SLEEVE INSULATORS AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.10-20-2011
20100244251SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first semiconductor chip, an electrode pad formed in an upper surface portion of the first semiconductor chip, a second semiconductor chip formed on the first semiconductor chip, and a through-via formed in the second semiconductor chip. A hollowed portion is formed in the electrode pad, and a bottom portion of the through-via is embedded in the hollowed portion.09-30-2010
20100244250SEMICONDUCTOR INTEGRATED CIRCUIT, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING SEMICONDUCTOR INTEGRATED CIRCUIT - A step of forming a through hole in a semiconductor substrate, or a step of polishing the semiconductor substrate from its back surface requires a very long time and causes decrease of productivity. In addition, when semiconductor substrates are stacked, a semiconductor integrated circuit which is formed of the stack is thick and has poor mechanical flexibility. A release layer is formed over each of a plurality of substrates, layers each having a semiconductor element and an opening for forming a through wiring are formed over each of the release layers. Then, layers each having the semiconductor element are peeled off from the substrates, and then overlapped and stacked, a conductive layer is formed in the opening, and the through wiring is formed; thus, a semiconductor integrated circuit is formed.09-30-2010
20100244249SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a wire-bond of a first metallic composition, the wire-bond and the bond-pad being coated with a protection layer of a second metallic composition.09-30-2010
20100244248NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile memory device, includes: a lower side electrode aligned in a first direction; an upper side electrode positioned above the lower side electrode and aligned in a second direction intersecting the first direction; and a memory unit provided between the lower side electrode and the upper side electrode. At least one selected from the lower side electrode and the upper side electrode includes a first electrode and a second electrode, the first electrode having a forward-tapered side wall, the second electrode having a reverse-tapered side wall and being adjacent to the first electrode via an insulating layer in substantially identical plane.09-30-2010
20100244247VIA STRUCTURE AND VIA ETCHING PROCESS OF FORMING THE SAME - A via etching process forms a through-substrate via having a round corner and a tapered sidewall profile. A method includes providing a semiconductor substrate; forming a hard mask layer and a patterned photoresist layer on the semiconductor substrate; forming an opening in the hard mask and exposing a portion of the semiconductor substrate; forming a via passing through at least a part of the of semiconductor substrate using the patterned photoresist layer and hard mask layer as a masking element; performing a trimming process to round the top corner of the via; and removing the photoresist layer.09-30-2010
20090091033Fabrication of metal oxide films - A process of fabricating a metal oxide film includes depositing a multiphase, metal-based precursor film comprising the metal and an oxide of the metal on a substrate. The process further includes thermally growing a metal oxide film from the precursor film in a humid atmosphere for a predetermined period of time and at a predetermined temperature.04-09-2009
20080277787METHOD AND PAD DESIGN FOR THE REMOVAL OF BARRIER MATERIAL BY ELECTROCHEMICAL MECHANICAL PROCESSING - A method and apparatus for processing barrier and metals disposed on a substrate in an electrochemical mechanical planarizing system are provided. In certain embodiments a method for electroprocessing a substrate is provided. The method comprises contacting the substrate with the non-conductive surface of a polishing pad assembly, establishing a first electrically conductive path through an electrolyte between an exposed layer of barrier material and a first electrode, establishing a second electrically conductive path through the electrolyte between the exposed layer of barrier material and a second electrode, applying a voltage to the first electrode to cause a voltage drop between the substrate and the second electrode, and removing the barrier material from the substrate.11-13-2008
20110042811SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, electrodes separated from each other and extending from a first main surface in the direction of depth of the semiconductor substrate, and an interconnect portion coupling the electrodes to each other and extending from the first main surface in the direction of depth of the semiconductor substrate without passing through the semiconductor substrate. One of the electrodes is a through electrode passing through the semiconductor substrate to reach a second main surface. For semiconductor devices having through electrodes and vertically stacked on each other, the interconnect portion serves to enhance the degree of design freedom.02-24-2011
20120146222Circuit Structures and Electronic Systems - The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.06-14-2012
20120146220SEMICONDUCTOR INTEGRATED-CIRCUIT DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor integrated-circuit device using the copper wiring having increased electromigration resistance, low resistivity, and a line width of 70 nm or less, is provided. The present invention is characterized by the annealing treatment wherein a copper wiring having a line width of 70 nm or less is heated with a heating rate of 1 K to 10 K per second, and then the temperature is constantly maintained for a prescribed time duration.06-14-2012
20100059887SEMICONDUCTOR DEVICE HAVING INSULATING FILM WITH SURFACE MODIFICATION LAYER AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a first SiOCH film and a surface modification layer including an SiOCH film formed by modifying a surface layer of the first SiOCH film, the SiOCH film having a lower carbon concentration and a higher oxygen concentration than the first SiOCH film has. The cap insulating film contacts with surfaces of the metal wiring and the surface modification layer.03-11-2010
20110147934Metal Plugged Substrates with No Adhesive Between Metal and Polyimide - In a method and apparatus for fabricating a semiconductor device having a flexible tape substrate, a hole is punched in the flexible tape substrate. The flexible tape substrate includes a metal layer attached to a polyimide layer without an adhesive there between. A cover is placed on the metal layer to cap a base of the hole. A metal is deposited on the cover exposed at the base of the hole, the metal being used to form a bond with the metal layer. The metal being deposited causes the hole to be plugged up to a selective height. Upon removal of the cover, the metal may also be deposited on the metal layer to increase a thickness of the metal layer.06-23-2011
20110147933MULTIPLE SURFACE FINISHES FOR MICROELECTRONIC PACKAGE SUBSTRATES - Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate masking the first area of the substrate without masking a second area of the substrate, applying a second different surface finish to connection pads of the second area of the substrate, and removing the mask.06-23-2011
20110169165SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a substrate, an IC chip that is fixed over the substrate, a conductor that is disposed over a surface of the substrate, a solder resist that covers the surface of the substrate and the conductor and includes an opening that exposes the conductor in a section corresponding to a fixed surface of the IC chip, and an adhesive that contacts an exposed part of the conductor, in which the exposed part is made by the opening.07-14-2011
20110186999SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Hardness of bonding end portions of an external connection terminal to be bonded to circuit patterns of an insulating substrate which is not lower than 90 in Vickers hardness is disclosed. An ultrasonic welding tool is used. In the external connection terminal in which the bonding end portions are provided integrally with a bar, one of the bonding end portion located substantially in the lengthwise center of the bar is first bonded, and the other bonding end portions are bonded alternately in order toward either end. The hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased. Since the external connection terminal including the bonding end portions is bonded in such a manner that the bonding end portion located substantially in the center is first bonded and the other bonding end portions are then bonded in order of increasing distance substantially from the central bonding end portion, displacement of the bonding end portion in either end from its regular position can be suppressed to keep bonding strength high. In this manner, the bonding strength of the ultrasonic welding portions between the external connection terminal and the circuit patterns of the insulating substrate can be increased so that long-term reliability can be secured in a semiconductor device.08-04-2011
20110115089Semiconductor device, production method for the same, and substrate - A semiconductor device is provided in which a semiconductor chip is bonded to a substrate with a sufficiently increased bonding strength and cracking is assuredly prevented which may otherwise occur due to heat shock, heat cycle and the like. The semiconductor device includes a semiconductor chip and a substrate having a bonding area to which the semiconductor chip is bonded via a metal layer. The metal layer includes an Au—Sn—Ni alloy layer and a solder layer provided on the Au—Sn—Ni alloy layer. Undulations are formed in an interface between the Au—Sn—Ni alloy layer and the solder layer.05-19-2011
20110115088INTERCONNECT WITH FLEXIBLE DIELECTRIC LAYER - An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion.05-19-2011
20110115087SELF-ALIGNED LOWER BOTTOM ELECTRODE - A method of fabricating a lower bottom electrode for a memory element and a semiconductor structure having the same includes forming a dielectric layer over a semiconductor substrate having a plurality of conductive contacts formed therein to be connected to access circuitry, forming a dielectric cap layer over exposed portions of the dielectric layer and the conductive contacts, depositing a planarizing material over the dielectric cap layer, etching a via to an upper surface of each conductive contact, removing the planarizing material, depositing electrode material over the dielectric cap layer and within the vias, the electrode material contacting an upper surface of each conductive contact, and planarizing the electrode material to form a lower bottom electrode over each conductive contact.05-19-2011
20110115086METAL NONOPARTICLE COMPOSITIONS - Methods and compositions for preparing highly conductive electronic features are disclosed. When organoamine-stabilized silver nanoparticles are exposed to an alkaline composition, the resulting electronic feature is highly conductive. Such methods are particularly advantageous when applied to aged silver nanoparticle compositions.05-19-2011
20100301478Substrate Having a Coating Comprising Copper and Method for the Production Thereof by Means of Atomic Layer Deposition - A method can be used for the production of a coated substrate. The coating contains copper. A copper precursor and a substrate are provided. The copper precursor is a copper(I) complex which contains no fluorine. A copper-containing layer is deposited by means of atomic layer deposition (ALD) at least on partial regions of the substrate surface by using the precursor. Optionally, a reduction step is performed in which a reducing agent acts on the substrate obtained in the layer deposition step. In various embodiments, the precursor is a complex of the formula L12-02-2010
20120146221METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH SIDE CONTACT - A semiconductor device includes an active region having a side contact region in a sidewall thereof, wherein the side contact has a bulb shape, an ohmic contact region formed over a surface of the side contact region, and a bitline connected to the active region through the ohmic contact.06-14-2012
20120306079SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a surface electrode of aluminum-containing material formed on the substrate, a metal film of solderable material formed on the surface electrode, and an end-securing film securing an end of the metal film and having a portion on the surface electrode and also having an overlapping portion which is formed integrally with the portion on the surface electrode and which overlaps the end of the metal film.12-06-2012
20120038048STABILIZED NICKEL SILICIDE INTERCONNECTS - A method of forming nickel monosilicide is provided that includes providing a silicon-containing surface, and ion implanting carbon into the silicon-containing surface.02-16-2012
20120038046SEMI-CONDUCTOR CHIP WITH COMPRESSIBLE CONTACT STRUCTURE AND ELECTRONIC PACKAGE UTILIZING SAME - A method of forming a compressible contact structure on a semi-conductor chip which comprises bonding a compressible polymer layer to the chip's surface, forming a plurality of openings within the layer, depositing electrically conductive material within the openings to form electrical connections with the chip's contacts, forming a plurality of electrically conductive line elements on the polymer layer extending from a respective opening and each including an end portion, and forming a plurality of contact members each on a respective one of the line segment end portions. The compressible polymer layer allows the contact members to deflect toward (compress) the chip when the contact members are engaged by an external force or forces. A semi-conductor chip including such a compressible contact structure is also provided.02-16-2012
20120038047Semiconductor Device and Method of Forming B-Stage Conductive Polymer Over Contact Pads of Semiconductor Die in FO-WLCSP - A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. A b-stage conductive polymer is deposited over the contact pads on the semiconductor wafer. The semiconductor wafer is singulated to separate the die. An insulating layer is formed over a carrier with openings formed in the insulating layer. The die is mounted to the carrier with the conductive polymer disposed in the openings of the insulating layer. The conductive polymer is heated to a glass transition temperature to liquefy the conductive polymer to an electrically conductive state. An encapsulant is deposited over the die and insulating layer. The carrier is removed to expose the conductive polymer. An interconnect structure is formed over the die, encapsulant, and conductive polymer. The interconnect structure is electrically connected through the conductive polymer to the contact pads on the die.02-16-2012
20110163447High-Purity Copper or High-Purity Copper Alloy Sputtering Target, Process for Manufacturing the Sputtering Target, and High-Purity Copper or High-Purity Copper Alloy Sputtered Film - Provided is a high-purity copper or high-purity copper alloy sputtering target of which the purity is 6N or higher and in which the content of the respective components of P, S, O and C is 1 ppm or less, wherein the number of nonmetal inclusions having a particle size of 0.5 μm or more and 20 μm or less is 30,000 inclusions/g or less. As a result of using high-purity copper or high-purity copper alloy from which harmful inclusions of P, S, C and O system have been reduced as the raw material and controlling the existence form of nonmetal inclusions, the present invention addresses a reduction in the percent defect of wirings of semiconductor device formed by sputtering a high-purity copper target so as to ensure favorable repeatability.07-07-2011
20110316159CHIP STACK PACKAGE - A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.12-29-2011
20110316158METHOD AND SYSTEM FOR THIN MULTI CHIP STACK PACKAGE WITH FILM ON WIRE AND COPPER WIRE - A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.12-29-2011
20100155947SOLDER JOINTS WITH ENHANCED ELECTROMIGRATION RESISTANCE - Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.06-24-2010
20110049713DUAL CONTACT METALLIZATION INCLUDING ELECTROLESS PLATING IN A SEMICONDUCTOR DEVICE - Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.03-03-2011
20120061837METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device according to an embodiment, an etching stopper, an oxide film and a mask material are formed. A trench pattern is formed in the mask material. The oxide film is etched to form the trench pattern therein by using the mask material having the trench pattern formed therein as a mask. The etching stopper is etched until the etching stopper is penetrated to form the trench pattern therein, by using the oxide film having the trench pattern formed therein as a mask. A Cu film is formed to be filled in the trench pattern formed in the etching stopper and the oxide film and to cover the top surface of the oxide film. CMP is performed on the Cu film and the oxide film until the top surface of the etching stopper serving as a stopper is exposed.03-15-2012
20120061836SPRAY PYROLYSIS OF Y-DOPED ZnO - One example embodiment includes a method for applying a transparent conducting oxide. The method includes providing a solution, where the solution includes a solvent, a zinc precursor and an yttrium precursor. The method also includes spraying the solution on a heated substrate, where the heated substrate turns the solution into an yttrium-doped zinc oxide film. The method further includes annealing the film on the substrate in a controlled environment.03-15-2012
20110079906PRE-PACKAGED STRUCTURE - A pre-packaged structure includes a substrate with a substrate circuit, a die having a core circuit and disposed on the substrate, a passivation selectively covering the core circuit, a buffer metal layer electrically connected to the core circuit and completely covering the passivation and a copper wire bond electrically connected to the buffer metal layer and the substrate circuit.04-07-2011
20120153475METHOD OF ASSEMBLING TWO INTEGRATED CIRCUITS AND CORRESPONDING STRUCTURE - A semiconductor device includes an assembly of two integrated circuits. The assembly has a layer of photoresist filling the space between the two integrated circuits, and at least one electrically conducting pillar within the resist and electrically coupling the two integrated circuits.06-21-2012
20120153474INTEGRATED CIRCUIT SYSTEM WITH REDUCED POLYSILICON RESIDUE AND METHOD OF MANUFACTURE THEREOF - A method of manufacturing an integrated circuit system includes: providing a substrate; forming a polysilicon layer over the substrate; forming an anti-reflective coating layer over the polysilicon layer; etching an anti-reflective coating pattern into the anti-reflective coating layer leaving an anti-reflective coating residue over the polysilicon layer; and etching the anti-reflective coating residue with an etchant gas mixture comprising hydrogen bromide, chlorine, and oxygen to remove the anti-reflective coating residue for mitigating the formation of a polysilicon protrusion.06-21-2012
20090140426FLIP CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.06-04-2009
20120126408INTEGRATED CIRCUIT MANUFACTURING METHOD AND INTEGRATED CIRCUIT - The present invention discloses an integrated circuit (IC) comprising a bond pad (05-24-2012
20090057903Semiconductor module, method for manufacturing semiconductor modules, semiconductor apparatus, method for manufacturing semiconductor apparatuses, and portable device - Cost is suppressed and a semiconductor module is made thinner. The semiconductor is of a structure where a semiconductor element is embedded in a recess formed in a wiring substrate. A substrate electrode provided around the recess and an element electrode are electrically connected through a wiring formed integrally with bumps.03-05-2009
20090057902METHOD AND STRUCTURE FOR INCREASED WIRE BOND DENSITY IN PACKAGES FOR SEMICONDUCTOR CHIPS - A semiconductor package provides an IC chip on at least one package substrate and including signal bond pads, ground bond pads and power bond pads. The package substrate includes signal contact pads, ground contact pads and power contact pads which are respectively coupled to signal bond pads, ground bond pads and power bond pads formed on the IC chip. The contact pads are coupled to the associated bond pads by a bonding wire. The bonding wires that connect the power and ground pads have a thickness that is greater than the thickness of the bonding wires that couple the signal pads. The various bond pads on the IC chip may be staggered to provide for enhanced compactness and integration. The package substrates may be a plurality of stacked package substrates.03-05-2009
20100052166Sandwiched metal structure silicidation for enhanced contact - Embodiments of an apparatus and methods for forming enhanced contacts using sandwiched metal structures are generally described herein. Other embodiments may be described and claimed.03-04-2010
20090096101BRIDGE FOR SEMICONDUCTOR INTERNAL NODE - A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a lower end in electrical contact with first and second transistor elements, respectively; one or more intermediate metal pillars disposed between and in electrical contact with an upper end of the metal pillars; and one or more separation regions of dielectric disposed below the intermediate metal pillar and between the lower ends of the first and second metal pillars.04-16-2009
20120074569SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a terminal portion formed on a surface of the substrate.03-29-2012
20120074568METHOD AND SYSTEM FOR MINIMIZING CARRIER STRESS OF A SEMICONDUCTOR DEVICE - A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier.03-29-2012
20120261822Out-of-Plane Spacer Defined Electrode - In one embodiment, a method of forming an out-of-plane electrode includes providing an oxide layer above an upper surface of a device layer, providing a first cap layer portion above an upper surface of the oxide layer, etching a first electrode perimeter defining trench extending through the first cap layer portion and stopping at the oxide layer, depositing a first material portion within the first electrode perimeter defining trench, depositing a second cap layer portion above the first material portion, vapor releasing a portion of the oxide layer, depositing a third cap layer portion above the second cap layer portion, etching a second electrode perimeter defining trench extending through the second cap layer portion and the third cap layer portion, and depositing a second material portion within the second electrode perimeter defining trench, such that a spacer including the first material portion and the second material portion define out-of-plane electrode.10-18-2012
20110121455Semiconductor Devices Having Interconnection Structures - An interconnection structure for a semiconductor device may include lower interconnection patterns disposed in a checker board shape and upper interconnection patterns disposed in a checker board shape and connecting two adjacent lower interconnection patterns to each other.05-26-2011
20110121456Techniques for Modular Chip Fabrication - Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.05-26-2011
20100327443JOINING STRUCTURE AND A SUBSTRATE-JOINING METHOD USING THE SAME - The present invention concerns a joining structure and a substrate-joining method using the same. The joining structure comprises a substrate, and comprises a plurality of joining patterns which are located on the said substrate and which are spaced apart from each other. The substrate-joining method using the joining structure can comprise: a stage involving the formation of a plurality of joining patterns which are spaced apart from each other on a first substrate; and a stage of joining a second substrate on the plurality of joining patterns. When the said joining structure is employed, it is possible to reduce or prevent damage due to spreading of the joining substance during joining of the two substrates.12-30-2010
20100252927Pattern-Print Thin-Film Transistors with Top Gate Geometry - A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.10-07-2010
20110241207DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION - Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure.10-06-2011
20100230813Semiconductor Constructions and Methods of Forming Layers - The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.09-16-2010
20130020704BONDING SURFACES FOR DIRECT BONDING OF SEMICONDUCTOR STRUCTURES - Methods of directly bonding a first semiconductor structure to a second semiconductor structure include directly bonding at least one device structure of a first semiconductor structure to at least one device structure of a second semiconductor structure in a conductive material-to-conductive material direct bonding process. In some embodiments, at least one device structure of the first semiconductor structure may be caused to project a distance beyond an adjacent dielectric material on the first semiconductor structure prior to the bonding process. In some embodiments, one or more of the device structures may include a plurality of integral protrusions that extend from a base structure. Bonded semiconductor structures are fabricated using such methods.01-24-2013
20120326309OPTIMIZED ANNULAR COPPER TSV - The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.12-27-2012
20120091587METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D IC based system comprising a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper; a second mono-crystallized semiconductor layer comprising second transistors and overlaying the metal layer; wherein the second mono-crystallized semiconductor layer thickness is less than 150 nm, and wherein at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.04-19-2012
20120091586CONFORMAL COATING OF HIGHLY STRUCTURED SURFACES - Method of applying a conformal coating to a highly structured substrate and devices made by the disclosed methods are disclosed. An example method includes the deposition of a substantially contiguous layer of a material upon a highly structured surface within a deposition process chamber. The highly structured surface may be associated with a substrate or another layer deposited on a substrate. The method includes depositing a material having an amorphous structure on the highly structured surface at a deposition pressure of equal to or less than about 3 mTorr. The method may also include removing a portion of the amorphous material deposited on selected surfaces and depositing additional amorphous material on the highly structured surface.04-19-2012
20130020707NOVEL SEMICONDUCTOR SYSTEM AND DEVICE - A 3D IC based system including: a first semiconductor layer including first alignment marks and first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer; and wherein the second transistors include a plurality of N-type transistors and P-type transistors, and wherein the second mono-crystallized semiconductor layer is transferred from a reusable donor wafer.01-24-2013
20130020706SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a semiconductor device includes a substrate, a line-and-space structure, a first film and a second film. The line-and-space structure includes line patterns arranged on the substrate parallel to one another at a predetermined distance. The first film is formed on side surfaces and bottom surfaces of the line patterns by an insulating film material. The second film is formed on the line-and-space structure across a space between the line patterns by a material showing low wettability to the first film. Space between the line patterns includes an air gap in which at least a bottom surface of the first film is totally exposed.01-24-2013
20130020705METHOD TO FORM UNIFORM SILICIDE BY SELECTIVE IMPLANTATION - Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.01-24-2013
20080237857Semiconductor package - There is disclosed a method of making an electronic package (10-02-2008
20080224313Method for forming a seed layer for damascene copper wiring, and semiconductor wafer with damascene copper wiring formed using the method - A method for forming a seed layer for damascene copper wiring is provided. The method comprises the step of forming a seed layer, during damascene copper wiring formation, using an electroless plating solution comprising a water-soluble nitrogen-containing polymer and glyoxylic acid as a reducing agent, wherein the weight-average molecular weight (Mw) of the water-soluble nitrogen-containing polymer is 1,000 to less than 100,000. Preferably, the electroless plating solution further comprises phosphinic acid.09-18-2008
20130181349SEMICONDUCTOR DEVICE HAVING THROUGH-SUBSTRATE VIA - According to an embodiment, a semiconductor device includes a first circuit block, a first through-substrate via, and a back surface wiring. The first circuit block is provided on a surface side of a semiconductor substrate. The first through-substrate via is provided along a circumference of the first circuit block so as to separate the first circuit block from other circuit blocks. The first circuit block is provided so as to penetrate the surface of the semiconductor substrate. The first circuit block is isolated from the surroundings. The first circuit block has conductivity. The back surface wiring is provided on the back surface side of the semiconductor substrate. The back surface wiring is connected to the first through-substrate via. The back surface wiring connects the first through-substrate via to a power supply terminal or a shield potential terminal.07-18-2013
20130168860Semiconductor Package with Ultra-Thin Interposer Without Through-Semiconductor Vias - There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer.07-04-2013
20120248606INTEGRATED CIRCUIT DEVICE - An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit, a second circuit, at least one interconnect line and an electrostatic discharge protection circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically connected to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically connected to the second circuit. The first internal bonding pad is electrically connected to the second internal bonding pad via the bonding wire. The first internal bonding pad is electrically connected to the electrostatic discharge protection circuit via the interconnect line. The electrostatic discharge protection circuit is electrically connected to the external bonding pad which is used for electrically connecting an external package lead.10-04-2012
20130134590FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES - A microelectronic substrate which includes a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface; a plurality of metal lines of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface of the dielectric layer; a dielectric cap layer having a first portion overlying the surfaces of the metal lines and a second portion overlying the dielectric layer between the metal lines, the first portion has a first height above the surface of the dielectric layer, and the second portion has a second height above the surface of the dielectric layer, the second height being greater than the first height; and an air gap disposed between the metal lines, the air gap underlying the second portion of the cap layer.05-30-2013
20130134589CHIP-PACKAGE AND A METHOD FOR FORMING A CHIP-PACKAGE - A chip-package includes a chip-carrier configured to carry a chip, the chip arranged over a chip-carrier side, wherein the chip-carrier side is configured in electrical connection with a chip back side; an insulation material including: a first insulation portion formed over a first chip lateral side; a second insulation portion formed over a second chip lateral side, wherein the first chip lateral side and the second chip lateral side each abuts opposite edges of the chip back side; and a third insulation portion formed over at least part of a chip front side, the chip front side including one or more electrical contacts formed within the chip front side; wherein at least part of the first insulation portion is arranged over the chip-carrier side and wherein the first insulation portion is configured to extend in a direction perpendicular to the first chip lateral side further than the chip-carrier.05-30-2013
20110272810STRUCTURE AND METHOD FOR AIR GAP INTERCONNECT INTEGRATION - Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.11-10-2011
20110272809SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.11-10-2011
20110272808SEMICONDUCTOR PROCESS AND STRUCTURE - A semiconductor process includes the following steps. Firstly, a conductive substrate is provided. Then, at least one insulating pattern is formed on the conductive substrate. Thereafter at least one metal pattern is formed on the insulating pattern. After that, a passivation layer is formed on the conductive substrate to cover the metal pattern by an electroplating process.11-10-2011
20130113100SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. Firstly, a semiconductor substrate having an active surface and a back surface is provided. The active surface is opposite to the back surface, and the semiconductor substrate includes at least one grounding pad disposed on the active surface. Secondly, at least one through silicon via is formed through the semiconductor substrate from the back surface to the active surface thus exposing the grounding pad. Then, a conductive layer is formed on the back surface of the semiconductor substrate and filled into the through silicon via to electrically connect to the grounding pad and the semiconductor substrate.05-09-2013
20130147045Flash Memory Having Multi-Level Architecture - Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same.06-13-2013
20080197495STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES - A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.08-21-2008
20080197494Semiconductor device including copper wiring and via wiring having length longer than width thereof and method of manufacturing the same - A semiconductor device has an interconnect and a via material. The via material is provided under the interconnect and is in contact with an end portion of the interconnect. The interconnect and the via are made of copper as one piece. The via material has a top surface coupled to a bottom surface of the interconnect. The top surface has a first portion parallel with a longitudinal direction of the interconnect and a second portion parallel with a direction perpendicular to the longitudinal direction, and the first portion is larger than the second portion.08-21-2008
20110248401NANOTUBE-BASED ELECTRODES - Transparent electrodes are manufactured. In accordance with various example embodiments, a transparent electrode is manufactured by generating a solution including a composite material having nanotubes and a conjugated polymer, in which the nanotubes constitute a majority of the composite material by weight. The conjugated polymer is used to disperse the nanotubes in the solution, and the solution is coated onto a substrate to form an electrode including a network of the carbon nanotubes.10-13-2011
20100283152INTEGRATED CIRCUITS INCLUDING ILD STRUCTURE, SYSTEMS, AND FABRICATION METHODS THEREOF - An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 Å or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure.11-11-2010
20100289143METHOD FOR PRODUCING LOW-k FILM, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - Hydrophobicity of a low dielectric constant film comprising a porous silica film is improved by applying a raw material for forming a porous silica film onto a substrate, and performing vapor-phase transport treatment to expose the substrate to an atmosphere of organic amine vapor to which no water is added. Simultaneously, reduction in a dielectric constant, reduction in leakage current, and improvement in mechanical strength are attained by controlling a pore diameter in a predetermined range.11-18-2010
20100308462GLASS COMPOSITIONS USED IN CONDUCTORS FOR PHOTOVOLTAIC CELLS - The invention relates to glass compositions useful in conductive pastes for silicon semiconductor devices and photovoltaic cells. The thick film conductor compositions include one or more electrically functional powders and one or more glass frits dispersed in an organic medium. The thick film compositions may also include one or more additive(s). Exemplary additives may include metals, metal oxides or any compounds that can generate these metal oxides during firing.12-09-2010
20100314763INTEGRATED CIRCUIT SYSTEM EMPLOYING LOW-K DIELECTRICS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.12-16-2010
20100314762Semiconductor Substrate with Through-Contact and Method for Production Thereof - The interlayer connection of the substrate is formed by a contact-hole filling (12-16-2010
20130119543THROUGH SILICON VIA FOR STACKED WAFER CONNECTIONS - Stacked wafer connections are enhanced by forming a though silicon via including a first via portion formed in an upper portion of a via hole and a second via portion in a lower portion of the via hole. Embodiments include forming a via hole in a first surface of a substrate; partially filling the via hole with a dielectric material; filling the remainder of the via hole with a first conductive material; removing a portion of a second surface of the substrate to expose the dielectric material; removing the dielectric material from the via hole; and filling a the via hole with a second conductive material electrically conductively connected to the first conductive material.05-16-2013
20110309506CONDUCTIVE INTERCONNECT STRUCTURES AND FORMATION METHODS USING SUPERCRITICAL FLUIDS - Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns or more. The method can further include disposing a conductive material in the via while the via is exposed to a supercritical fluid. For example, copper can be disposed in the via by introducing a copper-containing precursor into the supercritical fluid and precipitating the copper from the supercritical fluid. Interconnect structures can be formed using this technique in a single generally continuous process, and can produce conductive structures having a generally uniform grain structure across the width of the via.12-22-2011
201301935743D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP - A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.08-01-2013
20130193573METHODS OF STRESS BALANCING IN GALLIUM ARSENIDE WAFER PROCESSING - Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.08-01-2013
20130200517INTERPOSER FRAME AND METHOD OF MANUFACTURING THE SAME - The mechanisms of using an interposer frame to form a PoP package are provided in the disclosure. The interposer frame is formed by using a substrate with one or more additives to adjust the properties of the substrate. The interposer frame has openings lined with conductive layer to form through substrate vias (TSVs) with solder balls on adjacent packages. The interposer frame enables the reduction of pitch of TSVs, mismatch of coefficients of thermal expansion (CTEs), shorting, and delamination of solder joints, and improve mechanical strength of the package.08-08-2013
20130207264Stress Reduction Apparatus - A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.08-15-2013
20130207265STRUCTURE AND METHOD OF MAKING THE SAME - A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.08-15-2013

Patent applications in class Of specified material other than unalloyed aluminum

Patent applications in all subclasses Of specified material other than unalloyed aluminum