Entries |
Document | Title | Date |
20080197486 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate that has an integrated circuit and an electrode electrically connected to the integrated circuit; a first resin layer that is formed in a first region overlapping the integrated circuit over a surface of the semiconductor substrate where the electrode is formed; a wiring that is electrically connected to the electrode and is formed on the first resin layer; and a second resin layer that is formed on the surface of the semiconductor substrate in a second region surrounding the first region, is the second resin layer being spaced a distance from the first resin layer. | 08-21-2008 |
20080197487 | Semiconductor Device Including a Coupled Dielectric Layer and Metal Layer, Method of Fabrication Thereof, and Material for Coupling a Dielectric Layer and a Metal Layer in a Semiconductor Device - A passivating coupling material for, on the one hand, passivating a dielectric layer in a semiconductor device, and on the other hand, for permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. In a particular example, the dielectric layer may be a porous material having a desirably decreased dielectric constant k, and the passivating coupling material provides steric shielding groups that substantially block the adsorption and uptake of ambient moisture into the porous dielectric layer. The passivating coupling materials also provides metal nucleation sides for promoting the deposition of a metal thereon in liquid phase, in comparison with metal deposition without the presence of the passivating coupling material. The use of a liquid phase metal deposition process facilitates the subsequent manufacture of the semiconductor device. In one example, the passivating coupling material has multiple Si atoms in its chemical composition, which desirably increases the thermal stability of the material. | 08-21-2008 |
20080203562 | Method for designing semiconductor device and semiconductor device - A method for designing a semiconductor device and a semiconductor device of the present invention permits the achievement of a predetermined pattern area ratio while power supply lines are reinforced by connecting a dummy metal line, which is formed in an unoccupied region of a wiring layer for the purpose of achieving the predetermined area ratio, at its two or more points with a power supply line for VDD or VSS. | 08-28-2008 |
20080211090 | Packed Semiconductor Sensor Chip For Use In Liquids - The present invention provides a packed semiconductor sensor chip ( | 09-04-2008 |
20080211091 | Power Semiconductor Module and Method for Producing the Same - A method for producing a power semiconductor module including forming a contact between a contact region and a contact element as an ultrasonic welding contact via a sonotrode. The ultrasonic welding operation also being used for joining the contact regions with the contact ends and consequently for joining the contacts and the foot regions. | 09-04-2008 |
20080265409 | INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM - An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer. | 10-30-2008 |
20080284006 | Semiconductor devices including interlayer conductive contacts and methods of forming the same - In a semiconductor device and a method of forming the same, the semiconductor device comprises: a first insulating layer on an underlying contact region of the semiconductor device, the first insulating layer having an upper surface; a first conductive pattern in a first opening through the first insulating layer, an upper portion of the first conductive pattern being of a first width, an upper surface of the first conductive pattern being recessed relative to the upper surface of the first insulating layer so that the upper surface of the first conductive pattern has a height relative to the underlying contact region that is less than a height of the upper surface of the first insulating layer relative to the underlying contact region; and a second conductive pattern contacting the upper surface of the first conductive pattern, a lower portion of the second conductive pattern being of a second width that is less than the first width. | 11-20-2008 |
20080284007 | Semiconductor module and method for manufacturing semiconductor module - A semiconductor module includes a first metal foil; an insulating sheet mounted on a top surface of the first metal foil; at least one second metal foil mounted on a top surface of the insulating sheet; at least one semiconductor device mounted on the second metal foil; and a resin case for surrounding the first metal foil, insulating sheet, second metal foil, and semiconductor device. A bottom end of a peripheral wall of the resin case is located above a bottom surface of the first metal foil. A resin is provided inside the resin case to fill the inside of the resin case. The bottom surface of the first metal foil and the resin form a flat bottom surface so that the flat bottom surface contacts an external mounting member. | 11-20-2008 |
20080303141 | METHOD FOR ETCHING A SUBSTRATE AND A DEVICE FORMED USING THE METHOD - The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate | 12-11-2008 |
20090001566 | Semiconductor Device Having Improved Gate Electrode Placement and Decreased Area Design - In one aspect provides a semiconductor device that includes gate electrodes having ends that overlap isolation regions, wherein each gate electrode] is located over an active region located within a semiconductor substrate. A gate oxide is located between each of the gate electrodes and the active region, and source/drains are located adjacent each of the gate electrodes and within the active region. An etch stop layer is located over each of the gate electrodes and each of the gate electrodes has at least one electrical contact that extends through the etch stop layer and contacts a portion of the gate electrode that overlies the active region. | 01-01-2009 |
20090045507 | Flip chip interconnection - Methods for forming flip chip interconnection, in which the bump interconnect is defined at least in part by an underfill. The underfill includes a material that is thermally cured; that is, raising the temperature of the underfill material can result in progressive curing of the underfill through stages including a gel stage and a fully cured stage. According to the invention, during at least an early stage in the process the semiconductor chip is carried by a thermode, which is employed to control the temperature of the assembly in a specified way. Also, flip chip interconnections and flip chip packages made according to the methods of invention. | 02-19-2009 |
20090051027 | Method of Manufacture and Identification of Semiconductor Chip Marked For Identification with Internal Marking Indicia and Protection Thereof by Non-black Layer and Device Produced Thereby - An electronic integrated circuit has a planar front surface and a planar backsurface. Internal marking indicia identification are marked upon an marking surface on the exterior surface of the chip. The internal identification indicia on the chip surface are protected against remarking by a non-black, colored, optically transmissive layer, so the indicia are visible through the optically transmissive material. Electrical interconnection means connect to the electrical contact site through the package. There is least one electrical contact site on an exterior surface of the chip. | 02-26-2009 |
20090057886 | SEMICONDUCTOR DEVICE AND SUBSTRATE - A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes. | 03-05-2009 |
20090085201 | DIRECT DEVICE ATTACHMENT ON DUAL-MODE WIREBOND DIE - A dual-mode integrated circuit comprises wirebondable and solderable electrical connectors. | 04-02-2009 |
20090096089 | METHOD FOR PRODUCING A THIN SEMICONDUCTOR CHIP COMPRISING AN INTEGRATED CIRCUIT - In a method for producing a thin film chip including an integrated circuit, a semi-conductor wafer having a first surface is provided. At least one cavity is produced under a defined section of the first surface by means of porous silicon. A circuit structure is produced in the defined section. The defined wafer section is subsequently released from the semiconductor wafer by severing local web-like connections, which hold the wafer section above the cavity and on the remaining semiconductor wafer. | 04-16-2009 |
20090096090 | Photolithography Process and Photomask Structure Implemented in a Photolithography Process - In a photolithography process, a photoresist layer is formed on a substrate. A photomask is aligned over the substrate to transfer pattern images defined in the photomask on the substrate. The photomask includes first and second patterns of different light transmission rates, and a dummy pattern surrounding the second pattern having a light transmission rate lower than that of the first pattern. The substrate is exposed to a light radiation through the photomask. The photoresist layer then is developed to form the pattern images. The dummy pattern is dimensionally configured to allow light transmission, but in a substantially amount so that the dummy pattern is not imaged during exposure. | 04-16-2009 |
20090096091 | SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns. | 04-16-2009 |
20090134513 | METHOD AND STRUCTURES FOR FABRICATING MEMS DEVICES ON COMPLIANT LAYERS - Methods and structures for fabricating MEMS devices on compliant layers are provided. In particular, disclosed are methods and structures that can include the use of a sacrificial layer composed of a material having material properties relative to one or more other layers. These methods and structures can reduce final device shape sensitivity to process parameters, deposition temperature differences, specific material, time, and/or geometry. Further, such methods and structures can improve the final as-built shape of released devices, reduce variability in the as-built shape, eliminate decoupling of the deposited layers from the substrate, and reduce variability across a product array, die, or wafer. | 05-28-2009 |
20090140418 | METHOD FOR INTEGRATING POROUS LOW-K DIELECTRIC LAYERS - Described herein are methods for integrating low-k dielectric layers with various interconnect structures. In one embodiment, a method for restoring a porous dielectric layer includes forming an opening in the porous low-k dielectric layer. The method further includes forming an opening in a barrier layer. The method further includes depositing a restoring dielectric layer to seal a surface layer of pores of the porous dielectric layer. In one embodiment, the restoring dielectric layer is non-porous and hydrophobic to prevent the porous dielectric layer from adsorbing moisture and consequently increasing the dielectric constant of the porous dielectric layer. The method further includes performing a clean operation on the interconnect structure prior to metallization. The method further includes depositing, masking, and etching a metal layer. | 06-04-2009 |
20090146296 | Method of forming high-k dielectric stop layer for contact hole opening - A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow. | 06-11-2009 |
20090174067 | AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING - The present invention provides a method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. | 07-09-2009 |
20090174068 | Semiconductor device, circuit board, and electronic instrument - A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device ( | 07-09-2009 |
20090194871 | SEMICONDUCTOR PACKAGE AND METHOD OF ATTACHING SEMICONDUCTOR DIES TO SUBSTRATES - A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds. | 08-06-2009 |
20090206475 | Method of manufacturing semiconductor device, and semiconductor device - A method of manufacturing a semiconductor device which includes step of forming a lower resist film over an insulating interlayer; forming a first opening having a circular geometry in a plan view, and second to fifth openings arranged respectively on four sides of the first opening, in the lower resist film; and etching the film-to-be-etched while using the lower resist film as a mask, wherein in the step of etching the film-to-be-etched, a hardened layer is formed in a region of the lower resist film fallen between the first opening and each of the second to fifth openings, and the film-to-be-etched is etched while using the hardened layers as a mask, so as to form a contact hole having a rectangular geometry in a plan view in the film-to-be-etched at a position correspondent to the first opening of the lower resist film. | 08-20-2009 |
20090230545 | ELECTRONIC DEVICE CONTACT STRUCTURES - Electronic device contact structures are disclosed. | 09-17-2009 |
20090243088 | Multiple Layer Metal Integrated Circuits and Method for Fabricating Same - A method of fabricating a plurality of layers of metal on a substrate depositing a first layer of metal on the substrate; depositing a first layer of planarization material over the substrate and first layer of metal to a depth above the top of the first layer of metal; polishing the first layer of planarization material down to at least the top of the first layer of metal; and depositing a second layer of metal on the first layer of metal and the first layer of planarization material. | 10-01-2009 |
20090243089 | MODULE INCLUDING A ROUGH SOLDER JOINT - A module includes a metallized substrate including a metal layer, a base plate, and a joint joining the metal layer to the base plate. The joint includes solder contacting the base plate and an inter-metallic zone contacting the metal layer and the solder. The inter-metallic zone has spikes up to 100 μm and a roughness (R | 10-01-2009 |
20090256254 | WAFER LEVEL INTERCONNECTION AND METHOD - A semiconductor assembly includes a semiconductor wafer including backside contact pads coupled to respective contact regions of different signal types and insulation separating the backside contact regions by signal type. The semiconductor assembly further includes metallization situated over at least a portion of the insulation and interconnecting the backside contact pads. | 10-15-2009 |
20090278254 | Dielectric materials and methods for integrated circuit applications - An integrated circuit device is provided having a substrate and areas of electrically insulating and electrically conductive material, where the electrically insulating material is a hybrid organic-inorganic material that requires no or minimal CMP and which can withstand subsequent processing steps at temperatures of 450° C. or more. | 11-12-2009 |
20090289355 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE - A semiconductor manufacturing apparatus which performs a rapid heat treatment in which metallic thin films | 11-26-2009 |
20090302462 | Prepreg, Method for Manufacturing Prepreg, Substrate, and Semiconductor Device - A prepreg which can meet a demand for thickness reduction is provided. The prepreg has first and second resin layers having different applications, functions, capabilities, or properties, and allows an amount of a resin composition in each of the first and second resin layers to be set appropriately depending on a circuit wiring portion to be embedded into the second resin layer. Further, a method for manufacturing the above prepreg, and a substrate and a semiconductor device having the prepreg are also provided. The prepreg according to the present invention includes a core layer including a sheet-shaped base member and having one surface and the other surface which is opposite to the one surface, the first resin layer provided on the one surface of the core layer and formed of a first resin composition, and the second resin layer provided on the other surface of the core layer and formed of a second resin composition, wherein at least one of a requirement that a thickness of the first resin layer is different from that of the second resin layer and a requirement that a constitution of the first resin composition is different from that of the second resin composition is satisfied. | 12-10-2009 |
20090315174 | Semiconductor Die Separation Method - According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out. | 12-24-2009 |
20100044858 | Product Chips and Die With a Feature Pattern That Contains Information Relating to the Product Chip, Methods for Fabricating Such Product Chips and Die, and Methods for Reading a Feature Pattern From a Packaged Die - Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging. | 02-25-2010 |
20100065963 | METHOD OF WIREBONDING THAT UTILIZES A GAS FLOW WITHIN A CAPILLARY FROM WHICH A WIRE IS PLAYED OUT - Contact structures for a variety of electronic components can be formed to have primarily elastic properties. The contact structures can be free standing, and can be coupled to a variety of different electronic components such as a probe card assembly, a semiconductor wafer or dies, an interposer, or the like. Tips of the contact structures can have a topology that facilities contact with another electronic component. | 03-18-2010 |
20100072614 | 3-DIMENSIONAL INTEGRATED CIRCUIT DESIGNING METHOD - A 3-dimensional integrated circuit designing method includes forming a temporary layout region for an original integrated circuit on an XY plane, the plane being short in an X direction and long in a Y direction perpendicular to the X direction, dividing the temporary layout region into 2N (N is an integral number of not smaller than 2) or more subregions in the Y direction, configuring one block for every successive N subregions to prepare a plurality of blocks, and forming N layers of layout by alternately folding each of the blocks in the Y direction in units of one subregion to selectively set a kN-th (k is an integral number not less than 1) subregion and (kN+1)th subregion of each block to one of an uppermost layer and lowermost layer. | 03-25-2010 |
20100090337 | SYSTEM AND METHOD FOR MULTI-LAYER GLOBAL BITLINES - A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device. | 04-15-2010 |
20100096748 | Combined semiconductor apparatus with semiconductor thin film - A combined semiconductor apparatus includes a semiconductor substrate having an integrated circuit, a planarized region formed in a surface of the semiconductor substrate, and a semiconductor thin film including at least one semiconductor device and bonded on the planarized region. A surface of the semiconductor thin film, in which the semiconductor device is formed, is disposed on a side of the planarized region. The apparatus may further include a planarized film disposed between the planarized region and the semiconductor thin film. | 04-22-2010 |
20100109155 | RELIABLE INTERCONNECT INTEGRATION - A semiconductor device includes a dielectric layer in which an upper portion is densified. An interconnection is disposed in the dielectric layer. The densified portion reduces undercut during subsequent processing, improving reliability of the interconnection. | 05-06-2010 |
20100140793 | Process For Manufacturing Contact Elements For Probe Card Assembles - A process for making contact elements for a probe card assembly includes steps of forming a first continuous trench in a substrate along a first direction, and forming simultaneously a plurality of tip structures adjacent one to another in the first continuous trench in a second direction substantially normal to the first direction, each of the tip structures being part of, or adapted to be part of at least one corresponding contact element capable of forming an electrical contact with a terminal of an electronic device. | 06-10-2010 |
20100155936 | METHOD OF THINNING A SEMICONDUCTOR SUBSTRATE - A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 μm. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed. | 06-24-2010 |
20100164095 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING OF SAME - A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask. | 07-01-2010 |
20100171215 | Method of Producing Optoelectronic Components and Optoelectronic Component - A method of producing optoelectronic components is indicated, in which a plurality of semiconductor bodies, each with a semiconductor layer sequence, are provided. In addition, a component carrier assembly with a plurality of connection pads is provided. The semiconductor bodies are positioned relative to the component carrier assembly. An electrically conductive connection is produced between the connection pads and the associated semiconductor bodies and the semiconductor bodies are attached to the component carrier assembly. The optoelectronic components are finished in that one component carrier ( | 07-08-2010 |
20100207269 | Integrated Circuit Nanowires - Implementations of encapsulated nanowires are disclosed. | 08-19-2010 |
20100230807 | Method and Apparatus to Repair Defects in Nonvolatile Semiconductor Memory Devices - A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed. | 09-16-2010 |
20100264537 | Semiconductor Arrangement - A semiconductor arrangement, in particular a power semiconductor arrangement, in which a semiconductor having a top side provided with contacts is connected to an electrical connection device formed from a film assembly wherein an underfill is provided between the connection device and the top side of the semiconductor. The underfill has a matrix formed from a preceramic polymer. | 10-21-2010 |
20100270671 | MANIPULATING FILL PATTERNS DURING ROUTING - A CAD tool that supports an overlay-enabling operating mode. After the overlay-enabling operating mode is entered, the layout-editing facility permits modifications to the interconnect structure of an integrated circuit that is being designed regardless of whether a particular modification interferes with an existing pattern of metal fill. For example, a new signal wire can be added to electrically connect two specified points in the layout in a manner that causes the wire to cross over one or more metal-fill tiles. The CAD tool then modifies the fill pattern to get rid of any design-rule violations caused by the modifications to the interconnect structure by removing and/or modifying one or more fill tiles. | 10-28-2010 |
20100301471 | LOW-RESISTANCE ELECTRODE DESIGN - A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated. | 12-02-2010 |
20100308455 | Method for Manufacturing Hetero-Bonded Wafer - A method for manufacturing a hetero-bonded wafer having a large mismatch of thermal expansion coefficient comprises forming a wafer bonding means and an electrical interconnection means on at least one bonding surface of two wafers to be bonded with each other, forming grooves in the bonding surface of one wafer along dicing lines with an interval between the grooves being equal to or an even multiple of a die width, bonding the two wafers at a temperature less than 200° C. thinning a back side of the grooved wafer such that at least a portion of the grooves is exposed, and rebonding the bonded wafer pair at an elevated temperature higher than the first bonding temperature. The method for manufacturing a hetero-bonded wafer can avoid wafer level bow/warp and also reduce debonding and cracking in individual segments induced by thermal stress due to a mismatch of thermal expansion coefficient. Embodiments of the method are useful for wafer level packaging and the fabrication of hybrid devices by heterogeneous wafer bonding. | 12-09-2010 |
20100314751 | Processes and structures for IC fabrication - The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm. | 12-16-2010 |
20100314752 | FORMING AN ETCHED PLANARISED PHOTONIC CRYSTAL STRUCTURE - A method of forming a photonic crystal (PhC) structure and a PhC structure formed by such method. The method comprises forming holes in a Si-based host layer; filling the holes with a high-density plasma (HDP) deposited Si-based oxide and such that a surface of the Si-based host layer is directly covered with the Si-based oxide; performing at least a selective wet etching step for etching the Si-based oxide such that a surface of the resulting PhC structure is planarized. | 12-16-2010 |
20100314753 | SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING - A semiconductor device includes a substrate, a memory cell formed on the substrate, and a contact to the substrate. The contact is formed in an area away from the memory cell and functions to raise the potential of the substrate. | 12-16-2010 |
20110006414 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device includes a semiconductor chip includes a functional area at a desired position and a board mechanically and electrically joined to the semiconductor chip board, with the board layered over the semiconductor chip. An electronic device includes at least one first joint member that joins the semiconductor chip and the board to each other and a second joint member that joins the semiconductor chip and the board to each other. | 01-13-2011 |
20110024898 | METHOD OF MANUFACTURING SUBSTRATES HAVING ASYMMETRIC BUILDUP LAYERS - A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m≠n is disclosed. The method includes forming (m−n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials. | 02-03-2011 |
20110031614 | METHODS FOR FABRICATING SEMICONDUCTOR COMPONENTS AND PACKAGED SEMICONDUCTOR COMPONENTS - Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die having a semiconductor substrate and an integrated circuit. The substrate has a first side, a second side, a sidewall between the first and second sides, a first indentation at the sidewall around a periphery of the first side, and a second indentation at the sidewall around a periphery of the second side. The component can further include a first exterior cover at the first side and a second exterior cover at the second side. The first exterior cover has a first extension in the first indentation, and the second exterior cover has a second extension in the second indentation. The first and second extensions are spaced apart from each other by an exposed portion of the sidewall. | 02-10-2011 |
20110074013 | FILM FORMING METHOD OF SILICON OXIDE FILM, SILICON OXIDE FILM, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A silicon compound gas, an oxidizing gas, and a rare gas are supplied into a chamber ( | 03-31-2011 |
20110089559 | METHOD AND INSTALLATION FOR PRODUCING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method of producing a semiconductor device is provided, the semiconductor device including a substrate, a semiconductor layer and at least one metallization layer adjacent to at least one element chosen from the substrate and the semiconductor layer, the method including forming at least one metallization layer which, adjacent to at least one element chosen from the substrate and the semiconductor layer, includes oxygen. | 04-21-2011 |
20110121446 | Fabrication of Atomic Scale Devices - This invention concerns the fabrication of nano to atomic scale devices, that is electronic devices fabricated down to atomic accuracy. The fabrication process uses either an SEM or a STM tip to pattern regions on a semiconductor substrate. Then, forming electrically active parts of the device at those regions. Encapsulating the formed device. Using a SEM or optical microscope to align locations for electrically conducting elements on the surface of the encapsulating semiconductor with respective active parts of the device encapsulated below the surface. Forming electrically conducting elements on the surface at the aligned locations. And, electrically connecting electrically conducting elements on the surface with aligned parts of the device encapsulated below the surface to allow electrical connectivity and tunability of the device. In further aspects the invention concerns the devices themselves. | 05-26-2011 |
20110121447 | ADHESIVE FOR CONNECTION OF CIRCUIT MEMBER AND SEMICONDUCTOR DEVICE USING THE SAME - An adhesive for connecting circuit members, which is interposed between a semiconductor chip having protruding connecting terminals and a board having wiring patterns formed thereon for electrically connecting the connecting terminals and the wiring patterns facing each other and bonding the semiconductor chip and the board by applying pressure/heat, containing a resin composition containing a thermoplastic resin, a crosslinkable resin and a hardening agent for forming a crosslink structure of the crosslinkable resin; and composite oxide particles dispersed in the resin composition. | 05-26-2011 |
20110127667 | ADHESIVE FOR CONNECTION OF CIRCUIT MEMBER AND SEMICONDUCTOR DEVICE USING THE SAME - An adhesive for connecting circuit members, which is interposed between a semiconductor chip having protruding connecting terminals and a board having wiring patterns formed thereon for electrically connecting the connecting terminals and the wiring patterns facing each other and bonding the semiconductor chip and the board by applying pressure/heat, containing a resin composition containing a thermoplastic resin, a crosslinkable resin and a hardening agent for forming a crosslink structure of the crosslinkable resin; and composite oxide particles dispersed in the resin composition. | 06-02-2011 |
20110133330 | LOW TEMPERATURE CURING COMPOSITIONS - The present invention relates to thermosetting resin compositions that include maleimide-, nadimide- or itaconimide-containing compounds and a metal/carboxylate complex and a peroxide, which is curable at a low temperature at relative short period of time, such as less than about 100° C., for instance 55-70° C., over a period of time of about 30 to 90 minutes. The invention further provides methods of preparing such compositions, methods of applying such compositions to substrate surfaces, and packages and assemblies prepared therewith for connecting microelectronic circuitry. | 06-09-2011 |
20110186984 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device which are able to form a conductive film, which is dense, includes a low concentration of source-derived impurities and has low resistivity, at a higher film-forming rate. The substrate processing apparatus includes a processing chamber configured to stack and accommodate a plurality of substrates; a first processing gas supply system configured to supply a first processing gas into the processing chamber; a second processing gas supply system configured to supply a second processing gas into the processing chamber; and a control unit configured to control the first processing gas supply system and the second processing gas supply system. Here, at least one of the first processing gas supply system and the second processing gas supply system includes two nozzles which are vertically arranged in a stacking direction of the substrates and have different shapes, and the control unit is configured to supply at least one of the first processing gas and the second processing gas into the processing chamber through the two nozzles having different shapes when films are formed on the substrates by supplying the first processing gas and the second processing gas into the processing chamber at pulses having different film-forming rates. | 08-04-2011 |
20110193217 | Manufacturing of a Device Including a Semiconductor Chip - Metal particles are applied to a metal foil. A semiconductor chip is placed over the metal foil with contact elements of the semiconductor chip facing the metal particles. The metal particles are heated and the metal foil is structured after heating the metal particles. | 08-11-2011 |
20110221057 | Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant. | 09-15-2011 |
20110227213 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR DEVICE MADE THEREFROM - A method for fabricating semiconductor devices includes: (a) forming over a temporary substrate a sacrificial film layer; (b) growing laterally and epitaxially an epitaxial film layer; (c) forming over the epitaxial film layer a patterned mask that covers partially the epitaxial film layer and that defines a plurality of through holes to expose a plurality of epitaxial surface regions, respectively; (d) forming a plurality of conductive members respectively in the through holes and on the epitaxial surface regions; (e) removing the patterned mask and removing a part of the epitaxial film layer and a part of the sacrificial film layer beneath the patterned mask; (f) removing the sacrificial film layer; and (g) removing the temporary substrate. | 09-22-2011 |
20110227214 | WIRING BOARD AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A wiring board has a structure where multiple wiring layers are stacked one on top of another with insulating layers interposed therebetween. A sheet-shaped member is buried in an outermost insulating layer located on a side of the structure opposite to a side on which a semiconductor element is to be mounted. The sheet-shaped member has a modulus of elasticity and a coefficient of thermal expansion which are similar to a modulus of elasticity and a coefficient of thermal expansion of the semiconductor element. The sheet-shaped member is made of a material having a modulus of elasticity and a coefficient of thermal expansion which are enough to bring respective distributions thereof into a substantially symmetric form in a direction orthogonal to a surface of the wiring board in the case where the semiconductor element is mounted. | 09-22-2011 |
20110227215 | ELECTRONIC DEVICE, PACKAGE INCLUDING THE SAME AND METHOD OF FABRICATING THE PACKAGE - An electronic device, a package including the same, and a method of fabricating the package, the electronic device including a substrate having an operation structure therein; a first passivation layer on a first side of the substrate; and first conductive patterns on a second side of the substrate, the first conductive patterns being electrically connected to the operation structure, wherein the first passivation layer has a higher flexibility than the substrate when the substrate and the first passivation layer are bent. | 09-22-2011 |
20110241200 | ULTRA LOW DIELECTRIC CONSTANT MATERIAL WITH ENHANCED MECHANICAL PROPERTIES - An ultra low dielectric constant material is disclosed. The ultra-low dielectric constant material comprises a three dimensional random network porous dielectric comprising atoms of Si, C, O, and H. The ultra-low dielectric constant material also comprises a dielectric constant of not more than 2.6. The ultra-low dielectric constant material further comprises a carbon concentration of at least 15% and a content of carbon that is bonded as —CH2-groups, wherein a concentration of carbon is greater than a concentration of carbon in an ultra low dielectric constant material formed by using a single step ultra-violet curing process. | 10-06-2011 |
20110254150 | Method of Manufacturing a Semiconductor Device - The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements | 10-20-2011 |
20110309489 | METHOD FOR FORMING A DOPED REGION IN A SEMICONDUCTOR LAYER OF A SUBSTRATE AND USE OF SUCH METHOD - A method of forming a doped region in a semiconductor layer of a substrate by alloying with doping elements is disclosed. In one aspect, the method includes screen printing a paste layer of doping element paste to the substrate and firing the screen printed paste layer of doping element paste, wherein a highly pure doping element layer is applied to the semiconductor layer after which the paste layer is screen printed to the doping element layer. | 12-22-2011 |
20110316145 | NANO/MICRO-STRUCTURE AND FABRICATION METHOD THEREOF - A nano/micro-structure and a fabrication method thereof are provided. The method combines electroless plating and metal-assist etching to fabricate nano/micro-structure on a silicon substrate. | 12-29-2011 |
20120001320 | SUBSTRATE PROCESSING INCLUDING A MASKING LAYER - Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer. | 01-05-2012 |
20120001321 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING OF SAME - A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask. | 01-05-2012 |
20120018874 | Semiconductor Device and Method of Forming RDL over Contact Pad with High Alignment Tolerance or Reduced Interconnect Pitch - A semiconductor device has a semiconductor die with an active surface. A first conductive layer is formed over the active surface. A first insulating layer is formed over the active surface. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second insulating layer is removed over the first conductive layer so that no portion of the second insulating layer overlies the first conductive layer. A second conductive layer is formed over the first conductive layer and first and second insulating layers. The second conductive layer extends over the first conductive layer up to the first insulating layer. Alternatively, the second conductive layer extends across the first conductive layer up to the first insulating layer on opposite sides of the first conductive layer. A third insulating layer is formed over the second conductive layer and first and second insulating layers. | 01-26-2012 |
20120032320 | FLEXIBLE MICRO-SYSTEM AND FABRICATION METHOD THEREOF - A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems. | 02-09-2012 |
20120038037 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures with airgaps and/or metal linings and methods of manufacture are provided. The method of forming an airgap in a wiring level includes forming adjacent wires in a dielectric layer. The method further includes forming a masking layer coincident with the adjacent wire and forming a first layer on the masking layer to reduce a size of an opening formed in the masking layer between the adjacent wires. The method further includes removing exposed portions of the first layer and the dielectric layer to form trenches between the adjacent wires. The method further includes forming an interlevel dielectric layer upon the dielectric layer, where the interlevel dielectric layer is pinched off from filling the trenches so that an airgap is formed between the adjacent wires. A metal liner can also be formed in the trenches, prior to the formation of the airgap. | 02-16-2012 |
20120038038 | ALUMINUM NITRIDE SUBSTRATE, ALUMINUM NITRIDE CIRCUIT BOARD, SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING ALUMINUM NITRIDE SUBSTRATE - The present invention provides an aluminum nitride substrate and an aluminum nitride circuit board having excellent insulation characteristics and heat dissipation properties and having high strength, a semiconductor apparatus, and a method for manufacturing an aluminum nitride substrate. | 02-16-2012 |
20120038039 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A conventional transfer technique has low efficiency in separation at a separation layer and costs much. | 02-16-2012 |
20120056314 | Semiconductor Device and Method of Forming Base Leads from Base Substrate as Standoff for Stacking Semiconductor Die - A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die. | 03-08-2012 |
20120061819 | Semiconductor Module and Method for Production Thereof - This invention relates to a module including a semiconductor chip, at least two contact elements and an insulating material between the two contact elements. Furthermore, the invention relates to a method for production of such a module. | 03-15-2012 |
20120061820 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENT, AND ELECTRONIC COMPONENT - Provided is a method for manufacturing an electronic component by using a solder joining method for bonding a first electronic component having a metal electrode with a second electronic component having a solder electrode, the method comprising; (i) forming a resin layer containing a thermosetting resin on at least one of the solder joint surfaces of said first electronic component and said second electronic component; (ii) positioning said metal electrode of said first electronic component and said solder electrode of said second electronic component to face each other, heating said positioned electrodes and applying pressure, and thereby bringing said metal electrode and said solder electrode into contact; (iii) heating electronic components while applying pressure thereby fusion bonding said solder to said metal electrode; and (iv) heating said resin layer. | 03-15-2012 |
20120112339 | SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming the same are disclosed, which forms a low-dielectric-constant oxide film only at a peripheral part of a bit line conductive material, resulting in reduction in parasitic capacitance of the bit line. The semiconductor device includes a bit line formed over a semiconductor substrate, a first spacer formed over sidewalls of the bit line, and a second spacer formed over sidewalls of the first spacer, configured to have a dielectric constant lower than that of the first spacer. | 05-10-2012 |
20120112340 | Semiconductor Device and Method of Forming Insulating Layer Disposed Over The Semiconductor Die For Stress Relief - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 05-10-2012 |
20120112341 | METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications. | 05-10-2012 |
20120119352 | ELECTROLESS GOLD PLATING SOLUTION FOR FORMING FINE GOLD STRUCTURE, METHOD OF FORMING FINE GOLD STRUCTURE USING SAME, AND FINE GOLD STRUCTURE FORMED USING SAME - An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 μm or smaller, in terms of the width of the exposed substrate area, and having a height of 3 μm or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 μm or finer is formed therefrom. | 05-17-2012 |
20120119353 | UNDERFILL METHOD AND CHIP PACKAGE - A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material. | 05-17-2012 |
20120126392 | Methods for Making Micro Needles and Applications Thereof - The invention relates in a general aspect to a method of making vertically protruding elements on a substrate, said elements having a tip comprising at least one inclined surface and an elongated body portion extending between said substrate and said tip. The method comprises an anisotropic, crystal plane dependent etch forming said inclined surface(s); and an anisotropic, non crystal plane dependent etch forming said elongated body portion; combined with suitable patterning processes defining said protruding elements to have a predetermined base geometry. | 05-24-2012 |
20120126393 | RESIN COMPOSITION, MULTILAYER BODY CONTAINING THE SAME, SEMICONDUCTOR DEVICE, AND FILM - Disclosed is a resin composition which has high heat dissipation properties and high electrical insulation properties at the same time, while having low-temperature bondability to a conductor circuit or the like. The resin composition contains (A) a thermoplastic polyimide resin having a glass transition temperature of 160 DEG C or less and (B) an inorganic filler. The aspect ratio, that is the value of length/thickness, of the inorganic filler (B) is 9 or more, and the content of the inorganic filler (B) is 40-70 weight % relative to the total weight of the resin composition. The resin composition has a melt viscoelasticity of 10-300 MPa (inclusive) at 170 DEG C. | 05-24-2012 |
20120139100 | LAMINATED TRANSFERABLE INTERCONNECT FOR MICROELECTRONIC PACKAGE - A package for a plurality of semiconductor devices having: an electrical interconnect structure, comprising: an electrical interconnect structure; and an active device structure, comprising the plurality of semiconductor devices on an active device substrate. The electrical interconnect structure is bonded to the active device structure and the electrical interconnect structure provides electrical interconnection among the semiconductor devices. | 06-07-2012 |
20120139101 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device having a multilayer wiring structure, in which a dummy pattern is formed in a wiring void with favorable manufacturing efficiency. In a semiconductor device having a multilayer wiring structure, dummy pattern ( | 06-07-2012 |
20120153456 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device is manufactured by etching a semiconductor substrate including an active region, forming a bit line contact hole from which the active region is protruded, forming a first spacer exposing a top of the active region at each of an inner wall and a bottom of the bit line contact hole, forming a bit line contact plug and a bit line over the exposed active region, and forming a second spacer over the semiconductor substrate including not only the bit line contact plug but also the bit line. | 06-21-2012 |
20120153457 | SEMICONDUCTOR PACKAGE MANUFACTURING METHOD AND SEMICONDUCTOR PACKAGE - According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip. | 06-21-2012 |
20120161310 | Trap Rich Layer for Semiconductor Devices - An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer. | 06-28-2012 |
20120161311 | WIRING BOARD AND SEMICONDUCTOR PACKAGE - A wiring board includes a stacked body having a plurality of insulating layers and a plurality of wiring layers which are alternately stacked, and a solder-resist layer being formed on one side of the stacked body and covering the wiring layer exposed to the one side of the stacked body. The insulating layer is exposed to the other side of the stacked body. The solder-resist layer is in a transparent or semitransparent light yellow color. | 06-28-2012 |
20120181684 | Semiconductor Structure and Method for Manufacturing the Same - A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer. | 07-19-2012 |
20120181685 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device wherein the adhesion of resin to a substrate is improved at a low cost. A semiconductor element and one or two substrates opposing one or both of the surfaces of the semiconductor element are sealed by a resin, a resin bonding coat which is formed by spraying a metal powder by a cold spray method is formed on one or both of the substrates, and recess portions which are widened from a film surface in a depth direction are formed on the resin bonding coat. | 07-19-2012 |
20120187557 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein. | 07-26-2012 |
20120193777 | INTEGRATED CIRCUIT FABRICATION - A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width. | 08-02-2012 |
20120199965 | Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant. | 08-09-2012 |
20120205793 | SEED LAYER PASSIVATION - A method of processing a microfeature workpiece generally includes depositing a first conducting layer, at least partially reducing oxides on the first conducting layer to provide a reduced first conducting layer, and exposing the reduced first conducting layer to a substantially oxygen-free environment to provide a passivated first conducting layer. A microfeature workpiece generally includes a first conducting layer, a monolayer directly on the first conducting layer, and a second conducting layer. | 08-16-2012 |
20120211879 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer. | 08-23-2012 |
20120217631 | INTEGRATED CIRCUIT DEVICES INCLUDING AIR SPACERS SEPARATING CONDUCTIVE STRUCTURES AND CONTACT PLUGS AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes first and second conductive structures spaced apart from one another on a substrate along a first direction. The first and second conductive structures extend in a second direction substantially perpendicular to the first direction. A contact plug is interposed between the first and second conductive structures and is separated therefrom along the first direction by respective air gaps on opposite sides of the contact plug. The air gaps define first and second air spacers that electrically insulate the contact plug from the first and second conductive structures, respectively. An upper insulation layer covers the first and second air spacers and the first and second conductive structures. The air spacers may sufficiently reduce the loading capacitance between the conductive structures. Related fabrication methods are also discussed. | 08-30-2012 |
20120223424 | SEMICONDUCTOR COMPONENT AND PRODUCTION METHOD - Semiconductor component and method for production of a semiconductor component. The invention relates to a semiconductor component having a semiconductor chip, which is arranged on a substrate, in one embodiment on a chip carrier, and an encapsulation material, which at least partially surrounds the semiconductor chip. The chip carrier is at least partly provided with a layer of polymer foam. | 09-06-2012 |
20120228758 | ELECTRON BEAM INDUCED DEPOSITION OF INTERFACE TO CARBON NANOTUBE - A system and method are provided for fabricating a low electric resistance ohmic contact, or interface, between a Carbon Nanotube (CNT) and a desired node on a substrate. In one embodiment, the CNT is a Multiwalled, or Multiwall, Carbon Nanotube (MWCNT), and the interface provides a low electric resistance ohmic contact between all conduction shells, or at least a majority of conduction shells, of the MWCNT and the desired node on the substrate. In one embodiment, a Focused Electron Beam Chemical Vapor Deposition (FEB-CVD) process is used to deposit an interface material near an exposed end of the MWCNT in such a manner that surface diffusion of precursor molecules used in the FEB-CVD process induces lateral spread of the deposited interface material into the exposed end of the MWCNT, thereby providing a contact to all conduction shells, or at least a majority of the conduction shells, of the MWCNT. | 09-13-2012 |
20120235295 | BARRIER-METAL-FREE COPPER DAMASCENE TECHNOLOGY USING ENHANCED REFLOW - A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor. | 09-20-2012 |
20120248597 | SEMICONDUCTOR DEVICE WITH STOP LAYERS AND FABRICATION METHOD USING CERIA SLURRY - The present invention provides a method of fabricating a semiconductor device including forming stop layers ( | 10-04-2012 |
20120256309 | Integrated Circuit Having Pitch Reduced Patterns Relative To Photolithography Features - An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography. | 10-11-2012 |
20120267774 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices. | 10-25-2012 |
20120267775 | System and Method to Manufacture an Implantable Electrode - The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason. | 10-25-2012 |
20120286415 | METHOD OF PRODUCING SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE - In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole | 11-15-2012 |
20120292758 | SEMICONDUCTOR ELEMENT AND ELECTRONIC APPARATUS - A semiconductor element including an organic semiconductor layer and a layer disposed on the upper surface of the organic semiconductor layer, wherein the outline of the layer is inside the outline of the organic semiconductor layer. | 11-22-2012 |
20120306068 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device is manufactured by forming a first dielectric film on a substrate, forming an aperture in the first dielectric film, mounting a semiconductor chip in the aperture, forming a second dielectric film on the first dielectric film and the semiconductor chip, and forming an interconnection wiring structure on the second dielectric film. The second dielectric film secures the semiconductor chip without the need to etch the substrate or use an adhesive die attachment film. | 12-06-2012 |
20120306069 | ELECTRONIC MODULE - An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 μm. | 12-06-2012 |
20120313236 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a connection electrode formed on the semiconductor element, and alignment marks formed on the semiconductor element. At least one of the alignment marks is made of a magnetic material. | 12-13-2012 |
20120313237 | BONDED SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING SAME - Embodiments of the invention include methods and structures for fabricating a semiconductor structure, and, particularly for improving the planarity of a bonded semiconductor structure comprising a processed semiconductor structure and a semiconductor structure. | 12-13-2012 |
20120319268 | CONDUCTIVE CONNECTION SHEET, METHOD FOR CONNECTING TERMINALS, METHOD FOR FORMING CONNECTION TERMINAL, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A conductive connecting sheet ( | 12-20-2012 |
20130001766 | PROCESSING METHOD AND PROCESSING DEVICE OF SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER - According to one embodiment, a substrate processing method is disclosed. The above method includes: grinding an outer edge portion on a back surface of a semiconductor wafer with a semiconductor element formed on its front surface with a first grindstone or blade to thereby form an annular groove; grinding a projecting portion on an inner side of the groove with a second grindstone to thereby form a recessed portion integrally with the groove on the back surface of the semiconductor wafer; and grinding a bottom surface of the recessed portion including a ground surface made by the second grindstone with a third grindstone. | 01-03-2013 |
20130001767 | PACKAGE AND METHOD FOR MANUFACTURING PACKAGE - A method for manufacturing a package, includes preparing a substrate having a first surface on which a connecting pad is formed, mounting a sacrificing material on the connecting pad, forming a package portion covering the first surface of the substrate, exposing the sacrificing material from a surface of the package portion, and removing the exposed sacrificing material from the side of the surface of the package portion, and forming an opening portion in the package portion on the connecting pad. | 01-03-2013 |
20130001768 | METHOD OF MANUFACTURING AN ELECTRONIC SYSTEM - A method of manufacturing an electronic system. One embodiment provides a semiconductor chip having a first main face and a second main face opposite to the first main face. A mask is applied to the first main face of the semiconductor chip. A compound is applied to the first main face of the semiconductor chip. The compound includes electronically conductive particles. The semiconductor chip is coupled to a carrier with the compound facing the carrier. | 01-03-2013 |
20130009302 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device ( | 01-10-2013 |
20130026617 | METHODS OF FORMING A METAL SILICIDE REGION IN AN INTEGRATED CIRCUIT - Methods of forming a metal silicide region in an integrated circuit are provided herein. In some embodiments, a method of forming a metal silicide region in an integrated circuit includes forming a silicide-resistive region in a first region of a substrate, the substrate having the first region and a second region, wherein a mask layer is deposited atop the substrate and patterned to expose the first region; removing the mask layer after the silicide-resistive region is formed in the first region of the substrate; depositing a metal-containing layer on a first surface of the first region and a second surface of the second region; and annealing the deposited metal-containing layer to form a first metal silicide region in the second region. | 01-31-2013 |
20130062753 | C-RICH CARBON BORON NITRIDE DIELECTRIC FILMS FOR USE IN ELECTRONIC DEVICES - A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of C | 03-14-2013 |
20130062754 | WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE - A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a rectangular plane shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a rectangular plane shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode. | 03-14-2013 |
20130069219 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and configured to seal the target circuit surface and the side surface, at least one wiring layer formed on the first surface of the first sealing insulating layer, at least one insulating layer formed on the at least one wiring layer, a second semiconductor chip mounted on the at least one insulating layer, and a second sealing insulating layer formed on the at least one insulating layer and configured to seal the second semiconductor chip. | 03-21-2013 |
20130069220 | Method of Forming Contacts for a Memory Device - The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask. | 03-21-2013 |
20130082378 | RESIN SEALING METHOD OF SEMICONDUCTOR DEVICE - A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin. | 04-04-2013 |
20130105965 | CHIP | 05-02-2013 |
20130113091 | METHOD OF PACKAGING SEMICONDUCTOR DIE - A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure. | 05-09-2013 |
20130113092 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF - A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure. | 05-09-2013 |
20130119531 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method for manufacturing a semiconductor device includes: forming an underlayer film that contains atoms selected from the group consisting of aluminum, boron and alkaline earth metal; and forming a silicon oxide film on the underlayer film by a CVD method or an ALD method by use of a silicon source containing at least one of an ethoxy group, a halogen group, an alkyl group and an amino group, or a silicon source of a siloxane system. | 05-16-2013 |
20130127038 | SEMICONDUCTOR DEVICE BONDED BY AN ANISOTROPIC CONDUCTIVE FILM - A semiconductor device bonded by an anisotropic conductive film, the anisotropic conductive film including a conductive adhesive layer and an insulating adhesive layer stacked thereon, an amount of reactive monomers in the conductive adhesive layer being higher than an amount of reactive monomers in the insulating adhesive layer. | 05-23-2013 |
20130134576 | SEMICONDUCTOR APPARATUS, SEMICONDUCTOR-APPARATUS MANUFACTURING METHOD AND ELECTRONIC EQUIPMENT - A method for manufacturing the semiconductor apparatus includes an anchor process of forming a barrier metal film and carrying out physical etching making use of sputter gas. The anchor process is carried out at the same time on a wire connected to the lower portion of a first aperture serving as a penetration connection hole and a wire connected to the lower portion of a second aperture serving as a connection hole having an aspect ratio different from the aspect ratio of the penetration connection hole. The first and second apertures are apertures created on a semiconductor substrate obtained by bonding first and second semiconductor substrates to each other. The present technology can be applied to the semiconductor apparatus such as a solid-state imaging apparatus. | 05-30-2013 |
20130154086 | Exposing Connectors in Packages Through Selective Treatment - A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed. | 06-20-2013 |
20130154087 | METHOD FOR FORMING INTERCONNECTION PATTERN AND SEMICONDUCTOR DEVICE - According to one embodiment, a method for forming an interconnection pattern includes forming an insulating pattern, forming a self-assembled film, and forming a conductive layer. The insulating pattern has a side surface on a major surface of a matrix. The self-assembled film has an affinity with a material of the insulating pattern on the side surface of the insulating pattern. The forming the conductive layer includes depositing a conductive material on a side surface of the self-assembled film. | 06-20-2013 |
20130161809 | SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE DEVICE, AND MANUFACTURING METHOD OF SUBSTRATE STRUCTURE - A substrate structure, a semiconductor package device and a manufacturing method of substrate structure are provided. The substrate structure comprises a conductive structure comprising a first metal layer, a second metal layer and a third metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. Each of the second metal layer and the third metal layer has a first surface and a second surface opposite to the first surface. The first surface of the third metal layer is connected to the second surface of the second metal layer. The surface area of the first surface of the third metal layer is larger than that of the second surface of the second metal layer. | 06-27-2013 |
20130168847 | ANISOTROPIC CONDUCTIVE FILM AND ELECTRONIC DEVICE INCLUDING THE SAME - An electronic device includes an anisotropic conductive film as a connection material, the anisotropic conductive film being formed from an anisotropic conductive film-forming composition. The anisotropic conductive film-forming composition includes a polycyclic aromatic ring-containing epoxy resin, a fluorene epoxy resin, nano silica and conductive particles. | 07-04-2013 |
20130175680 | DIELECTRIC MATERIAL WITH HIGH MECHANICAL STRENGTH - A multiphase ultra low k dielectric process is described incorporating a first precursor comprising at least one of carbosilane and alkoxycarbosilane molecules containing the group Si—(CH | 07-11-2013 |
20130181337 | Power Routing with Integrated Decoupling Capacitance - An integrated circuit chip is disclosed having a semiconductor substrate and a plurality of conduction layers (metalz, metalz+1), disposed on the semiconductor substrate and separated by dielectric layers, for distribution of power and electrical signals on the chip. The integrated circuit chip comprises a power-supply distribution network ( | 07-18-2013 |
20130187264 | LOW OHMIC CONTACTS - A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth D | 07-25-2013 |
20130221515 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device including a first region and a second region contacting the first region along a boundary line, includes forming a pattern having an on-boundary-line line portion with a width defined by a first line which is arranged in the first region and is parallel to the boundary line, and a second line which is arranged in the second region and is parallel to the boundary line. The forming the pattern includes independently performing, for a photoresist applied on a substrate, first exposure for defining the first line, and second exposure for defining the second line, and developing the photoresist having undergone the individually performing the first exposure and the second exposure. | 08-29-2013 |
20130228915 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs. | 09-05-2013 |
20130234314 | FLEXIBLE MICRO-SYSTEM AND FABRICATION METHOD THEREOF - A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems. | 09-12-2013 |
20130241048 | Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers - A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture. | 09-19-2013 |
20130249075 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer. | 09-26-2013 |
20130270692 | Method for Creating Semiconductor Junctions with Reduced Contact Resistance - Embodiments of the invention relate generally to creating semiconductor junctions with reduced contact resistance. In one embodiment, the invention provides a method of forming a composition of material, the method comprising: providing at least two populations of semiconducting materials; layering the at least two populations of semiconducting materials to form at least two layers; and consolidating the at least two populations of semiconducting materials, wherein the consolidating creates an electrical connection between the at least two layers. | 10-17-2013 |
20130277822 | INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS AND THEIR FORMATION - An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive overpass over and coupled to the first and second conductors and passing over the dielectric. The second conductor would be floating but for its coupling to the conductive underpass or the conductive overpass. In other embodiments, another dielectric might be included that would electrically isolate the second conductor but for its coupling to the conductive underpass or the conductive overpass. | 10-24-2013 |
20130277823 | Split Loop Cut Pattern For Spacer Process - A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines. | 10-24-2013 |
20130277824 | Manufacturing Method for Semiconductor Device and Semiconductor Device - In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer. | 10-24-2013 |
20130277825 | Method for Preventing Corrosion of Copper-Aluminum Intermetallic Compounds - The packaging of an electric contact including a semiconductor chip ( | 10-24-2013 |
20130299964 | METHOD FOR FORMING A FINE PATTERN USING ISOTROPIC ETCHING - A method for forming a fine pattern using isotropic etching, includes the steps of forming an etching layer on a semiconductor substrate, and coating a photoresist layer on the etching layer, performing a lithography process with respect to the etching layer coated with the photoresist layer, and performing a first isotropic etching process with respect to the etching layer including a photoresist pattern formed through the lithography process, depositing a passivation layer on the etching layer including the photoresist pattern, and performing a second isotropic etching process with respect to the passivation layer. The second isotropic etching process is directly performed without removing the predetermined portion of the passivation layer. | 11-14-2013 |
20130307137 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer. | 11-21-2013 |
20130307138 | DESKEWED MULTI-DIE PACKAGES - A microelectronic package may have a plurality of terminals disposed at a face thereof which are configured for connection to at least one external component. e.g., a circuit panel. First and second microelectronic elements can be affixed with packaging structure therein. A first electrical connection can extend from a respective terminal of the package to a corresponding contact on the first microelectronic element, and a second electrical connection can extend from the respective terminal to a corresponding contact on the second microelectronic element, the first and second connections being configured such that a respective signal carried by the first and second connections in each group is subject to propagation delay of the same duration between the respective terminal and each of the corresponding contacts coupled thereto. | 11-21-2013 |
20130320519 | Semiconductor Device and Method of Backgrinding and Singulation of Semiconductor Wafer while Reducing Kerf Shifting and Protecting Wafer Surfaces - A semiconductor device has a semiconductor wafer with an interconnect structure formed over a first surface of the wafer. A trench is formed in a non-active area of the semiconductor wafer from the first surface partially through the semiconductor wafer. A protective coating is formed over the first surface and into the trench. A lamination tape is applied over the protective coating. A portion of a second surface of the semiconductor wafer is removed by backgrinding or wafer thinning to expose the protecting coating in the trench. A die attach film is applied over the second surface of the semiconductor wafer. A cut or modified region is formed in the die attach film under the trench using a laser. The semiconductor wafer is expanded to separate the cut or modified region of the die attach film and singulate the semiconductor wafer. | 12-05-2013 |
20130320520 | CHEMICALLY ALTERED CARBOSILANES FOR PORE SEALING APPLICATIONS - A method including forming a dielectric material including a surface porosity on a circuit substrate including a plurality of devices; chemically modifying a portion of the surface of the dielectric material with a first reactant; reacting the chemically modified portion of the surface with a molecule that, once reacted, will be thermally stable; and forming a film including the molecule. An apparatus including a circuit substrate including a plurality of devices; a plurality of interconnect lines disposed in a plurality of layers coupled to the plurality of devices; and a plurality of dielectric layers disposed between the plurality of interconnect lines, wherein at least one of the dielectric layers comprises a porous material surface relative to the plurality of devices and the surface comprises a pore obstructing material. | 12-05-2013 |
20130334678 | DEVICE FOR SUPPORTING A SUBSTRATE, AS WELL AS METHODS FOR MANUFACTURING AND USING SUCH A DEVICE | 12-19-2013 |
20130334679 | METAL CONSERVATION WITH STRIPPER SOLUTIONS CONTAINING RESORCINOL - Resist stripping agents useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits and/or liquid crystals with reduced metal and metal alloy etch rates (particularly copper etch rates and TiW etch rates), are provided with methods for their use. The preferred stripping agents contain low concentrations of resorcinol or a resorcinol derivative, with or without an added copper salt, and with or without an added amine to improve solubility of the copper salt. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods. | 12-19-2013 |
20130341783 | INTERPOSER WITH IDENTIFICATION SYSTEM - Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the identification information. | 12-26-2013 |
20140015121 | WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF - A wiring substrate includes: a core substrate made of glass and having: a first surface; a second surface opposite to the first surface; and a side surface between the first surface and the second surface; and an insulating layer and a wiring layer, which are formed on at least one of the first surface and the second surface of the core substrate. A plurality of concave portions are formed in the side surface of the core substrate to extend from the first surface to the second surface, and a resin is filled in the respective concave portions. | 01-16-2014 |
20140035124 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - An semiconductor device includes a semiconductor substrate; a metal layer arranged above the semiconductor substrate; a first passivation film that contacts at least a portion of one side surface of the metal layer; and a second passivation film that is arranged extending from the first passivation film to the metal layer, and contacts an upper surface of the first passivation film, and contacts at least a portion of an upper surface of the metal layer. | 02-06-2014 |
20140042612 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having a second width. The second width is different than the first width. The method includes forming a second conductive structure in a second metallization layer proximate the first metallization layer, and coupling a portion of the second conductive structure to the first portion of the first conductive structure. | 02-13-2014 |
20140042613 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided with: a semiconductor substrate; an insulation film formed above the semiconductor substrate; a pad formed on the insulation film, the pad including a trace; a first passivation film formed on the insulation film, located adjacent the pad, and separated from the pad; and a second passivation film formed on the first passivation film and the pad, the second passivation film covering the trace, and the second passivation film including an opening which exposes a part of the pad. | 02-13-2014 |
20140084450 | PROCESSES FOR MULTI-LAYER DEVICES UTILIZING LAYER TRANSFER - A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices are chemically attached to a receiving device made of a second semiconductor material different than the first semiconductor material, the receiving device having a receiving substrate attached to a surface of the receiving device opposite the plurality of devices. The release layer is etched to release the donor substrate from the plurality of devices. A second dielectric layer is applied over the plurality of devices and the receiving device to mechanically attach the plurality of devices to the receiving device. | 03-27-2014 |
20140084451 | Split Loop Cut Pattern For Spacer Process - A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines. | 03-27-2014 |
20140084452 | ELEMENT MOUNTING BOARD AND SEMICONDUCTOR MODULE - Prepared in advance is a substrate formed of metallic material where slits are formed between mounting regions. Oxide films are generated all over the substrate including end faces of the substrate. Exposed are only lateral faces corresponding to the cross sections cut when tie bars are cut. This structure and the fabrication method minimize the area of cutting faces in the metallic material. | 03-27-2014 |
20140091454 | Semiconductor Device and Method of Forming Supporting Layer Over Semiconductor Die in Thin Fan-Out Wafer Level Chip Scale Package - A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer. | 04-03-2014 |
20140091455 | Semiconductor Device and Method of Using a Standardized Carrier in Semiconductor Packaging - A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die. | 04-03-2014 |
20140103519 | Power Semiconductor Module - A power semiconductor module comprising a substrate. The power semiconductor module has first and second DC voltage load current connection elements and first and second power semiconductor components. The first and second power semiconductor components are arranged along a lateral first direction of the substrate. The power semiconductor module has a foil composite having a first metallic foil layer and a structured second metallic foil layer and an electrically insulating foil layer arranged between the first and second metallic foil layers. The first power semiconductor component and the second power semiconductor component are electrically conductively connected to the foil composite and to the substrate. The first and second power semiconductor components are arranged on a common side in relation to the first and second DC voltage load current connection elements. The invention provides a power semiconductor module having a particularly low-inductance construction. | 04-17-2014 |
20140117529 | Semiconductor Constructions, Patterning Methods, and Methods of Forming Electrically Conductive Lines - Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another. | 05-01-2014 |
20140117530 | Semiconductor Devices and Methods for Manufacturing Semiconductor Devices - A device includes a semiconductor material having a first main surface, an opposite surface opposite to the first main surface and a side surface extending from the first main surface to the opposite surface. The device further includes a first electrical contact element arranged on the first main surface of the semiconductor material and a glass material. The glass material includes a second main surface wherein the glass material contacts the side surface of the semiconductor material and wherein the first main surface of the semiconductor material and the second main surface of the glass material are arranged in a common plane. | 05-01-2014 |
20140117531 | SEMICONDUCTOR DEVICE WITH ENCAPSULANT - Described are techniques related to semiconductor devices that make use of encapsulant. In one implementation, a semiconductor device may be manufactured to include at least an encapsulant that includes at least glass particles. | 05-01-2014 |
20140131852 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and the impact diffusion layer for diffusing the impact, force applied to the semiconductor integrated circuit per unit area is reduced, so that the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low modulus of elasticity and high breaking modulus. | 05-15-2014 |
20140131853 | ELECTRONIC COMPONENT, METHOD OF MANUFACTURING SAME, COMPOSITE MODULE INCLUDING ELECTRONIC COMPONENT, AND METHOD OF MANUFACTURING SAME - A method of manufacturing a composite module prevents a connection electrode electrically coupled to a functional element from separating from a first principal surface of an element substrate. A transmission filter element, a reception filter element, connection electrodes electrically coupled to the transmission filter element and the reception filter element, and an insulating layer surrounding the transmission filter element, the reception filter element, and the connection electrodes are disposed on a first principal surface of an element substrate. The insulating layer covers at least a portion of the surface of each of the connection electrodes. Because the portion of the surface of each of the connection electrodes in an exposed state is covered with the insulating layer, the connection electrodes electrically coupled to the transmission filter element and the reception filter element are prevented from separating from the first principal surface of the element substrate. | 05-15-2014 |
20140138813 | Method for Manufacturing an Electronic Component - A semiconductor wafer includes a first main face and a second main face opposite to the first main face and a number of semiconductor chip regions. The wafer is diced along dicing streets to separate the semiconductor chip regions from each other. At least one metal layer is formed on the first main face of each one of the semiconductor chip regions. | 05-22-2014 |
20140159227 | PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS - Fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines and depositing a protective cap on at least some of the one or more conductive lines. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer pitches, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. Alternatively, fabricating conductive lines in an integrated circuit includes patterning a layer of a transition metal to form the conductive lines, wherein the conductive lines have sub-eighty nanometer line widths, and depositing a protective cap on at least some of the conductive lines, wherein the protective cap has a thickness between approximately five and fifteen nanometers. | 06-12-2014 |
20140159228 | HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE - Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads. | 06-12-2014 |
20140159229 | SEMICONDUCTOR DEVICE CONNECTED BY ANISOTROPIC CONDUCTIVE FILM - A semiconductor device connected by an anisotropic conductive film, the film having a storage modulus of 100 MPa to 300 MPa at 40° C. after curing of the film, and a peak point of 80° C. to 90° C. in a DSC (Differential Scanning calorimeter) profile of the film. | 06-12-2014 |
20140159230 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element in the form of a flat plate that has opposed first and second surfaces, an insulating layer that covers control wiring located on the first surface side of the semiconductor element, a metal block that is bonded to the first surface side of the semiconductor element via a solder layer, and a protective film that is formed between the metal block and the insulating layer, the protective film having a hardness equal to or greater than a hardness of the metal block. When viewed from the first surface side, the protective film is formed in an area at least including a position where an edge portion of the metal block and the control wiring cross each other. | 06-12-2014 |
20140167249 | INTERCONNECT STRUCTURE AND FABRICATION METHOD - An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed therein. A porous dielectric layer can be formed on the substrate. A surface treatment can be performed to the porous dielectric layer to form an isolation layer on the porous dielectric layer to prevent moisture absorption of the porous dielectric layer. An interconnect can be formed at least through the isolation layer and the porous dielectric layer to provide electrical connection to the semiconductor device disposed in the substrate. | 06-19-2014 |
20140167250 | SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming the same are disclosed, which forms a low-dielectric-constant oxide film only at a peripheral part of a bit line conductive material, resulting in reduction in parasitic capacitance of the bit line. The semiconductor device includes a bit line formed over a semiconductor substrate, a first spacer formed over sidewalls of the bit line, and a second spacer formed over sidewalls of the first spacer, configured to have a dielectric constant lower than that of the first spacer. | 06-19-2014 |
20140183720 | METHODS OF MANUFACTURING INTEGRATED CIRCUITS HAVING A COMPRESSIVE NITRIDE LAYER - Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer. | 07-03-2014 |
20140183721 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is provided, which includes the steps of: providing a carrier having an adhesive layer and at least a semiconductor element having a protection layer; disposing the semiconductor element on the adhesive layer of the carrier through the protection layer; forming an encapsulant on the adhesive layer of the carrier for encapsulating the semiconductor element; removing the carrier and the adhesive layer to expose the protection layer from the encapsulant; and removing the protection layer to expose the semiconductor element from the encapsulant. Since the semiconductor element is protected by the protection layer against damage during the process of removing the adhesive layer, the product yield is improved. | 07-03-2014 |
20140183722 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - This semiconductor device, which has electronic components provided in a cavity of a module having a cavity structure, can be prevented from being increased in size. In the device, the module having the cavity structure is provided with a plurality of components, for instance, an IC ( | 07-03-2014 |
20140191388 | 3D STACKING SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A 3D stacking semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. N layers of stacking structures are provided. Each stacking structure includes a conductive layer and an insulating layer. A first photoresister layer is provided. The stacking structures are etched P−1 times by using the first photoresister layer as a mask. A second photoresister layer is provided. The stacking structures are etched Q−1 times by using the second photoresister layer as a mask. The first photoresister layer is trimmed along a first direction. The second photoresister layer is trimmed along a second direction. The first direction is different from the second direction. A plurality of contact points are arranged along the first and the second directions in a matrix. The included angle between the first direction and the second direction is an acute angle. | 07-10-2014 |
20140191389 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers. | 07-10-2014 |
20140203427 | LOW ALPHA PARTICLE EMISSION ELECTRICALLY-CONDUCTIVE COATING - An electrically conductive paste providing low alpha particle emission is provided. A resin and conductive particles are mixed, and a curing agent is added. A solvent is subsequently added. The electrically conductive paste including a resin compound is formed by mixing the mixture in a high shear mixer. The electrically conductive paste can be applied to a surface of an article to form a coating, or can be molded into an article. The solvent is evaporated, and the electrically conductive paste is cured to provide a graphite-containing resin compound. The graphite-containing resin compound is electrically conductive, and provides low alpha particle emission at a level suitable for a low alpha particle emissivity coating. | 07-24-2014 |
20140210073 | CONDUCTIVE PASTE, ELECTRODE FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a conductive paste, an electrode for a semiconductor device manufactured by using the conductive paste, a semiconductor device and a method for manufacturing the semiconductor device. The conductive paste includes conductive powder made of a plurality of conductive particles and silver powder made of a plurality of silver particles. The conductive particles includes a base material made of ceramics and a conductive layer configured to cover at least a part of an outer surface of the base material. The ratio of the mass of the conductive layer relative to the total mass of the conductive particles is 10% or more by mass, and the ratio of the mass of the conductive powder relative to the total mass of the conductive powder and the silver powder is 25% or less by mass. | 07-31-2014 |
20140217577 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A device includes a semiconductor chip including a first main face and a second main face, the second main face being the backside of the semiconductor chip. The second main face includes a first region and a second region, the second region being a peripheral region of the second main face. The device further includes a dielectric material arranged over the second region and an electrically conductive material arranged over the first region. | 08-07-2014 |
20140231983 | FILM ADHESIVE, DICING TAPE WITH FILM ADHESIVE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - The present invention provides a film adhesive that can prevent a thermal effect to a semiconductor wafer and that can suppress warping of the semiconductor wafer; a dicing tape with a film adhesive; and a method of manufacturing a semiconductor device. | 08-21-2014 |
20140264822 | THERMOSETTING RESIN COMPOSITIONS WITH LOW COEFFICIENT OF THERMAL EXPANSION - Thermosetting resin compositions with low coefficient of thermal expansion are provided herein. | 09-18-2014 |
20140264823 | Systems and Methods for Fabricating Semiconductor Devices Having Larger Die Dimensions - A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device. A plurality of masks for a chip layout are obtained. The plurality of masks are exposed to encompass a chip area of the device using at least one reticle repeatedly. The at least one reticle is of a set of reticles. The chip area has a resultant dimension greater than a dimension of the at least one reticle. A developer is used to remove soluble portions of the photosensitive material forming a resist pattern in the chip area. level shifter system | 09-18-2014 |
20140264824 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface. | 09-18-2014 |
20140264825 | Ultra-Low Resistivity Contacts - Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10 | 09-18-2014 |
20140264826 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device has a structure including a substrate, a first insulating film formed over a part of a principal plane of the substrate, a conductive portion formed over a surface of the first insulating film, and a second insulating film which covers the principal plane of the substrate, the first insulating film, and the conductive portion and whose moisture resistance is higher than moisture resistance of the first insulating film. The first insulating film is placed between the substrate and the conductive portion to prevent the generation of parasitic capacitance. The first insulating film is covered with the second insulating film whose moisture resistance is higher than the moisture resistance of the first insulating film. The second insulating film prevents the first insulating film from absorbing moisture. | 09-18-2014 |
20140312488 | METHOD OF MANUFACTURING WIRING BOARD UNIT, METHOD OF MANUFACTURING INSERTION BASE, WIRING BOARD UNIT, AND INSERTION BASE - A method of manufacturing a wiring board unit, the wiring board unit including a semiconductor package that includes a memory chip, a wiring board on which the semiconductor package is mounted, and an insertion base inserted between the wiring board and the semiconductor package, the method includes: forming a plurality of connection portion groups in a base material, the connection portion groups each including a plurality of connection portions that each electrically connect a board-side pad of the wiring board and an external terminal of the semiconductor package to each other; forming the insertion base such that resistances of the connection portions included in the connection portion groups are adjusted in accordance with types of target memory chips; and connecting the external terminals and the board-side pads to one another by using the connection portion group selected in accordance with the type of the memory chip. | 10-23-2014 |
20140319675 | SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed. | 10-30-2014 |
20140319676 | ELECTRONIC COMPONENT MANUFACTURING METHOD AND ELECTRODE STRUCTURE - It is an object of the present invention to provide an electronic component manufacturing method, capable of suppressing reduction in a trench opening and suppressing diffusion of a metal film embedded in a trench. An embodiment of the present invention is an electronic component manufacturing method, including the steps of: forming a first electrode constituting layer (e.g., a TiAl film) in a recess (e.g., a trench) formed in a workpiece; forming an ultrathin barrier layer (e.g., a TiAlN film) by forming a nitride layer by plasma-nitriding a surface of the first electrode constituting layer; and forming a second electrode constituting layer (e.g., an Al wiring layer) on the ultrathin barrier layer. | 10-30-2014 |
20140346662 | FORMING MODIFIED CELL ARCHITECTURE FOR FINFET TECHNOLOGY AND RESULTING DEVICE - Methods for accommodating a non-integer multiple of the M2 pitch for the cell height of a semiconductor cell and the resulting devices are disclosed. Embodiments may include forming a cell within an integrated circuit (IC) with a height of a first integer and a remainder times a track pitch of a metal track layer, and forming power rails within the metal track layer at boundaries of the cell accommodating for the remainder. | 11-27-2014 |
20140353818 | Power module comprising two substrates and method of manufacturing the same - A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer | 12-04-2014 |
20150014842 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - A manufacturing method for a semiconductor device in which connection portions of a semiconductor chip are electrically connected to connection portions of a wiring circuit substrate or a semiconductor device in which connection portions of a plurality of semiconductor chips are electrically connected to each other, the method comprising a step of encapsulating at least part of the connection portions with an adhesive for a semiconductor containing a compound having a group represented by the following formula (1-1) or (1-2): | 01-15-2015 |
20150021757 | Systems and Methods for Reducing Contact Resistivity of Semiconductor Devices - Systems and methods are provided for reducing a contact resistivity associated with a semiconductor device structure. A substrate including a semiconductor region is provided. One or more dielectric layers are formed on the semiconductor region, the one or more dielectric layers including an element. A gaseous material is applied on the one or more dielectric layers to change a concentration of the element in the one or more dielectric layers. A contact layer is formed on the one or more dielectric layers to generate a semiconductor device structure. The semiconductor device structure includes the contact layer, the one or more dielectric layers, and the semiconductor region. A contact resistivity associated with the semiconductor device structure is reduced by changing the concentration of the element in the one or more dielectric layers. | 01-22-2015 |
20150028469 | SEMICONDUCTOR ASSEMBLY AND METHOD OF MANUFACTURE - A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented. | 01-29-2015 |
20150041969 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed. | 02-12-2015 |
20150041970 | SEMICONDUCTOR DEVICE - A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern. | 02-12-2015 |
20150048495 | ADHESIVE FOR SEMICONDUCTOR, FLUXING AGENT, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - An adhesive for a semiconductor, comprising an epoxy resin, a curing agent, and a compound having a group represented by the following formula (1): | 02-19-2015 |
20150061113 | Semiconductor Dies Having Opposing Sides with Different Reflectivity - A method of processing semiconductor dies is provided. Each semiconductor die has a first side with one or more terminals, a second side opposite the first side and sidewalls extending between the first and the second sides. The semiconductor dies are processed by placing the semiconductor dies on a support substrate so that the first side of each semiconductor die faces the support substrate and the second side faces away from the support substrate. A coating is applied to the semiconductor dies placed on the support substrate. The coating has a lower reflectivity than the first side of the semiconductor dies. The coating covers the second side and at least a region of the sidewalls nearest the second side of each semiconductor die. The semiconductor dies are removed from the support substrate after applying the coating for further processing as loose dies such as taping. | 03-05-2015 |
20150061114 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip and a joined member. The semiconductor chip has a semiconductor substrate, a first electrode, and a second electrode. The first electrode is arranged on a first surface of the semiconductor substrate. The second electrode is arranged on a second surface of the semiconductor substrate. The first electrode is joined to the joined member via a joint material. A tensile force in a surface direction of the first surface that is applied to the first surface of the semiconductor substrate from the first electrode due to thermal expansion of the first electrode at a melting temperature of the joint material is at least equal to a tensile force in the surface direction that is applied to the second surface of the semiconductor substrate from the second electrode due to thermal expansion of the second electrode at the melting temperature. | 03-05-2015 |
20150069600 | Embedded Silver Nanomaterials into Die Backside to Enhance Package Performance and Reliability - A method and apparatus for enhancing the electrical and thermal performance of semiconductor packages effectively, especially for laminated packages, where sinterable materials cannot be used. The concept of this invention is to embed silver or silver-coated nanomaterials, which can be nanoparticles, nanoflakes, nanowires etc., into die backside to improve the interface between die and die attach materials, thus enhancing electrical and thermal performance through sintering and enhancing reliability by improving adhesion. | 03-12-2015 |
20150069601 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device and a semiconductor device that is manufactured by the method. In the method of manufacturing a semiconductor device, a releasing sheet is disposed in close contact with a hole of an aluminum plate having the recessed hole, and a skeleton structure of a semiconductor device is put into the recessed hole. Then, liquid epoxy resin is poured into the recessed hole. After hardening, the epoxy resin body | 03-12-2015 |
20150084183 | INTEGRATED CIRCUITS WITH PROTECTED RESISTORS AND METHODS FOR FABRICATING THE SAME - Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided. | 03-26-2015 |
20150084184 | SEMICONDUCTOR DEVICE - A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern. | 03-26-2015 |
20150097282 | CHIP PACKAGES, CHIP ARRANGEMENTS, A CIRCUIT BOARD, AND METHODS FOR MANUFACTURING CHIP PACKAGES - A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material. | 04-09-2015 |
20150108633 | MECHANISMS FOR FORMING PROTECTION LAYER ON BACK SIDE OF WAFER - Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side. The semiconductor device structure also includes devices formed on the front side of the substrate and interconnect structures formed on the devices. The semiconductor device structure further includes a protection layer formed on the back side of the substrate, and the protection layer has a thickness over about 10 A. | 04-23-2015 |
20150123263 | TWO-STEP METHOD FOR JOINING A SEMICONDUCTOR TO A SUBSTRATE WITH CONNECTING MATERIAL BASED ON SILVER - The invention relates to a method for joining a semiconductor ( | 05-07-2015 |
20150137347 | ADHESIVE COMPOSITION AND SEMICONDUCTOR DEVICE USING SAME - An adhesive composition comprising silver particles containing silver atoms and zinc particles containing metallic zinc, wherein the silver atom content is 90 mass % or greater and the zinc atom content is from 0.01 mass % to 0.6 mass %, with respect to the total transition metal atoms in the solid portion of the adhesive composition. | 05-21-2015 |
20150137348 | ELECTRONIC DEVICE - In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer. | 05-21-2015 |
20150311182 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package may include an interposer; a first semiconductor chip disposed on a first surface of the interposer and at least one second semiconductor chip disposed at a predefined distance from the first semiconductor chip, a molding part filling spaces between the first semiconductor chip and the at least one second semiconductor chip and having a trench hole formed therein, and a thermal expansion buffer pattern filling the trench hole. | 10-29-2015 |
20150348877 | Contact Pad for Semiconductor Device - A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound. | 12-03-2015 |
20150348943 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first hybrid bonded device including a first device and a second device hybrid bonded face-to-face to the first device. The first device includes a first substrate having first bonding connectors and a first bonding layer disposed on a surface thereof. A second hybrid bonded device is bonded back-to-back to the first hybrid bonded device. The second hybrid bonded device includes a third device and a fourth device hybrid bonded face-to-face to the third device. The third device includes a second substrate having second bonding connectors and a second bonding layer disposed on a surface. The second bonding connectors of the third device are coupled to the first bonding connectors of the first device, and the second bonding layer of the third device is coupled to the first bonding layer of the first device. | 12-03-2015 |
20150357256 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die. | 12-10-2015 |
20150364394 | Method for Building Up a Fan-Out RDL Structure with Fine Pitch Line-Width and Line-Spacing - A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first insulating layer is formed over a first surface of the encapsulant and an active surface of the semiconductor die. A second insulating layer is formed over a second surface of the encapsulant opposite the first surface. A conductive layer is formed over the first insulating layer. The conductive layer includes a line-pitch or line-spacing of less than 5 μm. The active surface of the semiconductor die is recessed within the encapsulant. A third insulating layer is formed over the semiconductor die including a surface of the third insulating layer coplanar with a surface of the encapsulant. The second insulating layer is formed prior to forming the conductive layer. A trench is formed in the first insulating layer. The conductive layer is formed within the trench. | 12-17-2015 |
20150371898 | INTEGRATED CIRCUITS INCLUDING MODIFIED LINERS AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes contacting a liner that is disposed adjacent to a porous interlayer dielectric (ILD) layer of dielectric material with a selectively reactive gas at reaction conditions. A portion of the liner is reacted with the selectively reactive gas to form a converted expanded portion that is disposed between a remaining portion of the liner and the porous ILD layer. | 12-24-2015 |
20150371955 | Interconnect Structure and Method of Forming the Same - A structure includes a first metal line and a second metal line disposed on a first side of a substrate, and a dielectric structure separating the first metal line and the second metal line. The dielectric structure includes a first dielectric layer over the first side of the substrate, a second dielectric layer over the first dielectric layer and extending from the first metal line to the second metal line. The first dielectric layer has a first dielectric constant larger than or substantially equal to a second dielectric constant of the second dielectric layer. The dielectric structure further includes a third dielectric layer between the first dielectric layer and the first metal line, the third dielectric layer having a third dielectric constant larger than the first dielectric constant. | 12-24-2015 |
20150380309 | Metal-insulator-semiconductor (MIS) contact with controlled defect density - Metal-insulator-semiconductor (MIS) contacts for germanium and its alloys include insulator layers of oxygen-deficient metal oxide deposited by atomic layer deposition (ALD). The oxygen deficiency reduces the tunnel barrier resistance of the insulator layer while maintaining the layer's ability to prevent Fermi-level pinning at the metal/semiconductor interface. The oxygen deficiency is controlled by optimizing one or more ALD parameters such as shortened oxidant pulses, use of less-reactive oxidants such as water, heating the substrate during deposition, TMA “cleaning” of native oxide before deposition, and annealing after deposition. Secondary factors include reduced process-chamber pressure, cooled oxidant, and shortened pulses of the metal precursor. | 12-31-2015 |
20160002510 | DIENE/DIENOPHILE COUPLES AND THERMOSETTING RESIN COMPOSITIONS HAVING REWORKABILITY - Thermosetting resin compositions are provided that are useful for mounting onto a circuit board semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”) and the like (collectively, “subcomponents”), or semiconductor chips. Reaction products of the compositions are controllably reworkable when subjected to appropriate conditions. | 01-07-2016 |
20160005695 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit. | 01-07-2016 |
20160013285 | HIGH-FREQUENCY CONDUCTOR HAVING IMPROVED CONDUCTIVITY | 01-14-2016 |
20160043034 | DEVICE AND METHOD FOR MANUFACTURING A DEVICE - In various embodiments a method of forming a device is provided. The method includes forming a metal layer over a substrate and forming at least one barrier layer. The forming of the barrier layer includes depositing a solution comprising a metal complex over the substrate and at least partially decomposing of the ligand of the metal complex. | 02-11-2016 |
20160086894 | CONTROL OF WARPAGE USING ABF GC CAVITY FOR EMBEDDED DIE PACKAGE - Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material. | 03-24-2016 |
20160093547 | EPOXY RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE ENCAPSULATED USING THE SAME - An epoxy resin composition for encapsulating a semiconductor device and a semiconductor package, the composition including an epoxy resin; a polyorganosiloxane resin represented by Formula 3, below; a curing agent; a curing accelerator; and an inorganic filler: | 03-31-2016 |
20160111667 | LAYER-SELECTIVE LASER ABLATION PATTERNING - A method of fabricating an organic electronic device is provided. The organic electronic device has a structure including an upper conductive layer and an underlying layer immediately beneath said upper conducting layer and having at least one solution processable semiconducting layer. The upper conducting layer preferably has a thickness of between 10 nm and 200 nm. The method includes patterning said upper conductive layer of said structure by: laser ablating said upper conductive layer using a pulsed laser to remove regions of upper conductive layer from said underlying layer for said patterning; and wherein said laser ablating uses a single pulse of said laser to substantially completely remove a said region of said upper conductive layer to expose said underlying layer beneath. | 04-21-2016 |
20160118283 | ANODIZED METAL ON CARRIER WAFER - A method for processing a semiconductor wafer where an electrostatic layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be handled with machinery that uses an electrostatic chuck. The electrostatic layer may be manipulated to increase or decrease the conductivity, and may be removed to allow light to pass through the handling wafer. | 04-28-2016 |
20160155986 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME | 06-02-2016 |
20160163612 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to semiconductor packages and methods of manufacturing the same. In an embodiment, the semiconductor package includes a substrate, a semiconductor element, at least one connecting element, and an encapsulant. The semiconductor element is mounted to the substrate. The connecting element is disposed on the substrate and adjacent to the semiconductor element. The encapsulant covers at least a portion of the semiconductor element and at least a portion of the connecting element and defines at least one first groove surrounding the connecting element. | 06-09-2016 |
20190148127 | SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER FABRICATION METHOD | 05-16-2019 |