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Bump leads

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257734000 - COMBINED WITH ELECTRICAL CONTACT OR LEAD

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Class / Patent application numberDescriptionNumber of patent applications / Date published
257738000 Ball shaped 576
Entries
DocumentTitleDate
20130043584SEMICONDUCTOR DEVICES, PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES, PACKAGE STACK STRUCTURES, AND ELECTRONIC SYSTEMS HAVING FUNCTIONALLY ASYMMETRIC CONDUCTIVE ELEMENTS - A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit.02-21-2013
20130043583Dummy Flip Chip Bumps for Reducing Stress - A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.02-21-2013
20130043586METHOD FOR ENCAPSULATING ELECTRONIC COMPONENTS ON A WAFER - A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.02-21-2013
20130043585SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS - A semiconductor apparatus, including: a semiconductor component; a Cu stud bump that is formed on the semiconductor component; and a solder bump configured to electrically connect to the Cu stud bump.02-21-2013
20130069227Semiconductor Device and Method of Forming Protection and Support Structure for Conductive Interconnect Structure - A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.03-21-2013
20130026621METAL BUMP STRUCTURE - A semiconductor device comprises a substrate comprising a major surface and a plurality of metal bumps on the major surface. Each of the plurality of metal bumps comprises a metal via on the major surface and a metal pillar on the metal via having an overlay offset between the metal pillar and metal via. A first metal bump of the metal bumps has a first overlay offset and a second metal bump of the metal bumps farther than the first metal bump to a centroid of the substrate has a second overlay offset greater than the first overlay offset.01-31-2013
20130026629SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE UNIT, AND SEMICONDUCTOR DEVICE PRODUCTION METHOD - An example of a semiconductor device according to the present invention includes: a protective film (01-31-2013
20130026628Flip Chip Interconnection having Narrow Interconnection Sites on the Substrate - A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.01-31-2013
20130026624COAXIAL SOLDER BUMP SUPPORT STRUCTURE - A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.01-31-2013
20130026625FLIP-CHIP SEMICONDUCTOR DEVICE HAVING ANISOTROPIC ELECTRICAL INTERCONNECTION AND SUBSTRATE UTILIZED FOR THE PACKAGE - Disclosed is a flip-chip semiconductor device having isotropic electrical interconnection, primarily comprising a chip and a substrate. The chip has at least a first bump and a plurality of second bumps. The substrate has a plurality of bump pads disposed on the top surface and an isotropic connecting mechanism disposed inside the substrate consisting of a plurality of terminals electrically isolated from each other and a flexible vertical pad protruded from the top surface, wherein the disposition locations of the terminals circle around the flexible vertical pad as a disposition center. When the second bumps of the chip are bonded onto the corresponding bump pads, the first bump presses and bends the flexible vertical pad in a specific horizontal direction so that the flexible vertical pad selectively and electrically connect to a selected one of the terminals.01-31-2013
20130026623Semiconductor Devices, Packaging Methods and Structures - Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region.01-31-2013
20130026619BUMP STRUCTURES - The embodiments of bump and bump-on-trace (BOT) structures provide bumps with recess regions for reflowed solder to fill. The recess regions are placed in areas of the bumps where reflow solder is most likely to protrude. The recess regions reduce the risk of bump to trace shorting. As a result, yield can be improved.01-31-2013
20130026622BUMP STRUCTURES IN SEMICONDUCTOR DEVICE AND PACKAGING ASSEMBLY - A bump structure in a semiconductor device or a packing assembly includes an under-bump metallization (UBM) layer formed on a conductive pad of a semiconductor substrate. The UBM layer has a width greater than a width of the conductive pad.01-31-2013
20130026620SELF-ALIGNING CONDUCTIVE BUMP STRUCTURE AND METHOD OF MAKING THE SAME - The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body.01-31-2013
20130026618METHOD AND DEVICE FOR CIRCUIT ROUTING BY WAY OF UNDER-BUMP METALLIZATION - The present disclosure involves a semiconductor device. The semiconductor device includes a substrate that contains a plurality of electronic components. The semiconductor device includes an interconnect structure disposed over the substrate, the interconnect structure containing a plurality of interconnect layers. The semiconductor device includes a passivation layer disposed over the interconnect structure. The semiconductor device includes an Under-Bump Metallization (UBM) layer disposed over the passivation layer, the UBM layer containing a UBM pad and a plurality of UBM devices, the UBM devices including at least one of: a UBM trace that is electrically coupled to one of the electronic components through the interconnect structure, and a dummy UBM device. The semiconductor device includes a solder bump disposed on, and electrically coupled to, the UBM pad.01-31-2013
20090039505Thermally insulating bonding pad structure for solder reflow connection - A thermally insulating bonding pad for solder reflow is described. The bonding pad includes a structure. The structure forms the bonding pad. The bonding pad further includes an insulator formed on the structure. The insulator is configured to be interposed between the structure and a substrate of a component onto which said bonding pad is to be disposed. The bonding pad provides thermal insulation for said substrate when said bonding pad is subject to a solder reflow process being performed thereon.02-12-2009
20110180927ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, CIRCUIT BOARD MOUNTED WITH THE SAME, AND ELECTRONIC APPLIANCE COMPRISING THE CIRCUIT BOARD - An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device having a semiconductor chip with electrodes, a stress-relieving layer prepared on the semiconductor chip, a wire formed across the electrodes and the stress-relieving layer, and solder balls formed on the wire over the stress-relieving layer; and a bare chip as a second semiconductor device to be electrically connected to the first semiconductor device.07-28-2011
20130026626METHOD FOR FORMING BUMPS AND SUBSTRATE INCLUDING THE BUMPS - Disclosed herein are a method for forming bumps and a substrate including the bumps. The method includes: coating a solder resist on a substrate and electrodes formed on the substrate: performing laser etching treatment on the solder resist to form openings for forming bumps; printing a composition for forming bumps in the openings for forming bumps; and performing a reflowing process.01-31-2013
20110204510CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer.08-25-2011
20100052162SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device, includes a semiconductor substrate; and a solder bump part, which is formed on the semiconductor substrate and in which no grain boundary extends equal to or over ⅓ of a diameter dimension of said solder bump part from an outer circumferential surface between an end of a connection part with the semiconductor substrate and a lateral portion.03-04-2010
20130134583SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips.05-30-2013
20120168939CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.07-05-2012
20110186993SEMICONDUCTOR MODULE AND PORTABLE APPARATUS PROVIDED WITH SEMICONDUCTOR MODULE - A semiconductor element mounted on an insulating resin layer formed on a wiring layer is sealed by a sealing resin. On the wiring layer, a protruding electrode protruding to the side of the semiconductor element and a protruding section are integrally formed with the wiring layer, respectively. The protruding electrode is electrically connected to an element electrode of the semiconductor element by penetrating the insulating resin layer. The protruding section is arranged to surround the semiconductor element along the four sides of the semiconductor element, and is embedded in the sealing resin up to a position above a section where the protruding electrode and the element electrode are bonded.08-04-2011
20110186990PROTRUDING TSV TIPS FOR ENHANCED HEAT DISSIPATION FOR IC DEVICES - An integrated circuit (IC) device includes a substrate having a top surface including substrate pads, and a through substrate via (TSV) die including a semiconductor substrate including a topside semiconductor surface having active circuitry and a bottomside surface. The topside semiconductor surface includes bonding connectors that are coupled to the substrate pads on the top surface of the substrate. A plurality of TSVs include an inner metal core that extends from the topside semiconductor surface to protruding TSV tips which extend out from the bottomside surface. At least one of the plurality of TSVs are dummy TSVs that have their protruding TSV tips exclusive of any electrically connection thereto that provide additional surface area that enhances heat dissipation from the bottomside of the TSV die.08-04-2011
20110186985Semiconductor substrate, laminated chip package, semiconductor plate and method of manufacturing the same - A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof.08-04-2011
20100084763Metallic Bump Structure Without Under Bump Metallurgy And Manufacturing Method Thereof - The metallic bump is directly formed on a semiconductor wafer's I/O pad without UBM. First, a zinc layer is formed on the I/O pad or an anti-oxidation layer of the I/O pad is selectively etched off. Then, an isolative layer and a copper foil are arranged sequentially in this order above the I/O pad. The isolative layer is originally in a liquid state or in a temporarily solid state and later permanently solidified. Then, a via above the I/O pad is formed by removing part of the isolative layer and the cooper foil. Subsequently, A thin metallic layer connecting the copper foil and the I/O pad is formed in the via and a plating resist on the copper foil is formed. Then, a metallic bump is formed from the via whose height is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.04-08-2010
20130075892Method for Three Dimensional Integrated Circuit Fabrication - A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.03-28-2013
20130075895SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In one embodiment, a semiconductor device includes a chip stacked body disposed on an interposer substrate and an interface chip mounted on the chip stacked body. The chip stacked body has plural semiconductor chips, and is electrically connected via through electrodes provided in the semiconductor chips excluding a lowermost semiconductor chip in a stacking order of the plural semiconductor chips and bump electrodes. The interface chip is electrically connected to the interposer substrate via a rewiring layer formed on a surface of an uppermost semiconductor chip in the stacking order or through electrodes provided in the interface chip.03-28-2013
20110193225ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.08-11-2011
20110193224SEMICONDUCTOR DEVICE - In a semiconductor device, a pad electrode is disposed on a surface of a semiconductor substrate, and a surface-protective film is disposed on the surface of the semiconductor substrate and the pad electrode. The surface-protective film has an opening to expose a part of the pad electrode. A bump electrode is disposed on the part of the pad electrode exposed from the opening, and a bump is disposed on the bump electrode. The surface-protective film further has a slit at a location above the pad electrode. The slit has a frame shape surrounding a periphery of the bump electrode. The slit extends from a surface of the surface-protective film, which is opposite to the semiconductor substrate, and reaches the pad electrode.08-11-2011
20110193223SEMICONDUCTOR DEVICE, CHIP-ON-CHIP MOUNTING STRUCTURE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND METHOD OF FORMING THE CHIP-ON-CHIP MOUNTING STRUCTURE - A semiconductor device includes: a semiconductor chip having a semiconductor substrate; a pad electrode formed on the semiconductor substrate; a base metal layer formed on said pad electrode; and a bump electrode formed on the base metal layer, in which an exposed surface including a side surface of the base metal layer is covered with the solder bump electrode.08-11-2011
20110193222SEMICONDUCTOR MODULE, METHOD FOR FABRICATING THE SEMICONDUCTOR MODULE, AND MOBILE APPARATUS - A semiconductor module manufacturing method includes a step of bonding a semiconductor wafer, which has a plurality of semiconductor elements each of which has an element electrode formed thereon, on an expansible first insulating resin layer; a step of dicing the semiconductor wafer; a step of expanding the first insulating resin layer to widen a gap between semiconductor elements; a pressure-bonding step of pressure-bonding a metal plate whereupon an electrode is arranged and the semiconductor elements with the widened gaps in between, by having a second insulating resin layer in between, and electrically connecting the electrode and the element electrodes; a step of forming a wiring layer which corresponds to each semiconductor element by selectively removing the metal plate and forming a plurality of semiconductor modules connected by the first insulating resin layer and the second insulating resin layer; and a step of separating the semiconductor modules by cutting the first insulating resin layer and the second insulating resin layer.08-11-2011
201101932213DIC Architecture with Interposer for Bonding Dies - A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.08-11-2011
20110193220Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.08-11-2011
20110193219SEMICONDUCTOR DEVICE AND SEMICONDUCTOR ASSEMBLY WITH LEAD-FREE SOLDER - A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.08-11-2011
20110193218Solder Interconnect with Non-Wettable Sidewall Pillars and Methods of Manufacture - A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.08-11-2011
20130037935WAFER LEVEL PACKAGE STRUCTURE AND THE FABRICATION METHOD THEREOF - The present invention relates to a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.02-14-2013
20130037946SEMICONDUCTOR CHIP INCLUDING BUMP HAVING BARRIER LAYER, AND MANUFACTURING METHOD THEREOF - A semiconductor chip includes a first substrate including a first surface and a second surface, a through-via plug passing through the first substrate, and a first conduction layer connected to an end of the through-via plug on the first surface, and a first bump including a first barrier layer on the first conduction layer, and a first solder layer for connecting the first substrate and a second substrate on the first barrier layer, and the first barrier layer includes a barrier material for preventing diffusion of a conductive material of the first conduction layer into the first solder layer.02-14-2013
20130037947SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained.02-14-2013
20130037945SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.02-14-2013
20090289359SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively.11-26-2009
20130037943SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor device includes a semiconductor substrate, which includes a through hole that extends through the semiconductor substrate. An insulative layer includes a first surface, an opposite second surface covering the semiconductor substrate, and an opening aligned with the through hole. An insulative film covers an inner wall surface of the semiconductor substrate and the opening. A through electrode is formed in the through hole and the opening inward from the insulative film. The through electrode includes a first end surface that forms a pad exposed from the first surface of the insulative layer. The first end surface of the through electrode is flush with the first surface of the insulative layer.02-14-2013
20130037941SEMICONDUCTOR DEVICE REDUCING RISKS OF A WIRE SHORT-CIRCUIT AND A WIRE FLOW - A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and second wires connecting the second electrode pads with the second connection pads. The second wires have wide width parts at first ends. The first electrode pads are larger than the wide width parts while the second electrode pads are smaller than the wide width parts. The wide width parts are connected the second connection pads and the second wires have second ends connected to the second electrode pads via bump electrodes which are smaller than the second electrode pads.02-14-2013
20130037944Chip Stack Packages Having Aligned Through Silicon Vias of Different Areas - A chip stack package includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The first semiconductor chip includes a first through silicon via that extends through the first semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and includes a second through silicon via that extends through the second semiconductor chip. The second through silicon via is disposed on the first through silicon via, and has a cross-sectional area smaller than that of the first through silicon via. The third semiconductor chip is stacked on the first semiconductor chip, and includes a third through silicon via that extends through the third semiconductor chip. The third through silicon via is disposed on the second through silicon via, and has a cross-sectional area smaller than that of the second through silicon via.02-14-2013
20130037940METHOD FOR INHIBITING GROWTH OF INTERMETALLIC COMPOUNDS - The present invention relates to a method for inhibiting growth of intermetallic compounds, comprising the steps of: (i) preparing a substrate element including a substrate on which at least one layer of metal pad is deposited, wherein at least one thin layer of solder is deposited onto the layer of metal pad, and then carry out reflowing process; and (ii) further depositing a bump of solder with an appropriate thickness on the substrate element, characterized in that a thin intermetallic compound is formed by the reaction of the thin solder layer and the metal in the metal pad after appropriate heat treatment of the thin solder layer. In the present invention, the formation of a thin intermetallic compound is able to slow the growth of the intermetallic compound and to prevent the transformation of the intermetallic compounds.02-14-2013
20130037942SEMICONDUCTOR CHIPS HAVING A DUAL-LAYERED STRUCTURE, PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR CHIPS AND THE PACKAGES - Dual-layered structural semiconductor chips are provided. The semiconductor chip includes a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip. The first semiconductor chip includes a first substrate having a first bottom surface. The second semiconductor chip includes a second substrate having a second bottom surface. The first bottom surface directly contacts the second bottom surface. The related packages and the related methods are also provided.02-14-2013
20130037937BUMP PAD STRUCTURE - A bump pad structure for a semiconductor package is disclosed. A bump pad structure includes a conductive pad disposed on an insulating layer. A ring-shaped conductive layer is embedded in the insulating layer and is substantially under and along an edge of the conductive pad. At least one conductive via plug is embedded in the insulating layer and between the conductive pad and the ring-shaped conductive layer, such that the conductive pad is electrically connected to the ring-shaped conductive layer.02-14-2013
20130037939SEMICONDUCTOR PACKAGE AND STACK-TYPE SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a semiconductor chip having a first surface, a second surface which faces away from the first surface, and through holes which pass through the first surface and the second surface; a dielectric layer formed on one or more of the first surface and the second surface and formed with grooves around the through holes on a fourth surface of the dielectric layer facing away from a third surface of the dielectric layer which is attached to the semiconductor chip; through-silicon vias filling the through holes; and bumps formed on the through-silicon vias and on portions of the dielectric layer around the through-silicon vias and filling the grooves.02-14-2013
20130037936Semiconductor Device and Method of Forming a Stackable Semiconductor Package with Vertically-Oriented Discrete Electrical Devices as Interconnect Structures - A semiconductor device has a substrate and first semiconductor die to the substrate. A plurality of vertically-oriented discrete electrical devices, such as a capacitor, inductor, resistor, diode, or transistor, is mounted over the substrate in proximity to the first semiconductor die. A first terminal of the discrete electrical devices is connected to the substrate. A plurality of bumps is formed over the substrate adjacent to the discrete electrical devices. An encapsulant is deposited over and between the first semiconductor die and substrate. A portion of the bumps and a second terminal of the discrete electrical devices is exposed from the encapsulant. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. The semiconductor devices are stackable and electrically connected through the substrate, discrete electrical devices, and bumps. A heat spreader or second semiconductor die can be disposed between the stacked semiconductor devices.02-14-2013
20130037938EMBEDDED PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An embedded package includes a semiconductor chip divided into a cell region and a peripheral region, having a first surface and a second surface which faces away from the first surface, and including an integrated circuit which is formed in the cell region on the first surface, a bonding pad which is formed in the peripheral region on the first surface and a bump which is formed over the bonding pad; a core layer attached to the second surface of the semiconductor chip; an insulation component formed over the core layer including the semiconductor chip and having an opening which exposes the bump; and a circuit wiring line formed over the insulation component and the bump and electrically connected to is the bump, wherein the insulation component formed in the cell region has a thickness larger than a height of the bump.02-14-2013
20130037934INTEGRATED CIRCUIT CHIP WITH REDUCED IR DROP - An integrated circuit chip includes a power/ground interconnection network in a topmost metal layer over a semiconductor substrate and at least a bump pad on/over the power/ground interconnection network. The power/ground mesh interconnection network includes a first power/ground line connected to the bump pad and extending along a first direction, and a connection portion connected to the bump pad and extending along a second direction.02-14-2013
20130037933SEMICONDUCTOR PACKAGE WITH UNDER BUMP METALLIZATION ROUTING - A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.02-14-2013
20090140421Semiconductor Device and Method of Making Integrated Passive Devices - A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization.06-04-2009
20130026627ELECTRONIC CHIP COMPRISING CONNECTION PILLARS AND MANUFACTURING METHOD - An electronic chip including a semiconductor substrate (01-31-2013
20090020872WIRE BONDING METHOD AND SEMICONDUCTOR DEVICE - In order to prevent bonded wires from being damaged during another wire bonding in a semiconductor device, there is provided a wire bonding method for wire-connecting pads on a semiconductor chip and multiple leads corresponding to the pads in a semiconductor device to be manufactured by sealing the semiconductor chip and the leads together in one block, in which bumps and are formed with an ultrasonic vibration on all of the pads on the semiconductor chip and the leads included in the one block, and then wires are provided, with no ultrasonic vibration, for connection between the bumps and on the pads and the leads.01-22-2009
20100072616METHOD OF MANUFACTURING AN ELECTRONIC SYSTEM - A method of manufacturing an electronic system. One embodiment provides a semiconductor chip having a first main face and a second main face opposite to the first main face. A mask is applied to the first main face of the semiconductor chip. A compound is applied to the first main face of the semiconductor chip. The compound includes electronically conductive particles. The semiconductor chip is coupled to a carrier with the compound facing the carrier.03-25-2010
20130075894INTEGRATED CIRCUIT AND METHOD OF MAKING - Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends from the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. A conductive adhesive connects the conductive stud to the first side of the conductive layer.03-28-2013
20130032939CHIP PACKAGE STRUCTURE - A chip package structure includes a flexible substrate having a chip mounting region, a plurality of leads disposed on the flexible substrate, an insulating layer and a chip. Each lead includes a body portion and an inner lead portion connected to each other. The body portion is located outside the chip mounting region and has a thickness greater than that of the inner lead portion. The insulating layer is disposed on the inner lead portions. The chip has an active surface on which a plurality of bumps and a seal ring adjacent to the chip edges are disposed. The chip is mounted within the chip mounting region and electrically connects the flexible substrate by connecting the inner lead portions of the leads with the bumps. The insulating layer is corresponding to the seal ring in position when the chip is electrically connected to the flexible substrate.02-07-2013
20130032938THREE DIMENSIONAL SEMICONDUCTOR ASSEMBLY BOARD WITH BUMP/FLANGE SUPPORTING BOARD, CORELESS BUILD-UP CIRCUITRY AND BUILT-IN ELECTRONIC DEVICE - A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.02-07-2013
20130032941ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.02-07-2013
20130032940CHIP PACKAGE STRUCTURE - A chip package structure includes a chip, a flexible substrate, first leads and second leads. First bumps, second bumps and a seal ring are disposed on an active surface of the chip. The first and second bumps are respectively adjacent to first and second edges of the chip. The seal ring is located between the bumps and the edges. The chip is disposed in a chip mounting region of the flexible substrate. The first and second edges correspond to first and second sides of the chip mounting region respectively. The first leads disposed on the flexible substrate enter the chip mounting region through the first side and extend toward the second side to electrically connect the second bumps respectively. The second leads disposed on the flexible substrate enter the chip mounting region through the second side and extend toward the first side to electrically connect the first bumps respectively.02-07-2013
20130075893Synchronous Buck Converter Having Coplanar Array of Contact Bumps of Equal Volume - A packaged power supply module (03-28-2013
20130075891FLIP CHIP TYPE FULL WAVE RECTIFICATION SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - This invention reveals a flip-chip type full-wave rectification semiconductor device which includes at least a PNNP type and/or NPPN type flip-chip, and a sheet stuff or substrate including a plurality pins, and which is characterized in that: all the soldering points (bumps) of the PNNP type and/or the NPPN type flip-chip are on an identical surface, this can make easy connecting of the pins with the bumps of the flip-chips by soldering in pursuance of circuit arrangement of the full-wave rectification device, and complete manufacturing product after the steps of shaping/packing and cutting; such product has a function of making full-wave rectifying, and can simplify the manufacturing process, reduce the manufacturing cost, and get an effect of reducing the size of the product with better heat dissipation, being different from traditional full wave rectification semiconductor devices composed of two/four grains.03-28-2013
20130075903Semiconductor Device and Method of Forming Different Height Conductive Pillars to Electrically Interconnect Stacked Laterally Offset Semiconductor Die - A semiconductor device has a first semiconductor die mounted over a carrier. Wettable contact pads can be formed over the carrier. A second semiconductor die is mounted over the first semiconductor die. The second die is laterally offset with respect to the first die. An electrical interconnect is formed between an overlapping portion of the first die and second die. A plurality of first conductive pillars is disposed over the first die. A plurality of second conductive pillars is disposed over the second die. An encapsulant is deposited over the first and second die and first and second conductive pillars. A first interconnect structure is formed over the encapsulant, first conductive pillars, and second die. The carrier is removed. A second interconnect structure is formed over the encapsulant, second conductive pillars, and first die. A third conductive pillar is formed between the first and second build-up interconnect structures.03-28-2013
20130075897SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DRIVING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor integrated circuit device for driving an LCD, COG chip packaging is performed. To achieve this, an elongate and relatively thick gold bump electrode is formed over an aluminum-based pad having a relatively small area. In a wafer probe test performed after formation of the gold bump electrode, a cantilever type probe needle having gold as a main component and having an almost perpendicularly bent tip portion is used. The diameter of this probe needle in the vicinity of its tip is usually almost the same as the width of the gold bump electrode. This makes it difficult to perform the wafer probe test stably. To counteract this, a plurality of bump electrode rows for outputting a display device drive signal are formed such that the width of inner bump electrodes is made greater than the width of outer bump electrodes.03-28-2013
20130075899Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant - A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.03-28-2013
20130075898SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die.03-28-2013
20130075896SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof. The through electrode includes a resin core and a conductive film covering at least a part of the resin core.03-28-2013
20100032830THREE-DIMENSIONAL CONDUCTING STRUCTURE AND METHOD OF FABRICATING THE SAME - The three-dimensional conducting structure comprises a substrate, a first redistributed conductor, a second redistributed conductor and an insulator. The substrate has an active surface, a passive surface opposite to the active one, a pad on the active surface and a through hole. The first redistributed conductor comprises a projecting portion and a receiving portion. The projecting portion is projected from the active surface and electrically connected to the pad. The receiving portion is outside the active surface and in contact with the projecting portion, both of which constitute a recess communicating with the through hole. The second redistributed conductor is positioned within the through hole and the recess, in contact with the receiving portion, and extended toward the passive surface along the through hole. The insulator is filled between the second redistributed conductor and the substrate and between the second redistributed conductor and the projecting portion.02-11-2010
20130082380STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The microelectronic element can include a plurality of stacked electrically interconnected semiconductor chips. The substrate can have contacts facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.04-04-2013
20090166861WIRE BONDING OF ALUMINUM-FREE METALLIZATION LAYERS BY SURFACE CONDITIONING - In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. Moreover, reliable wire bond connections may be obtained by providing a protection layer, such as an oxide layer, after exposing the respective contact metal, such as copper, nickel and the like, thereby providing highly uniform process conditions during the subsequent wire bonding process. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon.07-02-2009
20090121349SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.05-14-2009
20130075902Semiconductor Device and Method of Forming Conductive Posts Embedded in Photosensitive Encapsulant - A semiconductor package includes a post carrier having a base plate and plurality of conductive posts. A photosensitive encapsulant is deposited over the base plate of the post carrier and around the conductive posts. The photosensitive encapsulant is etched to expose a portion of the base plate of the post carrier. A semiconductor die is mounted to the base plate of the post carrier within the etched portions of the photosensitive encapsulant. A second encapsulant is deposited over the semiconductor die. A first circuit build-up layer is formed over the second encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. The base plate of the post carrier is removed and a second circuit build-up layer is formed over the semiconductor die and the photosensitive encapsulant opposite the first circuit build-up layer. The second circuit build-up layer is electrically connected to the conductive posts.03-28-2013
20130075901SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 03-28-2013
20100044859Semiconductor device and method of fabricating semiconductor device - There is provided a semiconductor device including a semiconductor substrate on which at least one electrode pad is formed, a rewiring layer connected to the electrode pad, and an encapsulation part which encapsulates the semiconductor substrate, the electrode pad being formed of a first region including a connection part connected to the rewiring layer and a second region other than the first region, the device including: an insulating film provided on the semiconductor substrate, having an opening at which the first region in the electrode pad is exposed, and covering the second region of the electrode pad, wherein the rewiring layer is connected to the first region of the electrode pad exposed at the opening, and extends across the insulating film so as to cover the second region of the electrode pad from above.02-25-2010
20130075900Semiconductor Device and Method of Forming Insulating Layer on Conductive Traces for Electrical Isolation in Fine Pitch Bonding - A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around bumps between the semiconductor die and substrate.03-28-2013
20090160051Semiconductor Chip, Method of Fabricating the Same and Semiconductor Chip Stack Package - Provided are a semiconductor chip, a method of fabricating a semiconductor chip, and a semiconductor chip stack package. The semiconductor chip includes a semiconductor substrate and a semiconductor device on the semiconductor substrate. A dielectric covers the semiconductor device. A top metal is on the dielectric and electrically connected to the semiconductor device. A deep via penetrates the semiconductor substrate and the dielectric. An interconnection connects the deep via and the top metal electrically. A bump is in contact with the top metal and the interconnection.06-25-2009
20090160050SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND WAFER - A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.06-25-2009
20090160049Semiconductor device - A semiconductor device of the present invention includes a semiconductor chip; an internal pad for electrical connection formed on a surface of the semiconductor chip; a stress relaxation layer formed on the semiconductor chip and having an opening for exposing the internal pad; a connection pad made of a metal having solder wettability, formed on a part facing the opening of the internal pad and provided with a protruding portion protruding on the stress relaxation layer; a metal flange made of a metal having solder wettability, encompassing the periphery of the protruding portion and formed with a smaller thickness than a protruding amount of the protruding portion onto the stress relaxation layer; and a solder terminal for electrical connection with outside formed on the protruding portion and the metal flange.06-25-2009
20090020870ELECTRONIC DEVICE PROVIDED WITH WIRING BOARD, METHOD FOR MANUFACTURING SUCH ELECTRONIC DEVICE AND WIRING BOARD FOR SUCH ELECTRONIC DEVICE - An electronic device (01-22-2009
20100109159BUMPED CHIP WITH DISPLACEMENT OF GOLD BUMPS - A bumped chip is revealed, including a chip, a UBM layer, an Ag bump, and a creeping-resist layer. The chip has a bonding pad and a passivation layer covering one surface of the chip and exposing the bonding pad. The UBM layer is disposed on the bonding pad and covers the passivation layer at the peripheries of the opening. The Ag bump is disposed on the UBM layer to form as a pillar bump having a top surface and a pillar sidewall. The creeping-resist layer is formed at least on the pillar sidewall to fully encapsulate the Ag bump. Therefore, the disclosed bumped chip will have no Ag-creeping due to exerting stresses nor changing of joint heights under high temperature environment to meet the bumping requirements of lead-free, high reliability, and lower cost.05-06-2010
20100109160SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes the steps of preparing a semiconductor wafer having a connection pad, forming an insulating dam layer in which an opening portion is provided in an area including the connection pad, on the semiconductor wafer, and forming a bump electrode by mounting a conductive ball on the connection pad in the opening portion of the insulating dam layer.05-06-2010
20100109156BACK SIDE PROTECTIVE STRUCTURE FOR A SEMICONDUCTOR PACKAGE - The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; a conductive layer formed upon the back surface of the die; and a protection substrate formed on the conductive layer. An adhesive layer is formed between the conductive layer and the protective layer, if necessary. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming a conductive layer upon the back surface of the die; forming protection substrates on the conductive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation by exerting external force on the substrate. An adhesive layer is formed between the conductive layer and the protective layer, if necessary.05-06-2010
20100109158SEMICONDUCTOR DEVICE INCLUDING A REDUCED STRESS CONFIGURATION FOR METAL PILLARS - In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer that is in tight mechanical contact with the metal pillar.05-06-2010
20100109157CHIP STRUCTURE AND CHIP PACKAGE STRUCTURE - A chip structure and a chip package structure are disclosed herein. The chip structure includes a chip and a bump. The chip includes at least one pad. The bump is disposed on a bounding region of the pad. The shape of the bump is triangular pillar or trapezoidal pillar. A surface area of connection between the bump and the pad is less than or equal to the bounding region. Therefore, the material usage and the cost of the bump can be reduced. In addition, such shape of the bump has directional characteristic so that it is easy to perform the chip testing via the identifiable pads, and perform the package process of bonding the chip to a circuit board or any carriers.05-06-2010
20130082382SEMICONDUCTOR DEVICE - First and second sub-bumps are provided on both surfaces of each substrate along with a usual bump structure (first and second main bumps), and at least one of the first and second sub-bumps is made greater in height than the first and second main bumps, so that the sub-bumps come into contact with one another earlier than the main bumps at the time of joining semiconductor chips, thereby securing margins of joint among the main bumps and suppressing the thin-filming of a layer, such as a solder layer, to be fluidized by heating.04-04-2013
20130082381STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.04-04-2013
20130082379SEMICONDUCTOR PACKAGE INCLUDING AN INTEGRATED WAVEGUIDE - Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.04-04-2013
20100007016DEVICE WITH CONTACT ELEMENTS - A device with contact elements. One embodiment provides an electrical device including a structure defining a main face. The structure includes an array of cavities and an array of overhang regions, each overhang region defining an opening to one of the cavities. The electrical device further includes an array of contact elements, each contact element only partially filling one of the cavities and protruding from the structure over the main face.01-14-2010
20090134516Method of manufacturing semiconductor device and semiconductor device - According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.05-28-2009
20090134515SEMICONDUCTOR PACKAGE SUBSTRATE - A semiconductor package substrate includes a main body with a surface having a first circuit layer thereon and a dielectric layer covering the first circuit layer, with a plurality of vias on a portion of the first circuit layer; a plurality of first conductive vias disposed in the vias; a plurality of first electrically connecting pads on the first conductive vias and completely exposed on the dielectric layer having no extending circuits for a semiconductor chip to be mounted thereon, the first electrically connecting pad being electrically connected to the first circuit layer of the first conductive via; and an insulating protective layer disposed on the main body with an opening for completely exposing the first electrically connecting pads, whereby the circuit layout density is increased without disposing circuits between the electrically connecting pads.05-28-2009
20090127709SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes: a semiconductor chip; a wiring formed on the semiconductor chip; a passivation film, coating the wiring and having an opening for partially exposing the wiring from the passivation film; an interposing film, formed on a portion of the wiring facing the opening; and a post bump, raisedly formed on the interposing film and with a peripheral edge portion thereof protruding more toward a side than a peripheral edge of the interposing film.05-21-2009
20100065966Solder Joint Flip Chip Interconnection - A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.03-18-2010
20130087910SEMICONDUCTOR DEVICE HAVING MULTIPLE BUMP HEIGHTS AND MULTIPLE BUMP DIAMETERS - A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.04-11-2013
20130087911INTEGRATED CIRCUIT PACKAGE STRUCTURE - An integrated circuit (IC) package structure is provided, including: a first integrated circuit (IC) package, including: a first package substrate, having opposite first and second surfaces, wherein a first semiconductor chip is disposed over a first portion of the first surface of the first package substrate. In addition, a second integrated circuit (IC) package is disposed on a second portion different from the first portion of the first surface of the first package substrate, including: a second package substrate, having opposite third and fourth surfaces, wherein a second semiconductor chip is disposed over a portion of the third surface of the second package substrate, and the second semiconductor chip has a function different from that of the first semiconductor chip.04-11-2013
20130087909SEMICONDUCTOR DEVICE HAVING IMPROVED CONTACT STRUCTURE - A semiconductor die includes a first contact stack including a first die pad having a first pad perimeter, a first via through a dielectric layer to the first die pad having a first via perimeter, and a first UBM pad contacting the first die pad through the first via having a first UBM pad perimeter. A second contact stack includes a second die pad having a second pad perimeter shorter than the first pad perimeter, a second via through the dielectric layer to the second die pad having a second via perimeter shorter than the first via perimeter, and a second UBM pad contacting the second die pad through the second via having a second UBM pad perimeter that is shorter than the first UBM pad perimeter.04-11-2013
20130087912SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.04-11-2013
20130087913Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process - A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.04-11-2013
20130087907Metal Features to Reduce Crack-Inducing Stresses in Metallization Stacks - Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bump structure above a first metallization layer of a metallization system of the semiconductor chip, and a metal feature in the first metallization layer, wherein at least a first portion of the metal feature is located closer to a center of the semiconductor chip than any portion of the bump structure, and at least a second portion of the metal feature is positioned below the bump structure.04-11-2013
20130087906CIRCUIT BOARD, FABRICATING METHOD THEREOF AND PACKAGE STRUCTURE - The present invention provides a circuit board including a substrate, at least one lead, at least one bump, and a solder layer. The lead is disposed on the substrate, and the bump is disposed on the lead. The solder layer covers the lead and the bump.04-11-2013
20130087908BUMP WITH PROTECTION STRUCTURE - A semiconductor device includes a bump structure formed on a post-passivation interconnect (PPI) line and surrounded by a protection structure. The protection structure includes a polymer layer and at least one dielectric layer. The dielectric layer may be formed on the top surface of the polymer layer, underlying the polymer layer, inserted between the bump structure and the polymer layer, inserted between the PPI line and the polymer layer, covering the exterior sidewalls of the polymer layer, or combinations thereof.04-11-2013
20120181690Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers - A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.07-19-2012
20120181689Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices - A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.07-19-2012
20120181688PACKAGING SUBSTRATE WITH CONDUCTIVE STRUCTURE - A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.07-19-2012
20120181687MATERIALS, STRUCTURES AND METHODS FOR MICROELECTRONIC PACKAGING - Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.07-19-2012
20120181686METHOD OF PREPARING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DIE FOR SEMICONDUCTOR PACKAGE - A method of preparing a semiconductor package including disposing photosensitive adhesive film on a reinterconnected rear surface of a wafer on which the through electrodes are disposed, and forming a pattern corresponding to the through electrodes to prepare the semiconductor package.07-19-2012
20090045510SEMICONDUCTOR DEVICE AND METHOD FOR MOUNTING SEMICONDUCTOR CHIP - A semiconductor device includes a rigid substrate, a flexible solid-state image sensor and bumps. The bumps are aligned along a pair of opposing edges of the rigid substrate, and the diameter of the bumps gradually increases from the center to the ends of the edges. Owing to the difference in diameter of the bumps, the solid-state image sensor is curved convexly to the rigid substrate.02-19-2009
20090045509ELECTRONIC DEVICE - An electronic device including: a semiconductor chip on which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; a resin protrusion disposed on the semiconductor chip; an interconnect formed on the electrode and extending over the resin protrusion; a wiring board on which a wiring pattern is formed, the semiconductor chip being mounted on the wiring board so that part of the interconnect positioned over the resin protrusion faces and is electrically connected to the wiring pattern; and an adhesive that bonds the semiconductor chip and the wiring board. The resin protrusion is compressed in a direction in which the distance between the semiconductor chip and the wiring board decreases and is formed of a material having a negative coefficient of thermal expansion.02-19-2009
20100327436APPARATUS AND METHOD FOR STACKING INTEGRATED CIRCUITS - A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.12-30-2010
20100327434SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first semiconductor chip having a first active surface and a bonding surface forming an opposite side of the first active surface, the bonding surface being bonded to a mounting surface of a substrate; a second semiconductor chip having a second active surface facing the first active surface, and stacked on the first semiconductor chip; a slope section having a sloping surface with a shape of smoothing a step between the first active surface and the mounting surface, and adapted to bury the step in at least a part of a periphery of the first semiconductor chip; and a first wiring wire laid down between the mounting surface and the first active surface via the sloping surface of the slope section, and connected to a first bump provided to the second active surface on the first active surface.12-30-2010
20110001237ASSEMBLY OF A WIRE ELEMENT WITH A MICROELECTRONIC CHIP WITH A GROOVE COMPRISING AT LEAST ONE BUMP SECURING THE WIRE ELEMENT - The assembly comprises at least one microelectronic chip having two parallel main surfaces and lateral surfaces, at least one of the lateral faces comprising a longitudinal groove housing a wire element having an axis parallel to the longitudinal axis of the groove. The groove is delineated by at least two side walls. The wire element is secured to the chip at the level of a clamping area between at least one bump arranged on one of the side walls, and the side wall of the groove opposite said bump. The clamping area has a smaller height than the diameter of the wire element and a free area is arranged laterally to the bump along the longitudinal axis of the groove. The free area has a height, corresponding to the distance separating the two side walls, that is greater than the diameter of the wire element.01-06-2011
20130049194SELF-ALIGNED PROTECTION LAYER FOR COPPER POST STRUCTURE - A semiconductor device including a semiconductor substrate and a conductive post overlying and electrically connected to the substrate. The semiconductor device further includes a manganese-containing protection layer on a surface of the conductive post. A method of forming a semiconductor device. The method includes forming a bond pad region on a semiconductor substrate. The method further includes forming a conductive post overlying and electrically connected to the bond pad region. The method further includes forming a protection layer on a surface of the conductive post, wherein the protection layer comprises manganese (Mn).02-28-2013
20130049193FORMATION OF THROUGH-SILICON VIA (TSV) IN SILICON SUBSTRATE - To form a through-silicon via (TSV) in a silicon substrate without using plating equipment or using sputtering equipment or small metal particles, and form an interlayer connection by stacking a plurality of such silicon substrates, a through hole of a silicon substrate is filled using molten solder itself. In detail, solid solder placed above the through hole of the silicon substrate is molten and the molten solder is guided to and filled in the internal space. A metal layer can be deposited on an internal surface of the through hole beforehand, and also an intermetallic compound (IMC) can be formed in a portion other than the metal layer.02-28-2013
20130049190METHODS OF FABRICATING SEMICONDUCTOR CHIP SOLDER STRUCTURES - Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.02-28-2013
20130049189SEMICONDUCTOR FLIP-CHIP SYSTEM HAVING THREE-DIMENSIONAL SOLDER JOINTS - A solder joint between a trace (02-28-2013
20100102445WIRING SUBSTRATE, SOLID-STATE IMAGING APPARATUS USING THE SAME, AND MANUFACTURING METHOD THEREOF - In one embodiment, a miniaturized solid-state imaging apparatus includes a body having a cavity for mounting a semiconductor chip therein. The body has an overhanging portion extending toward the cavity. Further, a lead is disposed within the body. The lead has one end exposed through a top surface of the body and the other end exposed through a bottom surface of the body for electrical connection thereof.04-29-2010
20100102444WAFER LEVEL PACKAGE USING STUD BUMP COATED WITH SOLDER - A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed.04-29-2010
20090302466SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first metal post that has a first face, a second metal post that has a second face, a first plated layer that is provided on the first face, the first plated layer being discontiguous with an outer edge of the first face, a second plated layer that is provided on the second face, the second plated layer being discontiguous with an outer edge of the second face, an integrated circuit element that is fixed on the first face; a conductor that electrically connects the integrated circuit element with the second metal post, and a resin that seals the integrated circuit element and the conductor.12-10-2009
20090302464SEMICONDUCTOR DEVICE - A semiconductor device allowing for chip size reduction and thereby cost reduction without being restricted by a layout of bumps comprises a film substrate, an interposer substrate (12-10-2009
20090302463SEMICONDUCTOR DEVICE HAVING SUBSTRATE WITH DIFFERENTIALLY PLATED COPPER AND SELECTIVE SOLDER - A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip 12-10-2009
20120217634Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier - A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.08-30-2012
20120217633PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES - An embodiment of the disclosure provides a semiconductor device. The semiconductor device includes a plurality of metallization layers comprising a topmost metallization layer. The topmost metallization layer has two metal features having a thickness T08-30-2012
20120217632Extending Metal Traces in Bump-on-Trace Structures - A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.08-30-2012
20110006420SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: preparing a wiring board having a base substrate and wiring that is plated on surface with a plating metal; pressing a bump that is formed on the active side of the semiconductor chip against an end part of the wiring of the wiring board, thereby exfoliating the area surrounding the pressed portion of the wiring from the base substrate while keeping the end of the wiring bonded with the base substrate; melting the plating metal that is located on the end part of the wiring, thereby causing the plating metal and the bump to form an alloy that bonds the bump and the wiring and infiltrate the plating metal into a space between the wiring and the base substrate; and judging that the bump and the wiring are well bonded if the plating metal has infiltrated a space between the wiring and the base substrate so as to have an area, width or length of infiltration that exceeds a reference value.01-13-2011
20110006419FILM FOR USE IN MANUFACTURING SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A film for use in manufacturing a semiconductor device having at least one semiconductor element of the present invention is characterized by comprising: a base sheet having one surface; and a bonding layer provided on the one surface of the base sheet, the bonding layer being adapted to be bonded to the semiconductor element in the semiconductor device, the bonding layer being formed of a resin composition comprising a crosslinkable resin and a compound having flux activity. Further, it is preferred that in the film of the present invention, the semiconductor element is of a flip-chip type and has a functional surface, and the bonding layer is adapted to be bonded to the functional surface of the semiconductor element.01-13-2011
20130069226SEMICONDUCTOR PACKAGE HAVING INTERPOSER - A semiconductor package includes a first structural body having a first surface and a second surface which faces away from the first surface, and formed with first connection members on the first surface; a second structural body placed over the first structural body, and formed with second connection members on a surface thereof which faces the first surface of the first structural body; and an interposer interposed between the first structural body and the second structural body, and having a body which is formed with openings into which the first connection members and the second connection members are inserted and a conductive layer which is formed to fill the openings.03-21-2013
20130069222Semiconductor Device and Method of Forming a Reconfigured Stackable Wafer Level Package with Vertical Interconnect - A semiconductor device has a carrier with a semiconductor die mounting area. A plurality of conductive posts is formed in a periphery of the semiconductor die mounting area and in the carrier. A first portion of the carrier is removed to expose a first portion of the plurality of conductive posts such that a second portion of the plurality of conductive posts is embedded in a second portion of the carrier. A first semiconductor die is mounted to the semiconductor die mounting area and between the first portion of the plurality of conductive posts. A first encapsulant is deposited around the first semiconductor die and around the first portion of the plurality of conductive posts. A second portion of the carrier is removed to expose the second portion of the plurality of conductive posts. An interconnect structure is formed over the plurality of conductive posts and the first semiconductor die.03-21-2013
20130069230ELECTRONIC ASSEMBLY APPARATUS AND ASSOCIATED METHODS - An apparatus includes a substrate, and first and second die. The first die is assembled above the substrate. The first die includes electronic circuitry. The second die is assembled above the substrate. The second die includes electronic circuitry. The apparatus further includes first and second interconnects. The first interconnect includes a first set of copper pillars, and couples the first die to the substrate. The second interconnect includes a second set of copper pillars, and couples the second die to the first die.03-21-2013
20130069229PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad.03-21-2013
20130069224INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE UNDERLAYER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a routable layer having a column; mounting an integrated circuit structure in direct contact with the column; and forming a gamma connector to electrically connect the column to the integrated circuit structure.03-21-2013
20130069225Semiconductor Device and Method of Forming Protection and Support Structure for Conductive Interconnect Structure - A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.03-21-2013
20130069223FLASH MEMORY CARD WITHOUT A SUBSTRATE AND ITS FABRICATION METHOD - Disclosed is a flash memory card without a substrate, primarily comprising a memory chip component, a controller chip disposed on the memory chip, and an encapsulant encapsulating both chips. Formed on an active surface and a back surface of the memory chip component are a first RDL (redistribution layer) and a second RDL respectively. A plurality of TSVs (through silicon vias) penetrate from the active surface to the back surface to electrically connect both RDLs. A plurality of contacting fingers are disposed on the back surface of the memory chip component and electrically connected with the second RDL. Additionally, the encapsulant has a card appearance with one surface of each contacting finger to be exposed. Accordingly, the flash memory card can save conventional substrate structure with better reliability and efficiency for packaging processes.03-21-2013
20130069221Semiconductor Device and Method of Forming Conductive Protrusions Over Conductive Pillars or Bond Pads as Fixed Offset Vertical Interconnect Structures - A semiconductor device has a semiconductor die mounted to a substrate. A plurality of conductive pillars is formed over a semiconductor die. A plurality of conductive protrusions is formed over the conductive pillars. Bumps are formed over the conductive protrusions and conductive pillars. Alternatively, the conductive protrusions are formed over the substrate. A conductive layer is formed over the substrate. The semiconductor die is mounted to the substrate by reflowing the bumps at a temperature that is less than a melting point of the conductive pillars and conductive protrusions to metallurgically and electrically connect the bumps to the conductive layer while maintaining a fixed offset between the semiconductor die and substrate. The fixed offset between the semiconductor die and substrate is determined by a height of the conductive pillars and a height of the conductive protrusions. A mold underfill material is deposited between the semiconductor die and substrate.03-21-2013
20130056870FLIP-CHIP, FACE-UP AND FACE-DOWN WIREBOND COMBINATION PACKAGE - A microelectronic assembly can include a substrate having oppositely-facing first and second surfaces and a first aperture extending between the first and second surfaces, a first microelectronic element having a surface facing the first surface, a second microelectronic element having a front surface facing the first microelectronic element, signal leads connected to contacts of the second microelectronic element and extending through the first aperture to at least some of a plurality of electrically conductive elements on the substrate, and at least one power regulation component having active circuit elements therein disposed between the first surface of the substrate and the front surface of the second microelectronic element. The first microelectronic element can have another surface remote from the surface of the first microelectronic element, and an edge extending between the surfaces thereof. The contacts of the second microelectronic element can project beyond the edge of the first microelectronic element.03-07-2013
20130056868ROUTING UNDER BOND PAD FOR THE REPLACEMENT OF AN INTERCONNECT LAYER - The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.03-07-2013
20130056865Method of Three Dimensional Integrated Circuit Assembly - A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.03-07-2013
20120112344SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF - Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.05-10-2012
20120112343ELECTROPLATED POSTS WITH REDUCED TOPOGRAPHY AND STRESS - Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least three sides of the planarizing dielectric structures. The planarizing dielectric structures can be used on integrated circuits having bond pads of different sizes to electroplate metal posts having the same height.05-10-2012
20120112342SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR PACKAGE - A semiconductor device includes a first structural body having a first surface and a second surface which faces away from the first surface, and formed with first electrode pads on the first surface, a stress buffer layer formed on the first electrode pads and the first surface of the first structural body, and having a plurality of holes which expose the first electrode pads, and a plurality of bumps formed to be electrically connected with the first electrode pads through the plurality of holes, wherein the plurality of bumps include first bumps which are filled in corresponding holes of the plurality of holes and second bumps which are formed on the first bumps and the stress buffer layer and are disposed over the first electrode pads and portions of the first surface outside the first electrode pads.05-10-2012
20120306074SEMICONDUCTOR CHIP HAVING BUMP ELECTRODE, SEMICONDUCTOR DEVICE HAVING THE SEMICONDUCTOR CHIP, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor chip includes: a substrate; a first bump electrode formed on one face of the substrate; a second bump electrode formed on other face of the substrate; and a conductive bonding material layer formed on a top face of at least one of the first bump electrode and the second bump electrode. The first bump electrode has a convex top face and the second bump electrode has a concave top face.12-06-2012
20130056869PILLAR STRUCTURE HAVING A NON-PLANAR SURFACE FOR SEMICONDUCTOR DEVICES - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.03-07-2013
20130056867Semiconductor device and method of forming FO-WLCSP with recessed interconnect area in peripheralregion of semiconductor die - A semiconductor device has a temporary layer, such as a dam material or adhesive layer, formed over a carrier. A plurality of recesses is formed in the temporary layer. A first semiconductor die is mounted within the recesses of the temporary layer. An encapsulant is deposited over the first semiconductor die and temporary layer. The encapsulant extends into the recesses in the temporary layer. The carrier and temporary layer are removed to form recessed interconnect areas around the first semiconductor die. Alternatively, the recessed interconnect areas can be formed the carrier or encapsulant. Multiple steps can be formed in the recesses of the temporary layer. A conductive layer is formed over the first semiconductor die and encapsulant and into the recessed interconnect areas. A second semiconductor die can be mounted on the first semiconductor die. The semiconductor device can be integrated into PiP and Fi-PoP arrangements.03-07-2013
20130056866STACKED WAFER-LEVEL PACKAGE DEVICE - Wafer-level package devices are described that include multiple die packaged into a single wafer-level package device. In an implementation, a wafer-level package device includes a semiconductor device having at least one electrical interconnection formed therein. At least one semiconductor package device is positioned over the first surface of the semiconductor device. The semiconductor package device includes one or more micro-solder bumps. The wafer-level package device further includes an encapsulation structure disposed over and supported by the semiconductor device for encapsulating the semiconductor package device(s). When the semiconductor package device is positioned over the semiconductor device, each micro-solder bump is connected to a respective electrical interconnection that is formed in the semiconductor device.03-07-2013
20100084764Carbon nanotube-reinforced solder caps, methods of assembling same, and chip packages and systems containing same - A carbon nanotube solder is formed on a substrate of an integrated circuit package. The carbon nanotube solder exhibits high heat and electrical conductivities. The carbon nanotube solder is used as a solder microcap on a metal bump for communication between an integrated circuit device and external structures.04-08-2010
20090079067Method for Stacking Semiconductor Chips - In a semiconductor system (03-26-2009
20090267230PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE AND METHOD OF THE SAME - The present invention discloses a package structure for an integrated circuit device and method for manufacturing the same. The method includes providing a wafer with multiple integrated circuit devices; providing an extendable substrate having a first surface supporting the wafer; forming multiple anti-elongation layers on a second surface of the extendable substrate, the second surface being opposite to the first surface; forming multiple recesses in the wafer for separating the integrated circuit devices from each other; elongating the extendable substrate to enlarge the multiple recesses; and forming an insulating layer to fill the recesses and cover multiple integrated circuit devices.10-29-2009
20090267228INTERMETALLIC DIFFUSION BLOCK DEVICE AND METHOD OF MANUFACTURE - One embodiment of the present invention is directed to an under bump metallurgy material. The under bump metallurgy material of this embodiment includes an adhesion layer and a conduction layer formed on top of the adhesion layer. The under bump metallurgy material of this embodiment also includes a barrier layer plated on top of the conduction layer and a sacrificial layer plated on top of the barrier layer. The conduction layer of this embodiment includes a trench formed therein, the trench contacting a portion of the barrier layer and blocking a path of intermetallic formation between the conduction layer and the sacrificial layer.10-29-2009
20090267227PLASTIC BALL GRID ARRAY RUGGEDIZATION - A method and product which provides a thin metal or ceramic plate to the top of a plastic grid array (PGA) as a stiffener to maintain its flatness over temperature during a column attach process, and the columns are used for attachment to circuit boards or other circuit devices. These may be constructed in this manner initially or may be retrofitted plastic ball grid arrays from which the solder balls are removed and, the stiffener is attached to the top, and the solder columns have been added to replace the solder balls. The stiffener is a bonded thin metal or ceramic plate attached to the top of the PGA to maintain its flatness over temperature during the column attach process. An aluminum plate bonded to the top of a PGA results in a significant reduction in warping during a temperature cycle. This allows attachment of solder columns to the PBGA. The high melt solder columns are attached to an area array pattern on the PBGA substrate. This array is typically either a solid or perimeter grid. It is critical that the ends of the solder columns opposite the ends attached to the substrate align precisely with the matching grid of solder pads on the printed wiring board. The purpose of the stiffening plate is to maintain the flatness of the PBGA during the process of attaching the columns to the substrate as well as attaching the component to the printed wiring board such that the columns maintain their alignment over this temperature range.10-29-2009
20130062759ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.03-14-2013
20130062757No Flow Underfill or Wafer Level Underfill and Solder Columns - A preassembly semiconductor device comprises substrate soldering structures extending toward chip soldering structures for forming solder connections with the chip soldering structures, i.e., the chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures. In another embodiment the height of the chip soldering structures is greater than the height of the substrate soldering structures and the pre-applied underfill is contiguous with the semiconductor chip and sufficiently thick so as to extend substantially no further than the full height of the chip soldering structures. A process comprises manufacturing semiconductor assemblies from these devices by soldering the semiconductor chip and the substrate to one another.03-14-2013
20130062756SUBSTRATE STRUCTURE WITH COMPLIANT BUMP AND MANUFACTURING METHOD THEREOF - A substrate structure with compliant bump comprises a substrate, a plurality of bumps, and a metallic layer, wherein the substrate comprises a surface, a trace layer, and a protective layer. The trace layer comprises a plurality of conductive pads, and each of the conductive pads comprises an upper surface. The protective layer comprises a plurality of openings. The bumps are formed on the surface, and each of the bumps comprises a top surface, an inner surface and an outer surface and defines a first body and a second body. The first body is located on the surface. The second body is located on top of the first body. The metallic layer is formed on the top surface, the inner surface, and the upper surface.03-14-2013
20130062758SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device has a substrate, a first semiconductor chip, an electrode, a first and second connection member, and a first and second sealing member. The electrode is disposed on the first semiconductor chip and contains Al. The first connection member electrically connects the electrode and the substrate and contains Au or Cu. The first sealing member seals the first semiconductor chip and the first connection member. One or more second semiconductor chips are stacked on the first sealing member. The second sealing member seals the first connection member, the one or more second semiconductor chips, and the one or more second connection members. A ratio of a total weight W03-14-2013
20130062755ELONGATED BUMP STRUCTURE IN SEMICONDUCTOR DEVICE - A device includes a chip attached to a substrate. The chip includes a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a conductive trace and a mask layer overlying the conductive trace, wherein the mask layer has an opening exposing a portion of the conductive trace. An interconnection is formed between the conductive pillar and the exposed portion of the conductive trace. The opening has a first dimension (d03-14-2013
20080290512SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - For a suppressed breakage after a flip chip connection of a semiconductor device using a low-permittivity insulation film and a lead-free solder together, with an enhanced production yield, bump electrodes (11-27-2008
20120223428Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Semiconductor Die and Substrate - A semiconductor device has a semiconductor die and substrate with a plurality of stud bumps formed over the semiconductor die or substrate. The stud bumps include a base portion and stem portion extending from the base portion. The stud bumps include a non-fusible material or fusible material. The semiconductor die is mounted to the substrate with the stud bumps electrically connecting the semiconductor die to the substrate. A width of the base portion is greater than a mating conductive trace formed on the substrate. Alternatively, a vertical interconnect structure, such as a conductive column, is formed over the semiconductor die or substrate. The conductive column can have a tapered sidewall or oval cross sectional area. An underfill material is deposited between the semiconductor die and substrate. The semiconductor die includes a flexible property. The vertical interconnect structure includes a flexible property. The substrate includes a flexible property.09-06-2012
20120223426Semiconductor Device and Method of Forming Stress Relief Layer Between Die and Interconnect Structure - A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.09-06-2012
20120223425SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.09-06-2012
20110012258Semiconductor Device and Method of Laser-Marking Laminate Layer Formed Over EWLB With Tape Applied to Opposite Surface - A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking.01-20-2011
20130161814SEMICONDUCTOR CHIP WITH OFFSET PADS - A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures.06-27-2013
20130161813SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first surface, a second surface, and a through hole that extends through the semiconductor substrate from the first surface to the second surface. An insulating layer covers the first surface and includes an opening at a location facing the through hole. An insulating film covers an inner wall of the through hole and an inner wall of the opening. A through electrode is formed in the through hole and the opening that are covered by the insulating film. A first connecting terminal is formed integrally with the through electrode to cover one end of the through electrode exposed from the insulating layer. The first connecting terminal has a larger size than the through electrode as viewed from above.06-27-2013
20130161812DIE PACKAGES AND SYSTEMS HAVING THE DIE PACKAGES - A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.06-27-2013
20090236741CONDUCTIVE STRUCTURE OF A CHIP AND METHOD FOR MANUFACTURING THE SAME - A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the photomask can be economized and the cost of manufacturing can be reduced.09-24-2009
20090236740Window ball grid array package - A WBGA (window ball grid array) semiconductor package includes a substrate having a slot as a window for a chip. The slot has four straight sections and four rounded corners respectively interconnecting adjacent two straight sides. Each rounded corner has a radius satisfying the minimum distance between the pads and the slot according to the design rule so as to increase the pad pitch in the chip. The plain area increased due to the pad pitch is suitable for ESD circuit or capacitors layout.09-24-2009
20090236739SEMICONDUCTOR PACKAGE HAVING SUBSTRATE ID CODE AND ITS FABRICATING METHOD - A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code. The complexity of the semiconductor packaging processes is not increased and the circuits of the substrates are not easily damaged.09-24-2009
20090236738Semiconductor Device and Method of Forming Oxide Layer on Signal Traces for Electrical Isolation in Fine Pitch Bonding - A semiconductor device has a semiconductor die with a solder bump formed on its surface. A contact pad is formed on a substrate. A signal trace is formed on the substrate. The pitch between the contact pad and signal trace is less than 150 micrometers. An electroless surface treatment is formed over the contact pad. The electroless surface treatment can include tin, ENIG, or OSP. A film layer is formed over the contact pad with an opening over the signal trace. An oxide layer is formed over the signal trace. The film layer and surface treatment prevent formation of the oxide layer over the contact pad. The film layer is removed. The solder bump is reflowed to metallurgically and electrically bond to the contact pad. In the event that the solder bump physically contacts the oxide layer, the oxide layer maintains electrical isolation between the solder bump and signal trace.09-24-2009
20090032940Conductor Bump Method and Apparatus - Various semiconductor die conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a conductor pad of a semiconductor die. The conductor layer has a surface. A polymeric layer is formed on the surface of the conductor layer while a portion of the surface is left exposed. A solder structure is formed on the exposed portion of the surface and a portion of the polymeric layer.02-05-2009
20130069228FLIP-CHIP PACKAGE STRUCTURE AND FORMING METHOD THEREOF - A flip-chip package structure comprising a substrate, a chip, a bump structure and a solder resist is provided. The substrate has a circuit layer disposed on the surface thereof. The chip comprises a central region and two edge regions disposed on the two sides of the central region. The bump structure is disposed on the central region of the chip and faces the substrate. The solder resist is disposed on the substrate to partially cover the circuit layer. The chip is electrically connected to the substrate by the bump structure, and the solder resist is adapted to come into contact with the two edge regions of the chip to support the chip with the bump structure when the chip is disposed on the substrate.03-21-2013
20080258300WIRING BOARD MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND WIRING BOARD - A semiconductor device 10-23-2008
20130134579Structure for High-Speed Signal Integrity in Semiconductor Package with Single-Metal-Layer Substrate - A semiconductor chip (05-30-2013
20090026611ELECTRONIC ASSEMBLY HAVING A MULTILAYER ADHESIVE STRUCTURE - An electronic device comprises a substrate and a number of bump units over the substrate, wherein each of the bump units includes an electrically insulating bump-forming body extending in a first direction, and at least two conductive layers separated from each other on the electrically insulating bump-forming body, the at least two conductive layers extending in a second direction orthogonal to the first direction.01-29-2009
20090026609Semiconductor device and method for manufacturing the same - A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.01-29-2009
20130134580Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump - A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.05-30-2013
20130161815SEMICONDUCTOR DEVICE - The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.06-27-2013
20090001571SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device in which a semiconductor element 01-01-2009
20120235296IC DEVICES HAVING TSVS INCLUDING PROTRUDING TIPS HAVING IMC BLOCKING TIP ENDS - A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to protruding TSV tips is on a portion of the sidewalls of protruding TSV tips. The passivation layers is absent from a distal portion of protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends which cover a portion of the TSV sidewalls, are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ≧25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.09-20-2012
20130161810SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resistance layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace.06-27-2013
201301618113D IC CONFIGURATION WITH CONTACTLESS COMMUNICATION - A package comprises a die stack having at least two stacked dies coupled for contactless communications with each other. At least one of the stacked dies has a substrate joined to its major face. The substrate has a plurality of conductive traces in or on the substrate for conducting power to the dies and for conducting heat from the dies. At least one conductive pillar is joined to at least one of the conductive traces on at least a first edge of the substrate, for conducting power to the at least one die and for conducting heat from the at least one die.06-27-2013
20110042803Method For Fabricating A Through Interconnect On A Semiconductor Substrate - A method for fabricating a through interconnect on a semiconductor substrate includes the steps of forming a via on a first side of the substrate part way through the substrate, forming an electrically insulating layer on the first side and in the via, forming an electrically conductive layer at least partially lining the via, forming a first contact on the conductive layer in the via, and thinning the substrate from a second side at least to the insulating layer in the via. The method can also include the step of forming a second contact on a second side of the substrate in electrical contact with the first contact. The method can be performed on a semiconductor wafer to form a wafer scale interconnect component. In addition, the interconnect component can be used to construct semiconductor systems such as a light emitting diode (LED) systems.02-24-2011
20110024903Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring - A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive through hole vias (THV) are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.02-03-2011
20110024900SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM - A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 μm may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region.02-03-2011
20090045508OBLONG PERIPHERAL SOLDER BALL PADS ON A PRINTED CIRCUIT BOARD FOR MOUNTING A BALL GRID ARRAY PACKAGE - Methods, systems, and apparatuses for ball grid array land patterns are provided. A ball grid array land pattern includes a plurality of land pads and electrically conductive traces. The plurality of land pads is arranged in an array of rows and columns. A perimeter edge of the array includes a pair of adjacent oblong shaped land pads. An electrically conductive trace is routed between the pair of adjacent oblong shaped land pads from a land pad positioned in an interior of the array to a location external to the array. The oblong shaped land pads are narrower than standard round land pads, and thus provide more clearance for the routing of traces. The oblong shaped land pads enable more land pads of the land pattern array to be routed external to the array on each routing layer, and thus can save printed circuit board component and assembly costs.02-19-2009
20100013092Semiconductor device and manufacturing method therefor - Provided is a semiconductor device having a bump structure which is capable of resolving inconvenience in mounting. The semiconductor device comprises: an electrode pad; and a columnar bump formed on the electrode pad, the columnar bump comprising: a first high melting point metal layer (01-21-2010
20110057311SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 03-10-2011
20080272487SYSTEM FOR IMPLEMENTING HARD-METAL WIRE BONDS - A wire bond system including providing an integrated circuit die with a bond pad thereon, forming a soft bump on the bond pad, and wire bonding a hard-metal wire on the soft bump.11-06-2008
20120153464LOCALIZED ALLOYING FOR IMPROVED BOND RELIABILITY - Methods of forming gold-aluminum electrical interconnects are described. The method may include interposing a diffusion retardant layer between the gold and the aluminum, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material; bringing into contact the diffusion retardant layer, the gold, and the aluminum; forming alloys of gold and the diffusion retardant material in regions containing the material and forming gold-aluminum intermetallic compounds in regions substantially devoid of the material; and forming a continuous electrically conducting path between the aluminum and the gold. A structure for gold-aluminum interconnect is provided. The structure may include an aluminum alloy bond pad and a diffusion retardant layer in contact with the bond pad, the diffusion retardant layer including regions containing and regions substantially devoid of a diffusion retardant material. The structure may include a gold free air ball in contact with the diffusion retardant layer.06-21-2012
20110037170ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREFOR - Reduction of the size of and enhancement of the reliability, mounting strength, and mounting reliability of a semiconductor module are achieved. The semiconductor module includes: a wiring substrate; an electronic component placed over the upper surface of the wiring substrate; an electronic component placed over the under surface of the wiring substrate; a lead placed over the under surface of the wiring substrate; and encapsulation resin covering the under surface of the wiring substrate including the electronic component and the lead. The lead includes: a first portion coupled to an electrode pad via a joining material; a second portion bent from the first portion; and a third portion bent from the second portion. The third portion is positioned closer to the peripheral edge portion side of the under surface of the wiring substrate than the first portion. At the same time, the third portion is arranged at a position farther from the under surface of the wiring substrate than the first portion. The third portion of the lead is exposed from the main surface and side surface of the encapsulation resin and functions as a terminal for external coupling.02-17-2011
20120286423Doping Minor Elements into Metal Bumps - A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.11-15-2012
20110101521POST PASSIVATION INTERCONNECT WITH OXIDATION PREVENTION LAYER - A copper interconnect line formed on a passivation layer is protected by a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof.05-05-2011
20120098127POWER/GROUND LAYOUT FOR CHIPS - Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.04-26-2012
20110278721Semiconductor Package and Method of Mounting Semiconductor Die to Opposite Sides of TSV Substrate - A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable.11-17-2011
20110278723SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.11-17-2011
20110278720SEMICONDUCTOR SUBSTRATE STRUCTURE AND SEMICONDUCTOR DEVICE - A semiconductor substrate structure includes an electrode pad formed on a semiconductor substrate, a protective film formed on the semiconductor substrate with a distance from the electrode pad, and a bump formed on the electrode pad. The protective film has a barrier portion surrounding the electrode pad. The barrier portion has a height different from a height of a part of the protective film other than the barrier portion.11-17-2011
20110278719DIRECTING THE FLOW OF UNDERFILL MATERIALS USING MAGNETIC PARTICLES - Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate and a die, and coupling the die to the substrate, wherein a gap remains between the die and the substrate. The method also includes placing an underfill material on the substrate and delivering at least part of the underfill material into the gap. The method also includes controlling the flow of the underfill material in the gap using magnetic force. Other embodiments are described and claimed.11-17-2011
20110278718ASSEMBLY OF MULTI-CHIP MODULES USING REFLOWABLE FEATURES - A multi-chip module (MCM) that includes at least two substrates, having facing surfaces, which are mechanically coupled by a set of coupling elements having a reflow characteristic, is described. One of the two substrates includes another set of coupling elements having another reflow characteristic, which is different than the reflow characteristic. These different reflow characteristics of the sets of coupling elements allow different temperature profiles to be used when bonding the two substrates to each other than when bonding the one of the two substrates to a carrier. For example, the temperature profiles may have different peak temperatures and/or different durations from one another. These reflow characteristics may facilitate low-cost, high-yield assembly and alignment of the substrates in the MCM, and may allow temperature-sensitive components to be included in the MCM.11-17-2011
20110278717Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die Into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.11-17-2011
20110079901Methods of Forming Back Side Layers For Thinned Wafers and Related Structures - A method of processing a wafer including a plurality of integrated circuit devices on a front side of the wafer, may include thinning the wafer from a back side opposite the front side. After thinning the wafer, a back side layer may be provided on the back side of the thinned wafer opposite the front side, and the back side layer may be configured to counter stress on the front side of the wafer including the plurality of integrated circuit devices thereon. After providing the back side layer, the plurality of integrated circuit devices may be separated. Related structures are also discussed.04-07-2011
20090315178CONDUCTIVE BUMP, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC COMPONENT MOUNTED STRUCTURE - A conductive bump formed on an electrode surface of an electronic component. This conductive bump is composed of a plurality of photosensitive resin layers having different conductive filler contents. Consequently, this conductive bump is able to realize conflicting functions, namely, improvement in adhesion strength with the electrode and reduction of contact resistance.12-24-2009
20110127669SOLDER STRUCTURE, METHOD FOR FORMING THE SOLDER STRUCTURE, AND SEMICONDUCTOR MODULE INCLUDING THE SOLDER STRUCTURE - The invention provides a solder structure which is least likely to develop Sn whiskers and a method for forming such a solder structure. The solder structure includes an Sn alloy capable of a solid-liquid coexistent state and an Au (or Au alloy) coating covering at least part of the surface of the Sn alloy. The Au covering is a film that covers and coats at least part of the surface of the Sn alloy. As a preferable mode, the Au coating forms a netlike structure on the surface of the Sn alloy. The thickness of the Au coating is, for instance, 1 to 5 μm.06-02-2011
20110140270SEMICONDUCTOR MOUNTING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor mounting substrate according to the present invention comprises: a substrate; a semiconductor device, mounted on this substrate; solder bumps, which connect the semiconductor device and the substrate; a first resin, filled in a space between the semiconductor device and the substrate; and electronic components, mounted on a face side of the semiconductor device where the semiconductor device is mounted, wherein bond strength reinforcing resin section is provided at least between a side face in the vicinity of a corner part of the semiconductor device and a substrate surface of the substrate in a position corresponding to the corner part.06-16-2011
20090315177Semiconductor package with joint reliability - A semiconductor package with improved joint reliability and a method of fabricating the semiconductor package are disclosed. A conductive connector may be formed on a surface of a semiconductor wafer on which semiconductor devices may be arranged. A first insulating layer including a first opening through which a portion of the connection pad is exposed may be formed on the connection pad and the semiconductor wafer. A rewiring line electrically connected to an exposed portion of the connection pad may be formed on the first insulating layer. A second insulating layer including a second opening through which a portion of the rewiring line is exposed may be formed on the rewiring line and the first insulating layer. A connection terminal including one or more entangled wires may be formed on an exposed portion of the rewiring line so as to be electrically connected to the rewiring line.12-24-2009
20090315176SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package of this invention includes external electrode pad 12-24-2009
20100171216ELECTRONIC DEVICE AND ELECTRONIC APPARATUS - An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.07-08-2010
20110285018MULTIPLE SELECTABLE FUNCTION INTEGRATED CIRCUIT MODULE - An integrated circuit module has a common function known good integrated circuit die with selectable functions. The selectable functions arc selected during packaging of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions. Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. Also, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module. The second level module substrate has connector pins to provide physical and electrical connections between the external circuitry and the wiring connections on the second level substrate.11-24-2011
20120187559Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress - An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.07-26-2012
20110101523PILLAR BUMP WITH BARRIER LAYER - A copper pillar bump has a surface covered with by a barrier layer formed of a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof. The barrier layer depresses the copper diffusion and reaction with solder to reduce the thickness of intermetallic compound between the pillar pump and solder.05-05-2011
20110298124Semiconductor Structure - A semiconductor structure is provided. By using a composite bump with replace of a gold bump, the consumption of gold can be reduced and the manufacturing cost can be decreased accordingly. Moreover, by using an encapsulation material formed on a metal layer, the heat transferring efficiency of the semiconductor structure can be improved and the stability thereof can be increased.12-08-2011
20120139107SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE USING THE CHIP - A semiconductor chip includes at least one electrode pad formed on a substrate; a protective film formed on the substrate and the electrode pad, and having an opening exposing the electrode pad; an under barrier metal layer formed on the electrode pad to cover an edge of the opening of the protective film; and a bump formed on the under barrier metal layer. A contact angle between the under barrier metal layer and the protective film is less than 90° at an edge of the under barrier metal layer. A contact angle between the bump and the under barrier metal layer is less than 90° at an edge of the bump.06-07-2012
20090206478FLIP CHIP DEVICE AND MANUFACTURING METHOD THEREOF - A flip chip device made using LCD-COG (liquid crystal display-chip on glass) technique. The flip chip device comprises a substrate, at least one chip having active area with a plurality of compliant bumps thereon. The compliant bumps are centrally disposed in the center of the chip for electrically connecting the chip and the substrate. An adhesive is daubed on a joint area of the substrate and the chips for jointing the substrate and the chips. By limiting the position of the compliant bumps so that they are centrally disposed on the chips, the thermal warpage of the substrate is reduced.08-20-2009
20120001326Semiconductor Package and Method of Forming Similar Structure for Top and Bottom Bonding Pads - A semiconductor device includes a first semiconductor die. A plurality of conductive vias is formed around the first semiconductor die. A first conductive layer is formed over a first surface of the first semiconductor die and electrically connects to the plurality of conductive vias. A second conductive layer is formed over a second surface of the first semiconductor die opposite the first surface and electrically connects to the plurality of conductive vias. A first passivation layer is formed over the first surface and includes openings that expose the first conductive layer. A second passivation layer is formed over the second surface and includes openings that expose the second conductive layer. Bonding pads are formed within the openings in the first and second passivation layers and are electrically connected to the first and second conductive layers. An interconnect structure is disposed within the openings in the first and second passivation layers.01-05-2012
20090091030SEMICONDUCTOR DEVICE, METHOD FOR MOUNTING SEMICONDUCTOR DEVICE, AND MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE - In order to realize a semiconductor device which is easily mounted on a circuit board and which has high mounting reliability, a semiconductor device 04-09-2009
20110285014PACKAGING STRUCTURE AND PACKAGE PROCESS - A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.11-24-2011
20110285016SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate and a stress generating film. A first surface of the substrate includes a protruding part at each of two end portions. The substrate includes a semiconductor element. The stress generating film is formed so as to come into contact with a second surface of the substrate that is opposite to the first surface of the substrate. The stress generating film is in a shape which causes a second stress that offsets at least a part of a first stress occurring as a result of bonding between an external substrate and the protruding part.11-24-2011
20110285017METHOD FOR PRODUCING AN OPTOELECTRONIC DEVICE AND OPTOELECTRONIC DEVICE - A method for producing an optoelectronic device includes providing a carrier, applying at least one first metal layer on the carrier, providing at least one optical component, applying at least one second metal layer on the at least one optical component, and mechanically connecting the carrier to the at least one optical component by the at least one first and the at least one second metal layer, wherein the connecting includes friction welding or is friction welding.11-24-2011
20110285015BUMP STRUCTURE AND FABRICATION METHOD THEREOF - There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.11-24-2011
20110285013Controlling Solder Bump Profiles by Increasing Heights of Solder Resists - A device includes a first work piece bonded to a second work piece. The first work piece includes a solder resist at a surface of the first work piece, wherein the solder resist includes a solder resist opening, and a bond pad in the solder resist opening. The second work piece includes a non-reflowable metal bump at a surface of the second work piece. A solder bump bonds the non-reflowable metal bump to the bond pad, with at least a portion of the solder bump located in the solder resist opening and adjoining the non-reflowable metal bump and the bond pad. A thickness of the solder resist is greater than about 50 percent a height of the solder bump, wherein the height equals a distance between the non-reflowable metal bump and the bond pad.11-24-2011
20110285011CU PILLAR BUMP WITH L-SHAPED NON-METAL SIDEWALL PROTECTION STRUCTURE - An L-shaped sidewall protection process is used for Cu pillar bump technology. The L-shaped sidewall protection structure is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer or combinations thereof.11-24-2011
20110291262Strength of Micro-Bump Joints - A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.12-01-2011
20110298123CU PILLAR BUMP WITH NON-METAL SIDEWALL SPACER AND METAL TOP CAP - A bump has a non-metal sidewall spacer on a lower sidewall portion of Cu pillar, and a metal top cap on a top surface and an upper sidewall portion of the Cu pillar. The metal top cap is formed by an electroless or immersion plating technique after the non-metal sidewall spacer formation.12-08-2011
20110285012Substrate Contact Opening - An under-bump metallization (UBM) structure for a substrate, such as an organic substrate, a ceramic substrate, a silicon or glass interposer, a high density interconnect, a printed circuit board, or the like, is provided. A buffer layer is formed over a contact pad on the substrate such that at least a portion of the contact pad is exposed. A conductor pad is formed within the opening and extends over at least a portion of the buffer layer. The conductor pad may have a uniform thickness and/or a non-planar surface. The substrate may be attached to another substrate and/or a die.11-24-2011
20090236742WIRE BONDING OVER ACTIVE CIRCUITS - A semiconductor device includes a semiconductor die mounted over a package substrate. The die has a bond pad located thereover. A stud bump consisting substantially of a first metal is located on the bond pad. A wire consisting substantially of a different second metal is bonded to the stud bump.09-24-2009
20110291272CHIP STRUCTURE - A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.12-01-2011
20110291267Semiconductor wafer structure and multi-chip stack structure - A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface. Hence, the reliability of multi-chip stack package structure can be enhanced with the application of these soft metal caps.12-01-2011
20110291271SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor chip such as an MMIC is provided. The semiconductor chip has: a Si semiconductor as a substrate; and a low-loss transmission line, and can be easily connected to a circuit board on which the semiconductor chip is to be mounted and can ensure a stable GND potential. The semiconductor chip is a flip-chip semiconductor chip, and includes: a Si substrate; an integrated circuit manufactured on a main surface of the substrate; a dielectric film formed above the integrated circuit; and a conductor film for grounding formed on an upper surface of the dielectric film. The integrated circuit includes a wiring layer including a signal line which transmits signals for the integrated circuit. The signal line, the dielectric film, and the conductor film constitute a microstrip line.12-01-2011
20110291268Semiconductor wafer structure and multi-chip stack structure - A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface. Hence, the reliability of multi-chip stack package structure can be enhanced with the application of these soft metal caps.12-01-2011
20110291270MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND MOUNTING STRUCTURE THEREOF - A semiconductor device with improved quality and reliability is provided. In a UBM formed over an electrode pad located over a semiconductor substrate, the edge (end) of an Au film as an upper layer is located inside or in the same position as the edge (end) of a TiW film as a lower layer, which can suppress the formation of a suspended part in the Au film. This arrangement can prevent the occurrence of electrical short circuit between the adjacent pads due to the suspended part and the adhesion of the suspended part as foreign matter to the semiconductor substrate, thus improving the quality and reliability of the semiconductor device (semiconductor chip).12-01-2011
20110291266SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A MULTI-CHIP STRUCTURE - A semiconductor integrated circuit having a multi-chip structure includes a plurality of stacked semiconductor chips. At least one of the semiconductor chips includes first and second metal layers separately formed inside the semiconductor chip, a first internal circuit coupled in series between the first and second metal layers inside the semiconductor chip, a first metal path vertically formed over the second metal layer to a first side of the semiconductor chip, and a first through silicon via formed through the semiconductor chip from a second side of the semiconductor chip to the first metal layer.12-01-2011
20110291265SEMICONDUCTOR INTEGRATED CIRCUIT HAVING A MULTI-CHIP STRUCTURE - A semiconductor integrated circuit having a multi-chip structure includes a number of stacked semiconductor chips. Each of the semiconductor chips includes a first through electrode formed through the semiconductor chip, a first bump pad formed over the semiconductor chip at a region where the first bump pad is separated from the first through electrode, a first internal circuit formed inside the semiconductor chip, coupled to the first through electrode through a first metal path, and coupled to the first bump pad through a second metal path; and a redistribution layer (RDL) formed over a backside of the semiconductor chip.12-01-2011
20110291264INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor wafer having a chip pad; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer; removing the horizontal cover exposing the underfill and the protruding connector; and singulating an integrated circuit package from the semiconductor wafer.12-01-2011
20110291263IC HAVING DIELECTRIC POLYMERIC COATED PROTRUDING FEATURES HAVING WET ETCHED EXPOSED TIPS - A method of fabricating IC die includes providing a substrate having a topside semiconductor surface including active circuitry and a bottomside surface. The IC die includes at least one protruding feature coupled to the active circuitry that protrudes from the bottomside surface or the topside semiconductor surface. The topside semiconductor surface and/or bottomside surface and the protruding feature are coated with a dielectric polymer. A portion of the dielectric polymer is removed from the protruding feature using a solvent to expose a tip portion of the protruding feature for electrical connection thereto. With a solvent that does not corrode or oxidize the exposed protruding feature tips, the need for a conventional subsequent chemical exposure to remove corrosion or oxidation is avoided.12-01-2011
20110291261THREE DIMENSIONAL STACKED PACKAGE STRUCTURE - An apparatus, system, and method are disclosed for connecting integrated circuit devices. A plurality of primary electrically conductive contacts and a plurality of primary electrically conductive pillars are electrically coupled to a primary integrated circuit device. The plurality of primary electrically conductive contacts form a pattern corresponding to secondary electrically conductive contacts disposed on one or more secondary integrated circuit devices. The plurality of primary electrically conductive pillars extends away from the primary integrated circuit device. The plurality of primary electrically conductive pillars forms a pattern that corresponds to substrate electrically conductive contacts that are disposed on a substrate. The plurality of primary electrically conductive pillars and associated connecting material provide a standoff height between the primary integrated circuit device and the substrate that is greater than or equal to a height of the one or more secondary integrated circuit devices.12-01-2011
20110291259Reliable metal bumps on top of I/O pads after removal of test probe marks - In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.12-01-2011
20100052159Methods of forming C4 metal stud bump for fine pitch packaging applications and structures formed thereby - Methods of forming microelectronic device structures are described. Those methods may include forming a passivation layer on a substrate, wherein the substrate comprises an array of conductive structures, forming a first via in the passivation layer, forming a second via in the passivation layer that exposes at least one of the conductive structures in the array, and wherein the second via is formed within the first via space to form a step via, and forming a conductive material in the step via, wherein a round dimple is formed in the conductive material.03-04-2010
20090079068METHODS FOR ATTACHING A FLIP CHIP INTEGRATED CIRCUIT ASSEMBLY TO A SUBSTRATE - A method for fabricating an integrated circuit assembly, comprises forming a conductive material pattern on a substrate using a process in which the conductive material in wet when formed, the conductive material pattern comprising contact points, before curing the conductive material, placing a integrated circuit comprising contact bumps on the substrate such that the bumps come in contact with the contact points of the conductive material pattern, and allowing the conductive material cure such that the conductive material forms a bond with the bumps.03-26-2009
20120098126SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 04-26-2012
20120098125INTEGRATED CIRCUIT PACKAGE AND PHYSICAL LAYER INTERFACE ARRANGEMENT - An integrated circuit (IC) package includes an IC chip and a package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The IC layered structure includes a first physical layer interface and a second physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The second physical layer interface includes a plurality of second bump pads and a plurality of second inner pads electrically connected to the second bump pads, respectively. The second bump pads are mirror images of the first bump pads with respect to a first geometric plane perpendicular to the active surface. The second inner pads are mirror images of the first inner pads with respect to the first geometric plane.04-26-2012
20120098122WAFER LEVEL PACKAGING OF MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) AND COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) SUBSTRATES - The embodiments of methods and structures for forming through silicon vias a CMOS substrate bonded to a MEMS substrate and a capping substrate provide mechanisms for integrating CMOS and MEMS devices that use less real-estate and are more reliable. The through silicon vias electrically connect to metal-1 level of the CMOS devices. Copper metal may be plated on a barrier/Cu-seed layer to partially fill the through silicon vias, which saves time and cost. The formation method may involve using dual dielectric layers on the substrate surface as etching mask to eliminate a photolithographical process during the removal of oxide layer at the bottoms of through silicon vias. In some embodiments, the through silicon vias land on polysilicon gate structures to prevent notch formation during etching of the vias.04-26-2012
20120098121CONDUCTIVE FEATURE FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.04-26-2012
20120098120CENTRIPETAL LAYOUT FOR LOW STRESS CHIP PACKAGE - A low-stress chip package is disclosed. The package includes two substrates. The first substrate includes an array of first conductive structures in the corner area of the chip, and an array of second conductive structures in the peripheral edge area of the chip. The first and second conductive structures each has a conductive pillar having elongated cross section in the plane parallel to the first substrate and a solder bump over the pillar. The package also includes a second substrate having an array of metal traces. The elongated pillars each form a coaxial bump-on-trace interconnect with a metal trace respectively. The long axis of the elongated cross section of a pillar in the corner area of the chip points to chip's center area, and the long axis of the elongated cross section of a pillar in chip's peripheral edge area aligns perpendicular to the edge.04-26-2012
20090008776Electronic Component Mounted Body, Electronic Component with Solder Bump, Solder Resin Mixed Material, Electronic Component Mounting Method and Electronic Component Manufacturing Method - In an electronic component mounted body, an electrode of a first electronic component and an electrode of a second electronic component are electrically connected by a solder connecter, and the solder connecter contains solder and insulation filler. Alternatively, a solder bump is formed on the electrode of the electronic component, and the solder bump includes the insulation filler.01-08-2009
20110186994INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a device through via and a device interconnect, over a substrate with the device through via traversing the integrated circuit and the device interconnect attached to the device through via; attaching a conductive support over the substrate with the conductive support adjacent to the integrated circuit; providing a pre-formed interposer, having an interposer through via and a pre-attached interconnect, with the pre-attached interconnect attached to the interposer through via; mounting the pre-formed interposer over the integrated circuit and the conductive support with the pre-attached interconnect over the device through via; and forming an encapsulation over the substrate covering the integrated circuit, the conductive support, and partially covering the pre-formed interposer.08-04-2011
20110204512Wirebondless Wafer Level Package with Plated Bumps and Interconnects - A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die is mounted using a die attach adhesive. In one embodiment, a top surface of the first semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die. An underfill material is disposed in the die cavity between the first semiconductor die and a surface of the die cavity. A passivation layer is disposed over the first semiconductor die and exposes a contact pad of the first semiconductor die. An encapsulant is disposed over the carrier strip.08-25-2011
20100007017INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD FOR THE SAME - The present invention discloses an inter-connecting structure for a semiconductor package and a method for the same. The inter-connecting structure for the semiconductor package comprises a substrate formed to support a die thereon; core paste formed on the substrate and adjacent to the die; and a stiffener formed in an upper portion of the core paste, wherein the hardness of the stiffener is larger than the hardness of the core paste.01-14-2010
20100078810SEMICONDUCTOR APPARATUS, SUBSTRATE DESIGN METHOD, AND SUBSTRATE DESIGN APPARATUS - A semiconductor apparatus including: a substrate; and a semiconductor chip mounted on the substrate, wherein the substrate has plural holes, and the plural holes are provided such that the density on a substrate surface of the holes in a first area, which is an area of the substrate facing a semiconductor chip peripheral portion, is higher than the density on the substrate surface of the holes in an area excluding the first area on the substrate.04-01-2010
20090140419EXTENDED PLATING TRACE IN FLIP CHIP SOLDER MASK WINDOW - A flip chip in accordance with an exemplary embodiment of the present invention has a ball grid array and a die disposed on the ball grid array, wherein the ball grid array includes conducting pads disposed under the die. Traces connecting conducting pads under the die are accessible to leads on the die by way of a solder mask window. These traces continue through the solder mask window and extend out to the border of the ball grid array and are used for both signaling purposes and electroplating purposes.06-04-2009
20120032322FLIP CHIP PACKAGE UTILIZING TRACE BUMP TRACE INTERCONNECTION - A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.02-09-2012
20120032324SEMICONDUCTOR DEVICE - A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.02-09-2012
20130009303Connecting Function Chips To A Package To Form Package-On-Package - A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of bond-on-trace connections, and a second function chip on top of the first function chip, directly connected to the substrate. Another package-on-package (PoP) comprises: a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of solder mask defined (SMD) connections formed on SMD bonding pads connected to solder bumps, and a second function chip on top of the first function chip, directly connected to the substrate by a plurality of bond-on-trace connections.01-10-2013
20090278255SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a terminal portion formed on a surface of the substrate.11-12-2009
20090085203Method for Exchanging Semiconductor Chip of Flip-Chip Module and Flip-Chip Module Suitable Therefor - A process for replacing a semiconductor chip of such a flip-chip module and a suitable flip-chip module and an apparatus for implementing the method are disclosed. The flip-chip module comprises at least one semiconductor chip and a substrate. The semiconductor chip comprises contact posts on a surface that are disposed at right angles to the surface. With these contact posts it is connected with contact points of the substrate via a soldered connection. The contact posts completely cover the contact points with their end faces. Due to this it is possible to completely press the solder between the contact posts and contact points out of the intermediate area between the contact points and the contact posts after a renewed heating. This permits a renewed attachment of a further semiconductor chip.04-02-2009
20090230551SEMICONDUCTOR DEVICE - The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved.09-17-2009
20110169160REAL TIME MONITORING OF INDIUM BUMP REFLOW AND OXIDE REMOVAL ENABLING OPTIMIZATION OF INDIUM BUMP MORPHOLOGY - A method, apparatus, system, and device provide the ability to form one or more solder bumps on one or more materials. The solder bumps are reflowed. During the reflowing, the solder bumps are monitored in real time. The reflow is controlled in real time, thereby controlling a morphology of each of the solder bumps. Further, the wetting of the solder bumps to a surface of the materials is controlled in real time.07-14-2011
20120187558STRUCTURES FOR IMPROVING CURRENT CARRYING CAPABILITY OF INTERCONNECTS AND METHODS OF FABRICATING THE SAME - Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.07-26-2012
20090189279METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS - Methods of packaging integrated circuits are described. One method relates to attaching a singulated device wafer to a substrate. The singulated device wafer includes a multiplicity of integrated circuit dice arranged in a first configuration. The method also involves a substrate, which includes a sacrificial semiconductor wafer having device areas with metalized contacts. The device areas on the substrate may be arranged in a configuration matching that of the dice on the device wafer. The method also entails aligning the singulated device wafer as a whole with the substrate so that the dice of the device wafer are positioned substantially simultaneously over associated device areas on the substrate. The method also involves attaching the dice from the singulated wafer as a whole substantially simultaneously to the substrate such that each die of the device wafer is attached to an associated device area of the substrate.07-30-2009
20100065964COPPER-TOPPED INTERCONNECT STRUCTURE THAT HAS THIN AND THICK COPPER TRACES AND METHOD OF FORMING THE COPPER-TOPPED INTERCONNECT STRUCTURE - A copper-topped interconnect structure allows the combination of high density design areas, which have low current requirements that can be met with tightly packed thin and narrow copper traces, and low density design areas, which have high current requirements that can be met with more widely spaced thick and wide copper traces, on the same chip.03-18-2010
20100176509SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes: a mount body; a semiconductor chip mounted on the mount body via projecting connecting terminals; and a filling resin filled between the mount body and the semiconductor chip to seal the connecting terminals, the filling resin being retained inside the semiconductor chip in such a way as not to run out of at least one side portion in four side portions defining an outer peripheral portion of the semiconductor chip.07-15-2010
20090121352MUTLI-PACKAGE MODULE AND ELECTRONIC DEVICE USING THE SAME - A package substrate for a multi-package module. The package substrate comprises a substrate having a die region and at least one thermal channel region outwardly extending to an edge of the substrate from the die region. An array of bumps is arranged on the substrate except in the die and thermal channel regions, in which the interval between the bumps is narrower than the width of the thermal channel region. An electronic device with a package substrate is also disclosed.05-14-2009
20090121351Process for forming a bump structure and bump structure - A method for forming a bump structure and a bump structure for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon, used as an electric connection in an electronic circuit, includes the steps of forming a mandrel by steps including forming at least one opening extending through a bump-forming die body in the thickness direction thereof and positioning a bump-forming die lid on a surface of the bump-forming die body so as to cover one end of the opening and to thereby define a bump-forming recess. The bump-forming die body may be comprised of a metal sheet. A metal layer is formed at least on an inner surface of the bump-forming die lid exposed within the bump-forming recess. The mandrel is removed so as to expose the metal layer and form a bump structure.05-14-2009
20090152715Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die Having Pre-applied Protective Layer - A semiconductor device is made by first forming a protective layer over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.06-18-2009
20090152716WIRING SUBSTRATE AND ELECTRONIC COMPONENT MOUNTING STRUCTURE - A wiring substrate on which an electronic component is flip-chip bonded, including a substrate main body, a solder resist which is formed on the substrate main body and having an opening, and a plurality of conductive pattern formed on the substrate main body, including exposure surfaces exposed from the opening of the solder resist. The conductive patterns include, a narrow interval group, a wide interval group, an interval between the adjacent conductive patterns belonging to the narrow interval group is narrower than an interval between the adjacent conductive patterns belonging to the wide interval group, an exposure length of the conductive patterns of the narrow interval group is shorter than an exposure length of the conductive patterns of the wide interval group.06-18-2009
20080237853SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A conventional semiconductor device has a problem that reduction of a resistance value above a pad electrode is difficult because of an oxide film formed on a surface of the pad electrode. In a semiconductor device of this invention, an oxidation preventing metal layer is formed on a pad electrode, and the oxidation preventing metal layer is exposed at an opening region formed in a spin coat resin film at a portion above the pad electrode. In addition, a plating metal layer and a copper plated layer are formed on the oxidation preventing metal layer. With this structure, the resistance value above the pad electrode is reduced because the top surface of the pad electrode is difficult to oxidize, and the oxidation preventing metal layer having considerably smaller sheet resistivity than an oxidation film serves as part of a current path.10-02-2008
20100123245Semiconductor integrated circuit devices and display apparatus including the same - A semiconductor integrated circuit device includes: an electrostatic discharge (ESD) impurity region formed in a substrate; a bump formed on the substrate; and a first wiring layer and a second wiring layer formed at the same level under the bump. The first and second wiring layers are separated from each other, and at least part of each of the first and second wiring layers are overlapped by the bump. The first wiring layer is electrically connected to the ESD impurity region and the bump, and the second wiring layer is insulated from the bump.05-20-2010
20090315179SEMICONDUCTOR DEVICE HAVING SOLDER BUMPS PROTRUDING BEYOND INSULATING FILMS - A semiconductor device having projection electrodes with a narrow pad pitch, and a method of forming such semiconductor device, are provided. On a semiconductor wafer, a polyimide film, which does not cover each of a plurality of lands, is prepared between the respective lands which adjoin each other among the plurality of lands on the main surface of the semiconductor wafer. A soldering paste material is applied by a printing method, via a mask for printing, on each of a plurality of lands after polyimide film formation, and a solder bump is formed by performing heat curing of the soldering paste material after removing the mask for printing. The solder bump can be provided without generating an electric short circuit between bumps even in the case of a narrow pad pitch.12-24-2009
20090085205METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT PACKAGE AND ELECTRONIC COMPONENT PACKAGE - A manufacturing method of an electronic component package, includes: forming electrode pads on a main surface of a first electronic component; forming first bonding wires shaped in loop so as to be electrically connected with the electrode pads and elongated upward from the electrode pads and such that both ends of the first bonding wires are on the electrode pad, respectively; forming a resin layer over the main surface of the first electronic component so as to embed the first bonding wires; removing the resin layer so as to expose ends of the first bonding wires from the resin layer and removing the end of each of the first bonding wires so that two wires are elongated from on each of the electrode pads; and forming a metallic layer on the surface of the resin layer after removing so that the first bonding wires are electrically connected with the metallic layer.04-02-2009
20080303143Microelectronic Die Including Locking Bump and Method of Making Same - A microelectronic die and a method of providing same. The die includes a die substrate having an active surfaces and a locking bump on the active surface of the die substrate. The locking bump defines a recess adapted to receive therein a solder bump of a package substrate such that an apex of the solder bump contacts a bottom of the recess.12-11-2008
20080284013METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: when bonding a bump of an IC chip to a bonding position of a wiring pattern that is formed on an insulating film base member and has a surface covered by a plating layer, forming a plating layer around the bonding position among the wiring pattern at least in an outer peripheral section of a peeled surface of a portion of the wiring pattern peeled from the film base member.11-20-2008
20080265413SEMICONDUCTOR CHIP WITH POST-PASSIVATION SCHEME FORMED OVER PASSIVATION LAYER - The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns10-30-2008
20080265412Semiconductor device and method of manufacturing thereof - A package substrate has wires that electrically connect a semiconductor chip, and surface side terminals that are solid cylindrical and whose one ends are electrically connected to the wires. The semiconductor chip is sealed by a sealing resin. A surface of the sealing resin is made to be a same height (a same surface) as end surfaces of other ends of the surface side terminals, by grinding, from a surface, a resin layer that is formed by molding so as to cover the semiconductor chip. The surface of the sealing resin is a ground surface formed by grinding. The end surfaces of the surface side terminals are exposed at the ground surface of the sealing resin.10-30-2008
20080265411Structure of packaging substrate and method for making the same - A structure of a packaging substrate and a method for making the same are disclosed, wherein the structure comprises: a substrate body having a circuit layer on the surface thereof, wherein the circuit layer has a plurality of conductive pads which are each formed in a flat long shape to enhance the elasticity of circuit layout; a solder mask disposed on the substrate body and having a plurality of openings corresponding to and exposing the conductive pads, wherein the openings are each formed in a flat long shape; and a metal bump disposed in each of the openings of the solder mask and on each of the corresponding conductive pads.10-30-2008
20090001568Wafer-level solder bumps - In one embodiment, the present invention includes a semiconductor package having a support substrate coupled to a first semiconductor die, where the first semiconductor die includes first conductive bumps, and a second semiconductor die includes second conductive bumps, and where the first and second die are coupled by joints formed of the first and second conductive bumps and a solder material therebetween. Other embodiments are described and claimed.01-01-2009
20100123243FLIP-CHIP CHIP-SCALE PACKAGE STRUCTURE - The present invention relates to a flip-chip chip-scale package structure, and more particularly to a flip-chip chip-scale package structure with high thermal and electrical performance. The flip-chip chip-scale package structure comprising: a die, a substrate, and a metal ribbon. The die comprises a back-side metal and a plurality of bond pads. The die is bonded to the substrate by a plurality of bumps. The metal ribbon is bonded to the back-side metal by way of metal diffusion bonding. By using the package structure of the present invention, it provides high thermal and electrical performance for semiconductor devices.05-20-2010
20090315175ELECTRODE STRUCTURE AND SEMICONDUCTOR DEVICE - In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 12-24-2009
20100140799Extended Redistribution Layers Bumped Wafer - A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.06-10-2010
20100140796Manufacturing method of semiconductor device, and semiconductor device - A manufacturing method of a semiconductor device includes a first to fourth steps. The first step includes a step of determining an UBM (Under Bump Metal) radius of an UBM of a chip. The second step includes a step of determining a first curvature radius of a solder bump formed on the UBM. The third step includes a step of determining a SRO (Solider Resist Opening) radius of a SRO of a substrate such that a ratio of the SRO radius to the UMB radius is in a range from 0.8 to 1.2. The fourth step includes a step of determining a second curvature radius of a spare solder formed on an electrode in the SRO such that the second curvature radius is equal to or more than the first curvature radius.06-10-2010
20090302467ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, CIRCUIT BOARD MOUNTED WITH THE SAME, AND ELECTRONIC APPLIANCE COMPRISING THE CIRCUIT BOARD - An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device having a semiconductor chip with electrodes, a stress-relieving layer prepared on the semiconductor chip, a wire formed across the electrodes and the stress-relieving layer, and solder balls formed on the wire over the stress-relieving layer; and a bare chip as a second semiconductor device to be electrically connected to the first semiconductor device.12-10-2009
20090309217FLIP-CHIP INTERCONNECTION WITH A SMALL PASSIVATION LAYER OPENING - A flip-chip electrical coupling (12-17-2009
20090309218SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - When a through-hole electrode and a rear-surface wire are formed on a rear surface of a chip, a convex portion is formed on the rear surface of the chip due to a rear-surface wiring pad which is a part of the through-hole electrode and the rear-surface wire. This causes the air leakage when the chip is sucked, and therefore, the reduction of the sucking force of the chip occurs. A concave portion is formed in advance in a region where a rear-surface wiring pad and a rear-surface wire are formed. The rear-surface wiring pad and the rear-surface wire are provided inside the concave portion. Thus, a flatness of the rear surface of the chip is ensured by a convex portion caused by thicknesses of the rear-surface wiring pad and the rear-surface wire, so that the reduction of the sucking force does not occur when the chip is handled.12-17-2009
20090309216WAFER LEVEL PACKAGE AND MANUFACTURING METHOD THEREOF - A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.12-17-2009
20080284009Dimple free gold bump for drive IC - A conductive bump structure for an integrated circuit (IC) structure comprises a passivation layer, such as a silicon oxide/silicon nitride stack, that is formed on an upper surface of each of the conductive contact pads (e.g. Al pads) of the IC. A plurality of openings extend through the passivation layer to expose areas of the upper surface of the contact pad. The openings are larger in the longitudinal dimension than in the lateral dimension. A conductive bump, preferably comprising gold (Au), is formed on the passivation layer to extend through the openings in the passivation and into electrical contact with the exposed upper surface areas of the contact pad.11-20-2008
20100007019Semiconductor Device and Method of Forming Composite Bump-on-Lead Interconnection - A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu-OSP can be formed over the substrate.01-14-2010
20110147923Surface Mounting Integrated Circuit Components - An electronic apparatus may include a first component solder bonded to a second component. The first component may be, for example, an integrated circuit. The first component may have an array of metallic protrusions. Those protrusions may be coupled to circuit elements within said first component. The second component may include a plurality of solder portions coupled to the second component and engaged by the protrusions on the first component in a soldered connection.06-23-2011
20090289360WORKPIECE CONTACT PADS WITH ELEVATED RING FOR RESTRICTING HORIZONTAL MOVEMENT OF TERMINALS OF IC DURING PRESSING - A method of forming an electronic assembly including a plurality of IC die having bonding terminals that have a solderable material thereon and a workpiece. The workpiece includes workpiece contact pads including an elevated ring having a ring height at least 5 μm above a minimum contact pad height in an indented bonding region that is within the elevated ring. The bonding terminals and/or the plurality of workpiece contact pads include solder thereon. A plurality of IC die are mounted on the workpiece. Heat is applied so that the solder becomes tacky while remaining below its melting temperature to obtain a tacked position. The plurality of IC die are pressed using a pressing tool to heat the solder to a peak temperature that is above the melting temperature. The elevated ring resists horizontal movement of the plurality of IC die from their tacked positions during pressing.11-26-2009
20090267229CHIP PACKAGE STRUCTURE - A chip package structure is provided. The chip package structure comprises different layers of leads electrically connected to different circuits of a chip. The chip package structure comprises a chip and a flexible substrate layer. The chip has an active surface, a plurality of first pads, and a plurality of second pads. The first pads and the second pads are disposed on the active surface. The flexible substrate layer has a first conductive layer, a second conductive layer, a first surface, and a second surface opposite the first surface. The flexible substrate layer has an opening defined therein. The first conductive layer is formed on the first surface of the flexible substrate layer. The first conductive layer includes a plurality of first leads. The first leads electrically connect to the first pads. The second conductive layer is formed on the second surface of the flexible substrate layer. The second conductive layer includes a plurality of second leads. The second leads extend inwards into the opening and electrically connect to the second pads through the opening.10-29-2009
20110062584THREE-DIMENSIONALLY INTEGRATED SEMICONDUTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A wiring substrate has, on each of opposite faces thereof, connection pad portions to which various circuit elements are connected, and wiring traces for connecting the connection pad portions. The wiring substrate also has a through wiring portion for establishing mutual connection between the connection pad portions and the wiring traces on the front face and those on the back face. A post electrode component is formed such that it includes a plurality of post electrodes supported by a support portion. A semiconductor chip is attached to the back face of the wiring substrate, and is connected to the connection pad portions on the back face. After the post electrode component is fixed to and electrically connected to the wiring traces at predetermined positions, and resin sealing is performed, the support portion is separated so as to expose end surfaces of the post electrodes or back face wiring traces connected thereto. Another circuit element is disposed on the front face of the wiring substrate, and is connected to the connection pad portions on the front face.03-17-2011
20110062583STACKED DIE PACKAGE FOR PERIPHERAL AND CENTER DEVICE PAD LAYOUT DEVICE - An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.03-17-2011
20110062582Display device - A display device includes a display panel, and a semiconductor chip having plural bump electrodes and mounted on a substrate constituting the display panel. The plural bump electrodes include a first bump electrode arranged in the vicinity of a center for a longitudinal direction of the semiconductor chip, and a second bump electrode arranged in the vicinity of an end portion in the longitudinal direction of the semiconductor chip. The semiconductor chip has one or more than one conductive layer inside. Assuming that a surface of the semiconductor chip having the bump electrodes formed thereon is a lower side, the number of the conductive layers formed on the second bump electrode is greater than the number of the conductive layers formed on the first bump electrode. The conductive layer formed on the first and the second bump electrode includes a dummy conductive layer. Further, the plural bump electrodes are electrically connected to a wiring layer formed on a substrate constituting the display panel through an anisotropic conductive film.03-17-2011
20110062581SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes to and extend laterally in opposite directions so as to define a zigzag arrangement together.03-17-2011
20110062580PROTECTION LAYER FOR PREVENTING UBM LAYER FROM CHEMICAL ATTACK AND OXIDATION - A protection layer formed of a CuGe03-17-2011
20100007015INTEGRATED CIRCUIT DEVICE WITH IMPROVED UNDERFILL COVERAGE - An integrated circuit device (01-14-2010
20090206477SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer comprises an lamination surface to which another wafer is laminated; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another surface so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit and is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion so as to protrude from the lamination surface with a height equal to or larger than that of the protruding connection portion.08-20-2009
20090206476CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT - A conductive structure for a semiconductor integrated circuit is provided. The semiconductor integrated circuit comprises a pad, and a passivation layer partially overlapping the pad, which jointly define an opening portion. The conductive structure is adapted to be electrically connected to the pad through the opening portion. The conductive structure comprises an under bump metal (UBM). A first conductor layer formed on the under bump metal is electrically connected to the under bump metal. A second conductor layer formed on the first conductor layer and electrically connected to the first conductor layer and a cover conductor layer. Furthermore, the under bump metal, the first conductor layer, and the second conductor jointly define a basic bump structure. The cover conductor layer is adapted to cover the basic bump structure.08-20-2009
20090091027Semiconductor package having restraining ring surfaces against soldering crack - A semiconductor package with crack-restraining ring surfaces is revealed, primarily comprising a chip carrier, a chip disposed on the chip carrier, and a plurality of belfry-like bumps. The belfry-like bumps are disposed on a plurality of corresponding conductive pads on the bottom surface of the chip carrier as external terminals. Each belfry-like bump has at least a crack-restraining ring surface parallel to the conductive pads and between the top of the belfry-like bump and the conductive pad to prevent the spreading of the soldering cracks and to enhance the soldering strengths at the micro contacts to achieve higher package reliability.04-09-2009
20120091575Semiconductor Package And Method For Making The Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, at least one first chip, a dielectric layer and at least one second chip. The first chip is attached and electrically connected to the substrate. The first chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The dielectric layer is disposed on the first active surface. The second chip is attached and electrically connected to the substrate by metal bumps. The second chip includes a second active surface and a plurality of second signal coupling pads. The second active surface contacts the dielectric layer. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap between the first signal coupling pads of the first chip and the second signal coupling pads of the second chip is controlled by the thickness of the dielectric layer. Therefore, the mass-production yield of the semiconductor package is increased.04-19-2012
20080296759SEMICONDUCTOR PACKAGES - A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via.12-04-2008
20090091025METHOD FOR FORMING AND RELEASING INTERCONNECTS - A method for forming and releasing interconnects by using a dummy substrate. The method comprises applying metallization to the dummy substrate for creating a relatively strong bond between the metallization and the dummy substrate and a weak bond between a first end of each of the interconnects and the metallization; weakly bonding the first ends to the metallization; shaping the interconnects; releasing the weak bond between the metallization and the first ends by using a reduced release force to release the first end of the interconnects from the dummy substrate.04-09-2009
20090091028SEMICONDUCTOR DEVICE AND METHOD OF BUMP FORMATION - A semiconductor device including a semiconductor substrate, a contact pad, a passivation layer, a bump, and a seeding layer is provided. The semiconductor substrate has an active surface. The contact pad is disposed on the active surface. The passivation layer is disposed on the active surface and exposes a central part of the contact pad. The seeding layer is disposed on the exposed central part of the contact pad. The bump has a top surface, a bottom surface opposite to the top surface, and a side surface connecting the top surface and the bottom surface. The bump is disposed on the seeding layer. The bump is placed in contact with the seeding layer by the bottom surface and by part of the side surface.04-09-2009
20090091029SEMICONDUCTOR PACKAGE HAVING MARKING LAYER - The symbolization of a semiconductor device (04-09-2009
20090091026Stackable semiconductor package having plural pillars per pad - A stackable semiconductor package is revealed, primarily comprising a chip carrier, a chip, and a plurality of bottom bump sets. The chip carrier has a plurality of stacking pads disposed on the top surface and a plurality of bump pads on the bottom surface. The chip is disposed on and electrically connected to the chip carrier. The bottom bump sets are disposed on the corresponding bump pads and each consists of a plurality of conductive pillars. Solder-filling gaps are formed between the adjacent conductive pillars for filling and holding solder paste so that the soldering area can be increase and the anchoring effect can be enhanced due to complicated the soldering interfaces to achieve higher soldering reliability and less cracks at the soldering interfaces.04-09-2009
20090283906SEMICONDUCTOR DEVICE, METHOD FOR MOUNTING SEMICONDUCTOR DEVICE, AND MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes a semiconductor substrate on which an electrode and a Cu bump are stacked, and on the electrode and the Cu bump, a metal bump layer is provided, in which (i) a solder layer via which the semiconductor device is bonded and electrically connected to the mounting substrate by metal bonding and (ii) a Cu layer, an intermetallic compound being formed by interdiffusion of the Cu layer and the solder layer are included. Hence, the present semiconductor device can be mounted with a high bonding strength while avoiding a decrease in mounting reliability, by flip chip mounting by means of metal bonding.11-19-2009
20080211092ELECTRONIC ASSEMBLY HAVING A MULTILAYER ADHESIVE STRUCTURE - An electronic assembly comprising a first substrate, a number of bonds on the first substrate, a second substrate spaced apart from the first substrate, a number of bumps on the second substrate, each of the bumps including an insulating body and a conductive portion, the conductive portion extending from a top surface of the insulating body via at least one sidewall of the insulating body toward the second substrate, and an adhesive between the first substrate and the second substrate, the adhesive including an insulating layer and a conductive layer, the insulating layer and the conductive layer being laminated with respect to each other, wherein the insulating layer is positioned closer to the first substrate than the conductive layer.09-04-2008
20100123244Semiconductor device and method of manufacturing the same - Provided are a semiconductor device capable of reducing stress due to a density difference in the arrangement of bumps, and a method of manufacturing the semiconductor device. The semiconductor device includes: a wiring board including an electrode terminal group; a semiconductor chip including a bump formation surface where a bump group is formed and being mounted on the wiring board by using the bump group. The bump formation surface includes a first region where an area density of a region having bumps arranged therein is a first density, a second region where an area density of a region having bumps arranged therein is a second density lower than the first density, and a third region provided in a border portion between the first and second regions. In the third region, an area density of a region having bumps arranged therein is above the second density and below the first density.05-20-2010
20090273079SEMICONDUCTOR PACKAGE HAVING PASSIVE COMPONENT BUMPS - A semiconductor package includes contact bumps configured as passive circuit components. One or more contact bumps of the semiconductor package may be formed or configured as pull-up resistors, pull-down resistors, capacitors or inductors.11-05-2009
20090273080DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME - A display device includes a drive circuit chip, and a substrate on which the drive circuit chip is mounted. The drive circuit chip includes a semiconductor substrate, an insulation layer, a first conductive layer and a second conductive layer formed of metal between the semiconductor substrate and the insulation layer, and a first bump and a second bump formed over the insulation layer. The first bump is superposed with the first conductive layer, and a profile of the first bump in plan view is within a profile of the first conductive layer in plan view. The second bump is superposed with the second conductive layer, and a profile of the second pump in plan view is beyond a profile of the second conductive layer in plan view.11-05-2009
20110198750SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING SAME, ELECTRODE STRUCTURE OF SEMICONDUCTOR CHIP AND METHOD FOR FORMING SAME, AND SEMICONDUCTOR DEVICE - A semiconductor chip according to the present invention includes a semiconductor substrate, a bump of a metal projecting from a surface of the semiconductor substrate, and an alloy film covering the entire surface of the bump, the alloy film being composed of an alloy of the metal of the bump and a second metal.08-18-2011
20110198749Semiconductor chip package and method of manufacturing the same - Provided are a semiconductor chip package and a method of manufacturing the same. The semiconductor chip package includes a semiconductor chip comprising a chip pad, and a rerouting layer disposed on the semiconductor chip and including a metal interconnection electrically connected to the chip pad and a partial oxidation region formed by the oxidation of metal and insulating the metal interconnection.08-18-2011
20110198748Semiconductor device and method of fabricating same - A method of fabricating a semiconductor device includes: forming a semiconductor chip portion having an electrode on a main surface of a wafer; forming a first resist pattern having a first opening on the electrode; filling the first opening with a first electrically conductive material, thereby forming an electrically conductive post; removing the first resist pattern after said forming of the electrically conductive post; forming an interlayer dielectric film having a second opening positioned on the electrically conductive post; and forming an electrically conductive redistribution layer extending from an upper surface of the electrically conductive post over an upper surface of the interlayer dielectric film.08-18-2011
20110198747CONDUCTIVE PILLAR STRUCTURE FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - A semiconductor component formed on a semiconductor substrate is provided. The semiconductor substrate has a first surface and a second surface. The semiconductor substrate includes a plurality of devices on the first surface. A plurality of through silicon vias (TSVs) in the semiconductor substrate extends from the first surface to the second surface. A protection layer overlies the devices on the first surface of the semiconductor substrate. A plurality of active conductive pillars on the protection layer have a first height. Each of the active conductive pillars is electrically connected to at least one of the plurality of devices. A plurality of dummy conductive pillars on the protection layer have a second height. Each of the dummy conductive pillars is electrically isolated from the plurality of devices. The first height and the second height are substantially equal.08-18-2011
20090294959Semiconductor package device, semiconductor package structure, and fabrication methods thereof - A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.12-03-2009
20120193787MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A rewiring is formed by forming a Cu seed layer of copper over an opening and insulating films, forming a photoresist film over the Cu seed layer, a step of forming copper film by plating-growth over the Cu seed layer, and forming a Ni film. After forming an Au film in an opening (pad region) over the rewiring, the photoresist film is removed and passivation processing is performed on the Ni film. Then, the Cu seed layer other than the formation region of the rewiring is etched. According to these steps, a passivation film is formed on the surface of the Ni film and the reduction in film thickness of the Ni film by the etching can be reduced. Furthermore, it is possible to reduce trouble due to distortion of a substrate resulting from an increase in thickness of the Ni film in view of reduction in film thickness.08-02-2012
20090283905CONDUCTIVE STRUCTURE OF A CHIP - A conductive structure of a chip is provided. The conductive structure comprises a ground layer, a dielectric layer, a redistribution layer, an under bump metal and a solder bump. The ground layer electrically connects to the ground pad of the chip, while the dielectric layer overlays the ground layer. Thus, the conductive layer can result in impedance matching, and the packaged chip is adapted to transmit a high frequency signal.11-19-2009
20120193784METHOD FOR JOINING BONDING WIRE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for joining a bonding wire, the method including wedge-joining a bonding wire which has a core whose main component is a non-noble metal and a noble metal layer covering the core to a bump formed on an electrode of a semiconductor element via the noble metal layer.08-02-2012
20130099374PACKAGE OF ELECTRONIC DEVICE INCLUDING CONNECTING BUMP, SYSTEM INCLUDING THE SAME AND METHOD FOR FABRICATING THE SAME - A package of an electronic device, a system including the same and a method for fabricating the same are provided. The package of the electronic device includes a substrate, a step difference layer and a connecting bump. The substrate allows a connecting contact part to be exposed on a surface thereof. The step difference layer covers the substrate so as to leave the connecting contact part exposed. The connecting bump is connected to the connecting contact part so that one end part of the connecting bump is extended on the step difference layer, and has a sloped upper surface formed by a step difference formed by the step difference layer.04-25-2013
20130099376MICROELECTRONIC PACKAGES WITH DUAL OR MULTIPLE-ETCHED FLIP-CHIP CONNECTORS - A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.04-25-2013
20130099379SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT SUBSTRATE, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT - A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.04-25-2013
20090289361SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes at least a wiring board, a semiconductor chip that is mounted on one face side of the wiring board, connection pads that are formed on the one face side of the wiring board, and connect through bonding wires to electrode pads on the semiconductor chip, and bumps disposed on another face side of the wiring board; the semiconductor chip is disposed such that four chip sides face corners of the wiring board, and each chip corner is near one of the outer peripheral sides of the wiring board; and, on one face of the wiring board are provided corner regions which are enclosed by the chip sides of the semiconductor chip and the corners of the wiring board, and the connection pads are disposed in these corner regions.11-26-2009
20090289358SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SUBSTRATE - A semiconductor device includes a substrate and a plurality of bumps. The substrate is compartmentalized into a bump-free area provided along four sides of the substrate and a bump area which is surrounded by the bump-free area. The plurality of bumps is aligned in the bump area. The plurality of bumps includes a first group of bumps aligned along the four sides and a second group of bumps surrounded by the first group. A first subgroup of bumps included in the first group and aligned along one side of the four sides is shifted with respect to a second subgroup of bumps included in the first group and aligned along an opposing side of the four sides in a direction parallel to the one side.11-26-2009
20090289357SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor element includes: a substrate having an integrated circuit; and a wire connection electrode and a bump connection electrode which are provided on a same main surface of the substrate as electrodes having a same connection function to the integrated circuit. The wire connection electrode is provided in a periphery of the main surface. The bump connection electrode is provided inside the wire connection electrode on the main surface. When a straight line dividing the main surface into two regions is determined, the wire connection electrode and the bump connection electrode are located opposite to each other with respect to the straight line.11-26-2009
20090289356Wirebondless Wafer Level Package with Plated Bumps and Interconnects - A semiconductor package includes a carrier strip having a die cavity and a plurality of bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip using a die attach adhesive. In one embodiment, a top surface of the semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. Underfill material is deposited into the die cavity between the semiconductor die and a surface of the die cavity. In one embodiment, a passivation layer is deposited over the semiconductor die, and a portion of the passivation layer is etched to expose a contact pad of the semiconductor die. A metal layer is deposited over the package. The metal layer forms a package bump and a plated interconnect between the package bump and the contact pad of the semiconductor die. Encapsulant is deposited over the semiconductor package.11-26-2009
20100283149STRUCTURE AND METHOD OF FORMING A PAD STRUCTURE HAVING ENHANCED RELIABILITY - A semiconductor substrate is provided having a first metal layer formed over a first insulating layer. A second insulating layer is formed having a first damascene opening, the first opening having a second insulating layer portion formed therein. A resist layer is deposited to fill the first opening and the resist layer is thereafter patterned to form an etching mask for etching a second damascene opening. The second opening is etched into a portion of the second insulating layer, the second opening exposing a portion of the first metal layer. A second metal layer is formed to include filling the first and second damascene openings embedding the second insulating layer portion in the second metal layer. The second metal layer is planarized and a passivation layer is formed above the second insulating layer and the second metal layer, wherein the passivation layer partially covers the second metal layer.11-11-2010
20090294958WAFER LEVEL REDISTRIBUTION USING CIRCUIT PRINTING TECHNOLOGY - Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. A wafer has a surface defined by a plurality of integrated circuit regions Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. An ink jet printer is configured to print a plurality of routing interconnects on the surface of a wafer in the form of an ink. The ink jet printer is configured to print the plurality of routing interconnects such that each routing interconnect has a first portion in contact with a respective terminal of the plurality of terminals and has a second portion that extends over the passivation layer. Bump interconnects are attached to the routing interconnects. The wafer may be singulated to create a plurality of wafer-level integrated circuits.12-03-2009
20090008775SEMICONDUCTOR DEVICE WITH WELDED LEADS AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a manufacturing method for preventing mechanical and thermal damage to the semiconductor chip. A laser beam welds a first connection pad formed on a first external lead to a first electrode formed on the surface of the semiconductor chip. A first connection hole is formed in the first connection pad, and the first connection hole overlaps the first connection electrode. A laser beam irradiates an area including the first connection hole, and the first connection pad in a portion around the first connection hole is melted to form a melting section, that is welded to the first connection electrode to easily form a semiconductor device with more excellent electrical characteristics.01-08-2009
20090096095Semiconductor device and method of manufacturing the same - Provided is a semiconductor device having a substrate, a semiconductor chip flip-chip mounted on the substrate, and a stacked film provided in a gap between the substrate and the semiconductor chip. The stacked film is composed of a protective film covering the surface of the substrate, and an underfill film formed between the solder resist film and the semiconductor chip. The protective film is roughened on the contact surface brought into contacting said underfill film.04-16-2009
20100140800SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING MULTILAYER WIRING BOARD AND SEMICONDUCTOR DEVICE - A semiconductor device includes a multilayer wiring board and a semiconductor chip mounted on the multilayer wiring board. Electrode pads of the semiconductor chip include: first electrode pads including electrode pads respectively disposed in the vicinity of corners of the back surface of the semiconductor chip; and second electrode pads other than the first electrode pads. Connection pads of the multilayer wiring board include: first connection pads connected to the first electrode pads via bumps; and second connection pads connected to the second electrode pads via bumps. The first connection pads are supported by a first insulating region made of a thermoplastic resin, and the second connection pads are supported by a second insulating region made of a thermosetting resin.06-10-2010
20100140795Semiconductor Device and Method of Forming Conductive Pillars in Recessed Region of Peripheral Area Around the Device for Electrical Interconnection to Other Devices - A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar.06-10-2010
20090146297Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring - A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Through hole vias (THV) are formed in the die extension region. A conductive plane or ring is formed in a center area on the active surface of the semiconductor die. The conductive plane or ring is coupled to a first contact pad for providing a first power supply potential to the active circuits. The conductive plane or ring is electrically connected to a first THV. A conductive ring is formed partially around a perimeter of the conduction plane or ring. The conductive ring is coupled to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.06-11-2009
20080315413ELECTRONIC DEVICE MANUFACTURING METHOD AND ELECTRONIC DEVICE - There are provided the steps of forming a bump 12-25-2008
20100127392Semiconductor die - A semiconductor die includes a semiconductor substrate, electrodes provided on the semiconductor substrate, an isolating layer provided on the electrodes, an upper protective layer provided on the electrodes and the isolating layer, pads provided on the upper protective layer and connectors inserted through the upper protective layer and used to connect the electrodes to the pads. The area of the pads is larger than that of the electrodes.05-27-2010
20090096093INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF THE SAME - The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within the build-up layers; and conductive balls placed into the ball openings of the isolation base and attached on the ball pads within the build-up layers.04-16-2009
20100133687Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads - A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.06-03-2010
20090065934Wiring substrate, tape package having the same, display device having the tape package, method of manufacturing the wiring substrate, method of manufacturing a tape package having the same and method of manufacturing a display device having the tape package - A wiring substrate may include a base film, a plurality of wires, a first insulation member and a second insulation member. The base film may have a chip-mounting region where a semiconductor chip may be mounted thereon. The wires may extend from the chip-mounting region and the wires may include adhesive end portions that may be electrically connected to the semiconductor chip. The first insulation member may cover portions of the wires outside the chip-mounting region thereof. The second insulation member may cover portions of the wire inside the chip-mounting region, the adhesive end portion of the wire being exposed by the second insulation member.03-12-2009
20090166860FLEXIBLE FILM AND DISPLAY DEVICE COMPRISING THE SAME - A flexible film is provided. The flexible film includes a dielectric film; and a metal layer disposed on the dielectric film, wherein the ratio of the thickness of the metal layer to the thickness of the dielectric film is about 1:3 to 1:10. Therefore, it is possible to improve the peel strength, dimension stability, and tensile strength of a flexible film by limiting the ratio of the thicknesses of a dielectric film and a metal layer of the flexible film.07-02-2009
20090166859Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a wafer having an electrode pad; an insulating layer that is formed on the wafer and has an exposure hole formed in one side thereof, the exposure layer exposing the electrode pad, and a support post formed in the other side, the support post having a buffer groove; a redistribution layer that is formed on the top surface of the insulating layer and has one end connected to the electrode pad and the other end extending to the support post; an encapsulation layer that is formed on the redistribution layer and the insulating layer and exposes the redistribution layer formed on the support post; and a solder bump that is provided on the exposed portion of the redistribution layer.07-02-2009
20090166857Method and System for Providing an Aligned Semiconductor Assembly - A semiconductor assembly is provided that includes a first substrate that has a first surface. A second substrate is coupled to and spaced apart from the first substrate. The second substrate has a second surface facing the first surface of the first substrate. The second substrate includes a set of cavities. A set of non-conductive pillars is disposed on and protrudes from the first surface of the first substrate. The set of non-conductive pillars is configured and positioned to engage the set of cavities of the second substrate to align the second substrate with the first substrate.07-02-2009
20080230896Copper die bumps with electromigration cap and plated solder - Embodiments of the invention include apparatuses and methods relating to copper die bumps with electromigration cap and plated solder. In one embodiment, an apparatus comprises an integrated circuit die, a plurality of copper bumps on a surface of the die, electromigration (EM) caps substantially covering a mating surface of the copper bumps capable of controlling intermetallic formation between the copper bumps and a solder, and solder plating on the EM caps capable of protecting the EM caps from oxidation prior to packaging.09-25-2008
20090166858LGA SUBSTRATE AND METHOD OF MAKING SAME - An LGA substrate includes a core (07-02-2009
20080277784Semiconductor chip and manufacturing method thereof - A semiconductor chip formed with a bump such that the bump corresponds to a pad electrode. The pad electrode is covered with a nickel layer. The bump has an indium layer and an intermediate metal compound layer disposed between the indium layer and the nickel layer, and the intermediate metal compound layer is formed by alloying the indium layer and a copper layer containing copper atoms of not less than 0.5 atomic percent and not more than 5 atomic percent with respect to the indium atoms in the indium layer.11-13-2008
20080277785PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE AND METHOD OF THE SAME - A package structure for packaging at least one of a plurality of integrated circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of integrated circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of integrated circuit devices and on a sidewall of it.11-13-2008
20080296761Cylindrical Bonding Structure and method of manufacture - A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder.12-04-2008
20080296758Protection and Connection of Devices Underneath Bondpads - A circuit structure and a method for reducing stresses on semiconductor devices fabricated underneath bondpads include metal layers with a lattice planar configuration which spreads forces applied such as during wafer test probing or during wire bonding. Easing electrical connectivity among circuit elements and maintaining circuit performance is also carried out using the lattice. The lattice has metal strips which may connect circuit elements together or which may connect to a reference voltage source. The metal layer and bondpad corners and edges are formed preferentially without acute angles.12-04-2008
20080284010Apparatus for connecting integrated circuit chip to power and ground circuits - In a method and system for transferring at least one of power and ground signal between a die and a package base of a semiconductor device, a connector is formed there between. The connector, which is disposed above the die attached to the package base, includes a center pad electrically coupled to the die by a plurality of conductive bumps and a finger extending outward from the center pad towards the package base. The finger is electrically coupled to the package base by a conductive pad. A plurality of bond wires are formed to electrically couple the package base and the die. A resistance of a conductive path via the connector is much less than a resistance of a conductive path via any one of the plurality of bond wires to facilitate an efficient transfer of the at least one of power and ground signal.11-20-2008
20080284016Reliable metal bumps on top of I/O pads after removal of test probe marks - In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.11-20-2008
20080290510APPARATUS FOR CRACK PREVENTION IN INTEGRATED CIRCUIT PACKAGES - A microelectronic package having integrated circuits is provided. The microelectronic package includes multiple dielectric laminate layers, copper circuitry between the dielectric laminate layers where the copper circuitry includes circuit traces, and ball grid arrays/land grid arrays operatively connected to the copper circuitry such that conduction occurs. Further, proximate to the connection of the copper circuitry and the ball grid arrays/land grid arrays, a protective copper tongue is below an extension of the circuit traces, such that the protective copper tongue prevents the circuit traces from being affected by cracking propagated in the dielectric laminate layers or the ball grid arrays/land grid arrays.11-27-2008
20080290511Chip Assembly and Method of Manufacturing Thereof - An assembly of a first chip (11-27-2008
20080290509Chip Scale Package and Method of Assembling the Same - A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.11-27-2008
20080303148PAD ARRANGEMENT OF DRIVER IC CHIP FOR LCD AND RELATED CIRCUIT PATTERN STRUCTURE OF TAB PACKAGE - Output pads on an integrated circuit (IC) chip are arranged along a first longer side and are arranged along a second longer side with input pads. The output pads are connected to respective output patterns formed on top and bottom surfaces of a base film. All the output patterns may pass over the first longer side. Alternatively, the output patterns connected to the output pads at the second longer side may pass over a shorter side. These pattern structures establish an effective pad arrangement without increasing the size of a TAB package, yet allowing reduced the chip size.12-11-2008
20080303144STRUCTURE, METHOD AND SYSTEM FOR ASSESSING BONDING OF ELECTRODES IN FCB PACKAGING - Structures, methods, and systems for assessing bonding of electrodes in FCB packaging are disclosed. In one embodiment, a method comprises mounting a semiconductor chip with a plurality of first electrodes of a first shape to a mounted portion with a second electrode of a second shape, wherein the second shape is different from the first shape, bonding a respective on of the plurality of first electrodes and the second electrode using a first solder bump, generating an X-ray image of the first solder bump, and determining an acceptability of the bonding of the respective one of the plurality of first electrodes and the second electrode based on the X-ray image of the first solder bump.12-11-2008
20080303146PROCESS FOR MANUFACTURING SUBSTRATE WITH BUMPS AND SUBSTRATE STRUCTURE - A process for manufacturing a substrate with bumps is provided. First, a metallic substrate having a body and a plurality of conductive elements is provided. Next, a first dielectric layer is formed on the body, and the conductive elements are covered by the first dielectric layer. Then, a plurality of circuits and a plurality of contacts are formed on a surface of the first dielectric layer, and the contacts are electrically connected to the conductive elements. Next, a second dielectric layer is formed on the surface of the first dielectric layer, and the circuits are covered by the second dielectric layer. Finally, the body is patterned to form a plurality of bumps, and the bumps are electrically connected to the contacts by the conductive elements. The bumps are formed by etching the body, so the connection reliability between bumps and conductive elements is desirable, and the manufacturing cost is reduced.12-11-2008
20080303145Printed Circuit Board, Printed Circuit Board Manufacturing Method and Electronic Device - According to one embodiment, there is provided a printed circuit board which comprises a printed wiring board, a semiconductor package having a number of solder bonding members arranged on its back side and mounted on the printed wiring board by the solder bonding members being soldered to the wiring board, and reinforcing members which are formed of a reinforcing material having a solder flux function and locally reinforce the solder bonding members in a number of places on the semiconductor package mounting portion of the printed wiring board.12-11-2008
20120292760SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To increase the manufacturing yield of semiconductor devices by improving a joint failure of a bump electrode.11-22-2012
20080308931Electronic Structures Including Barrier Layers Defining Lips - Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer. A bump may be formed on the barrier layer, and the mask may be removed. In addition, portions of the seed layer may be selectively removed using the barrier layer as an etch mask.12-18-2008
20080308929SEMICONDUCTOR DEVICE, CHIP PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed.12-18-2008
20080284011BUMP STRUCTURE - A bump structure including at least one contact pad, at least one first polymer bump, at least one second polymer bump, and a conductive layer is provided. The contact pad is disposed on a substrate, and the first polymer bump is also disposed on the substrate. The second polymer bump is disposed on the substrate and is connected to the first polymer bump. The conductive layer covers the first polymer bump and electrically connects the contact pad.11-20-2008
20080265410Wafer level package - A wafer level package includes a substrate, a passivation layer, an elastic layer, a first insulation layer, a metal trace, a second insulation layer, and a bump. The passivation layer is formed on the substrate, and has one pad. The elastic layer is formed on the passivation layer. The first insulation layer is formed on the passivation layer and the elastic layer, and has a junction in contact with the pad. The metal trace is formed on the first insulation layer. The second insulation layer is formed on the metal trace, and a groove is formed correspondingly above the elastic layer. The bump is formed in the groove. An annular trench can be further formed around the bump. A groove can be furthermore formed in the first insulation layer correspondingly below the bump.10-30-2008
20080284014CHIP ASSEMBLY - A chip assembly includes a semiconductor chip, a bump and an external circuit. The semiconductor chip includes a semiconductor substrate, a transistor in and on the semiconductor substrate, multiple dielectric layers over the semiconductor substrate, a metallization structure over the semiconductor substrate, wherein the metallization structure is connected to the transistor, and a passivation layer over the metallization structure, over the dielectric layers and over the transistor. The bump is connected to the metallization structure through an opening in the passivation layer, wherein the bump includes an adhesion/barrier layer and a gold layer over the adhesion/barrier layer. The external circuit can be connected to the bump using a tape carrier package (TCP), a chip-on-film (COF) package or a chip-on-glass (COG) assembly.11-20-2008
20090032943SUBSTRATE, SUBSTRATE FABRICATION, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE FABRICATION - A substrate for fixing an integrated circuit (IC) element comprises: a substrate for fixing an integrated circuit element includes: a plurality of metal posts that are aligned in a longitudinal direction and a lateral direction in plan view, each of the plurality of metal posts having a first surface and a second surface facing an opposite direction to the first surface, the plurality of metal posts being configured identically; and a joining section that joins each of the plurality of metal posts together at a portion of each of the plurality of metal posts between the first surface and the second surface.02-05-2009
20090032944ELECTRONIC DEVICE, METHOD OF PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE - A semiconductor device includes n02-05-2009
20080296762SEMICONDUCTOR DEVICE - A semiconductor device of the invention includes a semiconductor substrate having a first insulating section formed on one surface thereof. A first conductive section is disposed on the one surface of the semiconductor substrate. A second insulating section is superimposed over the first insulating section and covers the first conductive section. A second conductive section is superimposed over the second insulating section. A third insulating section is disposed over the second insulating section and covers the second conductive section. These first conductive section, second insulating section, second conductive section, third insulating section, and terminal altogether constitute a structure. A third opening is formed between adjacent structures. The third opening is formed passing through the third and second insulating sections to expose the first insulating section.12-04-2008
20100127393Electronic device and semiconductor device - An electronic device includes: a wiring board having first and second regions; a plurality of first lands in the first region; a plurality of second lands in the second region; and an insulator covering the wiring board. More heat is applied to the first region than the second region. The second land is smaller in volume than the first land. The insulator has a plurality of openings being adjacent to the plurality of first lands and the plurality of second lands. Each of the plurality of openings has substantially the same area.05-27-2010
20090014874SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a semiconductor chip, a wired board, a plurality of bump electrodes, a plurality of external terminals, and insulating material. The semiconductor chip includes a plurality of electrode pads arranged in a central area on one surface. The wired board is arranged as facing one surface of the semiconductor chip, and includes a wiring. The bump electrode is provided between surfaces at which the semiconductor chip and the wired board face each other, and electrically connects the electrode pad and the wiring. The external terminal corresponds to a plurality of bump electrodes, and is mounted on the wired board. The insulating material is provided between the semiconductor chip and the wired board, and covers at least a connection part between the bump electrode and the wiring. The wiring of the wired board is configured to run in a straight line from a bump electrode-mounted position in a semiconductor chip-mounted surface of the wired board, to an external terminal-mounted surface of the wired board, and also, electrically connect the bump electrode and the corresponding external terminal.01-15-2009
20090014870SEMICONDUCTOR CHIP AND PACKAGE PROCESS FOR THE SAME - A semiconductor chip is provided. The semiconductor chip includes a chip and chip bump pads thereon. The chip bump pads include at least two chip bump pads that are physically connected.01-15-2009
20090014869SEMICONDUCTOR DEVICE PACKAGE WITH BUMP OVERLYING A POLYMER LAYER - A semiconductor device package, for example a flip-chip package, having a solder bump mounted above a polymer layer for use in flip-chip mounting of a semiconductor device to a circuit board. A polymer layer such as polybenzoxazole is formed overlying a wafer passivation layer. Solder bumps are attached to an under-bump metallization layer and electrically coupled to conductive bond pads exposed by openings in the wafer passivation layer.01-15-2009
20080246144METHOD FOR FABRICATING CONTACT PADS - A method for fabricating a contact pad is disclosed. A first metal layer is disposed on a substrate for serving as a probing region. A second metal layer is disposed on the substrate thereafter to serve as an electrical connection region. Preferably, the first metal layer and the second metal layer are composed of different material and are electrically connected. The present invention uses two different metals to form a probing region and an electrical connection region of a contact pad. The probing region is used for providing a contacting surface for a test probe, whereas the electrical connection region is used for establishing an electrical connection in the later bumping or wire bonding process. By providing a contact pad having two different regions, the present invention is able to achieve probing process while prevent the surface of the contact pad from being damaged by the contact of test probes.10-09-2008
20120292759SEMICONDUCTOR DEVICE HAVING CHIP CRACK DETECTION STRUCTURE - A device includes a semiconductor substrate, a first penetration electrode and a plurality of second penetration electrodes each penetrating the semiconductor substrate, a first terminal and a plurality of second terminals formed on a one side of the substrate, and a third terminal and a plurality of fourth terminals formed on an opposite side of the substrate. Each of the first and third terminals is vertically aligned with and electrically connected to first penetration electrode. Each of the second terminals is vertically aligned with an associated one of the second penetration electrodes and electrically connected to another one of the second penetration terminals that is not vertically aligned with the associated second terminal. Each of fourth terminals is vertically aligned with and electrically connected to an associated one of the second penetration electrodes.11-22-2012
20080303147HIGH-FREQUENCY CIRCUIT DEVICE AND RADAR - A semiconductor chip is provided with a high-frequency circuit. A multi-layer wiring section is comprised of organic material and formed on the semiconductor chip, an outermost layer of the multi-layer wiring section formed with a bump forming portion. A bump is formed on the bump forming portion. The multi-layer wiring section is provided with a reinforcing means for suppressing a deformation of a bonding portion between the bump and the bump forming portion when the high-frequency circuit device is bonded to a substrate with an ultrasonic vibration applied thereto.12-11-2008
20080284015BUMP ON VIA-PACKAGING AND METHODOLOGIES - A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections. A method of forming a semiconductor package having external package connections includes providing a semiconductor chip having under bump metallizations (UBMs) on a first surface; attaching the first surface of the semiconductor chip to a substrate, the UBMs of the semiconductor chip being in alignment with open vias formed in the substrate; encapsulating the semiconductor chip and the substrate; and filling with open vias with a conductor to form the external package connections.11-20-2008
20080272486CHIP PACKAGE STRUCTURE - A chip package structure includes a carrier, an interposer, a plurality of electrically conductive elements, a first sealant, a chip, and a second sealant. The interposer is disposed on the carrier. The electrically conductive elements electrically connect the interposer and the carrier. The first sealant seals the electrically conductive elements. A plurality of bumps of the chip is connected to the interposer. The second sealant seals the bumps. A first glass transition temperature of the first sealant is higher than a second glass transition temperature of the second sealant. Since glass transition temperatures of the first sealant and the second sealant are different, and the first glass transition temperature of the first sealant is higher than the second glass transition temperature of the second sealant, the inner stress will be lowered and the yield is promoted.11-06-2008
20130119534METAL PAD STRUCTURE FOR THICKNESS ENHANCEMENT OF POLYMER USED IN ELECTRICAL INTERCONNECTION OF SEMICONDUCTOR DIE TO SEMICONDUCTOR CHIP PACKAGE SUBSTRATE WITH SOLDER BUMP - A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering.05-16-2013
20130119535FLIP CHIP PACKAGES WITH IMPROVED THERMAL PERFORMANCE - Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity.05-16-2013
20130119536METHOD FOR FORMING STUDS USED FOR SELF-ALIGNMENT OF SOLDER BUMPS - A method and a combination of studs, silicon chips, and solder bumps configured to restrict motion of a plurality of silicon chips. The combination includes: a plurality of studs, a plurality of silicon chips, a plurality of target solder bumps, where the plurality of solder bumps are melted between the plurality of silicon chips, where lateral positions of the plurality of studs are in accord with a pitch of the plurality of target solder bumps by using the pitch as a reference, where (i) lateral positions and lateral widths of studs of the plurality of studs located at a first silicon chip of the plurality of silicon chips and (ii) lateral positions and lateral widths of studs of the plurality of studs located at a second silicon chip of the plurality of silicon chips are restricted such that relative lateral motion on the respective silicon chips is restricted.05-16-2013
20090096094SEMICONDUCTOR DEVICE - In a wafer level CSP package, with respect to signal wiring 04-16-2009
20110006415SOLDER INTERCONNECT BY ADDITION OF COPPER - A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.01-13-2011
20110006418SEMICONDUCTOR DEVICE PROVIDED WITH WIRE THAT ELECTRICALLY CONNECTS PRINTED WIRING BOARD AND SEMICONDUCTOR CHIP EACH OTHER - In one embodiment, a semiconductor device includes a printed wiring board provided with a connection pad, a semiconductor chip provided with an electrode pad and a conductive wire. One end of the conductive wire is connected to the connection pad of the printed wiring board and the other end of the conductive wire is connected to the electrode pad of the semiconductor chip. The semiconductor chip is mounted on the printed wiring board so that the first surface of the semiconductor chip provided with the electrode pad is oriented opposite to the printed wiring board. A first insulating layer is formed on the first surface of the semiconductor chip oriented opposite to the printed wiring board. A thermoplastic second insulating layer is formed on the first insulating layer. Part of the conductive wire between one end and the other end is buried in the second insulating layer.01-13-2011
20110006416STRUCTURE AND METHOD FOR FORMING PILLAR BUMP STRUCTURE HAVING SIDEWALL PROTECTION - A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above the conductive layer, the photoresist layer defining at least one opening therein. A metal layer is deposited in the at least one opening. Portions of the photoresist layer are etched along one or more interfaces between the photoresist layer and the metal layer to form cavities. A solder material is deposited in the at least one opening, the solder material filling the cavities and a portion of the opening above the metal layer. The remaining photoresist layer and the conductive layer not formed under the copper layer are removed. The solder material is then reflown to encapsulate the metal layer.01-13-2011
20100052161Semiconductor wafer with adhesive protection layer - A semiconductor wafer with an adhesive protection layer includes: a wafer body having a first surface and an opposing second surface; a plurality of electrical connection pads formed on the second surface of the wafer body; and the adhesive protection layer formed on the second surface of the wafer body and the plurality of electrical connection pads, wherein the protection layer is made of a material including a photosensitive adhesive, a thermal-setting adhesive and a dielectric material. The protection layer not only isolates circuits on the wafer surface from external moisture and contaminant, but also can be patterned and is adhesive, such that the wafer can be mounted to a circuit substrate in a subsequent process by the protection layer, without having to apply an additional adhesive on the wafer, thereby greatly simplifying the wafer-substrate attachment procedure during package fabrication processes.03-04-2010
20100052160BUMP STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention discloses a bump structure and a method for fabricating the same. The bump structure of the present invention comprises a semiconductor substrate having a plurality of connection pads; a passivation layer covering the substrate and having openings each corresponding to one connection pad, wherein the openings reveal a portion of each connection pad to form a plurality of electrical-connection areas; an elastic layer formed on the passivation layer; and a plurality of bumps each formed corresponding to one electric-connection area and extending to the elastic layer, whereby the elasticity and deformability of the bumps is enhanced. The present invention uses a larger-texture (≧20 μm) patterning process to fabricate an appropriate patterned elastic layer (having parallel lines, strips, or saw teeth) to enhance the elasticity and deformability of the bumps, whereby the bump structure of the present invention can apply to a fine-pitch IC.03-04-2010
20090032941Under Bump Routing Layer Method and Apparatus - Various semiconductor chip conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a semiconductor chip. The conductor structure has a first site electrically connected to a first redistribution layer structure and a second site electrically connected to a second redistribution layer structure. A solder structure is formed on the conductor structure.02-05-2009
20080258299Method of manufacturing a semiconductor device having an even coating thickness using electro-less plating, and related device - A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.10-23-2008
20080258298SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.10-23-2008
20080258297METHOD OF MAKING SOLDER PAD - A method of making a solder pad includes providing a substrate having a metal layer formed on it, and applying a photo resist to the metal layer. The photo resist is patterned. A first etching operation is performed on the metal layer to form voids in the metal layer. A second etching operation is performed on the metal layer to form the solder pad. A solder mask is formed on the substrate and a portion of the solder pad.10-23-2008
20100200987Semiconductor Device and a Method of Manufacturing the Same - A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 08-12-2010
20100200986Grooving Bumped Wafer Pre-Underfill System - A method of forming a semiconductor device includes providing a bumped wafer. A plurality of grooves is formed in an active surface of the bumped wafer. A pre-underfill layer is disposed over the active surface, filling the plurality of grooves. A first adhesive layer is mounted to the pre-underfill layer, and a back surface of the bumped wafer is ground. A second adhesive layer is mounted to the back surface of the bumped wafer. The first adhesive layer is peeled from the active surface of the bumped wafer, or the second adhesive layer is mounted to the first adhesive layer. The bumped wafer is singulated into a plurality of segments by cutting the bumped wafer along the plurality of grooves.08-12-2010
20100200985Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process - A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer.08-12-2010
20090091031Semiconductor device - A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.04-09-2009
20090127705Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device - There are provided a semiconductor device capable of accurately determining whether a semiconductor chip is bonded to a solid-state device such as the other semiconductor chip parallelly with each other, a semiconductor chip used for the semiconductor device, and a method of manufacturing the semiconductor chip. The semiconductor chip includes a functional bump projected with a first projection amount from the surface of the semiconductor chip and electrically connecting the semiconductor chip to the solid-state device, and a connection confirmation bump projected with a second projection amount, which is smaller than the first projection amount, from the surface of the semiconductor chip and used for confirming the state of the electrical connection by the functional bump.05-21-2009
20110266669SEMICONDUCTOR CHIP WITH POST-PASSIVATION SCHEME FORMED OVER PASSIVATION LAYER - The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns11-03-2011
20110204511System and Method for Improving Reliability of Integrated Circuit Packages - An integrated circuit package includes a die, a bump, an underbump metallization layer formed between the bump and the die, a portion of the underbump metallization layer under the bump having a first radius, and a redistribution layer formed between the underbump metallization layer and the die. The redistribution layer has a pad positioned under the underbump metallization layer. The pad has a second radius, and makes contact with the underbump metallization layer. The second radius is less than or equal to the first radius. The integrated circuit package also includes a first dielectric layer disposed between the die and the redistributing layer.08-25-2011
20090184418WIRING SUBSTRATE, TAPE PACKAGE HAVING THE SAME, AND DISPLAY DEVICE HAVING THE SAME - A wiring substrate includes a base film, a plurality of first wirings and a plurality of second wirings. The base film has a chip-mounting region configured for mounting a semiconductor chip thereon. The first wirings extend in a first direction from inside the chip-mounting region to outside the chip-mounting region, and include first connection end portions extending in a second direction different from the first direction. The first connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip. The second wirings extend in the first direction from inside the chip-mounting region to outside the chip-mounting region, and include second connection end portions extending in the opposite direction to the second direction in which the first connection end portions extend, and the second connection end portions may be formed inside the chip-mounting region and configured to electrically connect to the semiconductor chip.07-23-2009
20090127704Method and System for Providing a Reliable Semiconductor Assembly - A semiconductor assembly is provided that includes a substrate. A first set of non-conductive hedges is disposed on and protrudes from a first surface of the substrate. A chip is coupled to and spaced apart from the substrate. The chip has a second surface facing the first surface of the substrate. A second set of non-conductive hedges is disposed on and protrudes from the second surface of the chip. The first set of hedges is configured and positioned to engage the second set of hedges to restrict movement of the substrate with respect to the chip. The second set of hedges is configured and positioned to engage the first set of hedges to restrict movement of the chip with respect to the substrate.05-21-2009
20090127707SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having good radiation performance is provided. The semiconductor device is provided with a substrate having one surface in which external connection terminals are formed. The semiconductor device includes the substrate having a wiring layer; a semiconductor chip which is mounted on the one surface of the substrate; the external connection terminals formed on the one surface of the substrate so as to be located along the perimeter of the semiconductor chip; and a conductive part formed on the one surface and having a melting point higher than that of the external connection terminals and electrically insulated from the wiring layer.05-21-2009
20090127710UNDERCUT-FREE BLM PROCESS FOR PB-FREE AND PB-REDUCED C4 - A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer of the barrier metal stack removed by etching. The diffusion barrier and C4 solder bump may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.05-21-2009
20090127703Method and System for Providing a Low-Profile Semiconductor Assembly - A semiconductor assembly is provided that includes a substrate that has a first surface. A chip is coupled to the substrate. The chip has a second surface that faces the first surface of the substrate. The chip is spaced apart from the substrate forming a gap. At least a portion of the substrate is coupled to the chip by solder bumps. The solder bumps include a deformable material, such that as a height of the gap between the chip and the substrate increases, the solder bumps deform into a stretched state. An underfill material is applied between the substrate and the chip. The underfill material substantially fills the gap between the chip and the substrate and surrounds the solder bumps in the stretched state. Barricades comprising non-conductive protrusions are disposed between the first surface of the substrate and the second surface of the chip. The barricades confine the solder bumps in a compressed state.05-21-2009
20090140422SUBSTRATE FOR SEMICONDUCTOR PACKAGE WITH IMPROVED BUMPING OF CHIP BUMPS AND CONTACT PADS AND SEMICONDUCTOR PACKAGE HAVING THE SAME - The present invention relates to a substrate for a semiconductor package and a semiconductor package having the same. A substrate for a semiconductor package includes a substrate body; a contact pad group including a plurality of contact pads parallely arranged at a determined interval on a surface of the substrate body; dummy contact pads arranged at both sides of the contact pad group, respectively; and solder resist patterns covering the substrate body and having openings exposing the dummy contact pads and the contact pad group. When bumping the semiconductor chip having the bumps to the solders arranged on the contact pads formed on the substrate, the bumping defect caused due to different volumes of each solder can be prevented.06-04-2009
20100193947Flip Chip Interconnection Having Narrow Interconnection Sites on the Substrate - A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.08-05-2010
20090127706CHIP STRUCTURE, SUBSTRATE STRUCTURE, CHIP PACKAGE STRUCTURE AND PROCESS THEREOF - A chip package structure and process are provided; the structure includes a substrate, a chip, a solder layer and at least a stud bump. The substrate has at least a contact pad, and the chip has an active surface where at least a bonding pad is disposed. The stud bump is disposed on the bonding pad of the chip or on the contact pad of the substrate, and the stud bump joints with the solder layer to fix the chip on the substrate. The stud bump is made of gold-silver alloy containing silver below 15% by weight.05-21-2009
20090184419Flip Chip Interconnect Solder Mask - A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the remelt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.07-23-2009
20120139106Semiconductor Device and a Method of Manufacturing the Same - A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 06-07-2012
20110140269Semiconductor device and method for manufacturing the same - A semiconductor device includes an electrode pad and a protective insulating film having an opening to expose the electrode pad. The semiconductor device further includes a bump (resin core bump) that includes a bump core (resin core) formed on the protective insulating film and a conductive layer formed on the bump core. The semiconductor device further includes an interconnect that connects the conductive layer and the electrode pad. The bump core is in the form of a laminate of plural resin layers (for example, first and second resin layers) that have different elastic modulus.06-16-2011
20090014871SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment includes a semiconductor substrate and at least two insulating elements located above the semiconductor substrate or above a mold compound embedding the semiconductor substrate. The at least two insulating elements have a first face facing the semiconductor substrate or the mold compound and a second face facing away from the semiconductor substrate or the mold compound. A conductive element for each of the at least two insulating elements extends from the first face of the insulating element to the second face of the insulating element.01-15-2009
20090001567IC chip with finger-like bumps - A bumped chip has a plurality of finger-like bumps bonded on multiple openings of a chip. The chip primarily comprises a plurality of bonding pads and a passivation layer having a plurality of opening thereon. In one embodiment, the openings on each bonding pad are plural and disposed in linear, in parallel, or in an array. The finger-like bumps are protrusively disposed on the chip and each has a bump core and an extension finger. The bump cores are disposed within the corresponding bonding pads and cover the openings, and the extension fingers are disposed outside the corresponding bonding pads to maintain the bonding strengths of the bumps even at fine pitches. In an embodiment, the extension fingers overlap at least a trace of the chip.01-01-2009
20120068337Semiconductor Device and Method of Forming Composite Bump-on-Lead Interconnection - A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu—OSP can be formed over the substrate.03-22-2012
20120068336Method for Fabricating a Neo-Layer Using Stud Bumped Bare Die - A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.03-22-2012
20120068335PRINTED CIRCUIT BOARD HAVING HEXAGONALLY ALIGNED BUMP PADS FOR SUBSTRATE OF SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - Provided are a printed circuit board (PCB) having hexagonally aligned bump pads as a substrate of a semiconductor package, and a semiconductor package including the same. The PCB includes: a PCB body; a bottom metal layer at a bottom of the PCB body; and a top metal layer at a top of the PCB body, and the top metal layer includes: vias vertically connected to the PCB body; bump pads hexagonally aligned in a horizontal direction around the vias; and connection patterns connecting the vias to two or more of the bump pads. Accordingly, the number of bump pads in a unit area of the PCB may be increased.03-22-2012
20120068334SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.03-22-2012
20120068332INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a stack substrate with a component side; connecting an integrated circuit component to the component side; attaching a conductive post to the component side and adjacent the integrated circuit component, the conductive post having a protruded end above the integrated circuit component; forming a protection layer on a top and sides of the protruded end, the protection layer having a width equal to a width of the conductive post; applying a stack encapsulation over the integrated circuit component, over the stack substrate, and around a portion of the conductive post, the protection layer exposed from the stack encapsulation; and mounting a base package under the stack substrate, base package connected to the stack substrate.03-22-2012
20090212425SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique is provided which allows a chip mounted by wire bonding and a chip mounted by bump electrodes to share a manufacturing process. Both in a case where a chip is electrically coupled to an external circuit by bump electrodes and a case where the chip is electrically coupled to the external circuit by bonding wires, a bump coupling part and a bonding pad are both provided in a single uppermost wiring layer. When the bump electrodes are used, an opening is provided in an insulating film on the bump coupling part and a surface of the bonding pad is covered with the insulating film. On the other hand, when the bonding wires are used, an opening is provided in an insulating film on the bonding pad and a surface of the bump coupling part is covered with the insulating film.08-27-2009
20090212424ROUTING STRUCTURE OF RE-DISTRIBUTION LAYER AND METHOD FOR RE-DISTRIBUTING ROUTING STRUCTURE IN INTEGRATED CIRCUIT - A routing structure of an RDL of a chip is provided. The routing structure comprises a power route, a plurality of first stripes, a ground route, and a plurality of second stripes. The power route is arranged in a first direction and comprises a plurality of first bumps and a plurality of first line segments. Each of the first line segments connects adjacent first bumps. The first stripes are arranged in a second direction and connected to the power route. The ground route is disposed at one side of the power route in a third direction, and comprises a plurality of second bumps and a plurality of second line segments. Each of the second line segments connects adjacent second bumps. The second stripes, are arranged in a forth direction and connected to the ground route. The first stripes and the second stripes are interleaved without intersecting one another.08-27-2009
20090321926MOUNTING STRUCTURE AND MOUNTING METHOD - A mounting structure of the present invention includes a semiconductor element 12-31-2009
20110221058SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON DIFFERENT HEIGHT TRACES - A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved by forming different height first and second conductive layer above a substrate. A first patterned photoresist layer is formed over the substrate. A first conductive layer is formed in the first patterned photoresist layer. The first patterned photoresist layer is removed. A second patterned photoresist layer is formed over the substrate. A second conductive layer is formed in the second patterned photoresist layer. The height of the second conductive layer, for example 25 micrometers, is greater than the height of the first conductive layer which is 5 micrometers. The first and second conductive layers are interposed between each other close together to minimize pitch and increase I/O count while maintaining sufficient spacing to avoid electrical shorting after bump formation. An interconnect structure is formed over the first and second conductive layers.09-15-2011
20090051029FLIP-CHIP TYPE SEMICONDUCTOR DEVICE - A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrode terminals are completely covered with the sealing resin layer.02-26-2009
20090108443Flip-Chip Interconnect Structure - Various aspects can be implemented for providing flip-chip interconnect structures for connecting or mounting semiconductor chips to supporting substrates, such as cards, circuit boards, carriers, lead frames, and the like. In general, one aspect can be a method of providing a flip-chip interconnect structure that includes providing a semiconductor work piece that includes one or more bond pads. The method also includes depositing a first non-reflowable layer that has a first melting temperature higher than a predetermined first reflow temperature. The method further includes depositing a reflowable stress relief layer that reflows at the predetermined first reflow temperature. The method additionally includes depositing a second non-reflowable layer that has a second melting temperature higher than the predetermined first reflow temperature such that the deposited reflowable stress relief layer is between the first and the second non-reflowable layers.04-30-2009
20090085202Methods and Apparatus for Assembling Integrated Circuit Device Utilizing a Thin Si Interposer - Methods of assembling an integrated circuit are provided. An interposer supported by an integrated handler is solder bumped onto one or more bond pads on a substrate. The integrated handler is removed from the interposer. A side of the interposer opposite that of the substrate is solder bumped to one or more bond pads on a chip.04-02-2009
20090051028ELECTRONIC DEVICE AND ELECTRONIC APPARATUS - An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.02-26-2009
20090166856Semiconductor Device - A semiconductor device is provided whereby the signal interference among a plurality of function blocks is reduced.07-02-2009
20120104603INTERCONNECT ASSEMBLIES AND METHODS OF MAKING AND USING SAME - The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.05-03-2012
20120104602SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND CIRCUIT DEVICE USING SEMICONDUCTOR DEVICE - [Problem] A semiconductor device which achieves a fine pitch, a high throughput and a high connection reliability, especially in flip-chip mounting is provided. A method for manufacturing the semiconductor device and a circuit device using the semiconductor device are also provided.05-03-2012
20120104601Semiconductor Device and Method of Forming Wafer Level Ground Plane and Power Ring - A semiconductor die has active circuits formed on its active surface. Contact pads are formed on the active surface of the semiconductor die and coupled to the active circuits. A die extension region is formed around a periphery of the semiconductor die. Conductive THVs are formed in the die extension region. A wafer level conductive plane or ring is formed on a center area of the active surface. The conductive plane or ring is connected to a first contact pad to provide a first power supply potential to the active circuits, and is electrically connected to a first conductive THV. A conductive ring is formed partially around a perimeter of the conductive plane or ring and connected to a second contact pad for providing a second power supply potential to the active circuits. The conductive ring is electrically connected to a second THV.05-03-2012
20120104600STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE AND PACKAGING THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.05-03-2012
20120104599Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor - A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps.05-03-2012
20120104598PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT AND FABRICATION METHOD THEREOF - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented.05-03-2012
20120104596FLIP CHIP BUMP ARRAY WITH SUPERIOR SIGNAL PERFORMANCE - An integrated circuit (05-03-2012
20120104594GROUNDED SEAL RING STRUCTURE IN SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate having a seal ring region and a circuit region, at least one corner bump disposed in the circuit region, a seal ring structure disposed in the seal ring region, and a connector electrically coupling a metal layer of the seal ring structure to the at least one corner bump. The at least one corner bump is configured to be coupled to a signal ground. A method of fabricating a semiconductor device includes providing a substrate having a seal ring region and a circuit region, providing at least one corner bump in a triangular corner bump zone in the circuit region, providing a seal ring structure in the seal ring region, electrically coupling a metal layer of the seal ring structure to the at least one corner bump, and electrically coupling the at least one corner bump to a signal ground.05-03-2012
20120104595NO FLOW UNDERFILL - A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and other of the first or second conductive elements may include a bond metal disposed between some of the conductive posts. An underfill layer may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer and at least deform the bond metal. The microelectronic element and the dielectric element can be heated to join them together. The height of the posts above the surface may be at least forty percent of a distance between surfaces of the microelectronic element and dielectric element.05-03-2012
20090065933SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device that can suppresses poor connection caused by the variation of the heights of bumps during reflow heating, can be applied to a narrow array pitch, and can freely adjust the heights of the bumps.03-12-2009
20090039507Electronic Element, Electronic Element Device Using the Same, and Manufacturing Method Thereof - An electronic element including an electronic element base and electrodes each of which has a first electrode having a surface composed of at least Al or an Al alloy and a second electrode composed of a metal nanoparticle sintered body and bonded to the first electrode. A bonding interface between the first electrode and the second electrode has a multilayer structure including, from the side of the first electrode to the side of the second electrode, (a) a first layer primarily composed of Al, (b) a second layer primarily composed of an Al oxide, (c) a third layer primarily composed of an alloy of Al and a constituent element of metal nanoparticles, and (d) a fourth layer primarily composed of the constituent element of the metal nanoparticles.02-12-2009
20110140267ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.06-16-2011
20110140268HIGH-DENSITY INTER-PACKAGE CONNECTIONS FOR ULTRA-THIN PACKAGE-ON-PACKAGE STRUCTURES, AND PROCESSES OF FORMING SAME - An apparatus includes a coreless mounting substrate and an interposer disposed on the coreless mounting substrate with a chip disposed in a recess in the interposer and upon the coreless substrate. The apparatus may include an inter-package solder bump in contact with an interconnect channel in the interposer, and a top chip package including a top package substrate and a top die disposed on the top package substrate. The top package substrate is in contact with the inter-package solder bump.06-16-2011
20120068333Wire Bond Through-Via Structure and Method - A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.03-22-2012
20090096097Semiconductor device and manufacturing method of the same - Semiconductor device 04-16-2009
20090096096SEMICONDUCTOR DEVICE AND CIRCUIT DEVICE HAVING THE SAME MOUNTED THEREON - A semiconductor device has a semiconductor chip, terminals formed at a prescribed terminal pitch on the bottom side of the semiconductor chip, and columnar post electrodes formed on the terminals. The post electrodes are formed of two different metals, the side bonded with the terminals is constituted by first metallic portions while the side on which solder bumps is formed are constituted by second metallic portions. A dimension in the width direction of the first metallic portions is formed smaller than a dimension in the width direction of the second metallic portions.04-16-2009
20090014872METHOD FOR MANUFACTURING A CIRCUIT BOARD STRUCTURE, AND A CIRCUIT BOARD STRUCTURE - This publication discloses a method for manufacturing a circuit-board structure.01-15-2009
20090200665SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor construction assembly having a semiconductor substrate which has first and second surfaces, and has an integrated circuit element formed on the first surface, a plurality of connection pads which are connected to the integrated circuit element, a protective layer which covers the semiconductor substrate and has openings for exposing the connection pads, and conductors which are connected to the connection pads, arranged on the protective layer, and have pads. An upper insulating layer covers the entire upper surface of the semiconductor construction assembly including the conductors except the pads. A sealing member covers at least one side surface of the semiconductor construction assembly. An upper conductors is formed on the upper insulating layer, and has one ends electrically connected to the pads and an external connection pads, respectively, an external connection pad of at least one of the upper conductors being disposed in a region corresponding to the sealing member.08-13-2009
20090200663POLYMER AND SOLDER PILLARS FOR CONNECTING CHIP AND CARRIER - A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are similar in size to the first solder balls, on the corresponding surface of the package substrate to which the chip will be attached. Then, the method positions the surface of the semiconductor chip next to the corresponding surface of the package substrate. The adhesive bonds the distal ends of the polymer pillars to the corresponding surface of the package substrate. The method heats the first solder balls and the second solder balls to join the first solder balls and the second solder balls into solder pillars.08-13-2009
20090230550Method and system for the modular design and layout of integrated circuits - An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.09-17-2009
20090230549FLIP CHIP PACKAGE - A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.09-17-2009
20090230548SEMICONDUCTOR PACKAGE AND MULTI-CHIP PACKAGE USING THE SAME - A semiconductor package may have a semiconductor chip that includes a chip pad formed on a substrate including an integrated circuit, and a passivation layer exposing the chip pad, a first redistribution wiring layer that is connected to the chip pad and extends on the semiconductor chip and includes a wire bonding pad to provide wire bonding and a first solder pad to connect the first redistribution wiring layer to a second semiconductor chip, and a second redistribution wiring layer that is connected to the first redistribution wiring layer on the first redistribution wiring layer and includes a second solder pad to connect the second redistribution wiring layer to a third semiconductor chip.09-17-2009
20090230547DESIGN STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE AND PACKAGING THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.09-17-2009
20090230546MOUNTED BODY AND METHOD FOR MANUFACTURING THE SAME - A mounted body of the present invention includes: a multilayer semiconductor chip 09-17-2009
20090243095SUBSTRATE, MANUFACTURING METHOD THEREOF, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A substrate on which an IC element is fixed includes: a plurality of metal posts arranged in a plurality of columns in a lengthwise direction and in a plurality of rows in a crosswise direction when viewed in a plan view, the plurality of metal posts having first faces and second faces that face an opposite side to a side that the first faces face; first marks each of the first marks being disposed on extending lines of the plurality of columns; and second marks, each of the second marks being disposed on extending lines of the plurality of rows.10-01-2009
20090224401SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a package substrate, a semiconductor chip, a plurality of bump electrodes and one or more dummy chips. The semiconductor chip is mounted on one surface of the package substrate. The bump electrodes are the other surface of the package substrate and electrically connected to the semiconductor chip through a wiring structure. Each of the dummy chips is mounted on a predetermined region close to a corner portion of the semiconductor chip on the one surface of the package substrate.09-10-2009
20090250811Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask - A semiconductor device has a semiconductor die with an die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.10-08-2009
20080315410Substrate Including Barrier Solder Bumps to Control Underfill Transgression and Microelectronic Package including Same - A microelectronic substrate and a microelectronic package including the substrate and a die bonded thereto. The substrate includes a substrate panel having a die-side surface including a die-attach region; a system of interconnects extending through the substrate panel and adapted to allow a connection of the substrate to external circuitry; and a plurality of solder bumps including: die-attach solder bumps electrically coupled to the system of interconnects and disposed in the die-attach region; and barrier solder bumps isolated from the system of interconnects, the barrier solder bumps being disposed outside of the die-attach region and being adapted to substantially limit a flow of underfill away from the die-attach region.12-25-2008
20080315411INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING - An integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.12-25-2008
20080315414ELECTRONIC DEVICE MANUFACTURING METHOD AND ELECTRONIC DEVICE - There are provided the steps of forming a bump 12-25-2008
20080315412Package Structure with Flat Bumps for Integrate Circuit or Discrete Device and Method of Manufacture the Same - The invention discloses a novel package structure of integrate circuit or discrete device and packaging method, and includes the lead pins adjacent to the island; another metal layer formed at the bottom of the island; another metal layer formed at the bottom of lead pins; chip mounted on the island; wires bonded between the chip and the lead pins; the molded body encapsulating the top surface and side surface of the island and the lead pins, small protrusions of the island and the lead pins below the molded body; in the individual package, the number of the island can be one or more, lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island. The invention provides strong welding, good quality, low cost, smooth production, wide applicability, flexible arrangement of the chips.12-25-2008
20090212426SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, a region under a pad electrode with a bump can be utilized efficiently and a large amount of force is prevented from applying locally to a semiconductor substrate under the bump when the semiconductor device is mounted. A first layer metal wiring is formed on the semiconductor substrate. A pad electrode is formed on the first layer metal wiring through an interlayer insulation film. The pad electrode is connected with the first layer metal wiring through a via hole that is formed in the interlayer insulation film. A protection film is formed on the pad electrode. The protection film has an opening to expose the pad electrode and an island-shaped protection film formed in the opening. An Au bump connected with the pad electrode through the opening in the protection film is formed on the pad electrode. The via hole is formed under the island-shaped protection film, and incompletely filled with a portion of the pad electrode.08-27-2009
20090200664MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS - A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.08-13-2009
20090243090MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS - A mock bump system includes providing a flip chip integrated circuit having an edge and forming a mock bump near the edge.10-01-2009
20090243093CONTACT STRUCTURE AND CONNECTING STRUCTURE - A contact structure disposed on a substrate is provided. The contact structure includes at least one pad, at least one polymer bump and at least one conductive layer. The pad is disposed on the substrate and the polymer bump is disposed on the substrate. The polymer bump has a curved surface having a plurality of concave-convex structures. The polymer bump is covered by the conductive layer and the conductive layer is electrically connected with the pad.10-01-2009
20090243094Semiconductor device and manufacturing method thereof - The semiconductor device comprises a first area and a second area positioned adjacent to the outside of the first area, the semiconductor substrate having a main surface and side surfaces and disposed in such a manner that the main surface is positioned in the first area and each of the side surfaces is positioned at a boundary between the first area and the second area, a plurality of pads formed over the main surface of the semiconductor substrate and a plurality of external connecting terminals formed thereon, which are respectively electrically connected to the pads, a first resin portion which is formed over the main surface of the semiconductor substrate so as to cover the pads and has a main surface and side surfaces, and which is formed in such a manner that the external connecting terminals are exposed from the main surface and each of the side surfaces is positioned at the boundary, and a second resin portion which is positioned in the second area and formed so as to cover the side surfaces of the semiconductor substrate and the side surfaces of the first resin portion and which is different in composition from the first resin portion.10-01-2009
20090243092SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element; a plate member disposed opposite to an electronic-circuit forming portion of the semiconductor element; and an elastic body arranged in a compressed state between the semiconductor element and the plate member, wherein the elastic body includes at least one first protruding portion at one end in an extension direction of the elastic body, the first protruding portion being formed opposite to the electronic-circuit forming portion of the semiconductor element, and the semiconductor element and the plate member are fastened by an adhesive agent.10-01-2009
20090243091MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS - A mock bump system includes: providing a first structure having an edge; and forming a mock bump near the edge.10-01-2009
20090250812FLIP-CHIP MOUNTING SUBSTRATE AND FLIP-CHIP MOUNTING METHOD - A solder resist and a central pad to which a central Au bump provided on a semiconductor chip is flip-chip bonded are formed on a substrate main body. In a flip-chip mounting substrate where an underfill resin is provided after the semiconductor chip is mounted, a central opening portion for exposing the central pad is formed in the solder resist, and also, an edge portion forming the central opening portion of the solder resist is partially overlapped with the outer peripheral portion of the central pad.10-08-2009
20090250813INTEGRATED CIRCUIT SOLDER BUMPING SYSTEM - An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads.10-08-2009
20120193779SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.08-02-2012
20120193778INTEGRATED CIRCUIT HAVING PROTRUDING BONDING FEATURES WITH REINFORCING DIELECTRIC SUPPORTS - An integrated circuit (IC) die includes a substrate including a topside surface having active circuitry and a bottomside surface. A plurality of protruding bonding features are on the topside surface or bottomside surface and include at least one metal. The protruding bonding features including sidewalls having a neck region that includes an interface at or proximate to the topside surface or the bottomside surface. The protruding bonding features extend outward to a distal top edge. A dielectric support is positioned on the topside surface or bottomside surface between protruding bonding features. The dielectric support contacts and surrounds the sidewalls of the neck regions, does not extend beyond a height of the distal top edge, and is at least twenty percent taller where contacting the sidewalls as compared to a minimum non-zero height in a location between adjacent bonding features.08-02-2012
20120193782SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A semiconductor device includes a semiconductor element and an electronic element. The semiconductor element has a first protruding electrode, and the electronic element has a second protruding electrode. A substrate is disposed between the semiconductor element and the electronic element. The substrate has a through-hole in which the first and second protruding electrodes are fitted. The first and second protruding electrodes are connected together inside the through-hole of the substrate.08-02-2012
20120193781CUSTOMIZED RF MEMS CAPACITOR ARRAY USING REDISTRIBUTION LAYER - Disclosed is a method for fabricating a customized micro-electromechanical systems (MEMS) integrated circuit using at least one redistribution layer. The method includes steps of providing a substrate on which MEMS components are fabricated and coupling predetermined ones of the MEMS components via the redistribution traces.08-02-2012
20100264538METHOD FOR PRODUCING ELECTRICAL INTERCONNECTS AND DEVICES MADE THEREOF - A method for the fabrication of electrical interconnects in a substrate is disclosed. In one aspect, the method includes providing a substrate having a first main surface. The method may further include producing a ring structure in the substrate from the first main surface, which surrounds an inner pillar structure and has a bottom surface. The method may further include filling the ring structure with a dielectric material. The method may further include providing a conductive inner pillar structure, thereby forming an interconnect structure, which forms an electrical path from the bottom surface up until the first main surface. This conductive inner pillar structure can for example be provided by removing the inner pillar structure leaving a pillar vacancy and partially filling the vacancy with a conductive material. The dielectric material may be applied in liquid phase.10-21-2010
20120193786CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate.08-02-2012
20120193783PACKAGE ON PACKAGE - A package on package is provided herein, the package on package including a first semiconductor package including a first substrate, a first semiconductor chip stacked on the first substrate, a plurality of first connection members on an upper surface of the first substrate and in a first molding material, and a plurality of via holes which respectively expose the plurality of first connection members through the first molding material; a second semiconductor package including a second substrate, a second semiconductor chip stacked on the second substrate, and a plurality of second connection members on a lower surface of the second substrate; and a plurality of connection portions including a plurality of cores and a plurality of conductive fusion layers surrounding the plurality of cores, wherein the plurality of conductive fusion layers contact the upper surface of the first substrate and the lower surface of the second substrate.08-02-2012
20090273078Electronic packages - Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.11-05-2009
20100155944SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate and including a plurality of first portions and a second portion disposed between two of the first portions adjacent to each other; and an interconnect electrically connected to the electrode and extending over one of the first portions of the resin protrusion. A lower portion of a side surface of the second portion includes a portion which extends in a direction intersecting a direction in which the resin protrusion extends.06-24-2010
20100155941SEMICONDUCTOR DEVICE - A semiconductor device includes multiple electrode pads provided in an interconnection layer over a semiconductor substrate; an insulating layer provided on the interconnection layer so as to expose portions of the electrode pads; multiple conductive layers having their respective first ends connected to the exposed portions of the corresponding electrode pads so as to extend therefrom on the insulating layer; and multiple protruding electrodes provided at respective second ends of the conductive layers, wherein the conductive layers extend in a given direction relative to the electrode pads.06-24-2010
20080277783PRINTED CIRCUIT BOARD AND FLIP CHIP PACKAGE USING THE SAME WITH IMPROVED BUMP JOINT RELIABILITY - A printed circuit board and a flip chip package using the same are designed to minimize thermal stress due to different thermal coefficients present in areas having metal lines and solder resist versus other areas on the printed circuit board. The printed circuit board includes an insulation layer; a first metal line formed on one surface of the insulation layer and having at one end thereof a bump land and a projection which integrally extends from the bump land; a second metal line formed on the other surface of the insulation layer and having at one end thereof a ball land; a via metal line formed through the insulation layer to connect the first and second metal lines to each other; and solder resists formed on the upper and lower surfaces of the insulation layer to expose the bump land and the ball land.11-13-2008
20090065932Methods of forming nano-coatings for improved adhesion between first level interconnects and epoxy under-fills in microelectronic packages and structures formed thereby - Methods and associated structures of forming microelectronic devices are described. Those methods may include coating an interconnect structure disposed on a die with a layer of functionalized nanoparticles, wherein the functionalized nanoparticles are dispersed in a solvent, heating the layer of functionalized nanoparticles to drive off a portion of the solvent, and applying an underfill on the coated interconnect structure.03-12-2009
20100155945SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor chip; a plurality of electrodes formed on the semiconductor chip and arranged along one side of the semiconductor chip; a resin protrusion formed on the semiconductor chip and extending in a direction which intersects the side; and a plurality of electrical connection sections formed on the resin protrusion and electrically connected to the respective electrodes.06-24-2010
20100155940SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.06-24-2010
20100155943SEMICONDUCTOR CHIP USED IN FLIP CHIP PROCESS - A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.06-24-2010
20100155939CIRCUIT BOARD AND FABRICATION METHOD THEREOF AND CHIP PACKAGE STRUCTURE - A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.06-24-2010
20100155938FACE-TO-FACE (F2F) HYBRID STRUCTURE FOR AN INTEGRATED CIRCUIT - An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.06-24-2010
20100155937Wafer structure with conductive bumps and fabrication method thereof - A wafer structure with conductive bumps and fabrication method thereof are disclosed herein. Conductive bumps are later converted into conductive balls. A central area and a marginal area are defined on the wafer. To achieve heights among conductive balls formed on the wafer structure, the sizes (can be but not limited to one) of under bump metallurgy (UBM) layer blocks in the central area are smaller than that in the marginal area. The fabrication procedure for forming under bump metallurgy layer blocks of different size includes depositing a photoresist layer on the metallurgy layer and pattern the photoresist with a photomask of smaller opening area for the central area than for the marginal area, and removing the photoresist layer and the portion of metallurgy layer under the photoresist layer.06-24-2010
20090102049SEMICONDUCTOR DEVICE, LAYERED TYPE SEMICONDUCTOR DEVICE USING THE SAME, BASE SUBSTRATE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device has a plurality of external connection lands arranged on a base substrate for an external connection terminal used for electrical connection with an external member. The external connection lands at different arrangement positions have different heights in accordance with a warp of the base substrate which warp the base substrate would have when mounted. Thus, even when the semiconductor device, which attains a thin thickness and a high density, is warped, it is possible to provide a semiconductor device having a high connection yield and high connection reliability between the semiconductor device and a mounting substrate and between the semiconductor devices, and it is possible to provide a layered type semiconductor device using the same, a base substrate and a semiconductor device manufacturing method.04-23-2009
20100258938SUBSTRATE AND SEMICONDUCTOR DEVICE - A substrate (10-14-2010
20100187685SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (07-29-2010
20100176510Fusible I/O Interconnection Systems and Methods for Flip-Chip Packaging Involving Substrate-Mounted Stud Bumps - A semiconductor device has a semiconductor die with bond pads formed on a surface of the semiconductor die. A UBM is formed over the bond pads of the semiconductor die. A fusible layer is formed over the UBM. The fusible layer can be tin or tin alloy. A substrate has bond pads formed on a surface of the substrate. A plurality of stud bumps containing non-fusible material is formed over the bond pads on the substrate. Each stud bump includes a wire having a first end attached to the bond pad of the substrate and second end of uniform height electrically connected to the bond pad of the semiconductor die by reflowing the fusible layer or applying thermal compression bonding. An underfill material is deposited between the semiconductor die and substrate. An encapsulant is deposited over the semiconductor die and substrate.07-15-2010
20090079069Semiconductor Device and Method of Forming Interconnect Structure in Non-Active Area of Wafer - A semiconductor wafer includes a plurality of semiconductor die. Contact pads are formed on an active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. Solder bumps are formed on the contact pads in both the active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. The I/O terminal count of the semiconductor die is increased by forming solder bumps in the non-active area of the wafer. An encapsulant is formed over the solder bumps. The encapsulant provides structural support for the solder bumps formed in the non-active area of the semiconductor wafer. The semiconductor wafer undergoes grinding after forming the encapsulant to expose the solder bumps. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a package substrate with solder paste or socket.03-26-2009
20130214407SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances.08-22-2013
20130214408Interposer Having Conductive Posts - There are disclosed herein various implementations of an interposer for use in semiconductor packaging. One exemplary implementation comprises a conductive post formed from a wire bond. A first end of the conductive post is mechanically joined to a conductive pad on a first surface of the interposer, while a second end of the conductive post is capable of making electrical connection to a contact body on an active surface of a semiconductor die. Such an interposer may include a rigid or flexible interposer dielectric. In one exemplary implementation, the interposer dielectric has a via formed therein, the conductive post being situated in the via and extending through a second surface of the interposer opposite the first surface.08-22-2013
20130214409Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP - A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer.08-22-2013
20120032323SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL02-09-2012
20100187684System and Method for 3D Integrated Circuit Stacking - A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.07-29-2010
20100258939STACKED MICROFEATURE DEVICES AND ASSOCIATED METHODS - Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.10-14-2010
20100213610Semiconductor Device and Method of Forming an Interconnect Structure for 3-D Devices Using Encapsulant for Structural Support - A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.08-26-2010
20090294960SEMICONDUCTOR DEVICE - A semiconductor device, including: a substrate having an upper face on which a first ground pad, a first power supply pad, a first signal pad, and a second signal pad are formed; a first substrate formed on the substrate and having an upper face on which a third signal pad connected to the first signal pad and a first circuit are formed; and a semiconductor element including a second substrate having a reverse face on which a bump electrode connected to the first circuit and a second circuit are formed and an upper face on which a fourth signal pad connected to the second signal pad is formed, with a signal through via connected to the second circuit and the fourth signal pad being buried in the second substrate.12-03-2009
20120228767INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKABLE DEVICES AND A METHOD OF MANUFACTURE THEREOF - An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.09-13-2012
20100155942SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a connection electrode formed on a side of a semiconductor element substrate opposed to a bump, where the semiconductor element substrate includes a semiconductor element; a passivation layer covering the semiconductor element substrate and an end portion of the connection electrode; and a barrier metal layer covering the connection electrode and a portion of the passivation layer so as to be electrically connected to the bump. A recess is formed in a portion of the passivation layer connected with the barrier metal layer.06-24-2010
20090212421POLYMER INTERLAYER DIELECTRIC AND PASSIVATION MATERIALS FOR A MICROELECTRONIC DEVICE - Polymer interlayer dielectric and passivation materials for a microelectronic device are generally described. In one example, an apparatus includes one or more interconnect structures of a microelectronic device and one or more polymeric dielectric layers coupled with the one or more interconnect structures, the polymeric dielectric layers including copolymer backbones having a first monomeric unit and a second monomeric unit wherein the first monomeric unit has a different chemical structure than the second monomeric unit and wherein the copolymer backbones are cross-linked by a first cross-linker or a second cross-linker, or combinations thereof.08-27-2009
20100276801SEMICONDUCTOR DEVICE AND METHOD TO MANUFACTURE THEREOF - A semiconductor device 11-04-2010
20100001399Semiconductor Chip Passivation Structures and Methods of Making the Same - Various semiconductor chip passivation structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymeric passivation layer to a side of a semiconductor chip. The side of the semiconductor chip includes plural conductor pads. Plural openings are formed in the polymeric passivation layer to expose the plural conductor pads. Plural conductor structures are formed on the plural conductor pads.01-07-2010
20080315415Semiconductor device and manufacturing method thereof - The present invention provides a double-sided electrode package of a structure excellent in the reliability of connection and moisture resistance to another package, which is capable of being manufactured simply and at low cost. The present invention also provides a double-sided electrode package of a structure capable of forming inner wirings (electrode pads) in arbitrary layouts according to the number of pins of a semiconductor chip and the size thereof, which package is capable of being manufactured simply and at low cost. A copper foil is attached onto a core material formed with electrode pads, wirings, through electrodes, lands and a solder resist. The copper foil is wet-etched in several stages to form surface side terminals which stand on the wirings approximately vertically and each of which includes a plurality of protrusions (convex portions continuous in the circumferential direction) formed at their side faces over the full circumference along the circumferential direction. The peripheries of the surface side terminals are sealed with a sealing resin, and the end faces of the surface side terminals are exposed from a sealing resin layer, whereby redistribution wiring is performed at the surface of the sealing resin layer.12-25-2008
20120139105SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.06-07-2012
20120139102DISPOSING UNDERFILL IN AN INTEGRATED CIRCUIT STRUCTURE - In one embodiment, a method of forming a multi-die semiconductor device is provided. A plurality of dice is mounted on a semiconductor substrate, and neighboring ones of the dice are separated by a distance at which a first one of the neighboring dice will contact a meniscus of a flange of the neighboring die during underfill to form a capillary bridge between the neighboring dice. Solder bumps are reflowed to electrically connect contact terminals of the plurality of dice to contact terminals on a top surface of the substrate. Underfill is deposited along one or more edges of one or more of the plurality of dice. As a result of the capillary bridge formed between neighboring dice, flow of underfill is induced between the bottom surfaces of the neighboring dice and the top surface of the substrate. The dispensed underfill is cured.06-07-2012
20110210442Semiconductor Package and Trace Substrate with Enhanced Routing Design Flexibility and Method of Manufacturing Thereof - A semiconductor package, a method for manufacturing the semiconductor package, a trace substrate and a method for manufacturing the trace substrate are provided. The semiconductor package includes a trace substrate, a chip and a plurality of wires. The trace substrate includes a plurality of trace, a plurality of conductive studs, a plurality of traces pads and a trace modling compound. The conductive studs are formed on the lower surfaces of the traces. The trace modling compound encapsulates the conductive studs and the trace, and exposes the lower surfaces of the conductive studs and the upper surfaces of the traces. The chip is disposed on the trace substrate, and the wires electrically connect the chip and the trace pads. The trace pads are not overlapping to the conductive studs.09-01-2011
20100230809WIRE LOOP AND METHOD OF FORMING THE WIRE LOOP - A method of forming a wire loop is provided. The method includes: (1) forming a first fold of wire; (2) bonding the first fold of wire to a first bonding location to form a first bond; (3) extending a length of wire, continuous with the first bond, between (a) the first bond and (b) a second bonding location; and (4) bonding a portion of the wire to the second bonding location to form a second bond.09-16-2010
20110006421SOLDER INTERCONNECT PADS WITH CURRENT SPREADING LAYERS - Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.01-13-2011
20100140797DEVICE MOUNTING BOARD AND METHOD OF MANUFACTURING THE BOARD, SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE MODULE - A device mounting board is provided with: an insulating resin layer; a wiring layer provided on one major surface of the insulating resin layer; and a bump electrode electrically connected to the wiring layer and configured to be projected from the wiring layer toward the insulating resin layer. The bump electrode has an approximately convex-shaped top surface and at least the peripheral area on the top surface thereof is curve-shaped.06-10-2010
20120193785Multichip Packages - Multichip packages or multichip modules may include stacked chips and through silicon/substrate vias (TSVs) formed using enclosure-first technology. Enclosure-first technology may include forming an isolation enclosure associated with a TSV early in the fabrication process, without actually forming the associated TSV. The TSV associated with the isolation enclosure is formed later in the fabrication process. The enclosure-first technology allows the isolation enclosures to be used as alignment marks for stacking additional chips. The stacked chips can be connected to each other or to an external circuit such that data input is provided through the bottom-most (or topmost) chip, data is output from the bottom-most (or topmost) chip. The multichip package may provide a serial data connection, and a parallel connection, to each of the stacked chips.08-02-2012
20120193780SEMICONDUCTOR MOUNTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MOUNTING DEVICE - A semiconductor mounting device including a first substrate having first insulation layers, first conductor layers formed on the first insulation layers and via conductors connecting the first conductor layers, a second substrate having a core substrate, second conductor layers, through-hole conductors and buildup layers having second insulation layers and third conductor layers, first bumps connecting the first and second substrates and formed on the outermost first conductor layer on the outermost first insulation layer, and second bumps positioned to connect a semiconductor element and formed on the outermost third conductor layer on the outermost second insulation layer. The second substrate has greater thickness than the first substrate, the second conductor layers are formed on surfaces of the core substrate, respectively, the through-hole conductors are formed through the core substrate and connecting the second conductor layers, and the buildup layers are formed on the core substrate and second conductor layers, respectively.08-02-2012
20100207270SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, AND PORTABLE DEVICE - A semiconductor module is of a structure such that a wiring layer, an insulating resin layer and a semiconductor device are stacked in this order by bonding them together with compression. In the wiring layer, bump electrodes each having a base and a tip portion are provided in positions corresponding respectively to device electrodes of the semiconductor device. The bump electrodes penetrate the insulating resin layer and are electrically coupled to the corresponding device electrodes.08-19-2010
20100252924SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.10-07-2010
20100252925SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor chip having a rectangular surface on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the surface of the semiconductor chip; and a plurality of interconnects each of which is electrically connected to one of the electrodes and includes an electrical connection section disposed on one of the resin protrusions. At least part of the resin protrusions are disposed in a region near a short side of the surface and extend in a direction which intersects the short side.10-07-2010
20100252923SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device of the present invention includes a semiconductor chip formed with an electrode pad on a front side thereof, a wiring board having a wiring pattern, the wiring board having a front side opposing the back side of the semiconductor chip, a wire for electrically connecting the electrode pad of the semiconductor chip with the wiring pattern of the wiring board, an external terminal arranged on the back side of the wiring board for electrical connection with the electrode pad through the wire and the wiring pattern, and a sealant for fixing the semiconductor chip on the front side of the wiring board so as to form a hollow which is continuous to a portion straddling the entirety of the back side of the semiconductor chip and the front side of the wiring board, and continuous to a portion adjacent to at least one outer peripheral surface of the semiconductor chip except for the back side of the same. The wiring board includes a throughhole in communication with the hollow.10-07-2010
20090020874SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention is provided with a semiconductor chip in which a plurality of electrode pads is provided on a principal surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, a square-shaped wiring board which is disposed on a side of the principal surface of the semiconductor chip, and in which at least two sides of an outer circumference that face each other are positioned in an area on the principal surface of the semiconductor chip, a plurality of external terminals which is provided on the wiring board, and which are electrically connected to a plurality of the bump electrodes through a wiring of the wiring board, and sealing material which is provided between the semiconductor chip and the wiring board, and which covers a connection part between the bump electrode and the wiring.01-22-2009
20090020873SEMICONDUCTOR APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 μm or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.01-22-2009
20100164100Bump-on-Lead Flip Chip Interconnection - A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.07-01-2010
20100164097Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch - A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.07-01-2010
20100164096Structures and Methods for Improving Solder Bump Connections in Semiconductor Devices - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer.07-01-2010
20110057312CONTACT STRUCTURE AND METHOD FOR PRODUCING A CONTACT STRUCTURE - The invention relates to a contact structure (03-10-2011
20110057310SEMICONDUCTOR PACKAGE HAVING MEMORY DEVICES STACKED ON LOGIC DEVICE - A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes.03-10-2011
20110057309STRUCTURE, METHOD AND SYSTEM FOR ASSESSING BONDING OF ELECTRODES IN FCB PACKAGING - Structures, methods, and systems for assessing bonding of electrodes in FCB packaging are disclosed. In one embodiment, a method comprises mounting a semiconductor chip with a plurality of first electrodes of a first shape to a mounted portion with a second electrode of a second shape, wherein the second shape is different from the first shape, bonding a respective on of the plurality of first electrodes and the second electrode using a first solder bump, generating an X-ray image of the first solder bump, and determining an acceptability of the bonding of the respective one of the plurality of first electrodes and the second electrode based on the X-ray image of the first solder bump.03-10-2011
20110057308INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside the conductive pillar; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond.03-10-2011
20110057307Semiconductor Chip with Stair Arrangement Bump Structures - Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first conductor structure on a first side of a semiconductor chip and forming a second conductor structure in electrical contact with the first conductor structure. The second conductor structure is adapted to be coupled to a solder structure and includes a stair arrangement that has at least two treads.03-10-2011
20130127043MICRO SURFACE MOUNT DEVICE PACKAGING - A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of dice are mounted on a carrier (e.g., a plastic carrier). Each die has a plurality of wire bonded contact studs secured to its associated I/O pads. An encapsulant is applied over the carrier to cover the dice and at least portions of the contact studs to form an encapsulant carrier structure. After the encapsulant has been applied, a first surface of the encapsulant and the contact studs are ground such that exposed portions of the contact studs are smooth and substantially co-planar with the encapsulant. In some embodiments, a redistribution layer is formed over the encapsulant carrier structure and solder bumps are attached to the redistribution layer. A contact encapsulant layer is applied over the encapsulant carrier structure to provide extra mechanical support for the resulting packages.05-23-2013
20130127044MICRO SURFACE MOUNT DEVICE PACKAGING - A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of die cavities are formed in a plastic carrier. In some preferred embodiments, the die cavities are formed by laser ablation. A multiplicity of dice are placed on the carrier, with each die being placed in an associated die cavity. Each of the dice preferably has a multiplicity of I/O bumps formed thereon. An encapsulant is applied over the carrier to form an encapsulant layer that covers the dice and fills portions of the cavities that are not occupied by the dice. In some preferred embodiments, the encapsulant is an epoxy material applied by screen printing and the dice are not physically attached to the carrier prior to the application of the encapsulant. In these embodiments, the epoxy encapsulant serves to secure the dice to the carrier.05-23-2013
20130127047CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME - A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.05-23-2013
20100044860Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer - An interconnection element can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads, contacts, bond pads, traces, or the like exposed at the surface. A plurality of solid metal posts may overlie and project away from respective ones of the conductive elements. An intermetallic layer can be disposed between the posts and the conductive elements, such layer providing electrically conductive interconnection between the posts and the conductive elements. Bases of the posts adjacent to the intermetallic layer can be aligned with the intermetallic layer.02-25-2010
20090283903BUMP WITH MULTIPLE VIAS FOR SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF, AND SEMICONDUCTOR PACKAGE UTILIZING THE SAME - A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad to increase a surface area of an electrode interconnection. The multiple vias increase electrical and mechanical contact areas, thereby preventing current crowding and improving joint reliability. The bump for a semiconductor package may further comprise a stress relaxation layer at the lower portion of the bump.11-19-2009
20100065965METHODS OF FORMING SOLDER CONNECTIONS AND STRUCTURE THEREOF - A method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment with the trench structure. At least a pad metal containing layer is formed within the at least one opening (preferably by electroplating processes). The resist and the first metal layer underlying the resist are then etched (with the second metal layer acting as a mask, in embodiments). The method includes flowing solder material within the trench and on pad metal containing layer after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.03-18-2010
20100032831BUMP STRUCTURE FOE SEMICONDUCTOR DEVICE - There is provided a bump structure for a semiconductor device, comprising a first metal layer, and a second metal layer electrically connected to the first metal layer so as to be integrally formed with the first metal layer, and electrically connected to electrode pads of the semi-conductor device, in which the second metal layer is composed of one or more metals or alloys having the melting point higher than the melting point of the first metal layer or the eutectic temperature of the first metal layer and another substance when the first metal layer makes a fusion reaction to the surface of the another substance. Preferably, the second metal layer may have a thickness greater than that of the first metal layer. The bump structure may further comprise a diffusion prevention layer between the first metal layer and the second metal layer.02-11-2010
20090212427Solder Structures Including Barrier Layers with Nickel and/or Copper - An electronic device may include an electronic substrate, and an under bump seed metallurgy layer on the electronic substrate. A barrier layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the barrier layer and the electronic substrate, and the barrier layer may include nickel and/or copper. Moreover, portions of the under bump seed metallurgy layer may be undercut relative to portions of the barrier layer. In addition, a solder layer may be provided on the barrier layer so that the barrier layer is between the solder layer and the under bump seed metallurgy layer.08-27-2009
20090321927SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 12-31-2009
20090146298SEMICONDUCTOR DEVICE HAVING SOLDER-FREE GOLD BUMP CONTACTS FOR STABILITY IN REPEATED TEMPERATURE CYCLES - A semiconductor device has a chip (06-11-2009
20090140420SOFT ERROR RATE MITIGATION BY INTERCONNECT STRUCTURE - A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier.06-04-2009
20090039506SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR CHIP WHICH IS MOUNTED SPANING A PLURALITY OF WIRING BOARDS AND MANUFACTURING METHOD THEREOF - The semiconductor device is made up of two wiring boards, a semiconductor chip, and a sealing part. The two wiring boards are spaced apart, and a semiconductor chip is mounted so as to span the two wiring boards. The semiconductor chip includes a predetermined circuit and a plurality of electrode pads on one side thereof. The wiring board includes a plurality of connection pads on a semiconductor chip-mounting face, and a plurality of lands on the opposite side thereof. The land is electrically connected to a corresponding connection pad. An external terminal is formed on each of the lands. Further, the electrode pad formed in the semiconductor chip is electrically connected to the corresponding connection pad of the wiring board. Moreover, the semiconductor chip, the semiconductor chip mounting face of the wiring board, and the side faces of the wiring board are covered with the sealing part.02-12-2009
20080308930SEMICONDUCTOR DEVICE MOUNTING STRUCTURE, MANUFACTURING METHOD, AND REMOVAL METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device mounting structure includes a semiconductor device whose electrodes are aligned on its one main face; a circuit board having board electrodes electrically connected to the electrodes of the semiconductor device by solder bumps; and curable resin applied between at least the side face of the semiconductor device and the circuit board. Multiple types of thermally expandable particles with different expansion temperatures are mixed in this curable resin. This structure offers the semiconductor device mounting structure that is highly resistant to impact and suited for mass production, its manufacturing method, and a removal method of the semiconductor device. In addition, this structure facilitates repair and reworking, leaving almost no adhesive residue on the circuit board after repair. Stress applied to the circuit board during repair can also be minimized.12-18-2008
20090115057C4 JOINT RELIABILITY - In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.05-07-2009
20090115055MOUNTING STRUCTURE OF ELECTRONIC COMPONENT - A mounting structure of an electronic component includes: a substrate having a terminal and the electronic component which is mounted on the substrate; and a bump electrode included in the electronic component. This bump electrode has an underlying resin provided on an active surface of the electronic component, and a conductive film covering part of a surface of the underlying resin and exposing the rest so as to be electrically continued to an electrode terminal. In this mounting structure, the conductive film of the bump electrode makes direct conductive contact with the terminal, and the underlying resin of the bump electrode elastically deforms so that at least part of an exposed area which is exposed without being covered by the conductive film directly adheres to the substrate. Further, the substrate and the electronic component retain a state of the bump electrode making conductive contact with the terminal by adhesivity of the exposed area of the underlying resin to the substrate.05-07-2009
20090115054ELECTRONIC COMPONENT - An electronic component includes: an active surface; a plurality of external connection terminals included in the active surface; a bump electrode disposed to the active surface, the bump electrode including: an internal resin formed on the active surface as a core; and a conductive film on a surface of the internal resin, the internal resin being formed in a nearly half-cylindrical shape having a transverse section of one of a nearly semicircular shape, a nearly semielliptical shape, and a nearly trapezoidal shape and extending orthogonal to the transverse section, the transverse section being orthogonal to the active surface; and a global wiring line disposed on the active surface and connecting between the plurality of external connection terminals, and at least one of the external connection terminals being electrically connected to the conductive film.05-07-2009
20080303142ELECTRONIC SYSTEM WITH VERTICAL INTERMETALLIC COMPOUND - An electronic system is provided including forming a substrate having a contact, forming a conductive structure over the contact, mounting an electrical device having an external interconnect over the conductive structure, and forming a conductive protrusion from the conductive structure in the external interconnect.12-11-2008
20090072396Method of Forming Low Stress Multi-Layer Metallurgical Structures and High Reliable Lead Free Solder Termination Electrodes - Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed portion of the metal pad. A second film is deposited over the first film. A photoresist layer is deposited over the substrate, and a trench is formed in the photoresist layer directly over the portion of the metal pad. A first layer is electroplated in the trench over the second film, and a barrier layer is electroplated in trench over the first layer. A termination electrode, comprising tin, is electroplated in the trench over the barrier layer. The photoresist layer is removed. In addition, the method can include etching to remove the second film and first film beyond a predetermined area. The termination electrode is then reflowed. The barrier layer prevents formation of an intermetallic compound in proximity to the first layer by precluding diffusion of tin from the termination electrode to the first layer. In a specific embodiment, the first layer includes stress release copper underneath a barrier layer which includes nickel.03-19-2009
20090072395SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor element, a lead, and a gold wire electrically connecting an electrode of the semiconductor element and the lead. In the semiconductor device, the gold wire is covered with a metal and is a continuous film formed by plating.03-19-2009
20090072394SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer.03-19-2009
20090072393Structure and Method for Fabricating Flip Chip Devices - A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (03-19-2009
20090072392Techniques For Forming Solder Bump Interconnects - Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.03-19-2009
20090072391Structurally-enhanced integrated circuit package and method of manufacture - A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free form encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.03-19-2009
20080296760SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SAME - A semiconductor apparatus includes a semiconductor device having electrodes on its opposed frontside and backside, respectively, a first external electrode connected to the electrode at the frontside, the first external electrode having a first major surface generally parallel to the frontside of the semiconductor device, and a first side surface generally perpendicular to the first major surface, and a second external electrode having a second major surface generally parallel to the backside of the semiconductor device, a second side surface generally perpendicular to the second major surface, and a projection protruding perpendicular to the second major surface and connected to the electrode at the backside, The first side surface of the first external electrode and the second side surface of the second external electrode serve as mount surfaces. The semiconductor device is located between the first external electrode and the second external electrode.12-04-2008
20100219528Electromigration-Resistant Flip-Chip Solder Joints - A semiconductor device contact structure practically eliminating the copper diffusion into the solder as well as the current crowding at the contact with the subsequent electromigration in the solder. A column-like electroplated copper stud (09-02-2010
20080284012SEMICONDUCTOR MODULE MANUFACTURING METHOD, SEMICONDUCTOR MODULE, AND MOBILE DEVICE - A semiconductor substrate having on its surface an electrode of a semiconductor device and a pattern unit is prepared. A copper plate is formed provided with a first principle surface having a bump and a second principle surface, opposite to the first principle surface, having a trench. By adjusting the position of the copper plate so that a pattern unit and the corresponding trench have a predetermined positional relation, the bump and the electrode are aligned, the first principle surface of the copper plate and a semiconductor substrate are pressure-bonded via an insulating layer, and the bump and the electrode become connected electrically while the bump penetrating the insulating layer. A predetermined rewiring pattern is formed on the side of the second principle surface.11-20-2008
20090127708COPPER PILLAR TIN BUMP ON SEMICONDUCTOR CHIP AND METHOD OF FORMING THE SAME - Copper pillar tin bump on semiconductor chip comprises a copper layer composed on chip and a tin layer entirely wrapping whole outer surface of said copper layer. A method for forming of the copper pillar tin bump on semiconductor chip comprises: composing the first copper layer on said chip; applying photoresist to said first copper layer, exposing and developing a part of said photoresist, composing the copper pillar layer at the developed part of photoresist, composing the upper tin layer, removing said photoresist, removing said the first copper layer except disposing place of copper pillar layer, composing side tin layer. The minute pattern makes it possible to form a high density packaging by reducing a pitch of copper pillar tin bump. Signal delay can be reduced by low electric resistance, and underfill can be easily soaked.05-21-2009
20100187686SEMICONDUCTOR PACKAGE COMPRISING ALIGNMENT MEMERS - A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further includes a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member.07-29-2010
20110108980STABLE GOLD BUMP SOLDER CONNECTIONS - A metallic interconnect structure (05-12-2011
20090108442SELF-ASSEMBLED STRESS RELIEF INTERFACE - A method of forming an interconnect assembly is provided in which contacts exposed at a face of a first element such as, for example, a microelectronic element are aligned and joined with corresponding contacts of an interconnect element confronting the face of the first element. At least one of the i) the contacts of the first element, ii) the corresponding contacts of the interconnect element, iii) a joining metal between the contacts and the corresponding contacts includes a catalyst metal. Subsequently, a material including an organic component contacting the catalyst metal reacts to form volume expansion accommodation elements in the presence of the catalyst metal, the reaction being limited by proximity with the catalyst metal, such that the interconnect assembly includes volume expansion accommodation elements adjacent to the joined contacts.04-30-2009
20090108445SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE USING THE SAME - A substrate structure is provided. The substrate structure includes a substrate and a patterned wiring layer formed on the substrate. The patterned wiring layer includes a plurality of conductive traces. An isolation layer covers the patterned wiring layer and has an opening to expose a portion of at least one of the conductive traces therefrom. A plurality of conductive coatings covers the exposed portions of the conductive traces. The present invention further provides a semiconductor package with the above substrate structure.04-30-2009
20090108446ELECTRODE STRUCTURE FOR SEMICONDUCTOR CHIP - The bump electrode 04-30-2009
20090108444CHIP PACKAGE STRUCTURE AND ITS FABRICATION METHOD - A chip package structure and its fabrication method are disclosed. Method of electrically connecting a chip with plural different metal layers is utilized to replace the conventional method of connecting identical metal layer merely. Besides, the method of a protective layer directly set on the metal layer to cover the chip and the conductive connecting structure is different from the general method of coating the solder mask on the metal layer. Moreover, a carrier utilized for support makes lighter and thinner substrate be fabricated. The fabrication method is utilized to manufacture by using the fabrication process of present package manufacturing. No additional equipments and fabrication processes are needed so that the PCB production flow may be simplified to reduce the package cost.04-30-2009
20090026607Electronic Device and Method of Manufacturing Same - It is proposed a method of manufacturing an electronic system wherein a first substrate comprising first connection elements on a first surface of the first substrate is provided; a second substrate comprising second connection elements on a first surface of the second substrate is provided; a polymer layer is applied to at least one of the two first surfaces; the first connection elements are attached to the second connection elements; and the polymer layer is caused to swell during or after the attachment.01-29-2009
20100295173Composite Underfill and Semiconductor Package - Embodiments of the invention exploit physical properties of nanostructures by using nanostructures in a composite underfill. An embodiment is a composite underfill comprising an epoxy matrix applied between a substrate and a semiconductor chip and a suspension of nanostructures distributed within the epoxy matrix. Another embodiment is a semiconductor package comprising a semiconductor chip, a carrier, wherein the semiconductor chip is bonded to the carrier, and a composite underfill comprising a plurality of nanostructures dispersed in an epoxy medium between the carrier and the semiconductor chip. Further embodiments include a method for creating a semiconductor package comprising a composite underfill.11-25-2010
20100295174WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate includes: a semiconductor chip on which a plurality of bumps are mounted, and a plurality of connection pads which are joined to the bumps mounted on the semiconductor chip in a flip chip method, wherein the connection pads of a peripheral portion of the wiring substrate are formed in a non-solder mask defined structure, and the connection pads of a center portion of the wiring substrate are formed in a solder mask defined structure.11-25-2010
20100295178SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A first wiring pattern is formed on a surface of a first support plate; a semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions. Post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a second support plate are collectively fixed and electrically connected to the first wiring pattern formed on the first support plate at predetermined positions. After sealing with resin, the first and second support plates are separated; a glass substrate is affixed on a front face side; and external electrodes connected to the second wiring pattern are formed on a back face side.11-25-2010
20100301473COMPONENT BUILT-IN WIRING BOARD AND MANUFACTURING METHOD OF COMPONENT BUILT-IN WIRING BOARD - Disclosed is a component built-in wiring board, including a first insulating layer; a second insulating layer positioned in a laminated state on the first insulating layer; a semiconductor element buried in the second insulating layer, having a semiconductor chip with terminal pads and having surface mounting terminals arrayed in a grid shape connected electrically with the terminal pads; an electric/electronic component further buried in the second insulating layer; a wiring pattern sandwiched between the first insulating layer and the second insulating layer, including a first mounting land for the semiconductor element and a second mounting land for the electric/electronic component; a first connecting member connecting electrically the surface mounting terminal of the semiconductor element with the first mounting land; and a second connecting member connecting electrically the terminals of the electric/electronic component with the second mounting land, made of a same material as a material of the first connecting member.12-02-2010
20100301474Semiconductor Device Package Structure and Method for the Same - The present invention discloses a semiconductor device package and the method for the same. The method includes preparing a first substrate and a second substrate; opening a die opening window through the second substrate by using laser or punching; preparing an adhesion material; attaching the first substrate to the second substrate by the adhesion material; aligning a die by using the aligning mark of the die metal pad and attaching the die onto the die metal pad with force by the adhesion material; forming a first dielectric layer on top surfaces of the second substrate and the die and pushing the first dielectric layer into gap between the side wall of the die and the side wall of the die opening window under vacuum condition; opening a plurality of via openings in the first dielectric layer; and forming a redistribution layer in the plurality of via openings and on the first dielectric layer.12-02-2010
20100301472ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF - An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.12-02-2010
20120241951WAFER BUMPING USING PRINTED UNDER BUMP METALIZATION - Methods, systems, and apparatuses for printing under bump metallization (UBM) features on chips/wafers are provided. A wafer is received that has a surface defined by a plurality of integrated circuit regions. Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. A plurality of UBM features are formed on the surface of the wafer in the form of an ink such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals. An ink jet printer may be used to print the ink in the form of the UBM feature. A UBM feature may be formed directly on a corresponding terminal, or on routing that is coupled to the corresponding terminal. A bump interconnect may be formed on the UBM feature.09-27-2012
20130140692WIRING SUBSTRATE, MANUFACTURING METHOD OF WIRING SUBSTRATE, AND SEMICONDUCTOR PACKAGE INCLUDING WIRING SUBSTRATE - A wiring substrate includes an insulating layer having a first surface on which a projecting part is formed, and an electrode pad being formed on the projecting part and including a first electrode pad surface and a second electrode pad surface on a side opposite to the first electrode pad surface. The first electrode pad surface is exposed from the projecting part of the insulating layer. The second electrode pad surface is covered by the insulating layer. A cross-section of the projecting part is a tapered shape. One side of the cross-section toward the first electrode pad surface is narrower than another side of the cross-section toward the first surface of the insulating layer.06-06-2013
20100314755PRINTED CIRCUIT BOARD, SEMICONDUCTOR DEVICE COMPRISING THE SAME, AND METHOD OF MANUFACTURING THE SAME - Disclosed is a printed circuit board, which includes a first circuit layer embedded in one surface an insulating layer and including a bump pad and a wire bonding pad, thus realizing a high-density wire bonding pad. A semiconductor device including the printed circuit board and a method of manufacturing the printed circuit board are also provided.12-16-2010
20110121450SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - A semiconductor device includes a support plate having a hole formed therein and a conductor formed on a wall surface of the hole, a semiconductor element; and a conductive post formed by a conductor having a first end portion at one end, and a second end portion at an other end. The second end portion of the conductive post is connected to the semiconductor element, and a side surface of the conductive post is fixed to the conductor on the wall surface of the hole deformed by pressing force of the conductive post on a side closer to the first end portion than the second end portion.05-26-2011
20110121452Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers - A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.05-26-2011
20110121449Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP - A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.05-26-2011
20090243097SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC CONSTANT FILM AND MANUFACTURING METHOD THEREOF - A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric constant film/wiring line stack structure is covered with a sealing film. This provides a structure in which the low dielectric constant films do not easily come off. In this case, a lower protective film is provided on the lower surface of a silicon substrate to protect this lower surface against cracks.10-01-2009
20090243096SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a method of manufacturing the same are disclosed. The method is carried out by forming solder pads on a substrate by wet etching, flipping a semiconductor chip having a plurality of connection bumps formed on an active surface of the semiconductor chip for the connection bumps to be mounted by compression on the solder pads of the substrate correspondingly, at a temperature of the compression between the connection bumps and the solder pads lower than the melting points of the solder pads and the connection bumps, so as to allow the semiconductor chip to be engaged with and electrically connected to the substrate through the connection bumps and the solder pads, thereby enhancing the bonding strength of the solder pads and the connection bumps and increasing the fabrication reliability.10-01-2009
20100133686CHIP PACKAGE STRUCTURE - A chip package includes a die, a pad-mounting surface on the die, a plurality of bonding pad arranged at the pad-mounting surface, at least one dielectric layer cover over the pad-mounting surface, and at least one conductive wire set in the dielectric layer. The formation of the conductive wire consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.06-03-2010
20110006417SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor element having a first terminal surface on which a first terminal is disposed and a first rear surface on which no terminal is disposed; a second semiconductor element having a second terminal surface on which a second terminal is disposed and a second rear surface on which no terminal is disposed, the second rear surface being bonded to the first rear surface; a terminal member having a surface set substantially flush with the second terminal surface; and a conductive wire connecting the terminal member and the first terminal.01-13-2011
20100181667SEMICONDUCTOR DEVICE MOUNTED STRUCTURE AND ITS MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MOUNTING METHOD, AND PRESSING TOOL - While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding use resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding use resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. In the semiconductor chip mounted structure formed in this way, entire side faces at the corner portions of the semiconductor chip are covered with the seal-bonding use resin. As a result, loads generated at corner portions of the semiconductor chip due to board flexures for thermal expansion differences and thermal contraction differences among the individual members caused by heating process and cooling process in mounting operation as well as for mechanical loads after the mounting operation so that internal breakdown of the semiconductor chip can be avoided.07-22-2010
20110018130SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MODULE - A semiconductor package is provided with a functionally necessary minimum number of components with which stress concentrated on specific solder bumps is reduced and ruptures of the bumps are prevented even when stress caused by physical bending or a difference in thermal expansion coefficient is applied to the package. The semiconductor package includes a tabular die and bonding pads arranged on a mounting surface of the die. A passivation layer and a protective film are provided on the mounting surface such that central areas of the bonding pads are open. Under-bump metals (UBMs) connected to the bonding pads are provided in the openings, and solder bumps are provided on the surfaces of the UBMs. The diameter of the UBMs provided at corners of the die is less than that of the UBM provided at the approximate center of the die so that the elastic modulus of the UBMs provided at the corners is small.01-27-2011
20110108982PRINTED CIRCUIT BOARD - A printed circuit board includes a body part formed with connection pads on a first surface thereof; and a warpage compensating part formed over the first surface of the body part and having a height that increases from edges toward a center of the warpage compensating part so that an upper surface of the warpage compensating part facing away from the first surface of the body part is convex upward. The warpage compensating part comprises conductive layer patterns formed over the first surface of the body part to be electrically connected to the connection pads; and a solder resist formed over the first surface of the body part so as to expose the conductive layer patterns. The height of the solder resist gradually increases from both edges toward a center of the solder resist.05-12-2011
20110108981REDISTRIBUTION LAYER ENHANCEMENT TO IMPROVE RELIABILITY OF WAFER LEVEL PACKAGING - An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.05-12-2011
20090065931PACKAGED INTEGRATED CIRCUIT AND METHOD OF FORMING THEREOF - Disclosed is a packaged integrated circuit and a method of forming thereof. The packaged integrated circuit includes a substrate, a plurality of solder bumps, a semiconductor die and a plurality of copper bumps. The plurality of solder bumps are configured on the substrate. Each of the plurality of solder bumps has a height of about 40 micrometers (μm) to about 65 μm. Further, the plurality of copper bumps are configured on the semiconductor die. Each of the plurality of copper bumps has a height of about 10 μm to about 25 μm. The semiconductor die is disposed above the substrate such that the plurality of copper bumps are coupled to the plurality of solder bumps, which in turn, couples the semiconductor die to the substrate.03-12-2009
20110024901MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer. Next, a dielectric layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal via the second opening is formed by modifying a photosensitive resin film, and a bump that is electrically connected to the third conductive layer is formed.02-03-2011
20090014873ELECTRONIC DEVICE AND MANUFACTURING METHOD - An electronic device including a semiconductor device with a plurality of bump electrodes, a mounting board connected to the semiconductor device, thermally expandable particles, and adhesive. The thermally expandable particles are provided on the sides of the semiconductor device and the surface of the mounting board around a projected area of the semiconductor device. The adhesive is provided on the sides of the semiconductor device and the surface of the mounting board such that it covers the area of thermally expandable particles. This improves the impact resistance of the semiconductor device soldered onto the mounting board, and also facilitates removal of the semiconductor device from the mounting board when the semiconductor device needs repair.01-15-2009
20110127668Semiconductor Device and Method of Forming Bump Structure with Multi-Layer UBM Around Bump Formation Area - A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.06-02-2011
20110031617SEMICONDUCTOR PACKAGE SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.02-10-2011
20110031616STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands in contact with the underlying metal layer. The method also includes forming a solder bump in electrical connection to the plurality of metal line islands.02-10-2011
20090230552Bump-on-Lead Flip Chip Interconnection - A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die attach surface, in which the bumps are mated directly onto the traces. In some embodiments the interconnection is formed without employing a solder mask. In some methods a curable adhesive is dispensed either onto the bumps on the die or onto the traces on the substrate; the adhesive is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process.09-17-2009
20110042804CHIP PACKAGE AND FABRICATION METHOD THEREOF - The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.02-24-2011
20110042808SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor element having a plurality of element electrodes formed thereon, a circuit board having board electrodes respectively corresponding to the element electrodes formed thereon and having the semiconductor element mounted thereon, and bumps each of which is provided on at least one of the element electrode and the board electrode, and connects together the element electrode and the board electrode corresponding to each other when the semiconductor element is mounted on the circuit board. Furthermore, at least one of a dielectric layer and a resistive layer is provided between at least one of the bumps and the element or board electrode on which the at least one of the bumps is provided, so that the element or board electrode, the dielectric layer or the resistive layer, and the bump form a parallel-plate capacitor or electrical resistance.02-24-2011
20110042807CHIP PACKAGE AND FABRICATION METHOD THEREOF - The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.02-24-2011
20110042806MULTI-CHIP MODULE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a multi-chip module includes: securing a plurality of chips on a surface of a flat-shaped member through a solder bump; connecting the plurality of chips with each other by a bonding wire, at surfaces, opposite to the flat-shaped member side, of the plurality of chips; and electrically connecting the plurality of chips with a board, at the surfaces, opposite to the flat-shaped member side, of the plurality of chips.02-24-2011
20110042805PACKAGE STRUCTURES FOR INTEGRATING THERMOELECTRIC COMPONENTS WITH STACKING CHIPS - Package structures for integrating thermoelectric components with stacking chips are presented. The package structures include a chip with a pair of conductive through vias. Conductive elements are disposed one side of the chip contacting the pair of conductive through vias. Thermoelectric components are disposed on the other side of the chip, wherein the thermoelectric component includes a first type conductive thermoelectric element and a second type conductive thermoelectric element respectively corresponding to and electrically connecting to the pair of conductive through vias. A substrate is disposed on the thermoelectric component, wherein the thermoelectric component, the pair of conductive through vias and the conductive element form a thermoelectric current path. Therefore, heat generated from the chip is transferred outward through a thermoelectric path formed from the thermoelectric components, the conductive through vias and the conductive elements.02-24-2011
20110018128PACKAGE STRUCTURE AND METHOD FOR REDUCING DIELECTRIC LAYER DELAMINATION - A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.01-27-2011
20110121451ELECTRONIC DEVICE AND ELECTRONIC APPARATUS - An electronic device includes a semiconductor device and a wiring substrate having a wiring pattern. The semiconductor device includes: a semiconductor chip having an electrode; a convex-shaped resin protrusion provided on a surface of the semiconductor chip, the surface having the electrode; and wiring having a plurality of electrical coupling sections which are aligned on the resin protrusion and electrically coupled to the electrode. The semiconductor device is mounted to the wiring substrate so that the electrical coupling sections and the wiring pattern are brought into contact and electrically coupled with each other. The plurality of electrical coupling sections brought into contact with the wiring pattern include curved or bent shapes projecting in a longitudinal direction of the resin protrusion.05-26-2011
20110079898SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, CIRCUIT BOARD, AND ELECTRONIC INSTRUMENT - A substrate includes an insulating film in which a penetrating hole is formed, the penetrating hole extending between a first surface of the insulating film and a second surface of the insulating film opposite to the first surface of the insulating film. A wiring pattern is adhered to the first surface of the insulating film by an adhesive material. A first portion of the wiring pattern is formed over the penetrating hole, and a part of the adhesive material is formed on an internal wall surface forming the penetrating hole so as not to stop up the penetrating hole. An external electrode contacts the first portion of the wiring pattern and projects through the penetrating hole and extends beyond the second surface of the insulating film.04-07-2011
20110084388REDUCING UNDERFILL KEEP OUT ZONE ON SUBSTRATE USED IN ELECTRONIC DEVICE PROCESSING - Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a layer on the substrate outside of the die attach area. The layer may be formed from a fluoropolymer material. The method also includes coupling a die to the substrate in the die attach area, wherein a gap remains between the die and the die attach area. The method also includes placing an underfill material in the gap and adjacent to the layer on the substrate. Examples of fluoropolymer materials which may be used include polytetrafluoroethylene (PTFE) and perfluoroalkoxy polymer resin (PFA). Other embodiments are described and claimed.04-14-2011
20110084386Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask - A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate.04-14-2011
20110210441CHIP PACKAGE - A chip package includes a semiconductor chip, a flexible circuit film and a substrate. The substrate has a circuit structure in the substrate. The flexible circuit film is connected to the circuit structure of the substrate through metal joints, an anisotropic conductive film or wireboning wires. The semiconductor chip has fine-pitched metal bumps having a thickness of between 5 and 50 micrometers, and preferably of between 10 and 25 micrometers, and the semiconductor chip is joined with the flexible circuit film by the fine-pitched metal bumps using a chip-on-film (COF) technology or tape-automated-bonding (TAB) technology. A pitch of the neighboring metal bumps is less than 35 micrometers, such as between 10 and 30 micrometers.09-01-2011
20090032942SEMICONDUCTOR CHIP WITH SOLDER BUMP AND METHOD OF FABRICATING THE SAME - A semiconductor chip having a solder bump and a method of fabricating the same are provided. The semiconductor chip includes at least one under bump metal (UBM) layer formed on an electrode pad of the semiconductor chip, an adhesion enhance layer (AEL) formed on the UBM layer and having at least one concavo-convex portion on a top surface thereof, and the solder bump formed on the AEL. Thereby, adhesive solder bump is increased, and thereby the reliability of the semiconductor chip can be improved. Further, it is possible to prevent tin (Sn) in the solder bump from being diffused due to the AEL.02-05-2009
20100164099Semiconductor integrated circuit device - A semiconductor integrated circuit device includes plural circuit units each having plural logic circuits; and plural power terminals supplying power source from outside to the semiconductor integrated circuit device, in which the plural circuit units each having plural logic circuits have common packaging design with each other, and lengths in a vertical direction and a lateral direction of the circuit units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.07-01-2010
20100164098SEMICONDUCTOR DEVICE INCLUDING A COST-EFFICIENT CHIP-PACKAGE CONNECTION BASED ON METAL PILLARS - In sophisticated semiconductor devices, a chip-package interconnect structure may be established on the basis of a metal pillar without using a solder bump material in the package. In this case, the complexity of the manufacturing process for forming the wiring system of the package may be significantly reduced, while also providing the possibility of increasing packing density of the pillar structure.07-01-2010
20110074022Semiconductor Device and Method of Forming Flipchip Interconnect Structure - A semiconductor device has a semiconductor die with a plurality of bumps or interconnect structures formed over an active surface of the die. The bumps can have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. A plurality of conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites under pressure or reflow temperature so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the die and substrate. The masking layer can form a dam to block the encapsulant from extending beyond the semiconductor die. Asperities can be formed over the interconnect sites or bumps.03-31-2011
20090085204Wafer-level package and method of manufacturing the same - Provided is a wafer-level package including a wafer-level semiconductor chip having a plurality of integrated circuits (ICs) and pads formed on the top surface thereof; a molding material of which the outer portion is supported by the top surface of the semiconductor chip such that a cavity is provided on the semiconductor chip; and a conducive member filled in a plurality of vias which are formed in arbitrary positions of the molding material so as to pass through the molding material, the conductive member being connected to the pads.04-02-2009
20110241203SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, AND PORTABLE APPARATUS - A semiconductor module includes a device mounting board and a semiconductor device. The semiconductor device and the device mounting board are flip-chip connected to each other, and a device electrode provided in the semiconductor device and a substrate electrode provided in the device mounting board are connected by soldering. In a cross section along a line connecting the adjacent substrate electrodes, the width L10-06-2011
20110241202Dummy Metal Design for Packaging Structures - An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.10-06-2011
20110241201Radiate Under-Bump Metallization Structure for Semiconductor Devices - An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions.10-06-2011
20110079896SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device fabrication method, comprising the steps of: forming a solder portion on an electrode of a substrate on which a semiconductor chip is to be mounted; applying a resin layer onto the substrate to a thickness such that a top region of the solder portion is exposed; curing the resin layer; providing a thermosetting underfill material over a region where the semiconductor chip is to be mounted; placing an electrode of the semiconductor chip face down on the solder portion in such a manner that the electrode faces the solder portion; and heating the underfill material and the solder portion.04-07-2011
20100219527METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE INCLUDING METAL PILLARS HAVING A REDUCED DIAMETER AT THE BOTTOM - In a metallization system of a complex semiconductor device, metal pillars, such as copper pillars, may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks.09-02-2010
20110133334Semiconductor Device and Method of Confining Conductive Bump Material with Solder Mask Patch - A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate.06-09-2011
20090096092Bump I/O Contact for Semiconductor Device - A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown.04-16-2009
20090102048ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - Electronic device has substrate having at least one pad, electronic component having bump connected with pad of substrate electrically and mounting on substrate by flip chip bonding, conductive resin electrically connecting pad with bump, and insulation sheet disposed between substrate and electronic component. Substrate has recess on surface opposite to electronic component. Pad is formed on recess bottom. Conductive resin is provided on pad and in recess. Sheet has through hole corresponding to each bump. Opening area of through hole is smaller than that of recess. Bump is inserted into through hole, in contact with inner wall of through hole, electrically connected with pad via conductive resin, without direct contact with pad.04-23-2009
20090102047Flip chip package structure and carrier thereof - A flip chip package structure including a chip, a carrier, and a plurality of bumps is provided. The chip has a bonding surface and a plurality of bump pads thereon. The carrier is disposed corresponding to the chip and includes a substrate and a plurality of pre-solders. The substrate has a carrying surface and a patterned trace layer thereon. The patterned trace layer has a plurality of traces, and each of the traces has an outward protruding bonding portion corresponding to the bump. The line width of the bonding portion is greater than that of the trace. The pre-solders are disposed on the bonding portions, respectively. The bumps are disposed between the bump pads and the corresponding pre-solders such that the chip is electrically connected to the carrier through the bumps.04-23-2009
20110084387DESIGNS AND METHODS FOR CONDUCTIVE BUMPS - Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.04-14-2011
20110084384SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a semiconductor chip that is bonded to one of the faces of the substrate via bumps, and has a device formation face facing the one of the faces, and a resin that fills the space between the device formation face of the semiconductor chip and the one of the faces of the substrate. The resin includes: a first resin that is formed in a formation region of bumps placed on the outermost circumference of the bumps, and is formed inside the formation region, and a second resin that is formed outside the first resin. The thermal expansion coefficient of the substrate is higher than the thermal expansion coefficient of the first resin. The thermal expansion coefficient of the second resin is higher than the thermal expansion coefficient of the first resin.04-14-2011
20110084385Semiconductor device and information processing system including the same - A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.04-14-2011
20110084382CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed.04-14-2011
20110147924WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A wiring substrate includes an insulating layer, a wiring layer buried in the insulating layer, and a connection pad connected to the wiring layer via a via conductor provided in the insulating layer and in which at least a part is buried in an outer surface side of the insulating layer, wherein the connection pad includes a first metal layer (a first copper layer) arranged on the outer surface side, an intermediate metal layer (a nickel layer) arranged on a surface of an inner layer side of the first metal layer, and a second metal layer (a second copper layer) arranged on a surface of an inner layer side of the intermediate metal layer, and a hardness of the intermediate metal layer is higher than a hardness of the first metal layer and the second metal layer.06-23-2011
20110084383SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first circuit base member including a surface having multiple first electrodes formed thereon, a second circuit base member being provided above the first circuit base member and having first through holes and second through holes formed respectively above the first electrodes, a semiconductor package provided above the second circuit base member, and multiple first bumps provided inside the first through holes and the second through holes to connect the first electrodes to the semiconductor package.04-14-2011
20110084381Chip Having A Metal Pillar Structure - The present invention relates to a chip having a metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar. Therefore, when the pitch between two adjacent metal pillar structures of the chip is a fine pitch, the defect of solder bridge can be avoided, so that the yield rate is improved.04-14-2011
20090212420 INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING SAME - Fabricating an integrated circuit device includes providing a semiconductor substrate comprising a first surface and a sec-ond surface, forming a wiring layer on the first surface of the semiconductor substrate, providing a circuit chip, and arranging the circuit chip on the wiring layer of the semi-conductor substrate. The fabricating further includes forming an embedding layer on the wiring layer and on the circuit chip, the embedding layer encapsulating the circuit chip, thinning the semiconductor substrate at the second surface after forming the embedding layer, and forming a conductive via in the semiconductor substrate being electrically coupled to the wiring layer and exposed at the second surface of the semiconductor substrate. Moreover, an integrated circuit de-vice is described.08-27-2009
20100032829STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.02-11-2010
20090218687Semiconductor Chip with Passivation Layer Comprising Metal Interconnect and Contact Pads - The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.09-03-2009
20090218686SEMICONDUCTOR, SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING THE SEMICONDUCTOR MODULE, AND MOBILE APPARATUS - A semiconductor module includes a device mounting board and a semiconductor device mounted on the device mounting board. The device mounting board includes an insulating resin layer, a wiring layer provided on one main surface of the insulating resin layer, and bump electrodes, electrically connected to the wiring layer, which are protruded from the wiring layer toward the insulating resin layer. The semiconductor device has device electrodes which are disposed counter to a semiconductor substrate and the bump electrodes, respectively. The surface of a metallic layer provided on the device electrode lies on the same plane as the surface of a protective layer.09-03-2009
20090218685SEMICONDUCTOR MODULE AND METHOD OF PRODUCING THE SAME - A semiconductor module including: a semiconductor chip in which an integrated circuit is formed; an electrode formed on the semiconductor chip and electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having an opening positioned corresponding to the electrode; an elastic protrusion disposed on the insulating film, a surface of the elastic protrusion opposite to the insulating film being convexly curved; an interconnect extending from over the electrode to over the elastic protrusion; an elastic substrate on which a lead is formed, the lead being in contact with part of the interconnect positioned on the elastic protrusion; and an adhesive maintaining a space between a surface of the semiconductor chip on which the elastic protrusion is formed and a surface of the elastic substrate on which the lead is formed. The elastic substrate has a first depression formed by elastic deformation. The lead is in contact with the interconnect on a surface of the first depression.09-03-2009
20090218684AUTOCLAVE CAPABLE CHIP-SCALE PACKAGE - A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.09-03-2009
20100038778INTEGRATED CIRCUIT STRUCTURES AND FABRICATING METHODS THAT USE VOIDS IN THROUGH HOLES AS JOINING INTERFACES - A void that is created in a conductive electrode in a through hole that extends through an integrated circuit substrate can be used as a joining interface. For example, an integrated circuit structure includes an integrated circuit substrate having a conductive pad on a first face thereof, and a through hole that extends through the integrated circuit substrate from a second face of the integrated circuit substrate that is opposite to the first face and through the pad. A conductive electrode is provided in the through hole that extends from the second face to the first face through and onto the pad. The conductive electrode includes a void therein adjacent the second face. The void includes a void opening adjacent the second face that defines inner walls of the conductive electrode. A conductive material is provided in the void that directly contacts the inner walls of the conductive electrode. Related fabrication methods are also disclosed.02-18-2010
20100038777METHOD OF MAKING A SIDEWALL-PROTECTED METALLIC PILLAR ON A SEMICONDUCTOR SUBSTRATE - A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.02-18-2010
20100013091SEMICONDUCTOR DEVICE INCLUDING A COPOLYMER LAYER - A semiconductor device including a chip including an integrated circuit, a conductive layer, a copolymer layer and metal elements. The conductive layer is disposed over the chip and electrically coupled to the integrated circuit. The copolymer is disposed on the conductive layer. The metal elements are electrically coupled to the conductive layer via through-connects in the copolymer layer.01-21-2010
20100032834METHOD FOR FORMING BUMPS IN SUBSTRATES WITH THROUGH VIAS - A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump.02-11-2010
20100032833SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.02-11-2010
20100032832SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - In this semiconductor chip 02-11-2010
20100038779SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a first main surface having an electrode pad in an exposed state, and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-wiring layer including a wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion with a recessed polygonal shape and connected to the other end portion of the linear portion; a post electrode formed on the post electrode mounting portion and having a bottom surface with a contour crossing an upper contour of the post electrode mounting portion at more than two points; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode.02-18-2010
20090032939METHOD OF FORMING A STUD BUMP OVER PASSIVATION, AND RELATED DEVICE - A method of forming a stud bump over passivation, and related device. At least some of the illustrative embodiments are methods comprising depositing a first passivation layer over a semiconductor die, depositing a capping metal layer over the first passivation layer (the capping metal layer comprises a capping metal pad), and depositing a stud bump onto the capping metal pad.02-05-2009
20100072617Multiple die structure and method of forming a connection between first and second dies in same - A multiple die structure includes a first die (03-25-2010
20120146215BONDING PAD STRUCTURE AND INTEGRATED CIRCUIT COMPRISING A PLURALITY OF BONDING PAD STRUCTURES - A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.06-14-2012
20120241953UNIT FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device has a single unit capable of improving adhesion to a cooling body and a heat dissipation performance, and an aggregate of the single units is capable of configuring any circuit at a low cost. A single unit (09-27-2012
20120241949SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF MANUFACTURING WIRING BOARD - A semiconductor device includes: a solder bump including a barrier metal layer formed on an electrode pad portion of a substrate, and a solder layer formed at a central portion of an upper surface of the barrier metal layer so as to have a smaller outer diameter than that of the barrier metal layer.09-27-2012
20120241947INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LOCKING INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a hole, a lead extension, and an exterior pad under the lead extension with the hole abutting the lead extension; connecting an electrical interconnect between an integrated circuit and the lead extension; forming an encapsulation over the integrated circuit and surrounding the electrical interconnect and through the hole; and removing a bottom portion of the lead frame resulting in a stand-off lead from the lead extension with the exterior pad on the stand-off lead.09-27-2012
20120241946Semiconductor Device and Method of Forming High Routing Density Interconnect Sites on Substrate - A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.09-27-2012
20120241945Semiconductor Device and Method of Forming Flipchip Interconnect Structure - A semiconductor device has a semiconductor die with a plurality of bumps or interconnect structures formed over an active surface of the die. The bumps can have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. A plurality of conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites under pressure or reflow temperature so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the die and substrate. The masking layer can form a dam to block the encapsulant from extending beyond the semiconductor die. Asperities can be formed over the interconnect sites or bumps.09-27-2012
20090121350BOARD ADAPTED TO MOUNT AN ELECTRONIC DEVICE, SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREFORE, AND PORTABLE DEVICE - A board adapted to mount an electronic device includes an insulating resin layer, a wiring layer of a predetermined pattern provided on one surface of the insulating resin layer, a bump electrode provided on an insulating-resin-layer-side surface of the wiring layer, and a covering, formed of a metal layer, which covers a top surface of the bump electrode and a region, at a side surface of the bump electrode, continuous with the top surface excluding a region in contact with the wiring layer.05-14-2009
20090121348CHIP STRUCTURE AND PROCESS THEREOF AND STACKED STRUCTURE OF CHIPS AND PROCESS THEREOF - A chip structure and a stacked structure composed of the chip structures are provided. The chip structure has a substrate and at least one compliant contact. Furthermore, the chip structure may further have a redistribution layer for redistributing pads originally disposed around the substrate in a specific arrangement. The substrate has a first surface and a second surface. The compliant contact is embedded into the substrate and protrudes outside the first surface and the second surface of the substrate. The compliant contact has a compliant bump and a conductive layer encapsulating the compliant bump. The conductive layer can be connected with the redistribution layer. Two chip structures can be connected with each other through their compliant contacts or through their compliant contacts or redistribution layers.05-14-2009
20110175221CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages.07-21-2011
20110175220SEMICONDUCTOR DEVICE HAVING CONDUCTIVE PADS AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes at least two conductive pads, one of the conductive pads being formed above another of the at least two conductive pads, and a redistribution layer extending from at least one of the conductive pads. The semiconductor device also includes a bump structure formed over the conductive pads and electrically coupled to the conductive pads.07-21-2011
20110101522Multichip semiconductor device, chip therefor and method of formation thereof - A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.05-05-2011
20110101518Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress - An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device.05-05-2011
20110074028Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate - A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second die is less than or equal to a height of the bumps. A second substrate has a thermal conduction channel. A surface of the second semiconductor die opposite the first die is mounted to the thermal conductive channel of the second substrate. A thermal interface layer is formed over the surface of the second die. The bumps are electrically connected to contact pads on the second substrate. A conductive plane is formed over a surface of the second substrate.03-31-2011
20110074025SEMICONDUCTOR MODULE, METHOD OF MANUFACTURING SEMICONDUCTOR MODULE, AND MOBILE DEVICE - An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.03-31-2011
20110074017METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND MULTILAYER WAFER STRUCTURE - Grooves are formed on the front surfaces of first and second semiconductor wafers each including an aggregate of a plurality of semiconductor chips. The grooves each extend on a dicing line set between the semiconductor chips and to have a larger width than the dicing line. Thereafter the first and second semiconductor wafers are arranged so that the front surfaces thereof are opposed to each other, and the space between the first semiconductor wafer and the second semiconductor wafer is sealed with underfill. Thereafter the rear surfaces of the first and second semiconductor wafers are polished until at least the grooves are exposed, and a structure including the first and second semiconductor wafers and the underfill is cut on the dicing line.03-31-2011
20110074023Apparatus And Methods Of Forming An Interconnect Between A Workpiece And Substrate - Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.03-31-2011
20110101517MOLDED SEMICONDUCTOR PACKAGE HAVING A FILLER MATERIAL - An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.05-05-2011
20120199972Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps - A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump.08-09-2012
20110248399Semiconductor Device and Method of Forming High Routing Density Interconnect Sites on Substrate - A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.10-13-2011
20110101520Semiconductor Die Contact Structure and Method - A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.05-05-2011
20110101524Semiconductor Device with Bump Interconnection - A semiconductor device includes a semiconductor die having contact pads disposed over a surface of the semiconductor die, a die attach adhesive layer disposed under the semiconductor die, and an encapsulant material disposed around and over the semiconductor die. The semiconductor device further includes bumps disposed in the encapsulant material around a perimeter of the semiconductor die. The bumps are partially enclosed by the encapsulant material. The semiconductor device further comprises first vias disposed in the encapsulant. The first vias expose surfaces of the contact pads. The semiconductor device further includes a first redistribution layer (RDL) disposed over the encapsulant and in the first vias, and a second RDL disposed under the encapsulant material and the die attach adhesive layer. The first RDL electrically connects each contact pad of the semiconductor die to one of the bumps, and the second RDL is electrically connected to one of the bumps.05-05-2011
20110101519Robust Joint Structure for Flip-Chip Bonding - An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a copper bump at a main surface of the first work piece and having a first dimension; and a nickel-containing barrier layer over and adjoining the copper bump. The second work piece is bonded to the first work piece and includes a bond pad at a main surface of the second work piece; and a solder mask at the main surface of the second work piece and having a solder resist opening with a second dimension exposing a portion of the bond pad. A ratio of the first dimension to the second dimension is greater than about 1. Further, a solder region electrically connects the copper bump to the bond pad, with a vertical distance between the bond pad and the copper bump being greater than about 30 μm.05-05-2011
20110074016SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The size and thickness of a semiconductor device are reduced. A semiconductor package with a flip chip bonding structure includes: a semiconductor chip having a main surface with multiple electrode pads formed therein and a back surface located on the opposite side thereto; four lead terminals each having an upper surface with the semiconductor chip placed thereover and a lower surface located on the opposite side thereto; and a sealing body having a main surface and a back surface located on the opposite side thereto. In this semiconductor package, the distance between adjacent first lower surfaces of the four lead terminals exposed in the back surface of the sealing body is made longer than the distance between adjacent upper surfaces thereof. This makes it possible to suppress the production of a solder bridge when the semiconductor package is solder mounted to a mounting board and to reduce the size and thickness of the semiconductor package and further enhance the reliability of the semiconductor package.03-31-2011
20110074015STACKED SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME - An upper-side semiconductor chip is stacked on a lower-side semiconductor chip by connection through microbumps. In the lower-side semiconductor chip that forms a gap with the upper-side semiconductor chip to be filled with an underfill resin, and is sealed with a molding resin, a polyimide film is formed on the chip surface in a peripheral area excluding openings of bonding pads. A stacked semiconductor device and a method for manufacturing the stacked semiconductor device are provided that the device is capable of suppressing generation of a void in the underfill resin layer, prevents a decrease in measurement accuracy of the gap between the stacked semiconductor chips, and prevents peeling of the molding resin.03-31-2011
20110074021DEVICE MOUNTING BOARD, AND SEMICONDUCTOR MODULE - A device mounting board includes an insulating resin layer, a wiring layer provided on one of main surfaces of the insulating resin layer, and bump electrodes connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A semiconductor module is formed by having the bump electrodes connected to a semiconductor device. A recess is provided in the top face of each bump electrode. The recess communicates with an opening provided on a side surface of the bump electrode.03-31-2011
20110074027FLIP CHIP INTERCONNECTION WITH DOUBLE POST - A microelectronic assembly includes a substrate having a first surface, a plurality of first conductive pads exposed thereon, and a plurality of first metal posts. Each metal post defines a base having an outer periphery and is connected to one of the conductive pads. Each metal post extends along a side wall from the base to ends remote from the conductive pad. The assembly further includes a dielectric material layer having a plurality of openings and extending along the first surface of the substrate. The first metal posts project through the openings such that the dielectric material layer contacts at least the outside peripheries thereof. Fusible metal masses contact the ends of some of first metal posts and extend along side walls towards the outer surface of the dielectric material layer. A microelectronic element is carried on the substrate and is electronically can be connected the conductive pads.03-31-2011
20110074020SEMICONDUCTOR DEVICE AND METHOD FOR MOUNTING SEMICONDUCTOR DEVICE - A method for mounting a semiconductor device by mounting a semiconductor chip on a board by flip chip bonding, comprising: contacting an Au bump of the semiconductor chip with a Sn—Bi solder; and heating the Sn—Bi solder at a temperature which is not lower than the melting point thereof and which is not higher than 180° C. for 30 minutes or more.03-31-2011
20110074024Semiconductor Device and Method of Forming Bump-on-Lead Interconnection - A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.03-31-2011
20090026610SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention provides a semiconductor device having high reliability and a method of manufacturing the same. The semiconductor device of the invention has pad electrodes formed on a semiconductor die near the side surface portion thereof and connected to a semiconductor integrated circuit or the like in the semiconductor die, a supporting body formed on the pad electrodes, an insulation film formed on the side and back surface portions of the semiconductor die, wiring layers connected to the back surfaces of the pad electrodes and extending from the side surface portion onto the back surface portion of the semiconductor die so as to contact the insulation film, and a second protection film formed on the side surface portion of the supporting body.01-29-2009
20090026608Crosstalk-Free WLCSP Structure for High Frequency Application - A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.01-29-2009
20100295177ELECTRONIC COMPONENT MOUNTING STRUCTURE, ELECTRONIC COMPONENT MOUNTING METHOD, AND ELECTRONIC COMPONENT MOUNTING BOARD - In an electronic component mounting structure, a semiconductor element (an electronic component) provided with an electrode pad and a board provide with an electrode pad corresponding to the electrode pad are connected via a conductive material portion. On a surface of the board, there is formed solder resist having an opening regulating an area of the electrode pad. The conductive material portion is formed to protrude from a surface of the solder resist. An elastic coefficient of the conductive material portion is lower than that of the solder resist. A solder bump and the conductive material portion are connected via a metal layer. The conductive material portion is formed to have an area larger than that of the opening of the solder resist. An edge of the conductive material portion is adhered to a portion of the surface of the solder resist. Thus, in a case of mounting an electronic component on a board by flip-chip connection, a reliability of connection can be secured.11-25-2010
20110248400SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A manufacturing method of a semiconductor device includes: forming a columnar electrode on a semiconductor wafer; flip-chip bonding a second semiconductor chip onto the semiconductor wafer; forming a molding portion on the semiconductor wafer, the molding portion covering and molding the columnar electrode and the second semiconductor chip; grinding or polishing the molding portion and the second semiconductor chip so that an upper face of the columnar electrode and an upper face of the semiconductor chip are exposed; and cutting the molding portion and the semiconductor wafer so that a first semiconductor chip, where the second semiconductor chip is flip-chip bonded and the columnar electrode is formed, is formed.10-13-2011
20110248398WAFER-LEVEL CHIP-SCALE PACKAGE DEVICE HAVING BUMP ASSEMBLIES CONFIGURED TO MITIGATE FAILURES DUE TO STRESS - Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.10-13-2011
20110254158Mask Programmable Interface Selection - According to one exemplary embodiment, a semiconductor die with on-die preferred interface selection includes at least two groups of pads situated on an active surface of the semiconductor die, where each of the at least two groups of pads is coupled to its associated interface in the die. A set of bumps is mask-programmably routed to one of the at least two groups of pads, thereby selecting the preferred interface for the semiconductor die. A non-preferred interface is not routed to any bumps on the active surface of the semiconductor die, thereby reducing bump count on the die. Each of the at least two groups of pads can be situated in a corresponding pad ring on the active surface of said semiconductor die. The at least two groups of pads can be laid out substantially inline.10-20-2011
20100295175WAFER LEVEL CHIP SCALE PACKAGE - A semiconductor device of the invention includes a semiconductor substrate having a first insulating section formed on one surface thereof. A first conductive section is disposed on the one surface of the semiconductor substrate. A second insulating section is superimposed over the first insulating section and covers the first conductive section. A second conductive section is superimposed over the second insulating section. A third insulating section is disposed over the second insulating section and covers the second conductive section. These first conductive section, second insulating section, second conductive section, third insulating section, and terminal altogether constitute a structure. A third opening is formed between adjacent structures. The third opening is formed passing through the third and second insulating sections to expose the first insulating section.11-25-2010
20110147922STRUCTURES AND METHODS TO REDUCE MAXIMUM CURRENT DENSITY IN A SOLDER BALL - Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.06-23-2011
20080230897METHOD OF MANUFACTURING ELECTRONIC DEVICE, SUBSTRATE AND SEMICONDUCTOR DEVICE - A method includes a step of forming a bump 09-25-2008
20100059882SEMICONDUCTOR DEVICE - Signal lines which provide electric connections from an internal circuit formed on a main surface of a semiconductor chip and including, for example, MIS transistor to protective elements constituted by, for example, diodes are drawn out from outlet ports formed on wiring lines disposed between the protective elements, and a signal line region occupied by the signal lines is provided over the protective elements and under electrode pads. A wiring region on the main surface of the semiconductor chip can be enlarged without increasing the chip area.03-11-2010
20110163440SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a carrier and attaching a plurality of semiconductor chips to the carrier. The semiconductor chips have a first electrode pad on a first main face and at least a second electrode pad on a second main face opposite to the first main face, whereby the first electrode pad is electrically connected to the carrier. A plurality of first bumps are formed on the carrier, the first bumps being made of a conductive material. The carrier is then singulated into a plurality of semiconductor devices, wherein each semiconductor device includes at least one semiconductor chip and one first bump.07-07-2011
20080315409DIRECT EDGE CONNECTION FOR MULTI-CHIP INTEGRATED CIRCUITS - The present invention allows for direct chip-to-chip connections using the shortest possible signal path.12-25-2008
20090001572SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of the present invention includes a chip which has a pad; a bump electrode formed on the pad; and a wire whose stitch bonding is made on the bump electrode. The wire satisfies a condition: (modulus-of-elasticity/breaking strength per unit area)≧400.01-01-2009
20090001570ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a method of manufacturing an electronic device in which a plurality of first bumps serving as external connection terminals are formed on a conductive pattern. The method includes: (a) forming a second bump having a projection portion on an electrode pad formed on a substrate; (b) forming an insulating layer on the substrate; (c) exposing a portion of the projection portion from an upper surface of the insulating layer; (d) forming a flat stress absorbing layer in a bump providing area, in which the first bumps are provided, on the insulating layer; (e) forming a first conductive layer on the insulating layer and the stress absorbing layer and the exposed portion of the projection portion; (f) forming a second conductive layer by an electroplating using the first conductive layer as a power feeding layer; (g) forming the conductive pattern by patterning the second conductive layer; and (h) forming the first bumps on the conductive pattern formed on the stress absorbing layer.01-01-2009
20090001569SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor chip is characterized by a structure including a semiconductor chip on which electrode pads are formed, bumps which are formed on the respective electrode pads and which have projection sections, an insulating layer formed on the semiconductor chip, and a conductive pattern to be connected to the bumps, wherein extremities of the projection sections are inserted into the conductive pattern and the inserted extremities are flattened.01-01-2009
20110147927SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor chip having an element formation surface on which at least one element is formed and including a plurality of electrode pads formed on the element formation surface, an interconnect substrate having a principal surface facing the element formation surface of the semiconductor chip and including a plurality of connection pads formed at positions of the principal surface facing the respective corresponding electrode pads, and a plurality of solder bumps provided between the respective corresponding electrode pads and connection pads, and configured to electrically connect the respective corresponding electrode pads and connection pads together. An UBM layer is formed on a portion of each solder bump closer to the corresponding electrode pad and a barrier metal layer is formed on a portion of each solder bump closer to the corresponding connection pad, and the two layers have substantially the same composition of major materials.06-23-2011
20110147925PRE-SOLDERED LEADLESS PACKAGE - The invention relates to a method of manufacturing a semiconductor device, the method comprising: i) providing a substrate carrier comprising a substrate layer and a patterned conductive layer, wherein the patterned conductive layer defines contact pads; ii) partially etching the substrate carrier using the patterned conductive layer as a mask defining contact regions in the substrate layer; iii) providing the semiconductor chip; iv) mounting said semiconductor chip with the adhesive layer on the patterned conductive layer such that the semiconductor chip covers at least one of the trenches and part of the contact pads neighboring the respective trench are left uncovered for future wire bonding; v) providing wire bonds between respective terminals of the semiconductor chip and respective contact pads of the substrate carrier; vi) providing a molding compound covering the substrate carrier and the semiconductor chip, and vii) etching the backside (S06-23-2011
20120199968SEMICONDUCTOR PACKAGE - A semiconductor package and method of manufacturing thereof are provided. The package includes: a substrate; a first metal wire on a top surface of the substrate; a first semiconductor chip disposed on the substrate; a first insulation layer which covers the first semiconductor chip and at least a part of the substrate; a second metal wire formed on a top surface of the first insulation layer; a first via formed in the first insulation layer, wherein the first via electrically connects the second metal wire and the first metal wire; and a second semiconductor chip disposed on the second metal wire, wherein the second semiconductor chip is electrically connected to the second metal wire.08-09-2012
20100140798SEMICONDUCTOR CHIP BUMP CONNECTION APPARATUS AND METHOD - Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.06-10-2010
20100244245Filp Chip Interconnection Structure with Bump on Partial Pad and Method Thereof - A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.09-30-2010
20100244244Chip Having a Bump and Package Having the Same - The present invention relates to a chip having a bump and a package having the same. The chip includes a chip body, at least one via, a passivation layer, an under ball metal layer and at least one bump. The via penetrates the chip body, and is exposed to a surface of the chip body. The passivation layer is disposed on the surface of the chip body, and the passivation layer has at least one opening. The opening exposes the via. The under ball metal layer is disposed in the opening of the passivation layer, and is connected to the via. The bump is disposed on the under ball metal layer, and includes a first metal layer, a second metal layer and a third metal layer. The first metal layer is disposed on the under ball metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. As the bumps can connect two chips, the chip is stackable, and so the density of the product is increased while the size of the product is reduced.09-30-2010
20100244243SEMICONDUCTOR DEVICE - A semiconductor device has a flexible substrate which can be folded U-shape, and an outer surface of the flexible substrate being provided concave-convex portions for heat radiation. The semiconductor device also has a semiconductor chip which is mounted on an inner surface of the flexible substrate, and the chip being electronically connected with the flexible substrate.09-30-2010
20100244242SEMICONDUCTOR DEVICE - A semiconductor device including a first substrate having first and second surfaces, multiple first mounting pads formed on the first surface of the first substrate and for mounting a first semiconductor element on the first surface of the first substrate, multiple first connection pads formed on the first surface of the first substrate and positioned on the periphery of the multiple first mounting pads, a second substrate formed on the first substrate and having first and second surfaces, the second substrate having a second penetrating electrode which penetrates through the first and second surfaces of the second substrate, multiple second mounting pads formed on the first surface of the second substrate and for mounting a second semiconductor element, and a conductive member formed on one of the first connection pads and electrically connecting an end portion of the second penetrating electrode and the one of the first connection pads.09-30-2010
20100244241Semiconductor Device and Method of Forming a Thin Wafer Without a Carrier - A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.09-30-2010
20100244240STACKABLE ELECTRONIC PACKAGE AND METHOD OF MAKING SAME - An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to the first side of the first flex layer and a first encapsulant encapsulating the first component, the first encapsulant having a portion thereof removed to form a first plurality of cavities in the first encapsulant and to expose the first plurality of feed-thru pads by way of the first plurality of cavities.09-30-2010
20100244239Semiconductor Device and Method of Forming Enhanced UBM Structure for Improving Solder Joint Reliability - A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the first conductive layer. A second conductive layer is formed over first insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. An under bump metallization layer (UBM) is formed over the third insulating layer and second conductive layer. A UBM build-up structure is formed over the UBM. The UBM build-up structure has a sloped sidewall and is confined within a footprint of the UBM. The UBM build-up structure extends above the UBM to a height of 2-20 micrometers. The UBM build-up structure is formed in sections occupying less than an area of the UBM. A solder bump is formed over the UBM and UBM build-up structure. The sections of the UBM build-up structure provide exits for flux vapor escape.09-30-2010
20090115056DEVICE MOUNTING BOARD, SEMICONDUCTOR MODULE, AND MOBILE DEVICE - A device mounting board includes an insulating layer formed of an insulating resin, a glass cloth covering the surface of the insulating layer, and an electrode provided in a through hole extending through the glass cloth. The angle of contact with solder of the glass cloth is larger than that of the resin. Thus, solder bumps are formed on the electrode of the device mounting board 05-07-2009
20110254157Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant - A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.10-20-2011
20110254153DIE STRUCTURE AND DIE CONNECTING METHOD - A die structure and a die connecting method using the same are provided. The die structure includes a die and a bump structure. The bump structure includes a body and a solder layer. The body is disposed on the die. The solder layer is disposed on the body. The method includes providing a die structure mentioned above, providing a circuit board mentioned above, and soldering the solder layer of the die structure with the tine layer on the copper block of the circuit board. In different embodiments, a tin layer is omitted from the circuit board, wherein the solder layer of the die structure is directly soldered onto the surface of the copper block.10-20-2011
20110254151METHOD FOR FABRICATING BUMP STRUCTURE WITHOUT UBM UNDERCUT - A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile.10-20-2011
20080246145MOBILE BINDING IN AN ELECTRONIC CONNECTION - A method of creating an electrical contact involves locating a barrier material at a location for an electrical connection, providing an electrically conductive bonding metal on the barrier material, the electrically conductive bonding metal having a diffusive mobile component, the volume of barrier material and volume of diffusive mobile component being selected such that the barrier material volume is at least 20% of the volume of the combination of the barrier material volume and diffusive mobile component volume. An electrical connection has an electrically conductive bonding metal between two contacts, a barrier material to at least one side of the electrically conductive bonding metal, and an alloy, located at an interface between the barrier material and the electrically conductive bonding metal. The alloy includes at least some of the barrier material, at least some of the bonding metal, and a mobile material.10-09-2008
20120199971Embedded Semiconductor Die Package and Method of Making the Same Using Metal Frame Carrier - An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.08-09-2012
20120199970SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.08-09-2012
20120199966Elongated Bump Structure for Semiconductor Devices - An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump.08-09-2012
20120199969SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor chip mounted on a circuit board. The semiconductor chip includes: a semiconductor substrate; a first pad formed on the semiconductor substrate; a second pad formed on the first pad via an interlayer insulating film; a via formed through the interlayer insulating film for connecting the first pad with the second pad; a protection film that is formed on the second pad and has an opening exposing a center portion of the second pad; and a barrier metal layer formed on the portion of the second pad exposed from the opening of the protection film and on a portion of the protection film surrounding the opening. The diameter of the via is smaller than the diameter of the opening of the protection film, and the center of the via corresponds with the center of the barrier metal layer.08-09-2012
20120199967Interconnection Structure - An electrical interconnect for connecting an IC chip to a PCB, the electrical interconnect comprising a plurality of connection elements for connection to the PCB attached to a first surface of the electrical interconnect, wherein the amount of thermal and/or mechanical stress that each solder element connection can take before failing is improved.08-09-2012
20080251915Structure of semiconductor chip and package structure having semiconductor chip embedded therein - A semiconductor chip is disclosed, which comprises a chip having an active surface; plural electrode pads disposed on the active surface of the chip; a first passivation layer disposed on the chip, which has openings corresponding to the electrode pads to expose the electrode pads, wherein the first passivation layer is made of a material having high alkali resistance and low coefficient of elasticity; and plural metal bumps disposed in the openings of the first passivation layer. Therefore, as forming the metal bumps by a chemical deposition technique, the damage to the passivation layer can be prevented. Besides, as the semiconductor chip is embedded in a package structure, the problem of delamination occurred due to the mismatch in the coefficients of thermal expansion of the semiconductor chip and the dielectric layers can be avoided. Accordingly, the yield of the package structure having the semiconductor chip embedded therein can be improved.10-16-2008
20080251913SEMICONDUCTOR DEVICE INCLUDING WIRING SUBSTRATE HAVING ELEMENT MOUNTING SURFACE COATED BY RESIN LAYER - In one embodiment of the present invention, there is provided a semiconductor device including a first semiconductor element mounted, through flip-chip bonding, on the element mounting surface of a first wiring substrate, and a resin layer that coats substantially the entire element mounting surface of the first wiring substrate. The first semiconductor element has two opposite surfaces. One surface faces the element mounting surface of the first wiring substrate, and the other surface is not coated by the resin layer.10-16-2008
20120032321Electrical Contact Alignment Posts - An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.02-09-2012
20080203565SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device 08-28-2008
20080203564Semiconductor device having stress alleviating portion positioned at outer circumference of chip, wiring substrate, and method for producing the same - A semiconductor device has a wiring substrate, a semiconductor chip, a conductive bump, and an under-fill resin. The wiring substrate has a solder resist layer, and a stress alleviating portion. The stress alleviating portion is mounted on the solder resist layer opposed to the outer circumference of the semiconductor chip. The material of the stress alleviating portion is different from that of the solder resist layer. The stress alleviating portion alleviates the stress acting on the solder resist layer and the under-fill resin. The semiconductor chip is mounted above the wiring substrate via the conductive bump. The gap between the wiring substrate and the semiconductor chip is filled with the under-fill resin.08-28-2008
20080203563SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A COF package in exemplary form includes a flexible base film, inner leads each made of metal and having a thickness d08-28-2008
20110163441PB-FREE SOLDER BUMPS WITH IMPROVED MECHANICAL PROPERTIES - A method of forming a semiconductor device is disclosed. A semiconductor substrate is provided that has a first contact and an undoped electroplated lead-free solder bump (07-07-2011
20110163442METHOD OF MANUFACTURING A PLURALITY OF ICS AND TRANSPONDERS - A method of manufacturing a plurality of ICs for different transponder types adapted for different operating range is provided, wherein the method comprises manufacturing a first IC having a first capacitance corresponding to a first operating range of the first transponder and manufacturing a second IC having a second capacitance corresponding to a second operating range of the second transponder, wherein a common layout is used for manufacturing the first IC and the second IC.07-07-2011
20110260321Flip Chip Interconnection Structure - A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock10-27-2011
20100320598SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a stacked chip structure provided on a board and made up of semiconductor chips that are stacked via insulators. Each semiconductor chip has an integrated circuit surface, pads provided on the integrated circuit surface, and conductive connecting members having a wave shape with first ends electrically connected to the pads, and second ends extending outwardly from the at least one edge part and electrically connected to the connection terminals on the board.12-23-2010
20100320600SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die.12-23-2010
20100320597Wafer level stack structure for system-in-package and method thereof - A system-in-package, comprising a wafer level stack structure, including at least one first device chip including a first device region having a plurality of input/output(I/O) pads, and at least one second device chip including a second device region having a plurality of input/output(I/O) pads and a second peripheral region surrounding the second device region, wherein the size of the second device region is different from the size of the first device region, wherein the at least one first device chip and the at least one second device chip have approximately equal size; and a common circuit board to which the wafer level stack structure is connected.12-23-2010
20100320596METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME - Provided is a method for fabricating semiconductor package and a semiconductor package fabricated using the same. The method for fabricating semiconductor package dopes a mixture including the polymer material and the solder particle on the substrate in which the terminal is formed and applies heat, and thus the solder particle flows (or diffuses) toward the terminal in the heated polymer resin to adhere to the exposed surface of the terminal, i.e., the side surface and upper surface of the terminal, thereby forming the solder layer. The solder layer improves the adhesive strength between the terminal of the semiconductor chip and the terminal of the substrate in the subsequent flip chip bonding process.12-23-2010
20110254154ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.10-20-2011
20110254155Wafer Level Die Integration and Method Therefor - A method of manufacturing a semiconductor device includes providing a wafer for supporting the semiconductor device. An insulation layer is disposed over a top surface of the wafer. The method includes forming a first interconnect structure over the top surface of the wafer with temperatures in excess of 200° C., forming a metal pillar over the wafer in electrical contact with the first interconnect structure, connecting a semiconductor component to the first interconnect structure, and forming encapsulant over the semiconductor component. The encapsulant is etched to expose a portion of the metal pillar. A buffer layer is optionally formed over the encapsulant. The method includes forming a second interconnect structure over the encapsulant in electrical contact with the metal pillar with temperatures below 200° C., and removing a portion of a backside of the wafer opposite the top surface of the wafer.10-20-2011
20110024902STRUCTURE AND MANUFACTURING METHOD OF A CHIP SCALE PACKAGE WITH LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP - A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.02-03-2011
20100283145Stack structure with copper bumps - A stack structure with copper bumps on an integrated circuit board is disclosed. The stack structure includes a plurality of insulating layers and a plurality of conductive layers which are stacked alternately. The uppermost conductive layer has copper bumps as copper pillar pins for soldering the chip pins of an integrated circuit chip. Because the copper bumps have a certain height, the distance between the copper bumps and the chip pins is shortened, and therefore the solders needed for soldering may be reduced. Also, the shape of the solders is a long strap instead of spheroid due to the cohesion force between the copper bump surfaces and the solders so that the distance between the solders is scaled down and the gaps between the pins are reduced. Thus, the entire size of the integrated circuit board may also be miniatured.11-11-2010
20100283144IN-SITU CAVITY CIRCUIT PACKAGE - A flip chip semiconductor packaging device and method that incorporates in situ formation of cavities underneath selected portions of a die during a flip chip die bonding process. A method of flip chip semiconductor component packaging includes providing a die having a first surface, forming a barrier on first surface of the die, the barrier at least partially surrounding a designated location on the first surface of the die, bonding the die to a substrate in a flip chip configuration, and flowing molding compound over the die and over at least a portion of the substrate. Bonding the die to the substrate includes causing contact between the barrier and the substrate such that flow of the molding compound is blocked by the barrier to provide a cavity between the die and the substrate, the cavity being proximate the designated location on the first surface of the die.11-11-2010
20100283150Semiconductor device - The present invention provides a method for forming a semiconductor device, which comprises the steps of preparing a semiconductor wafer including an electrode pad, an insulating film formed with a through hole and a bedding metal layer which are formed in a semiconductor substrate, forming a first resist mask which exposes each area for forming a redistribution wiring, over the bedding metal layer, forming a redistribution wiring connected to the electrode pad and extending in an electrode forming area for a post electrode with the first resist mask as a mask, removing the first resist mask by a dissolving solution to expose each area excluding the electrode forming area for the redistribution wiring and forming a second resist mask disposed with being separated from each side surface of the redistribution wiring, forming a redistribution wiring protective metal film over upper and side surfaces of the exposed redistribution wiring with the second resist mask as a mask, removing the second resist mask by a dissolving solution, attaching a dry film over the semiconductor wafer and exposing the electrode forming area lying over the redistribution wiring, forming a post electrode in the electrode forming area with the dry film as a mask, removing the dry film by a removal solvent, and removing the redistribution wiring protective metal film after the removal of the dry film.11-11-2010
20100283147 METHOD FOR PRODUCING A PLURALITY OF CHIPS AND A CHIP PRODUCED ACCORDINGLY - A production method for chips, in which as many method steps as possible are carried out in the wafer composite, that is, in parallel for a plurality of chips disposed on a wafer. This is a method for producing a plurality of chips whose functionality is implemented on the basis of the surface layer of a substrate. In this method, the surface layer is patterned and at least one cavity is produced below the surface layer, so that the individual chip regions are connected to each other and/or to the rest of the substrate by suspension webs only, and/or so that the individual chip regions are connected to the substrate layer below the cavity via supporting elements in the region of the cavity. The suspension webs and/or supporting elements are cut when the chips are separated. The patterned and undercut surface layer of the substrate is embedded in a plastic mass before the chips are separated.11-11-2010
20110133336Semiconductor Wafer and Method of Manufacturing the Same and Method of Manufacturing Semiconductor Device - A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.06-09-2011
20110133333MICROELECTRONIC DEVICES INCLUDING CONDUCTIVE VIAS, CONDUCTIVE CAPS AND VARIABLE THICKNESS INSULATING LAYERS, AND METHODS OF FABRICATING SAME - Microelectronic devices include a conductive via that extends into a substrate face and that also protrudes beyond the substrate face to define a conductive via end surface and a conductive via sidewall that extends from the end surface towards the substrate face. A conductive cap is provided on the end surface, the conductive cap including a conductive cap body that extends across the end surface and a flange that extends from the conductive cap body along the conductive via sidewall towards the substrate face. Related fabrication methods are also described.06-09-2011
20110133331INTERFACE STRUCTURE FOR COPPER-COPPER PEELING INTEGRITY - An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.06-09-2011
20110074026Semiconductor Device and Method of Forming Insulating Layer on Conductive Traces for Electrical Isolation in Fine Pitch Bonding - A semiconductor device has a semiconductor die with a plurality of bumps formed over an active surface of the semiconductor die. A plurality of first conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A surface treatment is formed over the first conductive traces. A plurality of second conductive traces is formed adjacent to the first conductive traces. An oxide layer is formed over the second conductive traces. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. The oxide layer maintains electrical isolation between the bump and second conductive trace. An encapsulant is deposited around the bumps between the semiconductor die and substrate.03-31-2011
20110186995SOLDER BUMP INTERCONNECT - A semiconductor package includes a device pad on a substrate. A polybenzoxazole (PBO) layer overlies the substrate, and the PBO layer has an opening to expose the device pad. A redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the PBO layer and conductively coupled to the device pad. A polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the polymer layer. The UBM electrically connects to the landing pad through an opening in the polymer layer. A solder bump is secured to the UBM. A shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.08-04-2011
20110186992RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.08-04-2011
20110186991Package substrate and method of fabricating the same - There is provided a package substrate capable of controlling the degree of warpage thereof by improving the composition and formation of a post terminal and a method of fabricating the same. The package substrate includes a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a separation barrier layer provided on the conductive pad inside the opening and formed to be higher than the upper surface of the insulating layer along the side walls thereof; a post terminal provided on the separation barrier layer; and a solder bump provided on the post terminal.08-04-2011
20110186988Multi-Direction Design for Bump Pad Structures - An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction.08-04-2011
20090212423STACKED SOLDER BALLS FOR INTEGRATED CIRCUIT DEVICE PACKAGING AND ASSEMBLY - A semiconductor device is provided that includes a semiconductor chip, a plurality of solder bumps that electrically couple the semiconductor chip to the outside, and a metal bump being provided on the surface of each first solder bump which is at least a part of the plurality of solder bumps and being made of a metal having a melting point higher than that of the first solder bump. The wettability of the first solder bump is improved as each metal bump serves as a core when the corresponding first solder bump melts. Thus, the connection reliability of the first solder bump can be improved.08-27-2009
20090212422JOINT RELIABILITY OF SOLDER JOINT BETWEEN Sn-yAg SOLDER AND Ni-P UNDER BUMP METALLIC LAYER BY COBALT ADDITION - An improvement of joint reliability between Sn-yAg (0≦y≦4.0) solder and Ni—P under-bump metallic layers is achieved by cobalt (Co) addition. A solder joint with improved joint reliability is formed between a solder part of an electronic packaging and an under-bump metallic (UBM) layer, which has a specific structure comprising Sn-yAg-xCo (0.02≦x≦0.1, 0≦y≦4.0) alloy solder containing cobalt (Co) ingredient bonded to a Ni—P UBM. Also, a solder joint with a joint structure comprising Sn-yAg-xCo (0.02≦x≦0.1, 0≦y≦4.0) alloy solder with addition of Co ingredient and Ni—P UBM is formed, which is inserted between a PCB substrate and a silicon chip to join the same.08-27-2009
20110254156Semiconductor Device and Method of Wafer Level Package Integration - A method of making a wafer level chip scale package includes providing a temporary substrate, and forming a wafer level interconnect structure over the temporary substrate using wafer level processes. The wafer level processes include forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer. A first semiconductor die is mounted over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer, and a first encapsulant is deposited over the first semiconductor die. A second encapsulant is deposited over the first encapsulant, and the first and second encapsulants are cured simultaneously. The temporary substrate is removed to expose the first passivation layer.10-20-2011
20100148362SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an electronic part including an electrode, a substrate including a substrate electrode electrically connected to the first electrode on an upper surface thereof, the first substrate electrode and the first electrode being arranged, facing each other, a connecting member configured to connect the electrode with the substrate electrode, and a sealing material including a first resin portion which contains flux and contacts at least a connection portion between the connecting member and the substrate electrode, and a second resin portion which contains a lower concentration of flux than that of the first resin portion. A gap between the electronic part and the substrate is filled with the sealing film.06-17-2010
20100148361SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same, including: a substrate having a mounting surface formed with a plurality of bonding fingers and covered with an insulating layer, the insulating layer having an opening formed therein for exposing the bonding fingers; and a chip coupled to the substrate and including a body, a self-adhesive protective layer, and a plurality of bumps protruding from the self-adhesive protective layer. The self-adhesive protective layer is formed on the chip but leaves the bumps exposed. The self-adhesive protective layer is made of a photosensitive adhesive, thermosetting adhesive, or dielectric material. The chip is coupled to the substrate via the self-adhesive protective layer, thus allowing the bumps to be electrically connected to the bonding fingers and at least an end of the opening to be exposed. The method enables a more streamlined manufacturing process and lower fabrication costs by dispensing with adhesive dispensing.06-17-2010
20100148360Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.06-17-2010
20110169161SEMICONDUCTOR DEVICE - A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric and covering the active region when viewed from a top side; and a forbidden region provided in the semiconductor layer in a specific range positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad. A connection section at which the first conductive layer and the second conductive layer are connected is not provided in the forbidden region.07-14-2011
20100117227METHOD OF PREPARING DETECTORS FOR OXIDE BONDING TO READOUT INTEGRATED CHIPS - In one embodiment, a method of preparing detectors for oxide bonding to an integrated chip, e.g., a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon. A floating oxide layer is formed surrounding each of the bumps at a top portion thereof. An oxide-to-oxide bond is formed between the floating oxide layer and an oxide layer of the integrated chip which is provided in between corresponding bumps of the integrated chip. The oxide-to-oxide bond enables the bumps on the detector elements and the bumps on the integrated chip to be intimately contacted with each other, and removes essentially all mechanical stresses on and between the bumps. In another embodiment, a device has an interconnect interface that includes the oxide-to-oxide bond and an electrical connection between the bumps on the detector elements and the bumps on the integrated chip.05-13-2010
20100117226STRUCTURE AND METHOD FOR STACKED WAFER FABRICATION - A method for fabricating stacked wafers is provided. In one embodiment, the method comprises providing a wafer having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies is provided, each of the die bonded to one of the plurality of semiconductor chips. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material. The non-chip side of the wafer is thinned to an intended thickness. The wafer is then diced to separate the wafer into individual semiconductor packages.05-13-2010
20110068467Semiconductor device and method of manufacturing same - A semiconductor device includes the semiconductor chip connected in a flip-chip style to the substrate, and the underfill resin formed between the substrate and the semiconductor chip and including a filet, wherein the underfill resin includes a first resin layer and a second resin layer superposed on each other in at least a part of a region overlapping with the semiconductor chip in a plan view, and at least one of the first and the second resin layer is formed over an area including the region overlapping with said semiconductor chip in a plan view and the filet.03-24-2011
20110068466Wafer Backside Interconnect Structure Connected to TSVs - An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.03-24-2011
20110068465STRONG INTERCONNECTION POST GEOMETRY - A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint structure comprises an interconnect post between the first substrate and the second substrate and a joint solder between the interconnect post and the second substrate, wherein the interconnect post exhibits a width and a first height. A pitch defines a distance between each joint structure. The first height is less than half the pitch.03-24-2011
20110079894Template Process for Small Pitch Flip-Flop Interconnect Hybridization - A process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.04-07-2011
20110079900MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES - Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.04-07-2011
20110079899EMBEDDED INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an embedded integrated circuit package system includes: forming a first conductive pattern on a first structure; connecting a first integrated circuit die, having bumps on a first active side, directly on the first conductive pattern by the bumps; forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern; forming a channel in the substrate forming encapsulation; and applying a conductive material in the channel.04-07-2011
20110095418SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a semiconductor chip having a first bump group and a second bump group, and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the first bump group is disposed on the first pattern and the second bump group is disposed on the second pattern.04-28-2011
20110095420Semiconductor device and method of manufacturing semiconductor device - A semiconductor device includes a protective insulating film, an opening formed in the protective insulating film, an electrode pad located within the opening, a bump formed on the protective insulating film, and an interconnect. The bump includes a bump core and a conductive film. The bump core includes an insulating resin layer and a conductive resin layer located on the insulating resin layer. The conductive film is formed on at least the upper surface of the bump core. The interconnect connects the conductive film of the bump and the electrode pad.04-28-2011
20110095423SEMICONDUCTOR DEVICE MOUNTED STRUCTURE AND ITS MANUFACTURING METHOD - A semiconductor device mounted structure includes a semiconductor device having a plurality first electrodes, a circuit board having a plurality of second electrodes, a plurality of bumps respectively formed on the plurality of first electrodes, a plurality of bonding members respectively positioned between the bumps and the second electrodes to electrically connect the first electrodes to the second electrodes via the bumps, and a plurality of reinforcing resin members respectively positioned around the bonding members so as to cover at least the bonding members and bonding regions between the bonding members and the bumps. Adjacent reinforcing resin members are spaced away from each other so as not to have contact with each other without being in contact with the semiconductor device. This semiconductor device mounted structure enhances the reliability of joints in impact resistance and makes it easy to repair it.04-28-2011
20110095422ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE, METHODS OF MANUFACTURING THE SAME, CIRCUIT BOARD, AND ELECTRONIC INSTRUMENT - An electronic component including an electronic element, an electrode that is formed on a first surface of the electronic element, a first resin layer that is formed over the first surface of the electronic element, a wiring that is electrically connected to the electrode, a first portion of the wiring extending over the first resin layer, a second resin layer that is formed over the first resin layer and the wiring, the second resin layer having an opening, the opening overlapping the first portion of the wiring, an external terminal that is provided above the second resin layer, the external terminal being connected to the first portion of the wiring via the opening, and a third resin layer that is formed over the second resin layer, the third resin layer being provided around the external terminal.04-28-2011
20110095421Flip chip package and method of manufacturing the same - There is provided a flip chip package including an electronic device, a board including a conductive pad disposed inside a mounting region of the board on which the electronic device is mounted, and a connection pad disposed outside the mounting region, a resin layer formed on the board and including a trench formed by removing a part of the resin layer, and a dam member provided on the trench and preventing the leakage of an underfill between the mounting region and the connection pad. Since the dam member, formed on the processed resin layer, can prevent the leakage of the underfill, a package defect rate can be lowered, and connection reliability can be improved.04-28-2011
20110095417LEADLESS SEMICONDUCTOR DEVICE TERMINAL - This document discusses, among other things, a semiconductor die having a first conductive bump coupled to a first electrical terminal at a first die surface of a semiconductor die and a dielectric substantially covering the first die surface and substantially surrounding the first conductive bump. A surface of the dielectric can include a recessed terminal area, and a second electrical terminal can be coupled to the first conductive bump in the recessed terminal area.04-28-2011
20110095419CONDUCTIVE FILM, METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a conductive film. The conductive film includes: an anodized layer having a plurality of through holes extending therethrough in its thickness direction; a plurality of linear conductors each formed in a corresponding one of the through holes and each having first and second protrusions protruding from the anodized layer, wherein at least one of the first and second protrusions is covered by a coating material; and an uncured thermosetting resin layer formed on the anodized layer to cover at least one of the first and second protrusions.04-28-2011
20100059881SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the semiconductor package are disclosed. The semiconductor package in accordance with an embodiment of the present invention includes: a substrate, in which a conductive pattern formed on one surface of the substrate; an insulation layer, which is formed on one surface of the substrate, in which a through-hole is formed in the insulation layer such that the conductive pattern is exposed; a metal post, which is formed in the through-hole such that one end of the metal post is in contact with the conductive pattern and the other end of the metal post is protruded from the insulation layer; and a solder bump, which is formed on the other end of the metal post.03-11-2010
20110260318Integrated circuits with multiple I/O regions - Methods and/or associated devices and/or systems for creating integrated circuits (IC's) that have multiple connected I/O regions that can be designed and implemented using commonly available standard I/O libraries in conjunction with standard IC design flows and tools and in combination with one or more novel standardized I/O region interconnect cells for interconnecting between or through otherwise separated I/O regions. Specific embodiments support a wide variety of IC's that can be developed using standard libraries and design flows including: application specific integrated circuits (ASIC's), programmable logic devices (PLDs), custom IC's, analog IC's, CPU's, GPU's, and other IC's that require large numbers of input/ouput (IO) circuits while having relatively small core circuitry areas. Specific embodiments may involve innovative I/O cell functions, innovative IC topologies, and innovative IC packaging solutions for single die packages and multiple die packages.10-27-2011
20110260320METHOD OF MAKING A CONNECTION COMPONENT WITH POSTS AND PADS - A packaged microelectronic element includes connection component incorporating a dielectric layer (10-27-2011
20110260319THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS - Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.10-27-2011
20110260317CU PILLAR BUMP WITH ELECTROLYTIC METAL SIDEWALL PROTECTION - A copper pillar bump has a sidewall protection layer formed of an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, and electrolytic copper layer, or an electrolytic silver layer.10-27-2011
20110260316Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process - A semiconductor device has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.10-27-2011
20080217772Semiconductor device manufacturing method and semiconductor device - The present invention provides a method for forming a semiconductor device, which comprises the steps of preparing a semiconductor wafer including an electrode pad, an insulating film formed with a through hole and a bedding metal layer which are formed in a semiconductor substrate, forming a first resist mask which exposes each area for forming a redistribution wiring, over the bedding metal layer, forming a redistribution wiring connected to the electrode pad and extending in an electrode forming area for a post electrode with the first resist mask as a mask, removing the first resist mask by a dissolving solution to expose each area excluding the electrode forming area for the redistribution wiring and forming a second resist mask disposed with being separated from each side surface of the redistribution wiring, forming a redistribution wiring protective metal film over upper and side surfaces of the exposed redistribution wiring with the second resist mask as a mask, removing the second resist mask by a dissolving solution, attaching a dry film over the semiconductor wafer and exposing the electrode forming area lying over the redistribution wiring, forming a post electrode in the electrode forming area with the dry film as a mask, removing the dry film by a removal solvent, and removing the redistribution wiring protective metal film after the removal of the dry film.09-11-2008
20080217771Metallic electrode forming method and semiconductor device having metallic electrode - A metallic electrode forming method includes: forming a bed electrode on a substrate; forming a protective film with an opening on the bed electrode to expose the bed electrode from the opening; forming a metallic film covering the protective film and the opening; mounting the substrate on an adsorption stage, and measuring a surface shape of the metallic film by a surface shape measuring means; deforming the substrate by a deforming means so that a difference between the principal surface and a cutting surface is within a predetermined range; measuring a surface shape of the principal surface, and determining whether the difference is within a predetermined range; and cutting the substrate along with the cutting surface so that the metallic film is patterned to be a metallic electrode.09-11-2008
20080217769SEMICONDUCTOR MODULE, METHOD OF MANUFACTURING SEMICONDUCTOR MODULE, AND MOBILE DEVICE - An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area.09-11-2008
20080217768System and method for increased stand-off height in stud bumping process - System and method for creating single stud bumps having an increased stand-off height. A preferred embodiment comprises a capillary for use in creating stud bumps in a flip chip assembly, comprising a hole section adapted to pass a wire, a chamfer section providing a transition from the hole section to a stud bump section, and a sidewall within the stud bump section, the sidewall having a sidewall height, wherein the side wall height is equal to, or greater than, the a diameter of the stud bump section.09-11-2008
20080217767Stacked-Chip Semiconductor Device - A chip stacking semiconductor device which can be used without mounting a converter circuit and without altering the circuitry of the semiconductor chips even when semiconductor chips stacked in a plurality of stages are connected electrically. Through wiring (09-11-2008
20110186986T-Shaped Post for Semiconductor Devices - A T-shaped post for semiconductor devices is provided. The T-shaped post has an under-bump metallization (UBM) section and a pillar section extending from the UBM section. The UBM section and the pillar section may be formed of a same material or different materials. In an embodiment, a substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like, having T-shaped posts is attached to a contact of another substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like. The T-shaped posts may have a solder material pre-formed on the pillar section such that the pillar section is exposed or such that the pillar section is covered by the solder material. In another embodiment, the T-shaped posts may be formed on one substrate and the solder material formed on the other substrate.08-04-2011
20110133332Package substrate and method of fabricating the same - There is provided a package substrate allowing for enhanced reliability by improving the structure of a solder bump and a method of fabricating the same. The package substrate includes: a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a post terminal provided on the conductive pad inside the opening; and a solder bump provided on the post terminal and having an angle between a bottom surface and a side surface thereof ranging from 80° to 120°.06-09-2011
20110186989Semiconductor Device and Bump Formation Process - A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.08-04-2011
20110147926Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier - A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.06-23-2011
20110186987STRESS BUFFER STRUCTURES IN A MOUNTING STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - A mounting structure for a semiconductor device includes a stepwise stress buffer layer under a likewise stepwise UBM structure.08-04-2011
20110186996MULTI-CHIP SEMICONDUCTOR DEVICE - An interposer has an opening in the central portion. A plurality of first electrode terminals are formed on the front surface near the opening of the interposer, a plurality of second electrode terminals are formed on the front surface of the peripheral portion thereof and corresponding ones of the plurality of first and second electrode terminals are electrically connected to one another via a plurality of wirings. A plurality of bump electrodes is formed on the front surface of a child chip. A plurality of bump electrodes containing a plurality of bump electrodes for connection with the exterior are formed on the front surface of a parent chip. The front surfaces of the parent chip and child chip are set to face each other with the interposer disposed therebetween and the bump electrodes are electrically connected to one another in the opening of the interposer.08-04-2011
20110215469METHOD FOR FORMING A DOUBLE EMBOSSING STRUCTURE - A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposing said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; removing said first pattern-defining layer; forming a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposing said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first metal layer not under said second metal layer; and forming a polymer layer over said second metal layer, wherein said third metal layer is used as a metal bump bonded to an external circuitry.09-08-2011
20110215468Bump-on-Lead Flip Chip Interconnection - A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.09-08-2011
20110215466FLIP CHIP PACKAGE MAINTAINING ALIGNMENT DURING SOLDERING - Disclosed is a flip chip package maintaining alignment during soldering, primarily comprising a chip and a substrate. A plurality of bumps and at least an extruded alignment key are disposed on the active surface of the chip. The substrate has a plurality of bonding pads and at least an alignment base where the alignment base has a concaved alignment pattern corresponding to the extruded alignment key. When the chip is disposed on the substrate, the extruded alignment key is embedded into the concaved alignment pattern to achieve accurately align the bumps to the corresponding bonding pads. Therefore, even with the mechanical misalignment due to the accuracy of flip-chip die bonders and the transportation during reflow processes, the bumps of a chip still can accurately align to the bonding pads of the substrate to achieve accurate soldering which is especially beneficial to the mass production of MPS-C2 products.09-08-2011
20110215464Semiconductor package with embedded die and its methods of fabrication - Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.09-08-2011
20100025847SEMICONDUCTOR DEVICE MOUNTED STRUCTURE AND SEMICONDUCTOR DEVICE MOUNTED METHOD - A recess portion is formed on a board surface at a position facing a peripheral end portion of a semiconductor device so as to place a sealing-bonding use resin partially inside the recess portion. Thereby, increases of a placement area for a fillet portion (foot spreading portion) of the sealing-bonding use resin are suppressed while its inclination angle is increased. Thus, stress loads that occur to peripheral portions of the semiconductor device due to thermal expansion differences and thermal contraction differences among individual members caused by heating process and cooling process in mounting operation are relaxed, by which internal breakdown of the semiconductor device mounted structure is avoided.02-04-2010
20100019382SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small. By so doing, both prevention of a short-circuit and improvement of the layout density of lands are attained at a time.01-28-2010
20100019381SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device and method of manufacturing a semiconductor device. One embodiment provides an electrically conductive carrier. A semiconductor chip is placed over the carrier. An electrically insulating layer is applied over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. A first through-hole is in the electrically insulating layer. Solder material is deposited in the first through-hole and on the second face of the electrically insulating layer.01-28-2010
20120146216SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided. The package includes a package substrate with a first surface and a second surface on the opposite side, and a plurality of via sets connecting vertically the first surface with the second surface, said via sets having a plurality of micro vias and filled with conductive material. The micro vias are grouped together, and the distance between micro vias in the via set is smaller than the distance between neighboring via sets.06-14-2012
20120146213HIGH PERFORMANCE LOW PROFILE QFN/LGA - A method for manufacturing a semiconductor device is disclosed. In one embodiment a semiconductor die is formed overlying a substrate. The semiconductor die is flip chip mounted to the substrate, wherein the substrate comprises a plurality of conductive traces. The semiconductor die and substrate are encapsulated with an encapsulating material. A top side of the encapsulating material is subjected to one of polishing, etching, and grinding to expose a top side of the semiconductor die. Finally, the bottom side of the substrate is subjected to one of polishing, etching, and grinding to remove the substrate and to reduce a thickness of the plurality of conductive traces.06-14-2012
20110074014Semiconductor Device and Method of Forming Adhesive Material to Secure Semiconductor Die to Carrier in WLCSP - A semiconductor device is made by providing a temporary carrier and providing a semiconductor die having a plurality of bumps formed on its active surface. An adhesive material is deposited as a plurality of islands or bumps on the carrier or active surface of the semiconductor die. The adhesive layer can also be deposited as a continuous layer over the carrier or active surface of the die. The semiconductor die is mounted to the carrier. An encapsulant is deposited over the die and carrier. The adhesive material holds the semiconductor die in place to the carrier while depositing the encapsulant. An interconnect structure is formed over the active surface of the die. The interconnect structure is electrically connected to the bumps of the semiconductor die. The adhesive material can be removed prior to forming the interconnect structure, or the interconnect structure can be formed over the adhesive material.03-31-2011
20090174070Three-dimensional stacked substrate arrangements - Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.07-09-2009
20090174069I/O PAD STRUCTURE FOR ENHANCING SOLDER JOINT RELIABILITY IN INTEGRATED CIRCUIT DEVICES - A semiconductor device is described. The device includes an integrated circuit die having an active surface that includes a plurality of input/output (I/O) pads. The device further includes a plurality of crack resistant structures. Each crack resistant structure is formed over an associated I/O pad and includes an associated raised portion. Each I/O pad may be bumped with solder such that a solder bump is formed over the associated crack resistant structure on the I/O pad.07-09-2009
20090174071Semiconductor device including electrically conductive bump and method of manufacturing the same - A semiconductor device and method of manufacturing are provided that include forming an electrically conductive bump on a substrate and forming at least one passivation layer on the bump to reduce solder joint failures.07-09-2009
20100007018PROCESS FOR COATING A BUMPED SEMICONDUCTOR WAFER - A process is described that enables the active side of a bumped wafer to be coated with a front side protection (FSP) material or wafer level underfill (WLUF) without contaminating the solder bumps with the coating material and/or filler. In this process a repellent material is applied to a top portion of the solder bumps on the active side of the wafer, the front side of the wafer is then coated with the coating material, the coating material is hardened, and optionally the repellent material is removed from the solder bumps.01-14-2010
20100013093Chip Mounting - A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, said buffer layers having a Young's Modulus of 2.5 GPa or less.01-21-2010
20110115081MULTILAYER SEMICONDUCTOR DEVICE AND ELECTRONIC EQUIPMENT - A multilayer semiconductor device includes an interconnect substrate provided with first electrode lands and connection terminals on a top surface; a semiconductor chip mounted on the top surface of the interconnect substrate; first connecting members connecting the first electrode lands to a circuit formation surface of the semiconductor chip; first metal posts provided on the connection terminals; encapsulating resin filling a space between the interconnect substrate and the semiconductor chip; a package provided with second electrode lands on a main surface; and second connecting members electrically connecting the first metal posts to the second electrode lands.05-19-2011
20110115080SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CONSTRUCT INSTALLED ON BASE PLATE, AND MANUFACTURING METHOD OF THE SAME - A semiconductor device comprises a semiconductor construct including a semiconductor substrate, and an external connection electrode provided to protrude on the surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including the side surface of the semiconductor substrate.05-19-2011
20110115079Wafter and substructure for use in manufacturing electronic component packages - A wafer for electronic component packages is used for manufacturing a plurality of electronic component packages, each of the plurality of electronic component packages including: a base incorporating a plurality of external connecting terminals; and at least one electronic component chip bonded to the base and electrically connected to the plurality of external connecting terminals. The wafer has a plurality of sets of external connecting terminals corresponding to the plurality of electronic component packages, a retainer for retaining the plurality of sets of external connecting terminals, and a coupling portion for coupling the plurality of sets of external connecting terminals to one another. The wafer includes a plurality of pre-base portions that will each be subjected to bonding of the at least one electronic component chip thereto and will be subjected to separation from one another later so that each of them will thereby become the base.05-19-2011
20110115078FLIP CHIP PACKAGE - A flip chip package may include a semiconductor chip, a package substrate, a conductive magnetic bump and an anisotropic conductive member. The semiconductor chip may have a first pad. The package substrate may have a second pad confronting the first pad. The conductive magnetic bump may be interposed between the semiconductor chip and the package substrate to generate a magnetic force. The anisotropic conductive member may be arranged between the semiconductor chip and the package substrate. The anisotropic conductive member may have conductive magnetic particles induced toward the conductive magnetic bump by the magnetic force to electrically connect the first pad with the second pad. A predetermined number of the conductive magnetic particles may be positioned between the conductive magnetic bump and the pad, so that an electrical connection reliability between the pads may be increased.05-19-2011
20110115077Method for Reducing Voids in a Copper-Tin Interface and Structure Formed Thereby - An embodiment is a method for forming a semiconductor assembly comprising cleaning a connector comprising copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.05-19-2011
20110115076SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND FABRICATION PROCESS THEREOF - A semiconductor device includes: a semiconductor substrate that has a first surface and a second surface opposite to the first surface; an electrode that is provided on the first surface of the semiconductor substrate; an insulating film that is provided on the first surface of the semiconductor substrate, the insulating film having an aperture at least partly overlapping the electrode; a resin bump that is provided on the insulating film; and a wiring layer that is electrically connected to the electrode, a part of the wiring layer being partly provided on the resin bump, the wiring layer including a first conductive layer formed on the electrode and on the resin bump, and a second conductive layer formed on the first conductive layer, the first conductive layer including a first surface on the side of the semiconductor substrate, and a second surface on the side of the second conductive layer, and a first oxide film or a first nitride film that is provided on the second surface of the first conductive layer.05-19-2011
20110115075BUMPING FREE FLIP CHIP PROCESS - Methods, systems, and apparatuses for an integrated circuit package assembly process are provided. A wafer is received having a surface defined by a plurality of integrated circuit regions. Electrical conductors are accessible through corresponding first openings in a first passivation layer on the surface of the wafer. Solderable metal layer features are formed on the electrical conductors through the first openings. The wafer is singulated to form a plurality of flip chip dies. A plurality of package substrates is received. Each package substrate has a plurality of solder on pad (SOP) features on a respective surface. Each flip chip die is mounted to a corresponding package substrate such that each SOP feature is coupled to a corresponding solderable metal layer feature, to form a plurality of integrated circuit packages.05-19-2011
20110115074WAFER BUMPING USING PRINTED UNDER BUMP METALIZATION - Methods, systems, and apparatuses for printing under bump metallization (UBM) features on chips/wafers are provided. A wafer is received that has a surface defined by a plurality of integrated circuit regions. Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. A plurality of UBM features are formed on the surface of the wafer in the form of an ink such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals. An ink jet printer may be used to print the ink in the form of the UBM feature. A UBM feature may be formed directly on a corresponding terminal, or on routing that is coupled to the corresponding terminal. A bump interconnect may be formed on the UBM feature.05-19-2011
20110115073PAD STRUCTURE FOR SEMICONDUCTOR DEVICES - A semiconductor device is provided which includes a semiconductor substrate having a plurality of microelectronic elements formed therein; an interconnect structure formed over the substrate, the interconnect structure including metal layers isolated from one another by an inter-metal dielectric, the metal layers including a topmost metal layer; dummy metal vias formed between at least two metal layers and disposed within a region of the interconnect structure; and a bonding pad formed over the topmost metal layer such that the bonding pad is aligned with the region of the interconnect structure.05-19-2011
20110133335Through-Silicon Via With Air Gap - A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the liner, which is subsequently removed to form an air gap around the conductive material of the through-silicon via. A dielectric layer is formed of the backside of the semiconductor substrate to seal the air gap.06-09-2011
20110068468Semiconductor Package with Semiconductor Core Structure and Method of Forming the Same - A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure.03-24-2011
20110037169Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structures - A semiconductor device has dual-molded semiconductor die mounted to opposite sides of a build-up interconnect structure. A first semiconductor die is mounted to a temporary carrier. A first encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed. A first interconnect structure is formed over a first surface of the first encapsulant and first semiconductor die. The first interconnect structure is electrically connected to first contact pads of the first semiconductor die. A plurality of conductive pillars is formed over the first interconnect structure. A second semiconductor die is mounted between the conductive pillars to the first interconnect structure. A second encapsulant is deposited over the second semiconductor die. A second interconnect structure is formed over the second encapsulant. The second interconnect structure is electrically connected to the conductive pillars and first and second semiconductor die.02-17-2011
20100320599DIE STACKING APPARATUS AND METHOD - Various stacked semiconductor devices and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor die that has a first bulk semiconductor side and a first opposite side. A second semiconductor die is provided that has a second bulk semiconductor side and a second opposite side. The second opposite side of the second semiconductor die is coupled to the first opposite side of the first semiconductor die. Electrical connections are formed between the first semiconductor die and the second semiconductor die.12-23-2010
20120146212SOLDER BUMP CONNECTIONS - Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.06-14-2012
20110304043SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device comprises a semiconductor chip which comprises mode-set terminals, and mode-set wiring lines respectively connected to the mode-set terminals, a sealing layer which covers the semiconductor chip and also covers a land of a first mode-set wiring line that is one of the mode-set wiring lines, the sealing layer including a mode-set via hole formed above a land of a second mode-set wiring line, the second mode-set wiring line being one of the mode-set wiring lines and being different from the first mode-set wiring line, a mode-set embedded conductor provided within the mode-set via hole to be connected to the second mode-set wiring line, and a mode-set conductive pattern which is connected to the mode-set embedded conductor and which is provided on the sealing layer above the land of the first mode-set wiring line.12-15-2011
20110304042Copper Bump Structures Having Sidewall Protection Layers - A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.12-15-2011
20110304041ELECTRICALLY CONNECTING ROUTES OF SEMICONDUCTOR CHIP PACKAGE CONSOLIDATED IN DIE-ATTACHMENT - A chip package comprises a chip, a plurality of bumps, and a die-attaching tape where the bumps are jointed to the corresponding bonding pads on the active surface of the chip. The die-attaching tape consists of a wiring core, a first dielectric adhesive, and a second dielectric adhesive where the wiring core is sandwiched between the first dielectric adhesive and the second dielectric adhesive. The wiring core is of a thickness of a dielectric material and includes a plurality of conductive traces separated by the dielectric material. The conductive traces are also of the thickness of the dielectric material. The die-attaching tape is attached to the active surface of the chip by the first dielectric adhesive to make the bumps penetrate the first dielectric adhesive and joint to the corresponding conductive traces. Therefore, the die-attaching tape can have both functions of holding the chip and transversely transmitting signals to substrate or another chip to eliminate or reduce the conventional wire-bonding processes.12-15-2011
20100213609SOLDER BUMP, SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING THE SEMICONDUCTOR CHIP, CONDUCTIVE CONNECTION STRUCTURE, AND METHOD OF MANUFACTURING THE CONDUCTIVE CONNECTION STRUCTURE - A solder bump and a conductive connection structure are provided which can conductively connect a semiconductor chip and a substrate with high connection reliability. Filler 08-26-2010
20120306073Connector Design for Packaging Integrated Circuits - A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.12-06-2012
20120306072Semiconductor Wafer with Reduced Thickness Variation and Method for Fabricating Same - According to one embodiment, a semiconductor wafer comprises a plurality of solder bumps for providing device contacts formed over a functional region of the semiconductor wafer, and one or more support rings surrounding the functional region. The one or more support rings and the plurality of solder bumps are formed so as to have substantially matching heights. The presence of the one or more support rings causes the semiconductor wafer to have a substantially uniform thickness in the functional region after a thinning process is performed on the semiconductor wafer. A method for fabricating the semiconductor wafer comprises forming the plurality of solder bumps over the functional region, and forming the one or more support rings surrounding the functional region before performing the thinning process on the semiconductor wafer.12-06-2012
20120306071WAFER-LEVEL PACKAGE DEVICE - Wafer-level package semiconductor devices are described that have a smallest distance between two adjacent attachment bumps smaller than about twenty-five percent (25%) of a pitch between the two adjacent attachment bumps. The smallest distance between the two adjacent attachment bumps allows for an increase in the number of attachment bumps per area without reducing the size of the bumps, which increases solder reliability. The increased solder reliability may reduce stress to the attachment bumps, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on.12-06-2012
20120306070Electrical Connection for Chip Scale Packaging - A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.12-06-2012
20090057888IC Package Having IC-to-PCB Interconnects on the Top and Bottom of the Package Substrate - An integrated circuit package, according to one embodiment, includes a package substrate, an interface stratum and an integrated circuit die. Both the IC die and interface stratum are disposed on the package substrate. The integrated circuit die includes a microelectronic circuit having a plurality of inputs and outputs. A first set of the inputs and outputs are electrically coupled to a plurality of package-to-circuit connection regions on the package substrate. A second set of input and outputs are electrically coupled through the package substrate to package-to-circuit connection regions on the interface stratum.03-05-2009
20110024899SUBSTRATE STRUCTURE FOR CAVITY PACKAGE - Various embodiments provide semiconductor devices having cavity substrate structures for package-on-package assembly and methods for their fabrication. In one embodiment, the cavity substrate structure can include at least one top interconnect via formed within a top substrate. The top substrate can be disposed over a base substrate having at least one base interconnect via that is not aligned with the top interconnect via. Semiconductor dies can be assembled in an open cavity of the top substrate and attached to a base center portion of the base substrate of the cavity substrate structure. A top semiconductor package can be mounted over the top substrate of the cavity substrate structure.02-03-2011
20120146214SEMICONDUCTOR DEVICE WITH VIAS AND FLIP-CHIP - Semiconductor devices comprising a flip-chip having passive circuits such as spiral inductors on the back side are disclosed.06-14-2012
20120146217CONDUCTIVE PAD STRUCTURE, CHIP PACKAGE STRUCTURE AND DEVICE SUBSTRATE - A conductive pad structure, configured in a peripheral circuit area of a device substrate, is provided. The conductive pad structure includes a conductive pad and a plurality of conductive spacers. The conductive spacers are configured on the conductive pad and arranged as a non-closed pattern on the conductive pad. Besides, a chip package structure and a device substrate that both have the above-mentioned conductive pad structure are also provided.06-14-2012
20120038043MANUFACTURING FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump.02-16-2012
20120038042LEAD-FREE SOLDER ALLOY, SOLDER BALL, AND ELECTRONIC MEMBER COMPRISING SOLDER BUMP - A lead-free solder alloy, a solder ball and an electronic member comprising a solder bump which enable the prevention of the occurrence of yellow discoloration on the surface of a solder after soldering, the surface of a solder bump after the formation of the bump in a BGA, and the surface of a solder bump after a burn-in test of a BGA. Specifically disclosed are: a lead-free solder alloy; a solder ball; and an electronic member comprising a solder bump, containing at least one additive element selected from Li, Na, K, Ca, Be, Mg, Sc, Y, lanthanoid series elements, Ti, Zr, Hf, Nb, Ta, Mo, Zn, Al, Ga, In, Si and Mn in the total amount of 1 ppm by mass to 0.1% by mass inclusive, with the remainder being 40% by mass or more of Sn.02-16-2012
20120038041HEAT DISSIPATION STRUCTURE FOR ELECTRONIC DEVICE AND FABRICATION METHOD THEREOF - A heat dissipation structure for an electronic device includes a body having a first surface and a second surface opposite to the first surface. A silicon-containing insulating layer is disposed on the first surface of the body. An ultrananocrystalline diamond film is disposed on the silicon-containing insulating layer. A first conductive pattern layer is disposed on the silicon-containing insulating layer and enclosed by the ultrananocrystalline diamond film, wherein the ultrananocrystalline diamond film and the first conductive pattern layer do not overlap with each other as viewed from a top-view perspective. A method for fabricating a heat dissipation structure for an electronic device and an electronic package having the heat dissipation structure are also disclosed.02-16-2012
20090283904FLIPCHIP BUMP PATTERNS FOR EFFICIENT I-MESH POWER DISTRIBUTION SCHEMES - Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.11-19-2009
20100283148Bump Pad Structure - An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.11-11-2010
20120038040INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED LEAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit device to the substrate; forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity.02-16-2012
20120098128CHIP STRUCTURE AND PROCESS FOR FORMING THE SAME - A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.04-26-2012
20120098124SEMICONDUCTOR DEVICE HAVING UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device has a UBM (under-bump metallization) structure underlying and electrically connected to a solder bump. The UBM structure has a first metallization layer with a first cross-sectional dimension d04-26-2012
20120098123Molded Chip Interposer Structure and Methods - Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.04-26-2012
20120153461SEMICONDUCTOR COMPONENT, SEMICONDUCTOR WAFER COMPONENT, MANUFACTURING METHOD OF SEMICONDUCTOR COMPONENT, AND MANUFACTURING METHOD OF JOINING STRUCTURE - A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.06-21-2012
20120061827SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a first surface, a through silicon via (TSV) that is formed so that at least a part thereof penetrates through the semiconductor substrate, and an insulation ring. The insulation ring is formed so as to penetrate through the semiconductor substrate and so as to surround the TSV. The insulation ring includes a tapered portion and a vertical portion. The tapered portion has a sectional area which is gradually decreased from the first surface toward a thickness direction of the semiconductor substrate. The vertical portion has a constant sectional area smaller than the tapered portion.03-15-2012
20110316148WIRING SUBSTRATE - A wiring substrate includes plural wiring layers and plural insulation layers being alternately stacked one on top of the other. The plural insulation layers are formed with insulation resin having the same composition. The plural insulation layers are formed with a filler having the same composition. The filler content of each of the plural insulation layers ranges from 30 vol % or more to 65 vol % or less. The thermal expansion coefficient of each of the plural insulation layers ranges from 12 ppm/° C. or more to 35 ppm/° C. or less.12-29-2011
20110316150SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes a first board, a semiconductor chip having a first face and a second face at an opposite side to the first face, the semiconductor chip being mounted on the first board with the first face facing the first board, an insulating film provided on the second face of the semiconductor chip, and a second board stacked on the first board. A bump provided on a face of the second board facing the first board is connected to a pad provided on a face of the first board facing the second board and a gap is formed between the first board and the second board. The semiconductor chip and the insulating film are provided in the gap.12-29-2011
20110316154SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having a plurality of electrode pads, a protective film covering the upper surface of the semiconductor substrate and having an opening so that the electrode pad is exposed therethrough, a metal film formed on the electrode pad exposed through the opening, and a bump formed on the metal film. The metal film includes a plurality of grooves radially formed from the center thereof toward the periphery thereof.12-29-2011
20110316153SEMICONDUCTOR DEVICE AND PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate 12-29-2011
20110316151SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A semiconductor package includes a board, an under fill resin layer provided on the board, and a semiconductor chip having a first face and a second face at an opposite side to the first face, the semiconductor chip being flip-chip mounted on the board via the under fill resin layer with the first face facing the board. The semiconductor chip is covered with the under fill resin layer over the first face and from the first face to an edge part of the second face.12-29-2011
20110316149METHOD OF MOUNTING ELECTRONIC COMPONENT AND MOUNTING SUBSTRATE - In flip chip attach of electronic components, underfill is filled between the component and the substrate to alleviate, for example, thermal stress. In electronic component mounting using copper pillars conducted so far, filler contained in the underfill may cause separation in the process of heating and curing the resin. Disclosed is plating the surfaces of the copper pillars with solder. Mobilization of the filler charged in the underfill due to electric fields produced by local cells that are developed upon contact between dissimilar metals, is suppressed, and occurrence of crack at connection portions is obviated. Thus, connection reliability is increased.12-29-2011
20110316147Embedded 3D Interposer Structure - A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.12-29-2011
20110316146Semiconductor Device and Method of Forming Anisotropic Conductive Film Between Semiconductor Die and Build-Up Interconnect Structure - A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. An ACF is deposited over the bumps and active surface of the wafer. An insulating layer can be formed between the ACF and semiconductor die. The semiconductor wafer is singulated to separate the die. The semiconductor die is mounted to a temporary carrier with the ACF oriented to the carrier. The semiconductor die is forced against the carrier to compress the ACF under the bumps and form a low resistance electrical interconnect to the bumps. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected through the compressed ACF to the bumps. The ACF reduces shifting of the semiconductor die during encapsulation.12-29-2011
20110316152MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGES AND A SEMICONDUCTOR PACKAGE - Semiconductor chips are placed in recesses of a support carrier with electrode surfaces facing upward in a state where the semiconductor chips are arranged separately from each other. A seal resin part is formed by encapsulating the semiconductor chips by an insulating resin on said support carrier. Rewiring patterns are formed on a top surface of the seal resin part. External connection terminals are formed on the rewiring patterns. Bottom parts of the recesses of the support carrier are removed from the seal resin part while maintaining reinforcing members of the support carrier to be remained. The semiconductor packages are individualized by cutting the seal resin part along an outside of each reinforcing member.12-29-2011
20120043654MECHANISMS FOR FORMING COPPER PILLAR BUMPS USING PATTERNED ANODES - The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.02-23-2012
20120001322DOUBLE MOLDED CHIP SCALE PACKAGE - Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.01-05-2012
20120001324SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a circuit substrate, and first and second semiconductor chips mounted on it. The first semiconductor chip and the second semiconductor chip are flip-chip connected, and an underfill resin is filled between them. The underfill resin has a fillet portion. A thickness T01-05-2012
20110037171Electronic Structures Including Barrier Layers and/or Oxidation Barriers Defining Lips and Related Methods - An electronic device may include a substrate, a seed layer on the substrate, a barrier layer on the seed layer opposite the substrate, and an oxidation barrier on the barrier layer opposite the seed layer. The barrier layer and the seed layer comprise different materials, and the oxidation barrier and the barrier layer may comprise different materials. The seed layer may be undercut relative to the barrier layer and/or relative to the oxidation barrier so that the barrier layer and/or the oxidation barrier define a lip extending beyond the seed layer in a direction parallel with respect to a surface of the substrate. Related methods are also discussed.02-17-2011
20120001323Semiconductor Device Including Ultra Low-K (ULK) Metallization Stacks with Reduced Chip-Package Interaction - In complex semiconductor devices, sophisticated ULK materials may be used in metal line layers in combination with a via layer of enhanced mechanical stability by increasing the amount of dielectric material of superior mechanical strength. Due to the superior mechanical stability of the via layers, reflow processes for directly connecting the semiconductor die and a package substrate may be performed on the basis of a lead-free material system without unduly increasing yield losses.01-05-2012
20110156249WAFER-TO-WAFER STACK WITH SUPPORTING PEDESTAL - An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.06-30-2011
20110156248SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an integrated circuit having an electrode pad; a first insulating layer disposed on the integrated circuit; a redistribution layer including a plurality of wirings and disposed on the first insulating layer, at least one of the plurality of wirings being electrically coupled to the electrode pad; a second insulating layer having a opening on at least a portion of the plurality of wirings; a metal film disposed on the opening and on the second insulating layer, and electrically coupled to at least one of the plurality of wirings; and a solder bump the solder bump overhanging at least one of the plurality of wirings not electrically coupled to the metal film.06-30-2011
20100181666Semiconductor device having lead free solders between semiconductor chip and frame and gabrication method thereof - A semiconductor device includes a semiconductor chip having a current path between a first principal surface and a second principal surface opposite from the first principal surface, a first conductive frame having an opposite region to the first principal surface, and a second conductive frame electrically connected via electrical connection member to a pad formed on the second principal surface. In a gap between the first principal surface and the first conductive frame, there are arranged multiple column-shaped lead-free solders which are arranged within a circle drawn around a center of the opposite region and having a diameter corresponding to a narrow side of the opposite region, and which electrically connects the first conductive frame with the semiconductor chip, and a filler which is filled between the multiple column-shaped lead-free solders.07-22-2010
20100283146SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure including a substrate, an insulating layer, a composite pad structure, a passivation layer, and a bump is provided. A circuit structure is disposed on the substrate. The insulating layer covers the substrate and has a first opening exposing the circuit structure. The composite pad structure includes a first conductive layer, a barrier layer, and a second conductive layer which are sequentially disposed. The composite pad structure is disposed on the insulating layer and fills the first opening to electrically connect to the circuit structure. The passivation layer covers the composite pad structure and has a second opening exposing the composite pad structure. The bump fills the second opening and electrically connects to the composite pad structure.11-11-2010
20120007238Method of Manufacturing a Semiconductor Device - Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.01-12-2012
20120007237CHIP PACKAGE - A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.01-12-2012
20120007236SEMICONDUCTOR DEVICE AND PACKAGE - A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.01-12-2012
20120007235Chip Fanning Out Method and Chip-on-Film Device - A chip fanning out method is disclosed. The chip fanning out method includes mounting a chip on a film, forming a plurality of outer lead bonds spatially arranged in a bump correspondence order on the film, forming a plurality of bumps spatially arranged in a bump arrangement order on the chip, and forming a plurality of wires to connect the plurality of outer lead bonds to the plurality of bumps according to the bump correspondence order, wherein the bump correspondence order is different from the bump arrangement order.01-12-2012
20120007234SEMICONDUCTOR PACKAGE WITHOUT CHIP CARRIER AND FABRICATION METHOD THEREOF - A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.01-12-2012
20120007233SEMICONDUCTOR ELEMENT AND FABRICATION METHOD THEREOF - A semiconductor element and a fabrication method thereof. The method includes forming an encapsulating layer on a semiconductor silicon substrate having electrode pads and a passivation layer formed thereon, the encapsulating layer covering the electrode pads and a part of the passivation layer that surrounds the electrode pads; forming a covering layer on the passivation layer and the encapsulating layer with a plurality of openings that expose a part of the encapsulating layer; forming a bonding metallic layer on the part of the encapsulating layer that are exposed from the openings and electrically connecting the bonding metallic layer to the encapsulating layer, wherein the bonding metallic layer is not greater in diameter than the encapsulating layer; and forming a conductive element on the bonding metallic layer. The encapsulating layer provides a good buffering effect to prevent electrode pads from delamination or being broken caused by the direct stress from the conductive element.01-12-2012
20120056322SEMICONDUCTOR DEVICE WITH PADS OF ENHANCED MOISTURE BLOCKING ABILITY - A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.03-08-2012
20120056318SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a semiconductor device including a semiconductor element, an electrode pad of the semiconductor element, a buffer coat film, and a micro-bump. The buffer coat film has an opening corresponding to the electrode pad. The micro-bump is electrically connected to the electrode pad through the opening. A contact area between the micro-bump and side surfaces of the opening is larger than a contact area between the micro-bump and a bottom surface of the opening.03-08-2012
20120056316Semiconductor Device and Method of Forming Different Height Conductive Pillars to Electrically Interconnect Stacked Laterally Offset Semiconductor Die - A semiconductor device has a first semiconductor die mounted over a carrier. Wettable contact pads can be formed over the carrier. A second semiconductor die is mounted over the first semiconductor die. The second die is laterally offset with respect to the first die. An electrical interconnect is formed between an overlapping portion of the first die and second die. A plurality of first conductive pillars is disposed over the first die. A plurality of second conductive pillars is disposed over the second die. An encapsulant is deposited over the first and second die and first and second conductive pillars. A first interconnect structure is formed over the encapsulant, first conductive pillars, and second die. The carrier is removed. A second interconnect structure is formed over the encapsulant, second conductive pillars, and first die. A third conductive pillar is formed between the first and second build-up interconnect structures.03-08-2012
20120056317CHIP - A chip includes a body, a number of pins, and conductive pieces. The body includes a top surface and a bottom surface. The pins are arranged on the bottom surface. The conductive pieces are arranged on the top surface. The number of the conductive pieces equals to the number of the pins. Each pin is electrically connected to one conductive piece.03-08-2012
20120056320SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor substrate, a metal film, a surface modifying layer, and a redistribution trace are provided. On the semiconductor substrate, a wire and a pad electrode are formed. The metal film is formed over the semiconductor substrate. The surface modifying layer is formed on a surface layer of the metal film and improves the adhesion with a resist pattern. The redistribution trace is formed on the metal film via the surface modifying layer.03-08-2012
20120007231METHOD OF FORMING CU PILLAR CAPPED BY BARRIER LAYER - A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.01-12-2012
20120007232MICROELECTRONIC PACKAGES WITH DUAL OR MULTIPLE-ETCHED FLIP-CHIP CONNECTORS - A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.01-12-2012
20120007230CONDUCTIVE BUMP FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer.01-12-2012
20120013004Semiconductor Device Having an Interconnect Structure with TSV Using Encapsulant for Structural Support - A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.01-19-2012
20120013003BGA PACKAGE WITH TRACES FOR PLATING PADS UNDER THE CHIP - A semiconductor flip-chip ball grid array package with one-metal-layered substrate. The sites of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area, when the sites can be routed for metal plating. The space to place a maximum number of signal routing traces is opened up by interrupting the periodicity of the site array from the edge of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.01-19-2012
20120013001STACKABLE MOLDED MICROELECTRONIC PACKAGES WITH AREA ARRAY UNIT CONNECTORS - A microelectronic package having a substrate, a microelectronic element, e.g., a chip, and terminals can have conductive elements electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant can overlie the first surface of the substrate and at least a portion of a face of the microelectronic element remote from the substrate, and may have a major surface above the microelectronic element. A plurality of package contacts can overlie a face of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses, substantially rigid posts, can be electrically interconnected with terminals of the substrate, such as through the conductive elements. The package contacts can have top surfaces at least partially exposed at the major surface of the encapsulant.01-19-2012
20120013000STACKABLE MOLDED MICROELECTRONIC PACKAGES - A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts projecting above the first surface or projecting above a second surface of the substrate remote therefrom. Conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant overlies at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a recess or a plurality of openings each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials. In particular embodiments, the openings in the encapsulant at least partially expose conductive masses joined to posts, fully expose top surfaces of posts and partially expose edge surfaces of posts, or may only partially expose top surfaces of posts.01-19-2012
20100213608Solder bump UBM structure - Disclosed is an under bump metallization structure including a plurality of metal or metal alloy layers formed on chip bond pads. The disclosed UBM structure has a stress improvement on the semiconductor device because the thickness of the copper-base layer is reduced to between about 0.3 and 10 microns, preferably between about 0.3 and 2 micron. The presence of the pure tin layer prevents oxidation and contamination of the nickel-base layer. It also forms a good solderable surface for the subsequent processes. Also disclosed are semiconductor devices having the disclosed UBM structure and the methods of making the semiconductor devices.08-26-2010
20100224993Forming sacrificial composite materials for package-on-package architectures and structures formed thereby - Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.09-09-2010
20110018129Semiconductor Device - To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.01-27-2011
20110049709METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.03-03-2011
20110049708Semiconductor Chip Interconnection Structure and Semiconductor Package Formed Using the Same - A semiconductor chip interconnection structure and a semiconductor package formed using the same are provided. The semiconductor chip interconnection structure comprises a chip, a bump assembly and an electrical element. The chip comprises a pad and has a pad aperture from which the pad is exposed. The bump assembly comprises a first bump and a second bump. The first bump is disposed on the pad. The second bump is disposed on the first bump. The outer diameter of the second bump is not less than the outer diameter of the first bump. The electrical element is connected to the bump assembly.03-03-2011
20110049707SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes an electrode pad, a protective layer, a bump, and a resin layer. The electrode pad is formed on a semiconductor substrate. The protective layer includes a pad opening formed in the position of the electrode pad. The bump is formed in the pad opening and electrically connected to the electrode pad. The resin layer has a space provided between the resin layer and the bump and is formed on the protective layer via a metal layer. The resin layer is formed by using an adhesive resin material.03-03-2011
20110049706Front Side Copper Post Joint Structure for Temporary Bond in TSV Application - An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.03-03-2011
20110049705SELF-ALIGNED PROTECTION LAYER FOR COPPER POST STRUCTURE - A copper post is formed in a passivation layer to electrically connect an underlying bond pad region, and extends to protrude from the passivation layer. A protection layer is formed on a sidewall surface or a top surface of the copper post in a self-aligned manner. The protection layer is a manganese-containing oxide layer, a manganese-containing nitride layer or a manganese-containing oxynitride layer.03-03-2011
20110049704SEMICONDUCTOR DEVICE PACKAGES WITH INTEGRATED HEATSINKS - In one embodiment, a semiconductor device package includes a circuit substrate, a chip, a plurality of first solder balls, an encapsulant, and a heatsink. The circuit substrate includes a carrying surface and a plurality of first bonding pads thereon. The chip is disposed on the carrying surface and electrically connected to the circuit substrate. The first bonding pads are located outside of the chip. The first solder balls are disposed on the first bonding pads. The encapsulant is disposed on the carrying surface and covers the chip. The encapsulant includes a plurality of openings exposing the first solder balls. The heatsink is disposed over the encapsulant and bonded to the first solder balls, wherein the heatsink includes a plurality of protrusions on a bonding surface facing the encapsulant, and the protrusions are correspondingly embedded into the first solder balls.03-03-2011
20120012998Conductive Sidewall for Microbumps - Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.01-19-2012
20110049703Flip-Chip Package Structure - A flip-chip (FC) package structure is provided. The FC package structure includes a substrate, a chip, a plurality of copper platforms, a plurality of copper bumps, a plating layer, a circuit layer and a solder mask layer. The copper bumps are disposed on the substrate. The copper platforms are stacked on the copper bumps. The plating layer covers the copper bumps and the copper platforms, for contacting with chip foot pads configured at a bottom of the chip. The FC package structure does not need to reserve a space for wire bonding, thus saving the area of the substrate. The copper platforms are stacked on the copper bumps, and are higher than the circuit pattern layer. Therefore, the chip is blocked up, and the gap between the chip and the substrate is enlarged, thus preventing the risk of configuring voids when filling the cladding material and improving the packaging yield.03-03-2011
20120012999SEMICONDUCTOR-ENCAPSULATING ADHESIVE, SEMICONDUCTOR-ENCAPSULATING FILM-FORM ADHESIVE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator.01-19-2012
20120012997Recessed Pillar Structure - A bump structure that may be used to interconnect one substrate to another substrate is provided. A recessed conductive pillar is formed on a first substrate such that the recessed conductive pillar has a recess formed therein. The recess may be filled with a solder material. A conductive pillar on a second substrate may be formed having a contact surface with a width less than or equal to a width of the recess. The first substrate may be attached to the second substrate such that the conductive pillar on the second substrate is positioned over or in the recess of the first substrate. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.01-19-2012
20090020871SEMICONDUCTOR CHIP WITH SOLDER BUMP SUPPRESSING GROWTH OF INTER-METALLIC COMPOUND AND METHOD OF FABRICATING THE SAME - A semiconductor chip having a solder bump and a method of fabricating the same are provided. Conventionally, an inter-metallic compound (IMC) unexpectedly grows at an interface of the solder bump by means of heat generated during operation of the semiconductor chip, thereby weakening mechanical property of the semiconductor chip. To solve this drawback, the semiconductor chip includes at least one metal adhesion layer formed on an electrode pad of the semiconductor chip, an interlayer isolation layer formed on the metal adhesion layer, at least one penetration layer formed on the interlayer isolation layer and penetrating into the solder bump, and the solder bump formed on the penetration layer. Thereby, materials of the penetration layer penetrate into the solder bump to change the solder bump into a multi-component solder bump, so that the growth of the IMC is suppressed, and the reliability of the semiconductor chip can be improved.01-22-2009
20120061829METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE - A manufacturing method of a substrate for a semiconductor element, wherein a first step includes: forming a first and second photosensitive resin layer on a first and second surface of a metal plate, respectively; forming a first and second resist pattern on the first and second surface, for forming a connection post and a wiring pattern, respectively. A second step includes: forming the connection post and wiring pattern; filling in a premold liquid resin to the first surface which was etched; forming a premold resin layer by hardening the premold liquid resin; performing a grinding operation on the first surface, and exposing an upper bottom surface of the connection post from the premold resin layer. A groove structure is formed by the first and second steps, wherein a depth of the groove is up to an intermediate part in a thickness direction of the metal plate.03-15-2012
20120061828SEMICONDUCTOR DEVICE AND LAYOUT METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device that is resin-sealed in a wafer level after a rewiring layer forming process and a metal post forming process forming a metal post are performed on a semiconductor substrate of the semiconductor device includes devices formed on the semiconductor substrate. Further all of the devices are disposed in respective positions other than positions overlapping a peripheral border of the metal post when viewed from a top of the semiconductor substrate.03-15-2012
20120061825CHIP SCALE PACKAGE AND METHOD OF FABRICATING THE SAME - A chip scale package and a method of fabricating the chip scale package. The chip scale package includes a encapsulant having a first surface and a second surface opposing the first surface; a conductive pillar formed in the encapsulant and exposed from the first surface and the second surface; a chip embedded in the encapsulant while exposed from the first surface; a dielectric layer formed on the first surface, the conductive pillar and the chip; a circuit layer formed on the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer electrically connecting the circuit layer, electrode pads and the conductive pillar; and a solder mask layer formed on the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure.03-15-2012
20120061824SEMICONDUCTOR DEVICE AND METHOD OF FORMING BOND-ON-LEAD INTERCONNECTION FOR MOUNTING SEMICONDUCTOR DIE IN FO-WLCSP - A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer.03-15-2012
20130009304CHIP-STACKED SEMICONDUCTOR PACKAGE - A chip-stacked semiconductor package including a stacked chip structure including a plurality of separate chips stacked on each other; a flexible circuit substrate having the stacked chip structure mounted on a first side of the flexible circuit substrate in a first region of the flexible circuit substrate, and being electrically connected to at least one of the plurality of separate chips of the stacked chip structure by folding a second region of the flexible circuit substrate; a sealing portion sealing the stacked chip structure and the flexible circuit substrate; and an external connecting terminal on a second side of the flexible circuit substrate.01-10-2013
20120104597CHIP-ON-CHIP STRUCTURE AND MANUFACTURING METHOD THEROF - According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.05-03-2012
20120205798SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer attached on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; and a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer.08-16-2012
20120205797BUMP AND SEMICONDUCTOR DEVICE HAVING THE SAME - A bump includes a metal pillar formed over a structural body; and a diffusion barrier member formed to cover at least a portion of a side surface of the metal pillar.08-16-2012
20120205796SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a substrate having a connection terminal with a groove on its surface. Nanopowder may be disposed on a bottom of the groove. A semiconductor chip may be flip-chip bonded to the substrate by the nanopowder. A filler member may be interposed between the substrate and the semiconductor chip.08-16-2012
20120205799CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.08-16-2012
20120205794SEMICONDUCTOR CHIP PACKAGE STRUCTURE AND SEMICONDUCTOR CHIP - A semiconductor chip package structure including a first semiconductor chip, a second semiconductor chip and a supporting substrate is provided. The first semiconductor chip includes at least a first conductor unit. The first conductor unit has a first bonding surface and a second bonding surface exposed from the first semiconductor chip. The second semiconductor chip includes at least a second conductor unit. The second conductor unit has a third bonding surface and a fourth bonding surface exposed from the second semiconductor chip. The third bonding surface is contacted with and electrically connected to the first bonding surface. The supporting substrate includes a wire unit for electrically connecting to at least one of the second bonding surface and the fourth bonding surface. A semiconductor chip and a semiconductor chip group are also provided.08-16-2012
20120025373Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnects on Different Height Traces - A method of making a semiconductor device includes providing a substrate, and forming a first conductive layer over the substrate. A patterned layer is formed over the first conductive layer. A second conductive layer is formed in the patterned layer. A height of the second conductive layer is greater than a height of the first conductive layer. The patterned layer is removed. A first bump and a second bump are formed over the first and second conductive layers, respectively, wherein the second bump overlaps the first bump, and wherein an uppermost surface of the second bump is vertically offset from an uppermost surface of the first bump. Bond wires are formed on the first and second bumps. The bond wires are arranged in a straight configuration. Lowermost surfaces of the first conductive layer and second conductive layer are substantially coplanar.02-02-2012
20120025372CHIP HAVING A DRIVING INTEGRATED CIRCUIT - A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.02-02-2012
20120025374INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUNDED INTERCONNECT - An integrated circuit packaging system includes: a package carrier; an integrated circuit attached to the package carrier; a rounded interconnect on the package carrier; and an encapsulation over the package carrier covering the integrated circuit and exposing the rounded interconnect having a characteristic free of denting.02-02-2012
20120025371SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film.02-02-2012
20120025369SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor element, a plurality of element contacts and a molding compound. The substrate includes a passivation layer and a plurality of substrate pads. Each substrate pad includes a protrusion and an embedded portion. The embedded portion is embedded in the passivation layer, and the protrusion projects from the passivation layer. The semiconductor element includes a plurality of under bump metallurgies (UBM) with recesses. The ratio of the width of each recess to the first width of the protrusion is larger than 1. The element contacts connect the UBM and the substrate pads. The molding compound covers the semiconductor element.02-02-2012
20120025368Semiconductor Device Cover Mark - A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.02-02-2012
20120061830BACK SIDE PROTECTIVE STRUCTURE FOR A SEMICONDUCTOR PACKAGE - A back side protective structure for a semiconductor package provided with a conductive layer, which is elastic and contains conductive material, formed between a protection substrate and an adhesive layer for having the protection substrate more stably fixed on the semiconductor package and protecting the back side of the semiconductor package.03-15-2012
20120061822Semiconductor Device and Method of Forming Base Substrate With Cavities Formed Through Etch-Resistant Conductive Layer for Bump Locking - A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers.03-15-2012
20120061821SEMICONDUCTOR CHIP WITH REDUNDANT THRU-SILICON-VIAS - A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.03-15-2012
20120061831SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - A semiconductor package includes: a semiconductor substrate; an inner insulator layer formed on the substrate; at least one internal wiring extending from a front side of the substrate along one of lateral sides of the substrate to a rear side of the substrate; a first outer insulator layer disposed at the front side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole; and a second outer insulator layer disposed at the rear side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole which exposes a portion of the internal wiring.03-15-2012
20120061826SEMICONDUCTOR DEVICE - A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.03-15-2012
20120153466PACKAGE STRUCTURE - A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.06-21-2012
20120153465PACKAGE STRUCTURE - The invention discloses a package structure including a semiconductor device, a first protection layer, a second protection layer and at least one conductive bump. The semiconductor device has at least one pad. The first protection layer is disposed on the semiconductor device and exposes the pad. The second protection layer, disposed on the first protection layer, has at least one first opening and at least one second opening. The first opening exposes a partial surface of the pad. The second opening exposes a partial surface of the first protection layer. The conductive bump, opposite to the pad, is disposed on the second protection layer and coupled to the pad through the first openings.06-21-2012
20120205800PACKAGING STRUCTURE - A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.08-16-2012
20120205795STACKED PACKAGE AND METHOD OF MANUFACTURING THE SAME - A stacked package and method of manufacture are provided. The stacked package may include a first semiconductor package, a second semiconductor package, plugs and spacers. The second semiconductor package may be stacked on the first semiconductor package. The plugs may electrically connect the first semiconductor to the second semiconductor package. The spacer may be interposed between the first semiconductor package and the second semiconductor package to form a gap between the first semiconductor package and the second semiconductor package, thereby preventing an electrical short between the plugs.08-16-2012
20120153467Semiconductor Device and Method of Forming Thin Profile WLCSP with Vertical Interconnect over Package Footprint - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. The active surface of the first semiconductor die is oriented toward an active surface of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die. A portion of a back surface of the second semiconductor die opposite the active surface is removed. Conductive pillars are formed around the second semiconductor die. TSVs can be formed through the first semiconductor die. An interconnect structure is formed over the back surface of the second semiconductor die, encapsulant, and conductive pillars. The interconnect structure is electrically connected to the conductive pillars. A portion of a back surface of the first semiconductor die opposite the active surface is removed. A heat sink or shielding layer can be formed over the back surface of the first semiconductor die.06-21-2012
20120153469MICRO ELECTRONIC MECHANICAL SYSTEM STRUCTURE - A micro electronic mechanical system structure and a manufacturing method thereof are provided. A substrate has a plurality of conductive regions is provided. A dielectric layer is formed on the substrate. A plurality of openings and recesses are formed in the dielectric layer, wherein the openings expose the conductive regions. The recesses are located between the openings. A conductive layer is formed on the dielectric layer and the openings and the recesses are filled with the conductive layer. The conductive layer is patterned to form a plurality of strips of the first conductive patterns on the dielectric layer and a second conductive pattern on the sidewall and the bottom of each recess, wherein the first conductive patterns are connected with each other through the second conductive patterns. The dielectric layer is removed. The second conductive patterns between the first conductive patterns are removed.06-21-2012
20120153468Elimination of RDL Using Tape Base Flip Chip on Flex for Die Stacking - A flexible film interposer for stacking a flip chip semiconductor die onto a second (bottom) semiconductor die, semiconductor devices and stacked die assemblies that incorporate the flexible film interposer, and methods of fabricating the devices and assemblies are provided. The incorporation of the flexible film interposer achieves densely packaged semiconductor devices, without the need for a redistribution layer (RDL).06-21-2012
20120153463MULTILAYER WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.06-21-2012
20120153462SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.06-21-2012
20120153459METHOD FOR CHIP SCALE PACKAGE AND PACKAGE STRUCTURE THEREOF - This invention provides a method for chip scale package and a chip scale package structure. The chip scale package structure includes: a semiconductor substrate, on which sets a plurality of contact bonding pads being connected with semiconductor devices; and a plurality of bumps respectively attached to all of the contact bonding pads. The semiconductor substrate is divided into several regions according to different distances from a central point. The contact bonding pads and the bumps in the region which is closest to the central point are the smallest, while the contact bonding pads and the bumps in the region which is farthest to the central point are the largest. The invention effectively improves the situation that the bumps at the edge tend to flake off easily; in addition, it avoids short-circuit caused by bridging between the bumps.06-21-2012
20120153460BUMP STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a bump structure is provided. A substrate having at least one pad and a passivation layer is provided. The passivation layer has at least one first opening exposing the pad. An insulating layer is formed on the passivation layer. The insulating layer has at least one second opening located above the first opening. A metal layer is formed on the insulating layer. The metal layer electrically connects the pad through the first and second openings. A first bump is formed in the first and second openings. A second bump is formed on the first bump and a portion of the metal layer. The metal layer not covered by the second bump is partially removed by using the second bump as a mask, so as to form at least one UBM layer. The first bump is completely covered by the UBM layer and the second bump.06-21-2012
20120153458IC DEVICE HAVING ELECTROMIGRATION RESISTANT FEED LINE STRUCTURES - An integrated circuit (IC) device includes an electromigration resistant feed line. The IC device includes a substrate including active circuitry. A back end of the line (BEOL) metallization stack includes an interconnect metal layer that is coupled to a bond pad by the EM resistant feed line. A bonding feature is on the bond pad. The feed line includes a uniform portion and patterned trace portion that extends to the bond pad which includes at least three sub-traces that are electrically in parallel. The sub-traces are sized so that a number of squares associated with each of the sub-traces are within a range of a mean number of squares for the sub-traces plus or minus twenty percent or a current density provided to the bonding feature through each sub-trace is within a range of a mean current density provided to the bonding feature plus or minus twenty percent.06-21-2012
20100096749SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor substrate; a metal post, penetrating through the conductive pad, the semiconductor substrate, and the insulating layer; and an outer-layer circuit, being electrically connected to the metal post. With the present invention, it can become unnecessary to form an additional via for electrically connecting both surfaces of the semiconductor substrate, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the coupling reliability.04-22-2010
20110074019SEMICONDUCTOR DEVICE - To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.03-31-2011
20110074018SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a method of manufacturing a semiconductor device is disclosed. The method includes forming a cured film of an insulation resin on a surface of a first semiconductor chip and flip-chip bonding a second semiconductor via a bump on the first semiconductor chip on which the cured film of the insulation resin is formed. The insulation resin can be cured at temperature range from (A−50)° C. to (A+50)° C., wherein “A” is a solidification point of the bump.03-31-2011
20090134514METHOD FOR FABRICATING ELECTRICAL BONDING PADS ON A WAFER - A method for fabricating electrical bonding pads on one face of a wafer includes the production of electrically conductive areas and electrical connection branches connecting these conductive areas. A layer of mask material is deposited and openings are produced in this mask layer which extend above said conductive areas and at least some of which extend at least partly beyond the peripheral edges of the underlying conductive areas. Blocks made of a solder material are produces in the openings by electrodeposition in a bath. The mask material is then removed along with the connection branches. The wafer is passed through or placed in an oven so as to shape, on the conductive areas, the blocks into substantially domed electrical bonding pads.05-28-2009
20120119357SEMICONDUCTOR APPARATUS - A semiconductor apparatus having stacked first and second chips includes a first through line of the first chip configured to receive a first coding signal and be electrically connected to a first through line of the second chip; a second through line of the first chip configured to receive a second coding signal; and a second through line of the second chip configured to be electrically connected to the first through line of the first chip and receive the first coding signal.05-17-2012
20110089562SEMICONDUCTOR DEVICE HAVING WAFER-LEVEL CHIP SIZE PACKAGE - A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.04-21-2011
20110089561SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package has: a first chip; and a second chip. The first chip has: an insulating resin layer formed on a principal surface of the first chip; a bump-shaped first internal electrode group that is so formed in a region of the insulating resin layer as to penetrate through the insulating resin layer and is electrically connected to the second chip; an external electrode group used for electrical connection to an external device; and an electrostatic discharge protection element group electrically connected to the external electrode group. The first internal electrode group is not electrically connected to the electrostatic discharge protection element group.04-21-2011
20110089560Non-Uniform Alignment of Wafer Bumps with Substrate Solders - An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps.04-21-2011
20120119356SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR DEVICE - A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 μm or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.05-17-2012
20120313240SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes a substrate having a flip chip bonding area. A plurality of recessed bump pads are disposed in the flip chip bonding area. The substrate further includes a solder mask that covers a circuit area. A chip having a plurality of metal bumps is mounted in the flip chip bonding area. The metal bumps are respectively connected to the recessed bump pads. An underfill is filled into the gap between the substrate and the chip.12-13-2012
20120313239FLIP CHIP ASSEMBLY AND PROCESS WITH SINTERING MATERIAL ON METAL BUMPS - A microelectronic package includes a substrate overlying the front face of a microelectronic element. A plurality of metal bumps can project from conductive elements of the substrate towards the microelectronic element, the metal bumps having first ends extending from the conductive elements, second ends remote from the conductive elements, and lateral surfaces extending between the first and second ends. A conductive matrix material can contact the second ends and at least portions of the lateral surfaces of respective ones of the metal bumps and join the metal bumps with contacts of the microelectronic element.12-13-2012
20120313241METHODS FOR SURFACE ATTACHMENT OF FLIPPED ACTIVE COMPONENTS - A method for selectively transferring active components from a source substrate to a destination substrate includes pressing a first stamp having first pillars protruding therefrom against active components on the source substrate to adhere respective primary surfaces of the active components including electrical connections thereon to respective transfer surfaces of the first pillars. A second stamp having second pillars protruding therefrom is pressed against the active components on the first stamp to adhere respective secondary surfaces of the active components to respective transfer surfaces of the second pillars. The transfer surfaces of the second pillars have greater adhesive strength than the first pillars. The second stamp is pressed against a destination substrate to adhere the respective primary surfaces of the active components including the electrical connections thereon to a receiving surface of the destination substrate.12-13-2012
20110031615Semiconductor device - A semiconductor device having a structure that can reduce stress due to difference in coefficients of thermal expansion and prevent or suppress generation of cracks, and a semiconductor device manufacturing method, are provided. The semiconductor device includes a single crystal silicon substrate having a main face on which semiconductor elements are formed and a side face intersecting with the main face, and a sealing resin provided covering at least a portion of the side face. The side face covered by the sealing resin is equipped with a first face with a plane direction forming an angle of −5° to +5° to the plane direction of the main face.02-10-2011
20120211883ANCHORED CONDUCTIVE VIA AND METHOD FOR FORMING - A conductive via and a method of forming. The conductive via includes a portion located between a conductive contact structure and an overhang portion of a dielectric layer located above the conductive contact structure. In one embodiment, the overhang portion is formed by forming an undercutting layer over the conductive contact structure and then forming a dielectric layer over the conductive contact structure and the undercutting layer. An opening is formed in the dielectric layer and material of the undercutting layer is removed through the opening to create an overhang portion of the dielectric layer. Conductive material of the conductive via is then formed under the overhang portion and in the opening.08-23-2012
20120119361Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure - A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.05-17-2012
20120119360INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONNECTION STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.05-17-2012
20120119359BUMP STRUCTURE AND SEMICONDUCTOR PACKAGE HAVING THE BUMP STRUCTURE - Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.05-17-2012
20120119358SEMICONDIUCTOR PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a semiconductor package substrate including: a substrate for package having connection pads; and a solder resist layer formed on one surface or both surfaces of the substrate for package and having openings exposing the connection pads, wherein the solder resist layer includes a roughness layer formed thereon.05-17-2012
20120119355INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor to substrate to a second predetermined thickness, thereby exposing the bottom of the hole.05-17-2012
20120119354Protecting Flip-Chip Package using Pre-Applied Fillet - A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.05-17-2012
20120211884WAFER CHIP SCALE PACKAGE CONNECTION SCHEME - A method and structure for forming a semiconductor device, for example a device including a wafer chip scale package (WCSP), can include the formation of at least one conductive layer which contacts a bond pad. The at least one conductive layer can be patterned using a first mask, then a passivation layer can be formed over the patterned at least one conductive layer. The passivation layer can be patterned using a second mask to expose the at least one conductive layer, then a conductive layer such as a solder ball, conductive bump, metal-filled paste, or another conductor is formed on the at least one conductive layer. The method can result in a structure which is formed using a reduced number of mask steps.08-23-2012
20120211887Bump-on-Lead Flip Chip Interconnection - A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.08-23-2012
20120211886Method for Fabricating a Small Footprint Chip-Scale Package and a Device Made from the Method - A method for fabricating an integrated circuit chip-scale package and a device made from the method. One or more IC chips are mounted on a carrier and a stud bump defined on an IC pad. The stud-bumped IC is encapsulated to define a potted assembly layer which is thinned to expose the stud bump. Conductive first traces are defined and coupled to the stud bump to reroute the IC pads. A dielectric layer is provided and vias defined there through to expose the first traces. Electrically conductive second traces are disposed on the dielectric layer surface that are coupled to the first traces to reroute the IC pads to define a chip scale package.08-23-2012
20120211885SEMICONDUCTOR PACKAGE HAVING THROUGH SILICON VIA (TSV) INTERPOSER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package having a reduced size by including an interposer having through substrate vias (TSVs), the semiconductor package may comprise a lower semiconductor package which includes a lower base substrate, an interposer with TSVs on the lower base substrate, and a lower semiconductor chip on the interposer and electrically connected to the interposer. The semiconductor package may include an upper semiconductor package on the lower semiconductor package including an upper semiconductor chip and package connecting members on the interposer and electrically connect the upper semiconductor package to the interposer. An exterior molding member may be provided.08-23-2012
20120126402SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.05-24-2012
20120126403SEMICONDUCTOR DEVICE - Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.05-24-2012
20100289140SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor device, and a wiring board where the semiconductor device is mounted. The semiconductor device includes a semiconductor substrate, a piercing electrode configured to pierce the semiconductor substrate and electrically connect the wiring board and the semiconductor device, and a ring-shaped concave part provided so as to surround the piercing electrode, the ring-shaped concave part being configured to open to a wiring board side of the semiconductor substrate.11-18-2010
20100289139HARDWIRED SWITCH OF DIE STACK AND OPERATING METHOD OF HARDWIRED SWITCH - A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided.11-18-2010
20100289138SUBSTRATE STRUCTURE FOR FLIP-CHIP INTERCONNECT DEVICE - An integrated circuit (IC) and a method of forming the device are provided. The device includes a substrate and a metal trace formed on the substrate, the metal trace including a bond area and a routing area. The routing area includes a rough surface for promoting adhesion to underfill of a flip-chip die. The flip-chip die can include a bump bond connected to the bond area of the metal trace. The underfill is between the substrate and an active surface of the flip-chip die, the rough surface of the routing area adhering to the underfill in the absence of a photo resist on the routing area of the metal trace.11-18-2010
20120126396DIE DOWN DEVICE WITH THERMAL CONNECTOR - Methods and apparatuses for a die down device with a thermal connector are provided. In an embodiment, an integrated circuit (IC) device includes an IC die having opposing first and second surfaces, a thermal connector coupled to the first surface of the IC die, and a substrate. The second surface of the IC die is coupled to the substrate. The thermal connector is configured to be coupled to a circuit board.05-24-2012
20120126398INTEGRATED CIRCUIT PACKAGE AND PHYSICAL LAYER INTERFACE ARRANGEMENT - An integrated circuit (IC) package includes an IC chip, a package carrier, and a plurality of conductive bumps connecting the IC chip to the package carrier. The IC chip includes a substrate and an IC layered structure configured on an active surface of the substrate. The active surface has a core area and a signal area surrounding the core area. The IC layered structure includes a first physical layer interface. The first physical layer interface includes a plurality of first bump pads and a plurality of first inner pads electrically connected to the first bump pads, respectively. The first inner pads are arranged in multiple rows in the signal area.05-24-2012
20120126397SEMICONDUCTOR SUBSTRATE AND METHOD THEREOF - A semiconductor substrate includes a substrate having plurality of electrical contact pads formed thereon, a first insulating protective layer formed on the substrate that exposes the electrical contact pads, a plurality of metal layers formed on the exposed electrical contact pads, a second insulating protective layer formed on the first insulating protective layer that exposes a portion of the metal layers, and a plurality of solder bumps formed on the exposed metal layers having copper. Through the second insulating protective layer covering a portion of the metal layers, the solder bumps are prevented from falling off or crack when the semiconductor substrate is under a temperature test.05-24-2012
20120126395Semiconductor Device and Method of Forming Uniform Height Insulating Layer Over Interposer Frame as Standoff for Semiconductor Die - A semiconductor device has an interposer frame having a die attach area. A uniform height insulating layer is formed over the interposer frame at corners of the die attach area. The insulating layer can be formed as rectangular or circular pillars at the corners of the die attach area. The insulating layer can also be formed in a central region of the die attach area. A semiconductor die has a plurality of bumps formed over an active surface of the semiconductor die. The bumps can have a non-fusible portion and fusible portion. The semiconductor die is mounted over the insulating layer which provides a uniform standoff distance between the semiconductor die and interposer frame. The bumps of the semiconductor die are bonded to the interposer frame. An encapsulant is deposited over the semiconductor die and interposer frame and between the semiconductor die and interposer frame.05-24-2012
20120126394INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME - An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer.05-24-2012
20130015575Semiconductor Device with Solder Bump Formed on High Topography Plated Cu Pads - A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.01-17-2013
20130015574BUMP I/O CONTACT FOR SEMICONDUCTOR DEVICE - A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown.01-17-2013
20120126405SOLDER INTERCONNECT PADS WITH CURRENT SPREADING LAYERS - Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.05-24-2012
20120126404SEMICONDUCTOR DEVICE - In a semiconductor device comprising a semiconductor chip, electrodes formed on the major surface of the semiconductor chip, and a wiring board for mounting the semiconductor chip, for example, wirings for electrically connecting the wirings of the wiring board to the electrodes are provided. As the wirings, those relaxing stress generated between the semiconductor chip and the wiring board are used.05-24-2012
20120126400SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package may include a package substrate, a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may be arranged on the package substrate. The first semiconductor chip may have a plug electrically connected to the package substrate and at least one insulating hole arranged around the plug. The second semiconductor chip may be arranged on the first semiconductor chip. The second semiconductor chip may be electrically connected to the plug. Thus, the insulating hole and the insulating member may ensure an electrical isolation between the plug and the first semiconductor chip, and between the plugs.05-24-2012
20120126399THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH BUMP/BASE/FLANGE HEAT SPREADER AND BUILD-UP CIRCUITRY - A semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive and a build-up circuitry. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry includes a dielectric layer and conductive traces on the semiconductor device and the flange. The conductive traces provide signal routing for the semiconductor device.05-24-2012
20110001235STACKED SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR SAME - A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device. The linking interconnects extend from the first surface of the wiring board to the side surfaces and upper surface of the encapsulant, and moreover, electrically connect with wiring of the wiring board that projects from the encapsulant.01-06-2011
20110001234Semiconductor device and fabrication method thereof - Disclosed is a semiconductor device that comprises a first insulating film provided on a main face of a semiconductor substrate; a first pedestal provided at a first wiring layer on the first insulating layer; a second insulating film provided on the first wiring layer; and a second pedestal provided at a second wiring layer on the second insulating film, wherein, when the first and second pedestals are projected in a direction perpendicular to the main face onto a plane parallel to the main face, the second pedestal is larger than the first pedestal, and the whole of the first pedestal is disposed at an inside of the second pedestal.01-06-2011
20110001233SEMICONDUCTOR DEVICE MOUNTED STRUCTURE AND SEMICONDUCTOR DEVICE MOUNTING METHOD - In a semiconductor device mounted structure in which device electrodes of a semiconductor device and board electrodes of a board are connected to each other via bump electrodes, respectively, and in which a sealing-bonding use resin is placed between the semiconductor device and the board, a void portion is placed at a position corresponding to an edge portion of the semiconductor device in the sealing-bonding use resin. Thus, stress loads generated at corner portions of the semiconductor device due to board flexures for differences in thermal expansion and thermal contraction among the individual members caused by heating and cooling steps in mounting process of the semiconductor device, as well as for mechanical loads after the mounting process, can be absorbed by the void portion and thereby reduced, so that breakdown of the semiconductor device mounted structure is prevented.01-06-2011
20110001232Flip-Chip Module and Method for the Production Thereof - The invention relates to a flip-chip module with a semiconductor chip with contact posts, wherein the contact posts are connected electrically and mechanically to a substrate. Provided between the substrate and the semiconductor chip is a spacer, which is coupled mechanically to the substrate and/or the semiconductor chip. By this means, thermal stresses in the flip-chip module are absorbed by the spacer and kept away from the semiconductor chip.01-06-2011
20120161314TEMPLATE WAFER AND PROCESS FOR SMALL PITCH FLIP-CHIP INTERCONNECT HYBRIDIZATION - A process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.06-28-2012
20120161313SEMICONDUCTOR DEVICE, AND INSPECTION METHOD THEREOF - In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.06-28-2012
20120161312NON-SOLDER METAL BUMPS TO REDUCE PACKAGE HEIGHT - Electronic assemblies and their manufacture are described. One assembly includes a substrate and a die on a first side of the substrate. A plurality of non-solder metal bumps are positioned on a second side of the substrate. The assembly also includes a board to which the non-solder metal bumps are coupled. The assembly also includes solder positioned between the board and the substrate, wherein the board is electrically coupled to the substrate through the solder and the bumps. Other embodiments are described and claimed.06-28-2012
20100207271SEMICONDUCTOR DEVICE - In order to provide a wafer level semiconductor device, a protection film and a stress buffer layer are formed on a metal wiring formed on a semiconductor element, a via-hole that passes through the protection film and the stress buffer layer is formed so as to expose the metal wiring, and a bump electrode is formed on a conductive layer that fills the via-hole.08-19-2010
20120211880Flip Chip Interconnection Having Narrow Interconnection Sites on the Substrate - A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.08-23-2012
20120211882Semiconductor Device and Method of Confining Conductive Bump Material with Solder Mask Patch - A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate.08-23-2012
20120211881Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process - A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer.08-23-2012
20120133043Solder Joint Flip Chip Interconnection - A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.05-31-2012
20120133042MOUNTING STRUCTURE OF CHIP AND MODULE USING THE SAME - A mounting structure of chip comprises a substrate having a base, a chip on the upper surface of the base, and adhesive agents which bonds the base and the first chip. The adhesive agent is applied to the upper surface of the base. The chip has a rectangular shape to have a width and a length, and is bonded at its lower surface to the base. The adhesive agents comprises the first adhesive agent, the second adhesive agent, and the third adhesive agent which are disposed on the three spots of the upper surface of the base, respectively. The three spots on the base are located on vertexes of a triangle. The first chip is bonded to the base by only the first adhesive agent, the second adhesive agent, and the third adhesive agent.05-31-2012
20120133041Semiconductor Devices Having Electrodes and Methods of Fabricating the Same - Some embodiments provide a semiconductor device including a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion that supports the protruding portion. Methods of fabricating the same are also provided.05-31-2012
20090091024Stable Gold Bump Solder Connections - A metallic interconnect structure (04-09-2009
20120313238SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a substrate containing a dielectric element having first and second opposed surfaces. The dielectric element may include a first dielectric layer adjacent the first surface, and a second dielectric layer disposed between the first dielectric layer and the second surface. A Young's modulus of the first dielectric layer may be at least 50% greater than the Young's modulus of the second dielectric layer, which is less than two gigapascal (GPa). A conductive structure may extend through the first and second dielectric layers and electrically connect substrate contacts at the first surface with terminals at the second surface. The substrate contacts may be joined with contacts of a microelectronic element through conductive masses, and a rigid underfill may be between the microelectronic element and the first surface. The terminals may be usable to bond the microelectronic assembly to contacts of a component external to the microelectronic assembly.12-13-2012
20090057894Structure of Gold Bumps and Gold Conductors on one IC Die and Methods of Manufacturing the Structures - A method for fabricating multiple metal layers includes the following steps. An electronic component is provided with multiple contact points. A first metal layer is deposited over said electronic component. A first mask layer is deposited over said first metal layer. A second metal layer is deposited over said first metal layer exposed by an opening in said first mask layer. Said first mask layer is removed. A second mask layer is deposited over said second metal layer. A third metal layer is deposited over said second metal layer exposed by an opening in said second mask layer. Said second mask layer is removed. Said first metal layer not covered by said second metal layer is removed.03-05-2009
20090057895POST PASSIVATION STRUCTURE FOR A SEMICONDUCTOR DEVICE AND PACKAGING PROCESS FOR SAME - A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.03-05-2009
20090057893Semiconductor apparatus - In order to solve a problem of occurrence of delamination of interlayer film due to occurrence of a crack in an LSI wiring layer in a UBM lower layer immediately under a solder bump in an outer periphery of an LSI chip, a semiconductor apparatus of the present invention includes a stress boundary between compressive stress and tensile stress in an LSI wiring layer of a bump lower layer and in order to alleviate the stress present in the bump lower layer tensile stress material is arranged on a compressive stress side or compressive stress material is arranged on a tensile stress side with a stress boundary of the LSI wiring layer as a boundary.03-05-2009
20090057892ELECTRODE STRUCTURE IN SEMICONDUCTOR DEVICE AND RELATED TECHNOLOGY - A first insulation film having a first opening is provided on an electrode pad of a semiconductor chip. A second insulation film having a second opening is provided on the first insulation film. A ground metallic layer which is to be in contact with the electrode pad via the first opening is provided on the first insulation film. A bump which is to be mechanically and electrically connected to the ground metallic layer is provided. Further, the above placement is made in a way that the ground metallic layer is provided in the second opening, and the ground metallic layer is provided on an inner side than an outer periphery of the electrode pad, covering the first opening.03-05-2009
20090057891SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a supporting base whereupon an electrode terminal is placed; an intermediate member mounted on said supporting base; a semiconductor element, a portion thereof being supported with said intermediate member, and placed on said supporting base; and a convex-shaped member which corresponds to the electrode terminal of said semiconductor element and placed on said supporting base or said intermediate member; wherein the electrode terminal of said semiconductor element and the electrode terminal of said supporting base are connected with a bonding wire.03-05-2009
20090057890SEMICONDUCTOR DEVICE - In this semiconductor device, connection parts between wafers are electrically insulated from each other, and a junction face shape of second electrical signal connection parts is larger than the shape of a positioning margin face that is formed by an outer shape when the periphery of a minimum junction face, which has half the area of a junction area of the first electrical signal connection part, is enclosed by a same width dimension as a positioning margin dimension between the first wafer and the second wafer.03-05-2009
20090057889Semiconductor Device Having Wafer Level Chip Scale Packaging Substrate Decoupling - One aspect of the invention provides a semiconductor device that includes a microchip having an outermost surface. First and second bond pads are located on the microchip and near the outermost surface. A first UBM contact is located on the outermost surface and between the first and second bond pads. The first UBM contact is offset from the first bond pad. A second UBM contact is located on the outermost surface and between the first and second bond pads. The second UBM contact is offset from the second bond pad, and a capacitor supported by the microchip is located between the first and second UBM contacts.03-05-2009
20090057887WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS - A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads.03-05-2009
20120168934FLIP CHIP DEVICE HAVING SIMPLIFIED ROUTING - The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.07-05-2012
20120168941STACKABLE ELECTRONIC PACKAGE AND METHOD OF MAKING SAME - An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to the first side of the first flex layer and a first encapsulant encapsulating the first component, the first encapsulant having a portion thereof removed to form a first plurality of cavities in the first encapsulant and to expose the first plurality of feed-thru pads by way of the first plurality of cavities.07-05-2012
20120168940APPARATUS AND METHOD OF APPLYING A FILM TO A SEMICONDUCTOR WAFER AND METHOD OF PROCESSING A SEMICONDUCTOR WAFER - Implementations and techniques for applying a film to a semiconductor wafer and for processing a semiconductor wafer are generally disclosed.07-05-2012
20120168938PLASMA TREATMENT ON SEMICONDUCTOR WAFERS - A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice.07-05-2012
20120168937FLIP CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A flip chip package and a method of manufacturing the same are provided. The flip chip package include: a package substrate, a semiconductor chip and conductive hollow bumps. The semiconductor chip may be arranged over an upper surface of the package substrate. The conductive hollow bumps may be interposed between the semiconductor chip and the package substrate to electrically connect the semiconductor chip with the package substrate. Thus, a wide gap may be formed between the semiconductor chip and the package substrate by the thick conductive hollow bumps. As a result, a sufficient amount of the molding member may be supplied to each of the conductive hollow bumps to surround each of the conductive hollow bumps.07-05-2012
20120168935INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME - An integrated circuit device includes a bottom wafer having a first annular dielectric block, at least one stacking wafer having a second annular dielectric block positioned on the bottom wafer, and a conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner. In one embodiment of the present invention, the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, no bump pad is positioned between the bottom wafer and the stacking wafer, and the conductive via is positioned within the first annular dielectric block and the second annular dielectric block.07-05-2012
20120168933WAFER LEVEL MOLDING STRUCTURE - A wafer level molding structure and a manufacturing method thereof are provided. A molding structure includes a first chip and a second chip and an adhesive layer there between. The first chip includes a first back side, a first front side and a plurality of lateral sides, in which a plurality of first front side bumps are disposed on the first front side. The second chip includes a second back side and a second front side, and a plurality of second back side bumps and second front side bumps are respectively disposed on the second back side and the second front side. A plurality of through-hole vias is disposed in the second chip, and electrically connected the second back side bumps to the second front side bumps. Adhesive materials covering the lateral sides of the first chip, and electrically connect the second back side bumps with the first front side bumps. The adhesive materials include a plurality of conductive particles and/or a plurality of non-conductive particles.07-05-2012
20120168936MULTI-CHIP STACK PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A multi-chip stack package structure includes: an inner-layer heat sink having a first surface and a second surface opposing one another and having a plurality of conductive vias penetrating the first surface and the second surface; a first chip disposed on the first surface of the inner-layer heat sink; and a second chip disposed on the second surface of the inner-layer heat sink. Thereby, a heat-dissipating path is provided within inner-layers of the multi-chip stack package structure, and the rigidity of the overall structure is enhanced.07-05-2012
20100052163SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME AND METHOD OF REPAIRING SAME - A semiconductor device in which opposing electrodes of a semiconductor component and of a wiring board are arranged to conduct via bumps, comprises: a first conductive resin bump provided on the electrode of the semiconductor component; and a second conductive resin bump provided on the electrode of the wiring board. The difference between a glass transition temperature of the first conductive resin bump and a glass transition temperature of the second conductive resin bump is equal to or greater than 40° C.03-04-2010
20120175771Semiconductor Device and Method of Forming No-Flow Underfill Material Around Vertical Interconnect Structure - A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.07-12-2012
20120175770Semiconductor Device and Method of Forming Conductive Pillars in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices - A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar.07-12-2012
20120175769Semiconductor Device and Method of Dissipating Heat From Thin Package-on-Package Mounted to Substrate - A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second die is less than or equal to a height of the bumps. A second substrate has a thermal conduction channel. A surface of the second semiconductor die opposite the first die is mounted to the thermal conductive channel of the second substrate. A thermal interface layer is formed over the surface of the second die. The bumps are electrically connected to contact pads on the second substrate. A conductive plane is formed over a surface of the second substrate.07-12-2012
20120175768SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead.07-12-2012
20120175767SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS AND METHOD FOR MAKING THE SAME - The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.07-12-2012
20100019383METHOD OF FORMING WIRING ON A PLURALITY OF SEMICONDUCTOR DEVICES FROM A SINGLE METAL PLATE, AND A SEMICONDUCTOR CONSTRUCTION ASSEMBLY FORMED BY THE METHOD - In this manufacturing method of a semiconductor device, a metal plate having a plurality of projection electrodes in each of a plurality of semiconductor device formation areas is prepared. Next, the projection electrodes of each of the semiconductor formation areas are aligned corresponding to external connection electrodes of each semiconductor construction, and each semiconductor construction is separately arranged on the projection electrodes in the semiconductor device formation areas. Next, an insulating layer formation sheet is arranged on the metal plate, and the metal plate and the insulating layer formation sheet are joined by heat pressing. Then, the metal plate is patterned and a plurality of upper layer wirings that connect to the projection electrodes is formed.01-28-2010
20100270672Semiconductor device - A semiconductor device includes a conductive section formed on a semiconductor chip; and a bump electrode formed directly or indirectly on the conductive section. The conductive section includes a slit section having a thickness thinner than another portion of the conductive section. The bump electrode has a recessed section corresponds to the slit section above the slit section.10-28-2010
20120217635Packaging Structure and Method - A method of making a semiconductor device includes providing a substrate and forming a conductive layer on the substrate. The conductive layer includes a first metal. A semiconductor die is provided. A bump is formed on the semiconductor die. The bump includes a second metal. The semiconductor die is positioned proximate to the substrate to contact the bump to the conductive layer and form a bonding interface. The bump and the conductive layer are metallurgically reacted at a melting point of the first metal to dissolve a portion of the second metal from an end of the bump. The bonding interface is heated to the melting point of the first metal for a time sufficient to melt a portion of the first metal from the conductive layer. A width of the conductive layer is no greater than a width of the bump.08-30-2012
20120074565SEMICONDUCTOR DEVICE PROVIDED WITH REAR PROTECTIVE FILM ON OTHER SIDE OF SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - An opening is formed in a part of a rear protective film corresponding to the center of a dicing street by laser processing which applies a laser beam. The rear protective film is formed on the lower surface of a semiconductor wafer, and made of a resin. By using a resin cutting blade, parts of a sealing film and the upper side of the semiconductor wafer corresponding to the dicing street and both its sides are then cut to form a trench. By using a silicon cutting blade, parts of the semiconductor wafer and the rear protective film corresponding to the dicing street are then cut. In this case, cutting of the rear protective film with the silicon cutting blade is reduced by the opening.03-29-2012
20120074564SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device comprises a semiconductor substrate having a connection pad, an external connection electrode provided on the semiconductor substrate to be connected to the connection pad, and a sealing film provided to cover the external connection electrode, wherein an opening is provided in the sealing film to expose a center of the upper surface of the external connection electrode, and the sealing film is provided to cover an outer peripheral part of the upper surface of the external connection electrode.03-29-2012
20120074562Three-Dimensional Integrated Circuit Structure with Low-K Materials - A device includes an interposer free from active devices therein. The interposer includes a substrate; a through-substrate via (TSV) penetrating through the substrate; and a low-k dielectric layer over the substrate.03-29-2012
20090065930Package Substrate Including Surface Mount Component Mounted on a Peripheral Surface thereof and Microelectronic Package Including Same - A microelectronic combination and a method of making the combination. The combination includes a package substrate including a substrate body having a peripheral surface and contacts disposed at the peripheral surface; and a surface mount component electrically and mechanically bonded to the contacts.03-12-2009
20120223427FLIP CHIP PACKAGE - A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.09-06-2012
20120256310SEMICONDUCTOR DEVICE - A semiconductor device includes a multi-level wiring structure that includes a first wring layer, a plurality of first patterns, and a first mark. The first wring layer is disposed at a first wiring level of the multi-level wiring structure. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level.10-11-2012
20120256312SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor chip, an electrode pad formed on the semiconductor chip, an underlying barrier metal formed on the electrode pad, a solder bump formed on the underlying barrier metal, and an underfill material surrounding the underlying barrier metal and the solder bump. A junction interface of the solder bump with the underlying barrier metal corresponds to an upper surface of the underlying barrier metal, and a portion of the underfill material bonded to a side surface of the solder bump and an end surface of the underlying barrier metal forms a right angle or an obtuse angle.10-11-2012
20120256311SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A bump electrode, a dummy bump, and a heat-resistant polymer film, whose upper-surface heights are uniformed, are formed on each of a first silicon substrate and a second silicon substrate, and then, the first silicon substrate and the second silicon substrate are bonded to each other so that the bump electrodes formed on the respective substrates are electrically connected to each other. At this time, the dummy bump is arranged so as to be bonded to the heat-resistant polymer film on the silicon substrate opposed thereto, so that a semiconductor device having both of good electrical connection between the bump electrodes and bump protection performance obtained by a polymer film with high heat resistance and without voids can be achieved.10-11-2012
20120273945INTEGRATED CIRCUIT DEVICE INCLUDING A COPPER PILLAR CAPPED BY BARRIER LAYER - This description relates to an integrated circuit device including a semiconductor substrate, an under-bump-metallurgy (UBM) layer overlying the semiconductor substrate and a copper-containing pillar on the UBM layer. The copper-containing pillar includes a top surface, an upper sidewall surface adjacent to the top surface, and a lower sidewall surface adjacent to the UBM layer. The integrated circuit device further includes a barrier layer on the upper sidewall surface of the copper-containing pillar, wherein the barrier layer exposes the lower sidewall surface. The copper-containing pillar has a first height and the upper sidewall surface has a second height. The second height is greater than about 30 percent of the first height.11-01-2012
20100193946SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREOF - A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.08-05-2010
20100193945REINFORCED STRUCTURE FOR A STACK OF LAYERS IN A SEMICONDUCTOR COMPONENT - The present application relates to a reinforcing structure (08-05-2010
20100193944Semiconductor Flip-Chip System Having Oblong Connectors and Reduced Trace Pitches - A semiconductor chip (08-05-2010
20100193943Semiconductor Device Having a Diamond Substrate Heat Spreader - In accordance with one or more embodiments, a semiconductor device comprises a semiconductor die having a heat region disposed on at least one portion of the semiconductor die, and a diamond substrate disposed proximate to the semiconductor die, wherein the diamond substrate is capable of dissipating heat from the diamond substrate via at least one or more bumps coupling the diamond substrate to the heat region of the semiconductor die.08-05-2010
20090032945SOLDER BUMP ON A SEMICONDUCTOR SUBSTRATE - A solder bump on a semiconductor substrate is provided. The solder bump has a semiconductor substrate with a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further has a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.02-05-2009
20090020869INTERCONNECT JOINT - An interconnect joint comprises a substrate (01-22-2009
20120261813REINFORCED VIA FARM INTERCONNECT STRUCTURE, A METHOD OF FORMING A REINFORCED VIA FARM INTERCONNECT STRUCTURE AND A METHOD OF REDESIGNING AN INTEGRATED CIRCUIT CHIP TO INCLUDE SUCH A REINFORCED VIA FARM INTERCONNECT STRUCTURE - Disclosed is reinforced via farm interconnect structure for an integrated circuit chip that minimizes delamination caused by tensile stresses applied to the chip through lead-free C4 connections during thermal cycling. The reinforced via farm interconnect structure includes a plurality of vias electrically connecting metal wires within different wiring levels and, for reinforcement, further incorporates dielectric columns into the lower metal wire so that the areas around the metal-to-metal interface between the vias and the lower metal wire contain a relatively strong dielectric-to-dielectric interface. The reinforced via farm interconnect structure can be located in an area of the chip at risk for delamination and, for added strength, can have a reduced via density relative to conventional via farm interconnect structures located elsewhere on the chip. Also disclosed are a method of forming the reinforced via farm interconnect structure and a method of redesigning an integrated circuit chip to include reinforced via farm interconnect structure(s).10-18-2012
20120261814Packaging an Electronic Device - An electronic device comprises a plurality of integrated circuit dies mounted on different areas of a carrier. The carrier is folded into a plurality of layers, each layer comprising one of the different areas of the carrier and one of the integrated circuit dies, such that the plurality of integrated circuit dies form a stack. Adjacent surfaces of neighbouring layers are fixed together, for example by an adhesive layer, and the folded carrier and the integrated circuit dies are embedded in a moulded material.10-18-2012
20120261815SEALED SURFACE ACOUSTIC WAVE ELEMENT PACKAGE - An electronic component includes: a semiconductor substrate having a first surface and a second surface opposing to the first surface; a trans-substrate conductive plug that penetrates the semiconductor substrate from the first surface to the second surface; an electronic element provided in the vicinity of the first surface of the semiconductor; and a sealing member that seals the electronic element between the sealing member and the first surface, wherein the electronic element is electrically connected to the trans-substrate conductive plug.10-18-2012
20120261818Semiconductor Device and Method of Embedding Bumps Formed on Semiconductor Die into Penetrable Adhesive Layer to Reduce Die Shifting During Encapsulation - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.10-18-2012
20120261817Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution - A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.10-18-2012
20120261816DEVICE PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A device package substrate includes: a substrate having a cavity formed on a top surface thereof, the cavity having a chip mounting region; a first interconnection layer formed to extend to the inside of the cavity; a second interconnection layer formed to be spaced apart from the first interconnection layer; a chip positioned in the chip mounting region so as to be connected to the first and second interconnection layers; an insulating layer formed to cover the first and second interconnection layers and the chip and having a contact hole exposing a part of the second interconnection layer; and a bump pad formed in the contact hole so as to be connected to external elements.10-18-2012
20120228765SOLDER BUMP INTERCONNECT - A semiconductor package includes a device pad on a substrate. A first polymer layer overlies the substrate, and the first polymer layer has an opening to expose the device pad. In one embodiment, a redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the first polymer layer and conductively coupled to the device pad. A second polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the second polymer layer. In one embodiment, a shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0.5:1 up to 0.95:1.09-13-2012
20120228766Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch - A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.09-13-2012
20120228764PACKAGE STRUCTURE, FABRICATING METHOD THEREOF, AND PACKAGE-ON-PACKAGE DEVICE THEREBY - A package structure, a method of fabricating the package structure, and a package-on-package device are provided, where the package structure includes a metal sheet having perforations and a semiconductor chip including an active surface having electrode pads thereon, where the semiconductor chip is combined with the metal sheet via an inactive surface thereof. Also, a protective buffer layer is formed on the active surface to cover the conductive bumps, and the perforations are arranged around a periphery of the inactive surface of the semiconductor chip. Further, an encapsulant is formed on the metal sheet and in the perforations, for encapsulating the semiconductor chip and exposing the protective buffer layer; and a circuit fan-out layer is formed on the encapsulant and the protective buffer layer and having conductive vias penetrating the protective buffer layer and electrically connecting to the conductive bumps.09-13-2012
20120228763SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a pillar formed in a highly reliable manner and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a semiconductor chip including an internal circuit area and an I/O area disposed outside the internal circuit area, a package substrate coupled in a flip-chip manner to the semiconductor chip, and an electrically conductive pillar disposed between the semiconductor chip and the package substrate such that the electrically conductive pillar is located over two or more wirings in an uppermost wiring layer of the semiconductor chip and such that the two or more wirings are coupled together via the electrically conductive pillar.09-13-2012
20120228762SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.09-13-2012
20120228761SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first substrate and a second substrate being bonded to each other, a posterior interconnect layer interposed between the first and second substrates, a weld pad disposed in the posterior interconnect layer, and a first annular opening disposed in the first substrate. The device further includes a dielectric layer formed in the first opening, a via surrounded by the first annular opening, and an interconnect layer disposed in the via. The device also includes a conductive bump disposed on the interconnect layer and electrically connected to the weld pad through the interconnect layer.09-13-2012
20120228760SYSTEMS INCLUDING AN I/O STACK AND METHODS FOR FABRICATING SUCH SYSTEMS - Systems including an input/output (I/O) stack and methods for fabricating such systems are described. In one implementation, the methods include stacking an I/O die including I/O elements and excluding a logic element. Also in one implementation, the methods further include stacking an integrated circuit die with respect to the I/O die. The integrated circuit includes logic elements and excludes an I/O element. The separation of the I/O die from the integrated circuit die provides various benefits, such as independent development of each of the dies and more space for the I/O elements on an I/O substrate of the I/O die compared to that in a conventional die. The increase in space allows new process generation of the integrated circuit die in which an increasing number of logic elements are fitted within the same surface area of a substrate of the integrated circuit die.09-13-2012
20120228759SEMICONDUCTOR PACKAGE HAVING INTERCONNECTION OF DUAL PARALLEL WIRES - A semiconductor package having dual parallel wires is disclosed. A chip is attached on a substrate where the chip and the substrate are electrically connected by a bonding wire. The bonding wire consists of a first metal wire, a second metal wire, and an insulating body where the insulating body encapsulates the first and the second metal wires to make both metal wires parallel to each other. The insulating body forms a constant gap between the first and the second metal wires so that both metal wires do not contact to each other. Therefore, the electrical performance of the package can greatly be enhanced with the same productivity.09-13-2012
20110121453SEMICONDUCTOR SYSTEM-IN-PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor devices that contain a system in package and methods for making such packages are described. The semiconductor device with a system in package (SIP) contains a first IC die, passive components, and discrete devices that are contained in a lower level of the package. The SIP also contains a second IC die that is vertically separated from the first IC die by an array of metal interposers, thereby isolating the components of the first IC die from the components of the second IC die. Such a configuration provides more functionality within a single semiconductor package while also reducing or eliminating local heating in the package. Other embodiments are also described.05-26-2011
201003274403-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD - A die-on-die assembly has a first die (12-30-2010
20100327439SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.12-30-2010
20100327438NEAR CHIP SCALE SEMICONDUCTOR PACKAGES - Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.12-30-2010
20100327437WIRING BOARD AND SEMICONDUCTOR DEVICE USING THE WIRING BOARD - Provided is a wiring board wherein a circuit is not short-circuited when a IC chip is mounted on the wiring board. A wiring board (12-30-2010
20100327435ELECTRONIC COMPONENT AND MANUFACTURE METHOD THEREOF - An electronic component includes a package substrate, a plurality of conductive pads, an insulating material and a semiconductor device. The plurality of conductive pads is disposed on the package substrate. The insulating material is disposed between the plurality of conductive pads. The insulating material includes a top surface located on an identical plane to an upper surface of the plurality of conductive pads. The semiconductor device includes a conductive bump aligned on a corresponding conductive pad of the plurality of conductive pads.12-30-2010
20110079895BUMP STRUCTURE, CHIP PACKAGE STRUCTURE INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME - A bump structure includes a first substrate, a plurality of first bond pads, a plurality of dielectric bumps, a plurality of under bump metal layers, and a plurality of metal layers. The plurality of first bond pads are spaced apart on the first substrate. The plurality of dielectric bumps disposed corresponding to the first bond pads electrically isolate the first bond pads from each other. Each under bump metal layer is formed between the respective first bond pad and the dielectric bump, extending through a side surface of the respective dielectric bump, and correspondingly forming an extension portion between two adjacent dielectric bumps, wherein each extension portion has a length along the extending direction thereof shorter than the pitch between two adjacent dielectric bumps. Each metal layer is formed on the side surface of the respective dielectric bump and the respective extension portion.04-07-2011
20110079897INTEGRATED CIRCUIT CHIP AND FLIP CHIP PACKAGE HAVING THE INTEGRATED CIRCUIT CHIP - In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.04-07-2011
20120261812SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION - Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes providing a semiconductor chip that has a conductor pad and a passivation structure over the conductor pad. A first metallic layer is applied on the passivation structure and in electrical contact with the conductor pad. The first metallic layer covers a first portion but not a second portion of the passivation structure. A second metallic layer is applied to the first metallic layer. A polymer layer is applied to the second metallic layer. The polymer layer includes a first opening in alignment with the first metallic layer that exposes a portion of the second layer. A conducting solder barrier layer is applied to the exposed portion of the second metallic layer.10-18-2012
20120299180BONDING PAD STRUCTURE AND INTEGRATED CIRCUIT COMPRISING A PLURALITY OF BONDING PAD STRUCTURES - A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.11-29-2012
20120299179THROUGH MOLD VIA POLYMER BLOCK PACKAGE - Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be farmed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed.11-29-2012
20120299178SEMICONDUCTOR DEVICE - A semiconductor device includes: a main body chip; a circuit pattern on a front surface of the main body chip and including a first pad; a cap chip including a first recess in a front surface of the cap chip and a second recess in a back surface of the cap chip, the cap chip being joined to the main body chip with the first recess facing the circuit pattern; a second pad on a bottom surface of the first recess of the cap chip; a first metallic member inlaid in the second recess of the cap chip; a first through electrode electrically connecting the second pad to the first metallic member through the cap chip; and a bump electrically connecting the first pad to the second pad.11-29-2012
20120299177SEMICONDUCTOR COMPONENT AND METHOD OF FABRICATING THE SAME - A semiconductor component structure is provided, which includes a body formed with openings, an insulating layer formed on surfaces of the body and the openings, conductive bumps formed in the openings, and a re-distributed circuit formed by conductive traces electrically connecting the conductive bumps, wherein the conductive traces are formed on a portion of the insulating layer on the body. As the conductive traces and the conductive bumps are formed on and in the body prior to the formation of the re-distributed circuit. The process for fabricating the semiconductor component structure is simplified and the reliability of the semiconductor component structure is enhanced. A method for fabricating the semiconductor component is also provided.11-29-2012
20120299176Semiconductor Device and Method of Forming Bump Structure with Multi-Layer UBM Around Bump Formation Area - A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.11-29-2012
20110001236SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.01-06-2011
20110037174METHOD OF MANUFACTURING SEMICONDUCTOR COMPONENT, AND SEMICONDUCTOR COMPONENT - A method of manufacturing a semiconductor component of the present invention has: obtaining a semiconductor wafer having stud electrodes formed on a functional surface thereof, and a circuit board having solder bumps on one surface and having electrode pads on the other surface thereof; bonding the semiconductor wafer and the circuit board, while providing a resin layer having a flux activity between the semiconductor wafer and the circuit board, and so as to bring the stud electrodes into contact with the solder bumps, while penetrating the resin layer having a flux activity, to thereby obtain a bonded structure; applying a solder material onto the electrode pads of the bonded structure; and dicing the bonded structure to obtain a plurality of semiconductor components.02-17-2011
20110037173SEMICONDUCTOR DEVICE - Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.02-17-2011
20110037172Ultra Thin Bumped Wafer With Under-Film - A semiconductor device includes a wafer and a dicing saw tape that is laminated to a back surface of the wafer. An active surface of the wafer is opposite the back surface of the wafer. The semiconductor device further includes a lamination tape disposed in contact with the wafer. The lamination tape includes an under-film layer contacting the active surface of the wafer. The lamination tape further includes an adhesive layer contacting the under-film layer.02-17-2011
20120267776CHIP STACK PACKAGE - A chip stack package is provided. The chip stack package includes an n number of chips stacked on each other and an n number of interconnection strands connecting the chips. The interconnection strands are spirally rotated and insulated from each other. In one embodiment, the chips are substantially structurally identical. In another embodiment, each of the interconnection strands is electrically coupled to a chip selection signal.10-25-2012
20120267779SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.10-25-2012
20120267778CIRCUIT BOARD, SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING CIRCUIT BOARD, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A circuit board includes: an electrode portion which has a copper layer, a copper oxide layer formed thereon, and a removal portion formed by partially removing the copper oxide layer so as to partially expose the copper layer from the copper oxide layer; and a solder bump for flip chip mounting formed on the copper layer exposed by the removal portion.10-25-2012
20120267777MULTI-CHIP MODULE WITH STACKED FACE-DOWN CONNECTED DIES - A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate.10-25-2012
20130181343MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first active surface. The second semiconductor chip has a second active surface facing the first active surface. The second active surface is electrically connected with the first active surfaceand the first active surface of the first semiconductor chip and the second active surface of the second semiconductor chip are bonded to each other without an adhesive.07-18-2013
20130181345SEMICONDUCTOR DEVICE HAVING PENETRATION ELECTRODE PENETRATING THROUGH SEMICONDUCTOR SUBSTRATE - Disclosed herein is a device that includes: a semiconductor substrate having a first surface on which a plurality of circuit elements are formed and a second surface opposite to the first surface; an insulating layer covering the second surface of the semiconductor substrate; and a penetration electrode having a body section that penetrates through the semiconductor substrate and a protruding section that is connected to one end of the body section and protrudes from the second surface of the semiconductor substrate. The second surface of the semiconductor substrate is covered with the protruding section of the penetration electrode without intervention of the insulating layer.07-18-2013
20120319273Flip Chip Interconnect Solder Mask - A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.12-20-2012
20120267780CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.10-25-2012
20120267781MECHANISMS FOR FORMING COPPER PILLAR BUMPS USING PATTERNED ANODES - This disclosure relates to a bump structure on a substrate including a copper layer, wherein the copper layer fills an opening created in a dielectric layer and a polymer layer. The bump structure further includes an under-bump-metallurgy (UBM) layer lines the opening and the copper layer is deposited over the UBM layer. The bump structure further includes a surface of the copper layer facing away from the substrate is curved. This disclosure also relates to two bump structures with different heights on a substrate where a thickness of the first bump structure is different than a thickness of the second bump structure. This disclosure also relates to a semiconductor device including a bump structure.10-25-2012
20120319272Flip Chip Interconnect Solder Mask - A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.12-20-2012
20120319270Wafer Level Chip Scale Package with Reduced Stress on Solder Balls - A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.12-20-2012
20120319271BUMP STRUCTURE AND PROCESS OF MANUFACTURING THE SAME - A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other.12-20-2012
20110215467METAL POST CHIP CONNECTING DEVICE AND METHOD FREE TO USE SOLDERING MATERIAL - A metal post chip connecting device without soldering materials is revealed, primarily comprising a chip and a substrate. A plurality of metal pillars are disposed on and extruded from a surface of the chip where each metal pillar has an end surface and two corresponding parallel sidewalls. The substrate has an upper surface and a plurality of bonding pads disposed on the upper surface where each bonding pad has a concaved bottom surface and two corresponding concaved sidewalls. The chip is bonded onto the upper surface of the substrate through heat, pressure, and ultrasonic power so that the end surfaces of the metal pillars self-solder to the concaved bottom surfaces and two parallel sidewalls of the metal pillars partially self-solder to two concaved sidewalls to form U-shape cross-sections of metal bonding between the metal pillars and the bonding pads. Therefore, there is no need for the conventional solder paste as chip connection to increase conductivity of the soldering points, especially, to save the soldering cost for MPS-C2 products and to greatly enhance the bonding strength of the soldering points. The manufacturing method of the above described metal post chip connecting device is also revealed.09-08-2011
20120273936Micro Bump And Method For Forming The Same - A method for forming a micro bump includes forming a first nano-particle layer on a substrate and forming a second nano-particle layer on the first nano-particle layer. The first and second nano-particle layers include a plurality of first nano particles and a plurality of second nano particles, respectively. The method further includes irradiating a laser beam onto the second nano-particle layer, where the laser beam penetrates through the second nano-particle layer and is at least partially absorbed by at least some of the first nano particles to generate heat. The first nano particles and the second nano particles have different absorption rates with respect to the laser beam.11-01-2012
20120319269Enhanced Bump Pitch Scaling - An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.12-20-2012
20110227218SILICON SUBSTRATE FOR PACKAGE - In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity.09-22-2011
20110227217SEMICONDUCTOR PACKAGE WITH STACKED CHIPS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes at least two semiconductor chips stacked to have step surfaces and possessing bonding pads disposed over the step surfaces. Conductive patterns are disposed over the step surfaces and electrically connect the bonding pads of the semiconductor chips with one another. An insulation member is formed over side and upper surfaces of the stacked semiconductor chips excluding the step surfaces and the conductive patterns.09-22-2011
20110227216Under-Bump Metallization Structure for Semiconductor Devices - An under-bump metallization (UBM) structure for a semiconductor device is provided. A passivation layer is formed over a contact pad such that at least a portion of the contact pad is exposed. A protective layer, such as a polyimide layer, may be formed over the passivation layer. The UBM structure, such as a conductive pillar, is formed over the underlying contact pad such that the underlying contact pad extends laterally past the UBM structure by a distance large enough to prevent or reduce cracking of the passivation layer and or protective layer.09-22-2011
20120126401STACKABLE SEMICONDUCTOR ASSEMBLY WITH BUMP/BASE/FLANGE HEAT SPREADER AND ELECTROMAGNETIC SHIELDING - A stackable semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive, a terminal, a plated through-hole and build-up circuitry. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry provides signal routing for the semiconductor device. The plated through-hole provides signal routing between the build-up circuitry and the terminal. The heat spreader provides heat dissipation for the semiconductor device.05-24-2012
20100237497SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.09-23-2010
20120080788SEMICONDUCTOR DEVICE HAVING MULTILAYER WIRING STRUCTURE AND MANUFACTURING METHOD OF THE SAME - Disclosed is a semiconductor device 04-05-2012
20120080787Electronic Package and Method of Making an Electronic Package - An electrical package and a method of forming the electrical package, where the electrical package has a substrate with a frontside, an intergrated circuit coupled to the frontside of the substrate, and at least one non-collapsible metal connector created on the frontside of the first substrate.04-05-2012
20120080786ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME - An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a second surface on the opposite side of the first surface, multiple first bumps formed on a first conductive pattern positioned on the first surface of the wiring board among the conductive patterns of the wiring board, a semiconductor element mounted on the first surface of the wiring board through the first bumps, an encapsulating resin encapsulating the semiconductor element and at least a portion of a side surface of the wiring board, the side surface of the wiring board extending between the first surface and second surface of the wiring board, and multiple of second bumps formed on the second surface of the wiring board and connected to a second conductive pattern of the conductive patterns in the wiring board.04-05-2012
20100230812Microelectronic Assemblies Having Compliancy and Methods Therefor - A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.09-16-2010
20100230811SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE BUMP - In one embodiment, a semiconductor device includes a semiconductor substrate and a bonding pad disposed thereon. The semiconductor device also includes a passivation layer, a buffer layer, and an insulating layer sequentially stacked on the semiconductor substrate. According to one aspect, a first recess is defined within the passivation layer, the buffer layer, and the insulating layer to expose at least a region of the bonding pad and a second recess is defined within the insulating layer to expose at least a region of the buffer layer and spaced apart from the first recess such that a portion of the insulating layer is interposed therebetween. Further, the semiconductor device includes a conductive solder bump disposed within the first and second recesses. The conductive solder bump may be connected to the bonding pad in the first recess and supported by the buffer layer through a protrusion of the conductive solder bump extending into the second recess.09-16-2010
20100230810FLIP CHIP SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - There is provide a flip chip semiconductor package comprising: an electrode pad formed a semiconductor substrate; a lower metal bonding layer formed on the electrode pad; an upper metal bonding layer formed on the lower metal bonding layer and having a post shape of a predetermined height; and a conductive bump formed on the upper metal bonding layer, and a solder bump covers at least partially the surface of the upper metal bonding layer. An insulating layer for electrode reconfiguration is formed around the electrode pad on the substrate, and the insulating layer has a predetermined thickness to prevent the penetration of a particles from the solder bump. The semiconductor package may further comprise an oxidation preventing layer between the solder bump and the upper metal bonding layer. In accordance with the present invention, there is realized the flip chip semiconductor package which improves the adhesive strength of the solder bump and which more improves the reliability in the flip chip bump structure of fine pitches.09-16-2010
20120326303Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die - A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.12-27-2012
20120326302Semiconductor Device and Method of Forming PIP with Inner Known Good Die Interconnected with Conductive Bumps - A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.12-27-2012
20120326300LOW PROFILE PACKAGE AND METHOD - In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.12-27-2012
20120280385ELECTRONIC DEVICE PACKAGING STRUCTURE - An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.11-08-2012
20120280384SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.11-08-2012
20120280387THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS - Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.11-08-2012
20120280389CHIP PACKAGE AND FABRICATION METHOD THEREOF - The invention provides A chip package, comprising: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate.11-08-2012
20120280388COPPER PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE AND METHOD OF MAKING THE SAME - This description relates to an integrated circuit device including a conductive pillar formed over a substrate. The conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer between the substrate and the conductive pillar. The UBM layer has a surface region. The integrated circuit device further includes a protection structure on the sidewall surface of the conductive pillar and the surface region of the UBM layer. The protection structure is formed of a non-metal material.11-08-2012
20120280386PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A microelectronic assembly includes a substrate having a first surface and a second surface remote from the first surface. A microelectronic element overlies the first surface and first electrically conductive elements are exposed at one of the first surface and the second surface. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer extends from the first surface and fills spaces between the wire bonds such that the wire bonds are separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.11-08-2012
20110291269Semiconductor Device Comprising a Stacked Die Configuration Including an Integrated Peltier Element - In a stacked semiconductor device, a Peltier element may be incorporated as a distributed element so as to provide active heat transfer from a high power device into a low power device, thereby achieving superior temperature control in stacked device configurations. For example, a CPU and a dynamic RAM device may be provided as a stacked configuration, wherein waste heat of the CPU may be efficiently distributed into the low power memory device.12-01-2011
20110291260SEMICONDUCTOR ENCAPSULATION ADHESIVE COMPOSITION, SEMICONDUCTOR ENCAPSULATION FILM-LIKE ADHESIVE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor encapsulation adhesive composition comprising (a) an epoxy resin, (b) a curing agent and (c) an antioxidant.12-01-2011
20120326299SEMICONDUCTOR CHIP WITH DUAL POLYMER FILM INTERCONNECT STRUCTURES - Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a first polymer film to a side of a semiconductor chip and forming a first underbump metallization structure with at least a portion on the first polymer film. A second polymer film is applied on the first polymer film with an opening exposing a portion of the first underbump metallization structure.12-27-2012
20120326297Semiconductor Device and Method of Forming Protective Coating Over Interconnect Structure to Inhibit Surface Oxidation - A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.12-27-2012
20120091583SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.04-19-2012
20120091582MICROELECTRONIC ASSEMBLIES HAVING COMPLIANCY AND METHODS THEREFOR - A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.04-19-2012
20120091581PACKAGE UNIT AND STACKING STRUCTURE THEREOF - A package unit and a stacking structure thereof are provided. The package unit includes a substrate, a first patterned circuit layer, a first conductive pillar, a semiconductor element, an insulation layer, a second conductive pillar, a third conductive pillar, a second patterned circuit layer and a conductive bump. The first patterned circuit layer is disposed on a surface of the substrate. The first conductive pillar is deposited through the substrate. The semiconductor element is disposed on the substrate. The insulation layer covers the semiconductor element and the substrate. The second conductive pillar is deposited through the insulation layer. The third conductive pillar is deposited through the insulation layer. The second patterned circuit layer is disposed on the insulation layer. The conductive bump is disposed on the second patterned metal layer.04-19-2012
20120091580Semiconductor Devices And Methods Of Fabricating The Same - Provided is a semiconductor device. The semiconductor device may include a first semiconductor chip that includes a first through silicon via having a first protrusion height and a second through silicon via having a second protrusion height greater than the first protrusion height which are penetrating at least a portion of the first semiconductor chip, a second semiconductor chip may be electrically connected to the first through silicon via, and a third semiconductor chip may be electrically connected to the second through silicon via.04-19-2012
20120091579Semiconductor Packages And Methods Of Fabricating The Same - A semiconductor package includes a wiring board including an upper connection pad provided on a first surface and a lower connection pad provided on a second surface opposite to the first surface, a semiconductor chip having a bonding pad area in which a bonding pad is provided and an adhesive area except the bonding pad area, and being mounted on the first surface of the wiring board in a flip-chip manner such that the bonding pad is electrically connected to the upper connection pad, a first molding layer provided between the adhesive area of the semiconductor chip and the first surface of the wiring board, and a second molding layer provided between the bonding pad area of the semiconductor chip and the first area of the wiring board while covering the first surface of the wiring board and the semiconductor chip. The first molding layer has a lower modulus than the second molding layer.04-19-2012
20120091578SEMICONDUCTOR CHIP HAVING DIFFERENT PAD WIDTH TO UBM WIDTH RATIOS AND METHOD OF MANUFACTURING THE SAME - The present application describes an semiconductor chip having a substrate, a first conductive pad formed over the substrate, a second conductive pad formed over the substrate and positioned farther from a geometric center of the semiconductor chip than the first conductive pad, a first under bump metallurgy (UBM) structure formed over the first conductive pad, and a second UBM structure formed over the second conductive pad. The first conductive pad and the first UBM structure has a first pad width to UBM width ratio, and the second conductive pad and the second UBM structure has a second pad width to UBM width ratio that is greater than the first ratio.04-19-2012
20120091577COPPER PILLAR BUMP WITH COBALT-CONTAINING SIDEWALL PROTECTION - An integrated circuit device includes a Cu pillar and a solder layer overlying the Cu pillar. A Co-containing metallization layer is formed to cover the Cu pillar and the solder layer, and then a thermally reflow process is performed to form a solder bump and drive the Co element into the solder bump. Next, an oxidation process is performed to form a cobalt oxide layer on the sidewall surface of the Cu pillar.04-19-2012
20120091576UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME - An under-bump metallization (UBM) structure in a semiconductor device includes a copper layer, a nickel layer, and a Cu—Ni—Sn intermetallic compound (IMC) layer between the copper layer and the nickel layer.04-19-2012
20120091574CONDUCTIVE PILLAR STRUCTURE - The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls.04-19-2012
20120326301THERMOSETTING RESIN COMPOSITION, FLIP-CHIP MOUNTING ADHESIVE, SEMICONDUCTOR DEVICE FABRICATION METHOD, AND SEMICONDUCTOR DEVICE - The present invention is aimed to provide a thermosetting resin composition which is easily produced, has excellent storage stability and thermal stability while maintaining high transparency and preventing formation of voids on the occasion of semiconductor chip bonding, and gives a cured product having excellent heat resistance, a flip-chip mounting adhesive containing the thermosetting resin composition, a method for producing a semiconductor device using the flip-chip mounting adhesive, and a semiconductor device produced by the method for producing a semiconductor device. The present invention is a thermosetting resin composition including an epoxy resin, an acid anhydride having a bicycle skeleton, and an imidazole curing accelerator that is in a liquid form at an ordinary temperature.12-27-2012
20120326296Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect Structure - A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.12-27-2012
20120326298BUMP STRUCTURE WITH BARRIER LAYER ON POST-PASSIVATION INTERCONNECT - A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.12-27-2012
20120286418Semiconductor Device and Method of Forming Dummy Pillars Between Semiconductor Die and Substrate for Maintaining Standoff Distance - A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate.11-15-2012
20120286420CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has at least one opening penetrating through the second substrate, and the at least one opening defines a plurality of conducting regions electrically insulated from each other in the second substrate; a carrier substrate disposed on the second substrate; an insulating layer disposed on a surface and a sidewall of the carrier substrate, wherein the insulating layer fills the at least one opening of the second substrate; and a conducting layer disposed on the insulating layer on the carrier substrate and electrically contacting with one of the conducting regions.11-15-2012
20120286417METHOD AND STRUCTURE FOR CONTROLLING PACKAGE WARPAGE - A method comprises determining a warpage of an integrated circuit (IC) package design. The IC package design includes a substrate having a top solder mask on a first major surface and a bottom solder mask on a second major surface opposite the first major surface. The first major surface has an IC die mounted over the top solder mask. The design is modified, including modifying an average thickness of one of the group consisting of the top solder mask and the bottom solder mask, so as to reduce the warpage. An IC package is fabricated according to the modified design.11-15-2012
20120286416SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a microelectronic element having a plurality of element contacts at a face thereof, and a compliant dielectric element having a Young's modulus of less than about two gigapascal (GPa) and substrate contacts at a first surface joined to the element contacts. The substrate contacts may be electrically connected with terminals at a second surface of the compliant dielectric element that opposes the first surface, through conductive vias in the compliant dielectric element. A rigid underfill may be between the face of the microelectronic element and the first surface of the compliant dielectric element. The terminals may be usable for bonding the microelectronic assembly to corresponding contacts of a component external to the microelectronic assembly.11-15-2012
20120286419SEMICONDUCTOR PACKAGE WITH INTERPOSER BLOCK THEREIN - A semiconductor package substrate is provided. The package substrate includes a mold base and an interposer block embedded in the mold base, said interposer block having a plurality of vertical conductive lines therein. A metallization layer is formed on the surface of the interposer block or the mold base, said metallization layer being electrically connected to at least one of the vertical conductive lines. A semiconductor chip may be mounted on or embedded in the mold base.11-15-2012
20120286422Semiconductor Device and Method of Forming Interconnect Structure for Encapsulated Die having Pre-Applied Protective Layer - A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.11-15-2012
20120286421CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has at least one opening penetrating through the second substrate, and the at least one opening defines a plurality of conducting regions electrically insulated from each other in the second substrate; a first insulating layer disposed on a side of the first substrate and filling in the at least one opening of the second substrate; a carrier substrate disposed on the second substrate; a second insulating layer disposed on a surface and a sidewall of the carrier substrate; and a conducting layer disposed on the second insulating layer on the carrier substrate and electrically contacting with one of the conducting regions.11-15-2012
20120286424DIE STACKING WITH AN ANNULAR VIA HAVING A RECESSED SOCKET - A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die.11-15-2012
20120139104INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom side and a lead top side; applying a passivation over the lead with the lead top side exposed from the passivation; forming an interconnect structure directly on the passivation and the lead top side, the interconnect structure having an inner pad and an outer pad with a recess above the lead top side; mounting an integrated circuit over the inner pad and the passivation; and molding an encapsulation over the integrated circuit.06-07-2012
20120139103SEMICONDUCTOR DEVICE WITH STACKED POWER CONVERTER - A semiconductor device with a stacked power converter is described. In some examples, a semiconductor device includes: a first integrated circuit (IC) die having bond pads and solder bumps, the bond pads configured for wire-bonding; and a second IC die mounted on the first IC die, the second IC die having an active side and a backside opposite the active side, the second IC die including bond pads on the active side configured for wire-bonding, and solder bumps disposed on a backside opposite the active side; where the solder bumps of the first IC die are electrically and mechanically coupled to the solder bumps of the second IC die to form bump bonds.06-07-2012
20130009306PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate.01-10-2013
20130009305SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a first via and a first interconnect supplying a high current is provided in which a first surface having the first via and the first interconnect is planar. The semiconductor device has a first via penetrating a first substrate from a first surface of the first substrate and a first interconnect buried in the first surface of the first substrate and connected with one end of at least one first via. The first via has an inclined portion where an angle formed between a lateral side of the first via and the bottom of the first via is larger than an angle formed between a lateral side of the first interconnect and the bottom of the first interconnect.01-10-2013
20130015572ELECTRONIC ASSEMBLY INCLUDING AN EMBEDDED ELECTRONIC COMPONENTAANM Ostmann; AndreasAACI BerlinAACO DEAAGP Ostmann; Andreas Berlin DEAANM Manessis; DionysiosAACI BerlinAACO DEAAGP Manessis; Dionysios Berlin DEAANM Bottcher; LarsAACI BerlinAACO DEAAGP Bottcher; Lars Berlin DEAANM Karaszkiewicz; StefanAACI BerlinAACO DEAAGP Karaszkiewicz; Stefan Berlin DE - An electronic unit is produced including at least one electronic component at least partially embedded in an insulating material. A film assembly is provided with at least one conductive layer and a carrier layer. The conductive layer includes openings in the form of holes for receiving bumps, which are connected to contact surfaces of the at least one electronic component. The at least one component is placed on the film assembly such that the bumps engage with the openings of the conductive layer. The at least one component is partially embedded from the side opposite of the bumps into a dielectric layer. The carrier layer of the film assembly is removed such that the surface of the bumps is exposed. A metallization layer is then deposited on the side of the remaining conductive layer having the exposed bumps and so as to produce conductor tracks that overlap with the bumps.01-17-2013
20130015573BALL GRID ARRAY WITH IMPROVED SINGLE-ENDED AND DIFFERENTIAL SIGNAL PERFORMANCE - An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.01-17-2013
20130015569Semiconductor Device and Method of Forming Substrate With Seated Plane for Mating With Bumped Semiconductor DieAANM Anderson; Samuel J.AACI TempeAAST AZAACO USAAGP Anderson; Samuel J. Tempe AZ USAANM Smiley; Thomas B.AACI CarlsbadAAST CAAACO USAAGP Smiley; Thomas B. Carlsbad CA US - A semiconductor device has a first insulating layer formed over a substrate. The substrate has a plurality of conductive layers and plurality of second insulating layers formed between the conductive layers. The substrate can be a PCB or interposer. A plurality of openings is formed in the first insulating layer by etching or laser direct ablation. A semiconductor die has a plurality of bumps formed over a surface of the semiconductor die. The pattern of openings coincides with a pattern of the bumps. The die is mounted to the substrate with the bumps disposed within the openings in the first insulating layer. Alternatively, a conductive paste can be disposed within the openings in the first insulating layer. The bumps are reflowed to electrically connect the die to the first substrate. The bumps are substantially contained within the openings of the first insulating layer to reduce bridging between adjacent bumps.01-17-2013
20130015571Semiconductor Package And Method Of Manufacturing The SameAANM CHUN; Jung HwanAACI Chungcheongnam-DoAACO KRAAGP CHUN; Jung Hwan Chungcheongnam-Do KR - A semiconductor package and a method of manufacturing the same. The semiconductor package includes; a printed circuit board (PCB); a first semiconductor chip attached onto the PCB; an interposer that is attached onto the first semiconductor chip to cover a portion of the first semiconductor chip and comprises first connection pad units and second connection pad units that are electrically connected to each other, respectively, on an upper surface opposite to a surface of the interposer facing the first semiconductor chip; a second semiconductor chip attached onto the first semiconductor chip and the interposer as a flip chip type; a plurality of bonding wires that electrically connect the second connection pad units of the interposer to the PCB or the first semiconductor chip to the PCB; and a sealing member formed on the PCB to surround the first semiconductor chip, the second semiconductor chip, the interposer, and the bonding wires.01-17-2013
20130015576Solder Bump with Inner Core Pillar in Semiconductor Package - A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.01-17-2013
20130015570STACKED SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOFAANM Sato; TakaoAACI Edogawa-kuAACO JPAAGP Sato; Takao Edogawa-ku JP - In an embodiment, a stacked semiconductor package includes a wiring board having external connection terminals and internal connection terminals, and first and second modules stacked on the wiring board. Each of the first and second modules includes a plurality of semiconductor chips mounted on an interposer and a sealing resin layer. The interposers and the internal connection terminals of the wiring board are electrically connected by connecting members such as metal wires, printed wiring layers or metal bumps. The first and second modules are collectively sealed by a sealing resin layer formed on the wiring board.01-17-2013
20130015577Semiconductor Device and Method of Forming Base Substrate with Cavities Formed through Etch-Resistant Conductive Layer for Bump Locking - A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers.01-17-2013
20130020700CHIP PACKAGE AND FABRICATION METHOD THEREOF - An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.01-24-2013
20130020697TECHNIQUES AND STRUCTURES FOR TESTING INTEGRATED CIRCUITS IN FLIP-CHIP ASSEMBLIES - A method for rejoining an IC die, removed from an existing substrate, to a new substrate, is disclosed herein. In one embodiment, such a method includes grinding an existing substrate from an IC die to create a substantially planar surface exposing interconnects and surrounding underfill material. A new substrate is provided having electrically conductive pedestals protruding therefrom. The electrically conductive pedestals are positioned to align with the exposed interconnects and have a melting point substantially higher than the melting point of the interconnects. The method places the exposed interconnects in contact with the electrically conductive pedestals. The method then applies a reflow process to melt and electrically join the exposed interconnects with the electrically conductive pedestals. A structure produced by the method is also disclosed.01-24-2013
20130020698Pillar Design for Conductive Bump - A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive material such as solder when a conductive bump is formed onto the conductive pillar. The conductive pillar may then be electrically connected to another contact through the conductive material.01-24-2013
20130020699PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The invention provides a package structure, including: a substrate, wherein the substrate has a first surface and a second surface, and a first pattern metal layer is formed on the first surface, and a second patterned metal layer is formed on the second surface, and the substrate has a plurality of vias formed therein, wherein the first patterned metal layer is electrically connected to the second patterned metal layer through the plurality of vias, and the widths of the plurality of vias are gradually increased from the first surface to the second surface; a chip formed on the first surface of the substrate; and a molding material is formed on the substrate and the chip, wherein the chip is covered by the molding material.01-24-2013
20130020701SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.01-24-2013
20130168849Fully Molded Fan-Out - A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.07-04-2013
20120241952APPARATUSES AND METHODS TO ENHANCE PASSIVATION AND ILD RELIABILITY - Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.09-27-2012
20120241950SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - A semiconductor device includes a first wiring board, a first semiconductor element mounted on the first wiring board, a second wiring board disposed over the first semiconductor element, and a second semiconductor element mounted on the second wiring board. The wiring boards are electrically interconnected by a connecting portion interposed therebetween. A resin layer is formed between the wiring boards such that the first semiconductor element mounted on the first wiring board is sealed and such that the wiring boards having the respective semiconductor elements mounted thereon are bonded together.09-27-2012
20120241948INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a frame platform and a frame base; forming an elevated paddle on the frame platform and a base pad on the frame base; mounting an integrated circuit over the elevated paddle; forming an encapsulation on the lead frame and over the elevated paddle, the base pad, the integrated circuit, and the internal interconnect; and removing the lead frame to expose an encapsulation recess and an encapsulation base with the base pad exposed along the encapsulation base and the elevated paddle exposed in the encapsulation recess.09-27-2012
20080251914SEMICONDUCTOR DEVICE - In a structure for connecting a semiconductor element having a fine pitch electrode at 50 pm pitch or less and a pad or wirings on a substrate, for preventing inter-bump short-circuit or fracture of a connected portion due to high strain generated upon heating or application of load during connection, the substrate and the semiconductor element are connected by way of a bump having a longitudinal elastic modulus (Young's modulus) of 65 GPa or more and 600 GPa or less and a buffer layer including one of tin, aluminum, indium, or lead as a main ingredient and, further, protrusions are formed to at least one of opposing surfaces of the bump and the pad or the wirings on the substrate to each other, and the surfaces are connected by ultrasonic waves.10-16-2008
20080246146WIRING SUBSTRATE AND WIRING SUBSTRATE MANUFACTURING METHOD - A method of manufacturing a wiring substrate comprises: a first step of forming, on a support plate, an electrode pad made of metal; a second step of etching the support plate in such a manner that the support plate has a shape which includes a projection portion to be contacted with the electrode pad; a third step of forming, on the surface of the support plate, an insulating layer for covering the electrode pad; a fourth step of forming, on the surface of the insulating layer, a conductive pattern to be connected to the electrode pad; and, a fifth step of removing the support plate.10-09-2008
20100090338MICROELECTRONIC DEVICES INCLUDING MULTIPLE THROUGH-SILICON VIA STRUCTURES ON A CONDUCTIVE PAD AND METHODS OF FABRICATING THE SAME - A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.04-15-2010
20080237852SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which a high concentration n type impurity region to be a conductive path and a drain electrode are disposed in an outer circumferential end of the chip to be an inactive region as a device region. Thereby, an up-drain structure is obtained without reducing the device region or without increasing the size of a semiconductor chip. The provided n type impurity region and drain electrode causes a depletion layer of a substrate to be terminated without needing an additional conventional annular region or shield metal. This is because the n type impurity region and the drain electrode also function as the annular region and the shield metal, respectively. With this configuration, a MOSFET with the up-drain structure having necessary components is obtained, while avoiding a reduction of the device region or an increase of the chip area.10-02-2008
20080237851SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, COMPOSITE METAL BODY AND MANUFACTURING METHOD THEREOF - A semiconductor device having a structure in which a semiconductor element and a Cu or Ni electrode are connected by way of a bonding layer comprising Cu, and the Cu bonding layer and the Cu or Ni electrode are diffusion-bonded to each other. The bonding layer is formed by conducting bonding in a reducing atmosphere by using a bonding material containing particles of Cu oxide with an average particle size of 1 nm to 50 μm and a reducing agent comprising an organic material, thereby providing excellent bonding strength to Ni or Cu electrode.10-02-2008
20080237850COMPLIANT BUMP STRUCTURE AND BONDING STRUCTURE - A compliant bump structure includes a substrate, at least a first polymer bump, at least a second polymer bump and at least a conductive layer. The substrate has at least a pad on a surface thereof. The first polymer bump is disposed on the pad. The second polymer bump is disposed on the surface of the substrate outside the pad. The conductive layer is disposed on the first and second polymer bumps.10-02-2008
20080237849Method and apparatus providing integrated circuit having redistribution layer with recessed connectors - A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.10-02-2008
20080230900DETERMINING THE PLACEMENT OF SEMICONDUCTOR COMPONENTS ON AN INTEGRATED CIRCUIT - Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of a method, among others, comprises analyzing regions of a semiconductor die with respect to the susceptibility of the region to be exposed to radiation. This method further comprises placing the standard cell in one of the analyzed regions of the semiconductor die, the standard cell being placed based on the sensitivity of the standard cell to radiation. The method may also comprise running an algorithm, e.g. using a component placement engine, for determining the placement of semiconductor components on an integrated circuit die.09-25-2008
20080230899SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device according to the present invention, a plurality of opening regions 09-25-2008
20080230898SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device which includes a first semiconductor chip, a second semiconductor chip flip-chip bonded to the first semiconductor chip, a resin portion for sealing the first semiconductor chip and the second semiconductor chip such that a lower surface of the first semiconductor chip and an upper surface of the second semiconductor chip are exposed and a side surface of the first semiconductor chip is covered, and a post electrode which pierces the resin portion and is connected to the first semiconductor chip, and a manufacturing method thereof are provided.09-25-2008
20130168848PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING THE SEMICONDUCTOR DEVICE - The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.07-04-2013
20130168850SEMICONDUCTOR DEVICE HAVING A THROUGH-SUBSTRATE VIA - Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.07-04-2013
20130168851BUMP STRUCTURE AND ELECTRONIC PACKAGING SOLDER JOINT STRUCTURE AND FABRICATING METHOD THEREOF - A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.07-04-2013
20130168852MEMS Devices and Methods of Forming Same - A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.07-04-2013
20130168853PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - Disclosed herein are a package substrate and a method of fabricating the same. The method of fabricating the package substrate includes preparing a base substrate, forming a metal material layer surrounding an entire surface of the base substrate, forming sacrificial patterns on partial regions of the base substrate on which the metal material layer is formed, forming pads contacting lateral surfaces of the sacrificial patterns, forming a gold plating layer on upper surfaces of the pads, and removing the sacrificial patterns and removing portions of the metal material layer to form a conductive layer that remains on partial regions so as to contact lower surfaces of the pads.07-04-2013
20130140688Through Silicon Via and Method of Manufacturing the Same - The present invention discloses a through silicon via and method of manufacturing the same comprising the steps of providing a substrate, forming a plurality of through silicon via (TSV) holes in said substrate, forming a seed layer on the surface of said substrate and said a plurality of TSV holes, forming a patterned mask on said substrate, wherein said patterned mask comprises a plurality of first openings corresponding to said TSV holes and a plurality of second openings adjacent to or surrounding said a plurality of first openings, forming a material layer on said substrate, wherein said material layer is filled into said TSV holes and said first openings to form a plurality of through silicon vias, and said material layer is filled into said second openings to form a plurality of dummy bumps.06-06-2013
20080224311SEMICONDUCTOR DEVICE - A semiconductor device is disclosed including a data family pad layout wherein an effort is made to contrive layouts of a power lead wire and a ground lead wire to minimize effective inductance in priority to a length of a lead wire between a pad and a solder ball land of a semiconductor chip. Pad layouts are arrayed in two rows and one unit of the pad layout is configured such that a data power source and ground are adjacent to each other or one data is inserted between the data power source and the ground. Such configurations decrease mutual inductance between the data power sources and increase mutual inductance between the data power source and the ground causing reduction in effective inductance between the data power source and the ground with the resultant minimization of power and ground noises.09-18-2008
20080224310METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: preparing a wiring board having a base substrate and wiring that is plated on surface with a plating metal; pressing a bump that is formed on the active side of the semiconductor chip against an end part of the wiring of the wiring board, thereby exfoliating the area surrounding the pressed portion of the wiring from the base substrate while keeping the end of the wiring bonded with the base substrate; melting the plating metal that is located on the end part of the wiring, thereby causing the plating metal and the bump to form an alloy that bonds the bump and the wiring and infiltrate the plating metal into a space between the wiring and the base substrate; and judging that the bump and the wiring are well bonded if the plating metal has infiltrated a space between the wiring and the base substrate so as to have an area, width or length of infiltration that exceeds a reference value.09-18-2008
20080224309SEMICONDUCTOR DEVICE MOUNTED ON SUBSTRATE, AND MANUFACTURING METHOD THEREOF - The connection technology is provided in which, at the time of mounting the semiconductor device on the substrate, the thermal load or the stress, which is imposed upon the semiconductor device, is little, a reliability of the semiconductor device is obtained, a stand-off of the semiconductor device mounted on the substrate can be secured appropriately, and moreover the short circuit hardly occurs between the pads of the semiconductor device mounted on the substrate.09-18-2008
20080224308SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF - Provided is a semiconductor device including a substrate, an electrode pad disposed on the substrate, an external terminal disposed on the electrode pad, a container extended from the electrode pad into the external terminal, and a conductive liquid disposed inside the container. The conductive liquid solidifies when exposed to air. When a crack forms in the external terminal, the container suppresses propagation of the crack. Further, if the crack breaches the container, the conductive liquid fills the crack, thereby minimizing further crack propagation and recovering the resistance characteristics of the external terminal prior to the crack formation. A method of forming a semiconductor device including a container having a conductive liquid is also provided.09-18-2008
20080224307Semiconductor die with mask programmable interface selection - According to one exemplary embodiment, a semiconductor die with on-die preferred interface selection includes at least two groups of pads situated on an active surface of the semiconductor die, where each of the at least two groups of pads is coupled to its associated interface in the die. A set of bumps is mask-programmably routed to one of the at least two groups of pads, thereby selecting the preferred interface for the semiconductor die. A non-preferred interface is not routed to any bumps on the active surface of the semiconductor die, thereby reducing bump count on the die. Each of the at least two groups of pads can be situated in a corresponding pad ring on the active surface of said semiconductor die. The at least two groups of pads can be laid out substantially inline.09-18-2008
20130181348SEMICONDUCTOR DEVICE HAVING BACKSIDE REDISTRIBUTION LAYERS AND METHOD FOR FABRICATING THE SAME - Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench.07-18-2013
20130181338Package on Package Interconnect Structure - A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.07-18-2013
20130181339MULTI-CHIP SELF-ALIGNMENT ASSEMBLY WHICH CAN BE USED WITH FLIP-CHIP BONDING - A method and structure for mechanical self-alignment of semiconductor device features, for example multi-chip module features. Alignment of the features can be performed using mechanical alignment grooves within a layer of a first device and mechanical alignment pedestals of a second device. The alignment accuracy is limited by the patterning resolution of the semiconductor processing, which is in sub-micron scale. Flip-chip bonding can be used as the bonding process between chips to increase the alignment precision.07-18-2013
20130181340SEMICONDUCTOR DEVICES WITH COMPLIANT INTERCONNECTS - A method forms a connecting pillar to a bonding pad of an integrated circuit. A seed layer is formed over the bond pad. Photoresist is deposited over the integrated circuit. An opening is formed in the photoresist over the bond pad. The connecting pillar is formed in the opening by plating.07-18-2013
20130181341SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package structure and a method for manufacturing the same are provided, in which a semiconductor die is disposed in a spacer structure for packaging, and a connection pad, a first metallic layer, an insulating layer, a wiring layer, a pin base, a conductive via and a metallic bump are formed on the semiconductor die, wherein the wiring layer can be formed as a single layer or multiple layers, and the connection pad is electrically connected with an outer pin. Moreover, the positioning structures are also formed to overcome the conventional misalignment problems caused by the thermal expansion and the cooling contraction. The alignment of the conductive via with the connection pad can be more accurately achieved, which ensures that the connection pad is reliably connected with the outer pin.07-18-2013
20130181342SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate having first and second surfaces which face each other, a semiconductor chip mounted on the first surface, a first encapsulant formed on the first surface and at least partially encapsulating the semiconductor chip. A second encapsulant is formed on the second surface and first external connection terminals formed on the second surface to penetrate the second encapsulant. The external connection terminals have first ends in contact with the second surface. Second external connection terminals are attached to second ends of the first external connection terminals.07-18-2013
20130140690TSV Structures and Methods for Forming the Same - A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.06-06-2013
20130140693METHOD FOR FORMING AN INTEGRATED CIRCUIT - A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.06-06-2013
20080217770MOUNTING CONFIGURATION OF ELECTRONIC COMPONENT - An electronic component mounting configuration in which an electronic component chip having a plurality of protrusion-shaped electrodes distributed on its entire mounting surface is mounted through protrusion-shaped electrodes on a printed circuit board is provided which is capable of improving reliability of an electronic component by relieving thermal stress. The solder bumps are arranged so that intervals between solder bumps adjacent to one another become smaller from a central portion of a mounting surface of the electronic component chip toward the peripheral portion thereof. For example, an interval between the solder bump “09-11-2008
20100072615High-Electrical-Current Wafer Level Packaging, High-Electrical-Current WLP Electronic Devices, and Methods of Manufacture Thereof - The present invention has various aspects relating to the maximization of current carrying capacity of wafer level packaged chip scale solder pad mounted integrated circuits. In one aspect, the solder pad areas are maximized by using rectangular solder pads spaced as close together as reliable mounting to a circuit board will allow. In another aspect, multiple contact pads may be used for increasing the current capacity without using contact pads of different areas. In still another aspect, vias are used to directly connect one lead of high current component or components to a contact pad directly above that component, and to route a second lead of the high current component to an adjacent contact pad by way of a thick metal interconnect layer.03-25-2010
20120248602SEMICONDUCTOR DEVICE - In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r10-04-2012
20120248603SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P10-04-2012
20120248601Semiconductor Device and Method of Forming a Land Grid Array Flip Chip Bump System - A semiconductor device has a semiconductor wafer with a plurality of semiconductor die including a plurality of contact pads. An insulating layer is formed over the semiconductor wafer and contact pads. An under bump metallization (UBM) is formed over and electrically connected to the plurality of contact pads. A mask is disposed over the semiconductor wafer with a plurality of openings aligned over the plurality of contact pads. A conductive bump material is deposited within the plurality of openings in the mask and onto the UBM. The mask is removed. The conductive bump material is reflowed to form a plurality of bumps with a height less than a width. The plurality of semiconductor die is singulated. A singulated semiconductor die is mounted to a substrate with bumps oriented toward the substrate. Encapsulant is deposited over the substrate and around the singulated semiconductor die.10-04-2012
20120248600SEMICONDUCTOR DEVICE HAVING PLURAL STACKED CHIPS - Disclosed herein is a device including a substrate and first and second chips stacked on the substrate. The first and second chips have penetration electrodes that are penetrating therethrough. Power terminals of the first and second chips are connected to each other and arranged in a first arrangement pitch. Signal terminals of the first and second chips are connected to each other and arranged in a second arrangement pitch that is smaller than the first arrangement pitch.10-04-2012
20120248599RELIABLE SOLDER BUMP COUPLING WITHIN A CHIP SCALE PACKAGE - In one general aspect, an apparatus can include a semiconductor substrate including at least one semiconductor device, and a metal layer disposed on the semiconductor substrate. The apparatus can include a nonconductive layer defining an opening and having a cross-sectional portion of the nonconductive layer defining a protrusion disposed over a recess in the metal layer, and can include a solder bump having a portion disposed between the metal layer and the protrusion defined by the nonconductive layer.10-04-2012
20120248598SEMICONDUCTOR BONDING APPARATUS - An apparatus includes a tool head configured for bonding to establish 100 or more electrical and mechanical connections between a silicon chip having a thickness of about 50 microns (μm) or smaller and a substrate, wherein 100 or more solder bumps set on a plurality of contacts on the silicon chip or a plurality of contacts on the substrate are melted by heating between the plurality of contacts of the silicon chip and the substrate, and wherein the melted solder bumps are solidified by cooling using forced convection of air flowing from around the silicon chip. The tool head includes a pyrolytic graphite sheet configured to be used in direct contact with the silicon chip, and having a thickness between about 75 μm and 125 μm.10-04-2012
20130134582NOVEL BUMP STRUCTURES FOR MULTI-CHIP PACKAGING - The mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package.05-30-2013
20090302465DIE REARRANGEMENT PACKAGE STRUCTURE AND METHOD THEREOF - A die rearrangement package structure is provided and includes a die; an encapsulated structure is covered around the four sides of the die to expose the active surface and the reverse side of the die; a patterned protective layer is formed on the encapsulated structure and the active surface of the die, and the pads is to be exposed; one end of fan-out patterned metal layer is electrically connected the pads and other end is extended to cover the patterned protective layer; patterned second protective layer is provided to cover the patterned metal layer to expose the portions surface of the patterned metal layer; patterned UBM layer is formed on the exposed surface of the patterned metal layer; and a conductive component is formed on the patterned UBM layer, and electrically connected the patterned metal layer.12-10-2009
20130134578DEVICE HAVING MULTIPLE WIRE BONDS FOR A BOND AREA AND METHODS THEREOF - Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security.05-30-2013
20130134587MICROELECTRONIC PACKAGE WITH SELF-HEATING INTERCONNECT - A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate anda die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate.05-30-2013
20130134586Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers - A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.05-30-2013
20130093082SEMICONDUCTOR DEVICE, ELECTRODE MEMBER, AND ELECTRODE MEMBER FABRICATION METHOD - A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved.04-18-2013
20130093083SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted.04-18-2013
20130093078Process for Forming Package-on-Package Structures - A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.04-18-2013
20130093081IC CHIP PACKAGE AND CHIP-ON-GLASS STRUCTURE USING THE SAME - An IC chip package and a chip-on-glass structure using the same are provided. The IC chip package includes an IC chip having a circuit surface, and plural copper (Cu) bumps formed on the circuit surface. Moreover, a non-conductive film (NCF) could be formed on the circuit surface to cover the Cu bumps. The chip-on-glass structure includes a glass substrate, plural electrodes such as aluminum (Al) electrodes formed on the glass substrate, and a conductive film formed on the electrodes. The conductive film contains a number of conductive particles. When the IC chip package is coupled to the glass substrate, the Cu bumps can be coupled to the corresponding electrodes via conductive particles.04-18-2013
20130093077POST-PASSIVATION INTERCONNECT STRUCTURE - A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.04-18-2013
20130093080MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.04-18-2013
20130093079Connector Structures of Integrated Circuits - A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.04-18-2013
20130093076SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.04-18-2013
20110272802BUMP, METHOD FOR FORMING THE BUMP, AND METHOD FOR MOUNTING SUBSTRATE HAVING THE BUMP THEREON - A two-layer structure bump including a first bump layer of a bulk body of a first conductive metal, which is any of gold, copper, and nickel, formed on a substrate and a second bump layer of a sintered body of a powder of a second conductive metal, which is any of gold and silver, formed on the first bump layer. The bulk body composing the first bump layer is formed through any of plating, sputtering, or CVD. The sintered body composing the second bump layer is formed by sintering the powder of the second conductive metal having a purity of not lower than 99.9 wt % and an average particle diameter of 0.005 μm to 1.0 μm. The second bump layer has a Young's modulus 0.1 to 0.4 times that of the first bump layer.11-10-2011
20110272801SEMICONDUCTOR DEVICE WITH CONNECTION PADS PROVIDED WITH INSERTS - A semiconductor device includes an integrated circuit and external electrical connection pads. Each pad includes cavities that are at least partially filled with a material different from the material forming the pads, so as to form inserts.11-10-2011
20110272800SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME - A method of manufacturing a semiconductor package includes placing a semiconductor chip in a recess provided on a surface of a supporting body so that a part of the semiconductor chip projects from the recess; forming a resin part on the surface of the supporting body, the resin part encapsulating the projecting part of the semiconductor chip; removing the supporting body; and forming an interconnection structure electrically connected to the semiconductor chip by using the resin part as a part of the base body of the semiconductor package.11-10-2011
20110272799IC CHIP AND IC CHIP MANUFACTURING METHOD THEREOF - An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a chip body and at least one bump. The chip body has at least one conducting area on its surface. The bump is formed on the conducting area of the chip body. The bump includes a plurality of protrusions and at least one conducting material. The protrusions protrude out of the conducting area and are spaced apart from each other. The conducting material covers the protrusions and electrically connects the conducting area. The method includes: (A) providing a chip body having a conducting area on its surface; (B) forming a plurality of protrusions on the chip body, wherein the protrusions protrude out of the conducting area and are spaced apart from each other; and (C) forming at least one conducting material, wherein the conducting material covers the protrusions and electrically connects the conducting area.11-10-2011
20130099378Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die - A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.04-25-2013
20130099377Molded Chip Interposer Structure and Methods - Apparatus and methods for providing a molded chip interposer structure and assembly. A molded chip structure having at least two integrated circuit dies disposed within a mold compound is provided having the die bond pads on the bottom surface; and solder bumps are formed in the openings of a dielectric layer on the bottom surface, the solder bumps forming connections to the bond pads. An interposer having a die side surface and a board side surface is provided having bump lands receiving the solder bumps of the molded chip structure on the die side of the interposer. An underfill layer is formed between the die side of the interposer and the bottom surface of the molded chip structure surrounding the solder bumps. Methods for forming the molded chip interposer structure are disclosed.04-25-2013
20130099375SEMICONDUCTOR PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A semiconductor package substrate including a substrate body having a front surface configured for mounting a semiconductor chip on the front surface and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body.04-25-2013
20130099373SEMICONDUCTOR PACKAGES INCLUDING A PLURALITY OF UPPER SEMICONDUCTOR DEVICES ON A LOWER SEMICONDUCTOR DEVICE - Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other.04-25-2013
20130099372Methods of Forming Bump Structures That Include a Protection Layer - One illustrative method disclosed herein includes forming a conductive pad in a layer of insulating material, forming a passivation layer above the conductive pad, performing at least one etching process on the passivation layer to define an opening in the passivation layer that exposes at least a portion of the conductive pad, forming a protective layer on the passivation layer, in the opening and on the exposed portion of the conductive pad, forming a heat-curable material layer above the protective layer, performing an etching process to define a patterned heat-curable material layer having an opening that exposes a portion of the protective layer, performing an etching process on the protective layer to thereby expose at least a portion of the conductive pad and forming a conductive bump that is conductively coupled to the conductive pad.04-25-2013
20130099371SEMICONDUCTOR PACKAGE HAVING SOLDER JOINTED REGION WITH CONTROLLED AG CONTENT - A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The silver (Ag) content in the solder layer is between 0.5 and 1.8 weight percent.04-25-2013
20130099370SEMICONDUCTOR PACKAGE - A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm.04-25-2013
20130113094POST-PASSIVATION INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.05-09-2013
20130113096SEMICONDUCTOR DEVICE - A semiconductor device suitable for preventing malfunction is provided.05-09-2013
20130113093Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package - A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.05-09-2013
20130187270Multi-Chip Fan Out Package and Methods of Forming the Same - A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.07-25-2013
20130187271SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.07-25-2013
20110266668MICROELECTRONIC ASSEMBLIES HAVING COMPLIANCY - A microelectronic assembly includes a microelectronic element, such as a semiconductor wafer or semiconductor chip, having a first surface and contacts accessible at the first surface, and a compliant layer overlying the first surface of the microelectronic element, the compliant layer having openings in substantial alignment with the contacts of the microelectronic element. The assembly desirably includes conductive posts overlying the compliant layer and projecting away from the first surface of the microelectronic element, the conductive posts being electrically interconnected with the contacts of the microelectronic element by elongated, electrically conductive elements extending between the contacts and the conductive posts.11-03-2011
20110266667CU PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE - A sidewall protection structure is provided for covering at least a portion of a sidewall surface of a bump structure, in which a protection structure on the sidewalls of a Cu pillar and a surface region of an under-bump-metallurgy (UBM) layer is formed of at least one non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.11-03-2011
20130200511REDUCING STRESS IN MULTI-DIE INTEGRATED CIRCUIT STRUCTURES - An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.08-08-2013
20130127049Method for Stacking Devices and Structure Thereof - A semiconductor device that has a first device that includes a first through-silicon via (TSV) structure, a first coating material disposed over the first device, the first coating material continuously extending over the first device and covering the first TSV structure, a second device disposed over the first device and within the first coating material, the second device includes a second TSV structure and a plurality of conductive bumps, the plurality of conductive bumps are positioned within the first coating material, a second coating material disposed over the second device, the second coating material continuously extends over the second device and covers the second TSV structure, and a third device disposed over the second coating material, the third device includes a third TSV structure.05-23-2013
20130127051WINDOW BALL GRID ARRAY (BGA) SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.05-23-2013
20130127048DEVICE - A device has a first substrate having a first surface; a first electrode pad arranged on the first surface of the first substrate; a first insulator film provided on the first surface of the first substrate so that the first electrode pad is exposed; a first bump electrode provided on the first electrode pad and having a first diameter; and a second bump electrode provided on the first insulator film and having a second diameter smaller than the first diameter.05-23-2013
20130127050SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip.05-23-2013
20130127042Semiconductor Device and Method of Forming Conductive Layer Over Substrate with Vents to Channel Bump Material and Reduce Interconnect Voids - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.05-23-2013
20130127045MECHANISMS FOR FORMING FINE-PITCH COPPER BUMP STRUCTURES - The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.05-23-2013
20130127041BALL GRID ARRAY TO PIN GRID ARRAY CONVERSION - Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package.05-23-2013
20130127040DIE CARRIER FOR PACKAGE ON PACKAGE ASSEMBLY - A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.05-23-2013
20130127039Semiconductor Device and Method of Laser-Marking Laminate Layer Formed Over EWLB With Tape Applied to Opposite Surface - A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking.05-23-2013
20130134581PLANARIZED BUMPS FOR UNDERFILL CONTROL - The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved.05-30-2013
20130134584SEMICONDUCTOR DEVICE HAVING WIRING PAD AND WIRING FORMED ON THE SAME WIRING LAYER - Disclosed herein is a device that includes a first wiring provided as a first-level wiring layer and elongated in a first direction; and a first wiring pad provided as the first-level wiring layer, the first wiring pad being rectangular and including a first side edge that is elongated in the first direction and a second side edge that is elongated in a second direction crossing to the first direction, the first side edge being greater in length than the second side edge, the first wiring pad being greater in length in the second direction than the first wiring.05-30-2013
20130134585INTEGRATED CIRCUIT ASSEMBLY AND METHOD OF MAKING - An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate.05-30-2013
20130140689Bump-on-Trace Structures in Packaging - A package component includes a metal trace on a top surface of the package component, and an anchor via underlying and in contact with the metal trace. The anchor via is configured not to conduct currents flowing through the metal trace.06-06-2013
20130140691Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration - A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.06-06-2013
20130140694FLIP CHIP PACKAGE UTILIZING TRACE BUMP TRACE INTERCONNECTION - A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.06-06-2013
20130140695SOLDER BUMP CONNECTIONS - Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.06-06-2013
20100276800SEMICONDUCTOR MODULE - A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.11-04-2010
20110215465MULTI-CHIP INTEGRATED CIRCUIT - An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.09-08-2011
20130147037SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.06-13-2013
20130147038SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS WITHOUT OCCURRING OF CRACK - A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns. Remaining one or ones of the wiring patterns is kept covered by the insulating layer and includes the first wiring pattern.06-13-2013
20130127046REDUCED SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DURING 3D SEMICONDUCTOR DEVICE BONDING AND ASSEMBLY - Electrostatic discharge susceptibility is reduced when assembling a stacked IC device by coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to place the ground plane at substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements.05-23-2013
20130175683Semiconductor Device And Bump Formation Process - A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.07-11-2013
20130175682SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film.07-11-2013
20080197492Semiconductor device, connecting member, method for manufacturing a semiconductor device and method for manufacturing a connecting member - A semiconductor device has a semiconductor element having a plurality of connection terminals, a circuit substrate electrically connected with the semiconductor element; and a connecting member arranged between the semiconductor element and the circuit substrate having a plurality of conductive projections each having a columnar portion, each of columnar portions are connected with each of connection terminals, a cross section of the columnar portion along a plane parallel to a surface of the semiconductor element being smaller than a surface area of each of connection terminals of the semiconductor element.08-21-2008
20080197491SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - The semiconductor device includes a silicon interposer made of a semiconductor and a first semiconductor chip mounted on one surface of the silicon interposer. The semiconductor device is provided with a through electrode penetrating the silicon interposer and having a side surface insulated from the silicon interposer; and a wiring connecting one end of the through electrode and the silicon interposer. The through electrode is connected to a power supply wiring or a GND wiring provided on the first semiconductor chip.08-21-2008
20080197490Conductive structure for a semiconductor integrated circuit and method for forming the same - A conductive structure for a semiconductor integrated circuit and method for forming the conductive structure are provided. The semiconductor integrated circuit has a pad and a passivation layer partially overlapping the pad to define the first lateral size of the first opening. The conductive structure electrically connects to the pad via the first opening. The conductive structure overlaps the first opening portion and parts of the passivation layer to provide a lower conductive resistance for the pad when connecting to a bump. Meanwhile, the conductive structure provides no discontinuity over the passivation layer in other places, thereby providing a stable conduction.08-21-2008
20080197489Packaging conductive structure and method for manufacturing the same - A packaging conductive structure for a semiconductor substrate and a method for manufacturing the structure are provided. The structure comprises an under bump metal (UBM) that overlays a pad of the semiconductor substrate. At least one auxiliary component is disposed on the UBM. Then, a bump conductive layer is disposed thereon and a bump is subsequently formed on the bump conductive layer. Thus, the bump can electrically connect to the pad of the semiconductor substrate through the UBM and the bump conductive layer and can provide better junction buffer capabilities and conductivity.08-21-2008
20130147032PASSIVATION LAYER FOR PACKAGED CHIP - The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.06-13-2013
20130147039SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.06-13-2013
20130147034BUMP STRUCTURE DESIGN FOR STRESS REDUCTION - Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.06-13-2013
20130147035Semiconductor Device and Method of Forming Recesses in Conductive Layer to Detect Continuity for Interconnect Between Semiconductor Die and Substrate - A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over the substrate. The conductive layer has a channel in an interconnect site of the conductive layer. The channel extends beyond a footprint of the composite bump structures. The semiconductor die is disposed over the substrate. The bump material of the composite bump structures is melted. The composite bump structures are pressed over the interconnect site of the conductive layer so that the melted bump material flows into the channel. Electrical continuity between the composite bump structures and conductive layer is detected by a presence of the bump material in the channel. No electrical continuity between the composite bump structures and conductive layer is detected by an absence of the bump material in the channel. The electrical continuity can be detected by visual inspection or X-ray.06-13-2013
20130147036Semiconductor Device and Method of Forming UBM Structure on Back Surface of TSV Semiconductor Wafer - A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.06-13-2013
20130147030Landing Areas of Bonding Structures - A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The metal trace includes a portion having an edge, wherein the edge is not parallel to the lengthwise direction of the metal trace. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface and the edge of the portion of the metal trace.06-13-2013
20130147031SEMICONDUCTOR DEVICE WITH BUMP STRUCTURE ON POST-PASSIVATION INTERCONNCET - A semiconductor device includes a post-passivation interconnect (PPI) structure having a landing pad region. A polymer layer is formed on the PPI structure and patterned with a first opening and a second opening to expose portions of the landing pad region. The second opening is a ring-shaped opening surrounding the first opening. A bump structure is formed on the polymer layer to electrically connect the landing pad region through the first opening and the second opening.06-13-2013
20130147033POST-PASSIVATION INTERCONNECT STRUCTURE - A semiconductor device includes a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.06-13-2013
20130113095PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.05-09-2013
20100295176SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT SUBSTRATE, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT - A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.11-25-2010
20130140696SEMICONDUCTOR DEVICE - A semiconductor device includes a first substrate; a plurality of first electrodes formed on the first substrate; and a first insulating film formed on sidewalls of the plurality of first electrodes. The first insulating film is formed not to fill spaces between the plurality of first electrodes.06-06-2013
20100308459Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die - A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.12-09-2010
20100308458Semiconductor integrated circuit device - Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.12-09-2010
20100308457Semiconductor apparatus and manufacturing method of the same - Provided is a semiconductor apparatus that reduces on-resistance in wiring between a first electrode terminal and a second electrode terminal. The semiconductor apparatus includes the first electrode terminal, the second electrode terminal, and at least two wires that connect the first and second electrode terminals. At least two wires are electrically connected with each other by using a conductive adhesive in an extending direction of the wires. The first electrode terminal is a terminal of an external lead electrode, for example. The second electrode terminal is a terminal of a source electrode of a MOSFET, for example.12-09-2010
20120273944Power Semiconductor Package With Bottom Surface Protrusions - A package includes a body that encapsulates a semiconductor die, the body having a first pair of opposing lateral sides, a second pair of opposing lateral sides, a top, and a bottom. The bottom has a primary surface and a plurality of protrusions that extend outward from the primary surface. When the package is mounted to a printed circuit board (PCB) the protrusions contact the PCB and the primary surface is disposed a first distance away from the PCB. The package further includes a plurality of leads that extend outward from the first pair of opposing lateral sides.11-01-2012
20120273943Solder Joint Flip Chip Interconnection Having Relief Structure - A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact or near proximity of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.11-01-2012
20120273942Flip-chip Mounting Structure and Flip-chip Mounting Method - When a flip-chip mounting component with an Al/Au bonding structure is exposed to high temperature, voids may be caused in the Al electrode. The generation of voids causes failed connection or failed bonding between the Al electrode and the Au bump, thereby significantly degrading the connection reliability and bonding reliability in the flip-chip mounting structure. An object of the preset invention is to provide a flip-chip mounting structure that has high connection reliability and bonding reliability without being degraded even in high temperature. In a flip-chip mounting structure for wirelessly connecting an IC chip 11-01-2012
20120273941PACKAGE STRUCTURE HAVING EMBEDDED ELECTRONIC COMPONENT AND FABRICATION METHOD THEREOF - A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.11-01-2012
20120273940SEMICONDUCTOR APPARATUS AND METHOD FOR FABRICATING THE SAME - A semiconductor apparatus includes a first chip comprising a first bonding pad and a dielectric layer exposes a portion of the first bonding pad; a first bonding layer covering entirely or partially the first front side of the first chip, a second chip comprising a second bonding pad and a through-silicon via, and a conductive projection formed over the second bonding pad. The dielectric layer is formed on of the first chip, a second back side of the second chip is bonded to the first front side of the first chip by the medium of the first bonding layer, and the second bonding pad formed on a second front side of the second chip is coupled to the first bonding pad by the through-silicon via.11-01-2012
20120273935Semiconductor Device and Method of Making a Semiconductor Device - A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.11-01-2012
20120273934REDUCED-STRESS BUMP-ON-TRACE (BOT) STRUCTURES - The embodiments of bump-on-trace (BOT) structures and their layout on a die described reduce stresses on the dielectric layer on the metal pad and on the metal traces of the BOT structures. By orienting the axes of the metal bumps away from being parallel to the metal traces, the stresses can be reduced, which can reduce the risk of delamination of the metal traces from the substrate and the dielectric layer from the metal pad. Further, the stresses of the dielectric layer on the metal pad and on the metal traces may also be reduced by orienting the axes of the metal traces toward the center of the die. As a result, the yield can be increased.11-01-2012
20120273939FILLED THROUGH-SILICON VIA AND THE FABRICATION METHOD THEREOF - By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.11-01-2012
20120273938Semiconductor Device and Method of Forming an Interconnect Structure with Conductive Material Recessed Within Conductive Ring Over Surface of Conductive Pillar - A semiconductor device has a semiconductor die with a first conductive layer formed over an active surface of the semiconductor die. An insulation layer is formed over the active surface of the semiconductor die. A second conductive layer is conformally applied over the insulating layer and first conductive layer. Conductive pillars are formed over the first conductive layer. Conductive rings are formed around a perimeter of the conductive pillars. A conductive material is deposited over the surface of the conductive pillars within the conductive rings. A substrate has a third conductive layer formed over a surface of the substrate. The semiconductor die is mounted to a substrate with the third conductive layer electrically connected to the conductive material within the conductive rings. The conductive rings inhibit outward flow of the conductive material from under the conductive pillars to prevent electrical bridging between adjacent conductive pillars.11-01-2012
20120273937Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer - A semiconductor device has a substrate with a plurality of contact pads. A first insulation layer is formed over the substrate and contact pads. A portion of the first insulating layer is removed to form a toroid-shaped SRO over the contact pads while retaining a central portion of the first insulating layer over the contact pads. The central portion of the first insulating layer can extend above a surface of the first insulating layer outside the first conductive layer. A first conductive layer is formed over the central portion of the first insulating layer and through the SRO in the first insulating layer over the contact pads. The first conductive layer may extend above a surface of the first insulating layer outside the second conductive layer. A semiconductor die is mounted to the substrate with the bumps electrically connected to the first conductive layer.11-01-2012
20110233776SEMICONDUCTOR CHIP WITH COIL ELEMENT OVER PASSIVATION LAYER - A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.09-29-2011
20110233775Three-Dimensional Multichip Module - A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips.09-29-2011
20110233774ELECTRONIC DEVICES FORMED OF TWO OR MORE SUBSTRATES CONNECTED TOGETHER, ELECTRONIC SYSTEMS COMPRISING ELECTRONIC DEVICES, AND METHODS OF FORMING ELECTRONIC DEVICES - Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at least substantially parallel to each other through at least a portion of the first substrate. A plurality of bond pads is positioned on a surface of the first substrate and comprises a width extending over at least two of the plurality of conductive traces. A plurality of vias extends from adjacent at least some of the conductive traces to the plurality of bond pads. The second substrate is bonded to the first substrate and comprises support circuitry coupled to the plurality of bond pads on the first substrate with a plurality of conductive bumps. Memory devices and related methods of forming electronic devices and memory devices are also disclosed, as are electronic systems.09-29-2011
20110233773MANUFACTURING PROCESS AND STRUCTURE OF THROUGH SILICON VIA - A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.09-29-2011
20110233772SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor element includes: a substrate having an integrated circuit; and a wire connection electrode and a bump connection electrode which are provided on a same main surface of the substrate as electrodes having a same connection function to the integrated circuit. The wire connection electrode is provided in a periphery of the main surface. The bump connection electrode is provided inside the wire connection electrode on the main surface. When a straight line dividing the main surface into two regions is determined, the wire connection electrode and the bump connection electrode are located opposite to each other with respect to the straight line.09-29-2011
20110233771SEMICONDUCTOR PACKAGES HAVING WARPAGE COMPENSATION - A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.09-29-2011
20110233769SEMICONDUCTOR DEVICE PROVIDED WITH TIN DIFFUSION INHIBITING LAYER, AND MANUFACTURING METHOD OF THE SAME - A semiconductor device is disclosed wherein a tin diffusion inhibiting layer is provided above the land of a wiring line, and a solder ball is provided above the tin diffusion inhibiting layer. Thus, even when this semiconductor device is, for example, a power supply IC which deals with a high current, the presence of the tin diffusion inhibiting layer makes it possible to more inhibit the diffusion of tin in the solder ball into the wiring line.09-29-2011
20110233770CHIP PACKAGE - A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.09-29-2011
20110233768SEMICONDUCTOR DEVICE - A semiconductor device includes: an interconnection substrate on which a semiconductor chip is mounted; electrodes formed on a surface of the interconnection substrate; and solder bumps formed on the electrodes. The solder bump includes a base section and a surface layer section that covers the base section. The surface layer section includes conductive metal selected from the group consisting of Cu, Ni, Au, and Ag, and Sn at least and a ratio of the number of atoms of the conductive metal to the number of Sn atoms per a unit volume is more than 0.01.09-29-2011
20110233761CU PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE - Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof.09-29-2011
20110233767SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The semiconductor device manufacturing method includes the steps of attaching two or more solder particles on at least one electrode among a plurality of electrodes of an electronic component, arranging the electrode of the electronic component and an electrode of a circuit board so as to oppose each other, abutting the solder particles attached on a surface of the electrode of the electronic component to the electrode of the circuit board and heating the solder particles, and connecting electrically the electrode of the electronic component and the electrode of the circuit board via two or more solder joint bodies made by melting the solder particles.09-29-2011
20110233766Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections - A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump.09-29-2011
20110233765SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.09-29-2011
20110233764SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are mechanically disposed on and electrically connected to the first surface and around the cavity, wherein the active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure, wherein the bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.09-29-2011
20110233763INTEGRATED CIRCUIT SYSTEM WITH STRESS REDISTRIBUTION LAYER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate having a transistor and a metallization layer; forming a metal pad in direct contact with the metallization layer of the substrate; forming a passivation layer in direct contact with the metal pad and covering the substrate; forming a routing trace above the passivation layer in direct contact with the metal pad, and the routing trace is substantially larger than the metal pad, and the routing trace is not electrically insulated by a subsequent layer; and forming a bump connected to the metal pad with the routing trace.09-29-2011
20110233762WAFER LEVEL INTEGRATED INTERCONNECT DECAL AND MANUFACTURING METHOD THEREOF - A wafer level integrated interconnect decal manufacturing method and wafer level integrated interconnect decal arrangement. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.09-29-2011
20100314759SEMICONDUCTOR CHIP PASSIVATION STRUCTURES AND METHODS OF MAKING THE SAME - Various semiconductor chip passivation structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymeric passivation layer to a side of a semiconductor chip. The side of the semiconductor chip includes plural conductor pads. Plural openings are formed in the polymeric passivation layer to expose the plural conductor pads. Plural conductor structures are formed on the plural conductor pads.12-16-2010
20100314758THROUGH-SILICON VIA STRUCTURE AND A PROCESS FOR FORMING THE SAME - A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer.12-16-2010
20100314757SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a POP semiconductor device, a technology is provided which can increase the degree of freedom of semiconductor packages to be combined. A first metal conductive member is placed on a first wiring substrate which is a lower mounting substrate and a second metal conductive member is placed on a second wiring substrate which is an upper mounting substrate. By joining the corresponding portions of the first and second conductive members, the first and second wiring substrates are electrically coupled to each other. An electrode pad which is electrically coupled to the second conductive member and will have an upper semiconductor member 12-16-2010
20100314756Interconnect Structures Having Lead-Free Solder Bumps - An integrated circuit structure includes a semiconductor substrate, and a polyimide layer over the semiconductor substrate. An under-bump-metallurgy (UBM) has a first portion over the polyimide layer, and a second portion level with the polyimide layer. A first solder bump and a second solder bump are formed over the polyimide layer, with a pitch between the first solder bump and the second solder bump being no more than 150 μm. A width of the UBM equals one-half of the pitch plus a value greater than 5 μm.12-16-2010
20100314754METHOD OF FORMING WIRE BONDS IN SEMICONDUCTOR DEVICES - A method of forming a wire bond in a semiconductor device includes forming a first bump of a first composition proximate to a probe mark on a bond pad. A second bump of the first composition is formed adjacent to the first bump such that the first and second bumps are formed away from the probe mark. A wire of a second composition that is harder than the first composition is attached on top of the first and second bumps to form an interconnection.12-16-2010
20130175681CHIP PACKAGE STRUCTURE - A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.07-11-2013
20110254152CHIP STRUCTURE, CHIP BONDING STRUCTURE USING THE SAME, AND MANUFACTURING METHOD THEREOF - An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a chip body and at least one bump. The chip body has at least one conducting area on its surface. The bump is formed on the conducting area of the chip body. The bump includes a plurality of protrusions and at least one conducting material. The protrusions protrude out of the conducting area and are spaced apart from each other. The conducting material covers the protrusions and electrically connects the conducting area. The method includes: (A) providing a chip body having a conducting area on its surface; (B) forming a plurality of protrusions on the chip body, wherein the protrusions protrude out of the conducting area and are spaced apart from each other; and (C) forming at least one conducting material, wherein the conducting material covers the protrusions and electrically connects the conducting area.10-20-2011
20130154088Integrated Circuits with Components on Both Sides of a Selected Substrate and Methods of Fabrication - Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.06-20-2013
20130154089BUMP INCLUDING DIFFUSION BARRIER BI-LAYER AND MANUFACTURING METHOD THEREOF - Provided herein is a bump including a diffusion barrier bi-layer, the bump having: a conductive layer; a first diffusion barrier layer formed on or above the conductive layer, and comprising an alloy of nickel and phosphorus; a second diffusion barrier formed on or above the first diffusion barrier layer, and comprising copper; and a solder layer formed on or above the second diffusion barrier layer. A manufacturing method for producing a bump is also provided.06-20-2013
20130154090Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties - A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.06-20-2013
20130181347Bump Pad Structure - An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.07-18-2013
20130181344SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING THE SEMICONDUCTOR MODULE, AND MOBILE APPARATUS - Bump electrodes and wiring layers are formed by selectively removing a copper sheet while the copper sheet is being held on a supporting base by an adhesion layer. Subsequently, a device mounting board is formed by laminating an insulating resin layer in such a manner that Au/Ni layers are exposed on the bump electrodes and the adhesion layer. The device mounting board and a semiconductor device held on the supporting base are temporarily press-bonded to each other and then the supporting base and the adhesion layer are removed. Then the device mounting board and the semiconductor device are finally and permanently press-bonded together.07-18-2013
20130181346BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer.07-18-2013
20110278722SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: an electrode pad formed in a chip region on a substrate; and a protruding portion continuously formed in a region outside the electrode pad within the chip region so as to surround a region inside the chip region. The protruding portion is higher than the electrode pad.11-17-2011
20110278716METHOD OF FABRICATING BUMP STRUCTURE - A method for fabricating bump structure forms an under-bump metallurgy (UBM) layer in an opening of an encapsulating layer, and then forms a bump layer on the UBM layer within the opening of the encapsulating layer. After removing excess material of the bump layer from the upper surface of the encapsulating layer, the encapsulating layer is removed till a top portion of the bump layer protrudes from the upper surface of the encapsulating layer.11-17-2011
20130119537SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a wiring board, a semiconductor chip mounted on the wiring board, the semiconductor chip including a bump formation surface, a plurality of first bumps provided within a first region of the bump formation surface, the first bumps being arranged in a first area density, a plurality of second bumps provided within a second region of the bump formation surface, the second bumps being arranged in a second area density, and a plurality of third bumps arranged between the first region and the second region of the bump formation surface in a two-dimensional array. The plurality of third bumps are arranged in a third area density being higher than the second area density and being lower than the first area density.05-16-2013
20130119532Bumps for Chip Scale Packaging - A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.05-16-2013
20130119533Package for Three Dimensional Integrated Circuit - A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.05-16-2013
20110309500Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask - A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.12-22-2011
20110309499METHOD OF MANUFACTURING DEVICES - A method of manufacturing a device includes forming a covering layer having affinity for a filler to be injected into a space between a first base and a second base, on at least one of the opposing surfaces of the first base and the second base, and then injecting the filler into the space between the first base and the second base.12-22-2011
20110309498SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a bump electrode, a first insulating layer formed on the semiconductor substrate and arranged to a lateral direction of the bump electrode, a first wiring layer formed on the first insulating layer and connected to the bump electrode, a second insulating layer formed on the first wiring layer, a via hole formed in the second insulating layer, and reaching the first wiring layer, a second wiring layer formed on the second insulating layer and connected to the first wiring layer via a via conductor formed in the via hole, and an external connection terminal connected to the second wiring layer, wherein an elastic modulus of the second insulating layer is set lower than an elastic modulus of the first insulating layer.12-22-2011
20110309497Multi-chip stack package structure - A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.12-22-2011
20110309496Multi-chip stack package structure - A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.12-22-2011
20110309495Multi-chip stack package structure - A multi-chip stack package structure comprises a substrate, which has a chip placement area defined on its upper surface and a plurality of contacts disposed outside the chip placement area; a first chip is disposed in the chip placement area with the rear surface, a plurality of first pads being disposed on the active surface and a plurality of first bumps each being formed on one of the first pads; a plurality of metal wires connect the first bumps to the contacts; a second chip with a plurality of second pads being disposed on the active surface and a plurality of second bumps each being formed on one of the second pads, the second chip being mounted to the first chip with its active surface facing the active surface of the first chip, wherein the second bumps correspondingly connect the metal wires and the first bumps respectively.12-22-2011
20110309494SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - Various embodiments of the present invention include a semiconductor device and a fabrication method therefor, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefor, in which downsizing and cost reduction can be realized.12-22-2011
20110309493Electronic Device Package Locking System and Method - Device and method for an electronic device package is disclosed. The electronic device package includes a first pad, a second pad and an encapsulation surrounding the first and second pad, wherein the encapsulation includes a first opening underneath the first pad and a second opening underneath the second pad. A first bump is arranged in the first opening and a second bump is arranged in the second opening, wherein the encapsulation mechanically locks the first bump to the first pad and the second bump to the second pad.12-22-2011
20110309492INTEGRATED CIRCUIT SYSTEM WITH RECESSED THROUGH SILICON VIA PADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate with a face surface having a via therein and a back surface having a trench therein; filling the via with a conductive pillar; forming a recessed contact pad in the trench; filling the recessed contact pad partially with solder; and forming an under-bump metal having a base surface in electrical contact with the conductive pillar, and having sides that extend away from the face surface of the substrate and further extend beyond the base surface.12-22-2011
20110309491TUNGSTEN STIFFENER FOR FLEXIBLE SUBSTRATE ASSEMBLY - A flexible semiconductor package is formed by interposing a flexible substrate between a tungsten stiffener and a die. A tungsten stiffener is bonded to a first surface of the flexible substrate prior to flip chip bonding or die attach of a die to a second surface of the flexible substrate. The tungsten stiffener is dimensioned so as to substantially overlap the die and provide a rigid and flat surface on which the die/flexible substrate bonding occurs. The flat and rigid characteristic of a tungsten stiffener optimizes the electrical and mechanical bond between the die and the flexible substrate as well as minimizing CTE mismatch.12-22-2011
20110309490Plasma Treatment for Semiconductor Devices - A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.12-22-2011
20130187268Semiconductor Packaging Structure and Method - A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.07-25-2013
20130187269PACKAGE ASSEMBLY AND METHOD OF FORMING THE SAME - A package assembly including a semiconductor die electrically coupled to a substrate by an interconnected joint structure. The semiconductor die includes a bump overlying a semiconductor substrate, and a molding compound layer overlying the semiconductor substrate and being in physical contact with a first portion of the bump. The substrate includes a no-flow underfill layer on a conductive region. A second portion of the bump is in physical contact with the no-flow underfill layer to form the interconnected joint structure.07-25-2013
20130187267INCREASED SURFACE AREA ELECTRICAL CONTACTS FOR MICROELECTRONIC PACKAGES - A multilayer microelectronic device package includes one or more vertical electrical contacts. At least one semiconductor material layer is provided having one or more electrical devices fabricated therein. An electrical contact pad can be formed on or in the semiconductor material layer. Another material layer is positioned adjacent to the semiconductor material layer and includes a conductive material stud embedded in or bonded to the layer. A via is formed through at least a portion of the semiconductor material layer and the electrical contact pad and into the adjacent layer conducting material stud. The via is constructed such that the via tip terminates within the conducting material stud, exposing the conducting material. A metallization layer is disposed in the via such that the metallization layer contacts both the electrical contact pad and the conducting material stud exposed by the via tip.07-25-2013
20130187266INTEGRATED CIRCUIT PACKAGE ASSEMBLY AND METHOD OF FORMING THE SAME - An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit package and the second integrated circuit package. At least one support structure is disposed between the first integrated circuit package and the second integrated circuit package to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical signal connections.07-25-2013
20130187265PACKAGE STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF - A semiconductor structure comprises a carrier, a plurality of under bump metallurgy layers, a plurality of copper containing bumps and an organic barrier layer, wherein the carrier comprises a protective layer and a plurality of conductive pads, mentioned protective layer comprises a plurality of openings, the conductive pads exposed by the openings, mentioned under bump metallurgy layers being formed on the conductive pads, mentioned copper containing bumps being formed on the under bump metallurgy layers, each of the copper containing bumps comprises a top surface and a ring surface in connection with the top surface, mentioned organic barrier layer having a first coverage portion, and mentioned first coverage portion covers the top surface and the ring surface of each of the copper containing bumps.07-25-2013
20120001325Semiconductor Device and Method of Forming Compliant Stress Relief Buffer Around Large Array WLCSP - A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-l