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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257678000 - HOUSING OR PACKAGE

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Class / Patent application numberDescriptionNumber of patent applications / Date published
257724000 With discrete components 17
257725000 With electrical isolation means 3
20090072389STRUCTURE AND METHOD FOR FORMING A CAPACITIVELY COUPLED CHIP-TO-CHIP SIGNALING INTERFACE - A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a dielectric layer interposed between the first device and the second device, a first conductive pad positioned in the first device, and a second conductive pad positioned in the second device that capacitively communicate signals from the second device to the first device. In another embodiment, a method of forming a SiP device includes forming a first pad on a surface of a first semiconductor device, forming a second pad on a surface of a second semiconductor device, and interposing a dielectric layer between the first semiconductor device and the second semiconductor device that separates the first conductive signal pad and the second conductive signal pad.03-19-2009
20100148359Package on Package Assembly using Electrically Conductive Adhesive Material - Packages are joined together using an anisotropic conductive material that includes an electrically insulative component and a plurality of electrically conductive particles. The electrically conductive particles may complete electrical connection between inter-package connectors and bond pads that may otherwise fail. The electrically insulative component may be cured to act as an underfill to provide mechanical connection between the packages.06-17-2010
20080224306MULTI-CHIPS PACKAGE AND METHOD OF FORMING THE SAME - The present invention provides a structure of multi-chips package comprising: a substrate with a die receiving cavity formed within an upper surface of the substrate and a first through holes structure, wherein terminal pads are formed under the first through holes structure. A first die is disposed within the die receiving cavity and a first dielectric layer is formed on the first die and the substrate. A first re-distribution conductive layer (RDL) is formed on the first dielectric layer. A second dielectric layer is formed over the first RDL. A third dielectric layer is formed under a second die. A second re-distribution conductive layer (RDL) is formed under the third dielectric layer. A fourth dielectric layer is formed under the second RDL. Conductive bumps are coupled to the first RDL and the second RDL. A surrounding material surrounds the second die. The second die is coupled to the first die through the first RDL, second RDL and the conductive bumps.09-18-2008
Entries
DocumentTitleDate
20110175219METHOD FOR MODULAR ARRANGEMENT OF A SILICON BASED ARRAY AND MODULAR SILICON BASED ARRAY - A silicon based module, including: a substrate; a first chip assembly fixed to the substrate, the first chip assembly including a first silicon chip and a first driver die having electrical circuitry; and a second chip assembly fixed to the substrate, the second chip assembly including a second silicon chip and a second driver die having electrical circuitry. Portions of the first and second chip assemblies are aligned in a longitudinal direction for the substrate; and portions of the first and second silicon chips are aligned in a width direction orthogonal to the longitudinal direction. Method for forming a silicon based module.07-21-2011
20130037932Flange for Semiconductor Die - A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.02-14-2013
20100117225SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.05-13-2010
20100117224Sensor - A sensor die in a sensor device includes a conformal dielectric coating over at least a die sidewall adjacent an interconnect edge and, in some devices, a conformal dielectric coating over at least part of the active area of the front side of the die. The sensor die can be connected to circuitry in a support by an electrically conductive material that is applicable in a flowable form, such as a curable electrically conductive polymer, which is applied onto or adjacent the dielectric coating on the die sidewall, and which is cured to complete connection between interconnect pads on the die and exposed sites on the support circuitry. In some devices, a coating over the active area of the sensor die provides mechanical and chemical protection for underlying structures in and on the die. In an image sensor device, for example, the coating over the image sensor array on the die is substantially optically transparent. Also, a package contains such a sensor die mounted on and electrically connected to a support; and assemblies include such a sensor die and additional die mounted on and electrically connected to opposite sides of a support. Also, methods are disclosed for making the sensor die, devices, packages, and assemblies.05-13-2010
20100072613INKJET PRINTED LEADFRAME - Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.03-25-2010
20090121345SILICON INTERPOSER PRODUCING METHOD, SILICON INTERPOSER AND SEMICONDUCTOR DEVICE PACKAGE AND SEMICONDUCTOR DEVICE INCORPORATING SILICON INTERPOSER - A silicon interposer producing method comprising the steps of forming through holes 05-14-2009
20100044857WLCSP TARGET AND METHOD FOR FORMING THE SAME - The invention provides a Wafer Level Chip Size Packaging (WLCSP) target and a method for forming it. A WLCSP target is formed by recombining single chips, wafer parts each including two or more chips or half finished packaging targets which have been subjected to at least one previous step of packaging onto a first substrate, or bonding a wafer part which is formed by dicing a whole wafer and includes at least two chips to a second substrate for bonding. Thus, a wafer with a larger size can be packaged through the WLCSP on a WLCSP apparatus with a smaller size while benefiting from the advantages of the WLCSP, the WLCSP apparatus remains applicable within a longer period of time, the cost is lowered, and enterprises may keep up with the development of the market and the increase of the wafer size without having to update the WLCSP apparatus substantially.02-25-2010
20090079064METHODS OF FORMING A THIN TIM CORELESS HIGH DENSITY BUMP-LESS PACKAGE AND STRUCTURES FORMED THEREBY - Methods of forming microelectronic device structures are described. Those methods may include placing a plurality of support rings onto a tacky layer of a support carrier, wherein the support rings are disposed within a cavity of the support carrier; placing a plurality of thin die onto a pedestal of the support carrier, wherein a top surface of the thin die is substantially flush with at top surface of the support ring; and then building up layers on the top surface of the die.03-26-2009
20090267224CIRCUIT DEVICE INCLUDING ROTATED STACKED DIE - In a particular embodiment, a circuit device includes a first die coupled to a circuit substrate and having a substantially planar surface. The first die includes electrical contacts distributed on the substantially planar surface adjacent to at least three edges of the first die. The circuit device further includes a second die attached to the substantially planar surface of the first die. The second die is rotated by an offset angle about an axis relative to the first die. The offset angle is selected to allow horizontal and vertical access to the electrical contacts.10-29-2009
20090236736MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality of through holes in a substrate with the through holes arranged in arrays, and attaching a plurality of singulated microelectronic dies to the substrate with an active side of the individual dies facing toward the substrate and with a plurality of terminals on the active side of the individual dies aligned with corresponding holes in the substrate. The singulated dies are attached to the substrate after forming the holes in the substrate.09-24-2009
20090236735UPGRADEABLE AND REPAIRABLE SEMICONDUCTOR PACKAGES AND METHODS - A semiconductor device package includes a carrier, one or more semiconductor devices on the carrier, and a redistribution element above the uppermost of the one or more semiconductor devices. The redistribution element includes an array of contact pads that communicate with each semiconductor device of the package. The package may also include an encapsulant through which the contact pads of the redistribution element are at least electrically exposed. Methods for assembling and packaging semiconductor devices, as well as methods for assembling multiple packages, including methods for replacing the functionality of one or more defective semiconductor devices of a package according to embodiments of the present invention, are also disclosed.09-24-2009
20090236734Semiconductor Device With Cross-Talk Isolation Using M-CAP and Method Thereof - A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.09-24-2009
20090121344SILICON INTERPOSER AND SEMICONDUCTOR DEVICE PACKAGE AND SEMICONDUCTOR DEVICE INCORPORATING THE SAME - A silicon interposer 05-14-2009
20100181665System and Method of Achieving Mechanical and Thermal Stability in a Multi-Chip Package - A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.07-22-2010
20100078808PACKAGING HAVING TWO DEVICES AND METHOD OF FORMING THEREOF - A method of forming a semiconductor package includes providing a carrier, attaching a first surface of a first device on the carrier, wherein the first surface comprises a first active surface of the first device, and attaching a second surface of a second device on the carrier. In one embodiment, the second surface is opposite a third surface of the second semiconductor die and the third surface comprises a second active surface. A first insulating material can be formed between the first device and the second device.04-01-2010
20100123242INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT CARRIER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a semiconductor package system includes: attaching an internal stacking module die to a surface of an internal stacking module substrate having an internal stacking module bonding pad along an edge of an opposite surface thereof; and attaching a support carrier to support the internal stacking module substrate by two edges thereof with the internal stacking module bonding pad exposed.05-20-2010
20090001562SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a module including a first carrier having a first mounting surface and a second mounting surface, a first semiconductor chip mounted onto the first mounting surface of the first carrier and having a first surface facing away from the first carrier, a first connection element connected to the first surface of the first semiconductor chip, a second semiconductor chip having a first surface facing away from the first carrier, a second connection element connected to the first surface of the second semiconductor chip, and a mold material covering the first connection element and the second connection element only partially.01-01-2009
20100084762MEMORY CARD - Memory card (04-08-2010
20100078809Semiconductor Module with Micro-Buffers - The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die.04-01-2010
20100007014SEMICONDUCTOR DEVICE - According to an aspect of the invention, a semiconductor device includes: a semiconductor substrate; a memory chip disposed on the semiconductor substrate, the memory chip including: a first face that is not opposed to the semiconductor substrate; and a plurality of first pads disposed on the first face so that the first pads are aligned along a virtual line passing at a central portion on the first face; a controller chip disposed on the first face not to cover the first pads, the controller chip including: a second face that is not opposed to the first face; and a plurality of second pads disposed on the second face so that the second pads are aligned along at least one side of the second face; and a plurality of metal wires electrically connecting the first pads and the second pads.01-14-2010
20090091022SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR CHIP ASSEMBLY, AND METHOD FOR FABRICATING A DEVICE - A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element.04-09-2009
20090134511Multiple Size Package Socket - Various sockets for multiple sizes of chip package substrates are disclosed. In one aspect, an apparatus is provided that includes a socket that has a peripheral wall defining an interior space adapted to receive either of a first semiconductor chip package substrate and a second semiconductor chip package substrate. The first semiconductor chip package substrate has a first size and a first plurality of structural features and the second semiconductor chip package substrate has a second size different than the first size and a second plurality of structural features. The socket has a third plurality of structural features operable to engage the structural features of either of semiconductor chip package substrates to selectively enable the first semiconductor chip package substrate to be located at a first preselected position in the interior space and the second semiconductor chip package substrate to be located at a second preselected position in the interior space.05-28-2009
20090294957APPARATUS AND METHOD FOR INCREASING THE QUANTITY OF DISCRETE ELECTRONIC COMPONENTS IN AN INTEGRATED CIRCUIT PACKAGE - An apparatus and method for incorporating discrete passive components into an integrated circuit package. A first surface of a substrate is coated with a material to mechanically protect the first surface. A first metal layer and then an insulating layer are formed on a second surface of the substrate. Selected areas are removed from the insulating and a second metal layer is formed over the insulating layer and the exposed metal layer. Selected areas of the second metal layer are removed to form a plurality of structures, including at least one of a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which an electronic component may be attached. An electronic component may be attached to at least one of the structures. The resulting integrated circuit die may be incorporated into an electronic package.12-03-2009
20090289354ELECTRONIC MODULE - An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 μm.11-26-2009
20080277781MULTI-DIE MOLDED SUBSTRATE INTEGRATED CIRCUIT DEVICE - One embodiment includes a substrate having a plurality of dies and a support frame made of molding material which is molded between adjacent dies so as to join together and support adjacent dies. The embodiment further has a plurality of interconnects formed on selected die terminals and the molding material of the support frame joining adjacent dies. The interconnects may be formed utilizing a variety of techniques including those of the type used in conventional wafer fabrication techniques. Other embodiments are described and claimed.11-13-2008
20080284002INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THIN PROFILE - An integrated circuit package system is provided including attaching an external interconnect on a tape; attaching a backside element on the tape adjacent to the external interconnect; attaching an integrated circuit die with the backside element, the backside element is on a first passive side of the integrated circuit die; connecting a first active side of the integrated circuit die and the external interconnect; and forming a first encapsulation over the integrated circuit die with the backside element exposed.11-20-2008
20080308928Image sensor module with a three-dimensional die-stacking structure - This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.12-18-2008
20080203560Semiconductor device - A semiconductor device is produced using a housing having a hollow cavity for embracing a semiconductor sensor chip (e.g., a microphone chip) for detecting pressure variations and an LSI chip for driving the semiconductor sensor chip, both of which are mounted on a chip mount surface. An opening allowing the cavity to communicate with external space is formed at a prescribed position of the chip mount surface within the housing, wherein the LSI chip is positioned above the opening so as to cover at least a part of the opening of the housing. Thus, it is possible to reduce negative influences of environmental factors applied to the semiconductor sensor chip without using an environmental barrier, and it is possible to downsize the semiconductor device.08-28-2008
20090057884Multi-Chip Package - Various semiconductor chip packages and package lids are disclosed. In one aspect, a method of manufacturing is provided that includes forming a semiconductor chip package lid with a peripheral wall that defines a first interior space. A first bridge structure is formed in the first interior space. The first bridge structure is adapted to engage a surface of a substrate.03-05-2009
20090278253Semi-finished package and method for making a package - The present invention relates to a semi-finished package and a method for making a package. The semi-finished package includes a carrier and at least one molding compound. The molding compound is disposed on a surface of the carrier, and has a body and a plurality of outer protrusions. The outer protrusions are disposed at the periphery of the body, and the height of the outer protrusions is greater than that of the body. Thus, by utilizing the outer protrusions, the rigidity of the semi-finished package is increased, so as to overcome the warpage of the semi-finished package caused by different coefficients of thermal expansion of the molding compound and the carrier. Therefore, the yield rate of the package unit is increased.11-12-2009
20090085199INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLD LOCK SUBASSEMBLY - An integrated circuit package system includes: providing a substrate; attaching an integrated circuit over the substrate; attaching an integrated circuit subassembly system having a perforated interposer over the substrate with the perforated interposer having a slot; and forming a package encapsulation over the integrated circuit subassembly system, the perforated interposer, the integrated circuit, and the substrate with the slot filled with the package encapsulation.04-02-2009
20090200662SEMICONDUCTOR PACKAGE AND METHOD OF MAKING THE SAME - The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.08-13-2009
20090212419INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OVERHANG FILM - An integrated circuit package system includes: connecting a first interconnect between a carrier and a bottom integrated circuit thereover; forming a film, having an overhang portion, over the bottom integrated circuit with the overhang portion over the first interconnect; mounting a top integrated circuit over the film; connecting a second interconnect between the top integrated circuit and the carrier with the overhang portion between the first interconnect and the second interconnect; and forming an encapsulation over the carrier covering the top integrated circuit, the film, the first interconnect, and the second interconnect.08-27-2009
20080315406INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CAVITY SUBSTRATE - An integrated circuit package system includes a base substrate having a base substrate cavity, attaching a junction integrated circuit package over the base substrate with a portion of the junction integrated circuit package in the base substrate cavity, and attaching a base integrated circuit over the junction integrated circuit package and the base substrate.12-25-2008
20090096088SEALED WAFER PACKAGING OF MICROELECTROMECHANICAL SYSTEMS - Multiple microelectromechanical systems (MEMS) on a substrate are capped with a cover using a layer that may function as a bonding agent, separation layer, and hermetic seal. A substrate has a first side with multiple MEMS devices. A cover is formed with through-holes for vias, and with standoff posts for layer registration and separation. An adhesive sheet is patterned with cutouts for the MEMS devices, vias, and standoff posts. The adhesive sheet is tacked to the cover, then placed on the MEMS substrate and heated to bond the layers. The via holes may be metalized with leads for circuit board connection. The MEMS units may be diced from the substrate after sealing, thus protecting them from contaminants.04-16-2009
20090243087SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.10-01-2009
20090250809Semiconductor package having thermal stress canceller member - A semiconductor package includes a package-substrate, a first cavity formed on a first main surface of the package substrate, a first semiconductor chip mounted on the bottom surface of the first cavity, a first resin layer filled into the first cavity, and a thermal stress canceller member mounted on the package substrate for cancelling the thermal stress caused by the difference in the thermal expansion rates between the package substrate and mounting section including a first semiconductor chip and a first resin layer. The thermal stress canceller member may include a second cavity, a second resin layer filled into the second cavity, and a semiconductor chip.10-08-2009
20100230806Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors - A semiconductor device is made by forming a plurality of conductive pillars vertically over a temporary carrier. A conformal insulating layer is formed over the conductive pillars. A conformal conductive layer is formed over the conformal insulating layer. A first conductive pillar, conformal insulating layer, and conformal conductive layer constitute a vertically oriented integrated capacitor. A semiconductor die or component is mounted over the carrier. An encapsulant is deposited over the semiconductor die or component and around the conformal conductive layer. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure includes an integrated passive device. The first interconnect structure is electrically connected to the semiconductor die or component and vertically oriented integrated capacitor. The carrier is removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first side of the encapsulant.09-16-2010
20100001398SEMICONDUCTOR CHIP MODULE AND MANUFACTURING METHOD THEREOF - A semiconductor chip module includes a first flip-chip unit and a second flip-chip unit. The first flip-chip unit has a first chip and a first glass circuit board. The first chip is connected with the first glass circuit board by flip-chip bonding. The second flip-chip unit has a second chip and a second glass circuit board. The second chip is connected with the second glass circuit board by flip-chip bonding. The first flip-chip unit and the second flip-chip unit are attached to each other. A method for manufacturing the semiconductor chip module is also disclosed.01-07-2010
20100001397SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of NAND memory dies each including: a first wiring layer formed in the NAND memory die; a second wiring layer formed in the NAND memory die; a first insulation layer formed between the first wiring layer and the second wiring layer; and a first interlayer connector formed in the first insulation layer, a controller configured to control the NAND memory dies; a package housing the NAND memory dies and the controller; a connecting portion electrically connecting an inner side of the package and an outer side of the package; a first connecting wire; and a second connecting wire, wherein a resistance value per unit length of the first interlayer connector is larger than a resistance value per unit length of the first wiring layer, and wherein the first interlayer connector is cut off when a first current flows through the first interlayer connector.01-07-2010
20100001396REPAIRABLE SEMICONDUCTOR DEVICE AND METHOD - Repairable semiconductor device and method. In one embodiment a method, provides a first body having a first semiconductor chip and a first metal layer. A second body includes a second semiconductor chip and a second metal layer. Metal of the first metal layer is removed. The first semiconductor chip is removed from the first body. The second body is attached to the first body. The first metal layer is electrically coupled to the second metal layer.01-07-2010
20100224992SYSTEM AND METHOD FOR STACKED DIE EMBEDDED CHIP BUILD-UP - An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip.09-09-2010
20090250810INTEGRATED CIRCUIT PACKAGING SYSTEM WITH WARPAGE CONTROL SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system is provided including: providing a substrate; and placing a patterned layer over the substrate for substantially removing crying warpage from the substrate.10-08-2009
20080303139CHIP-IN-SLOT INTERCONNECT FOR 3D CHIP STACKS - A chip-in-slot interconnect for three-dimensional semiconductor chip stacks, and particularly having the ability of forming edge connections on semiconductor chips, wherein the semiconductor chips are mounted in one or more chip carriers which are capable of being equipped with embedded circuitry. Moreover, provision is made for unique methods for producing the edge connections on the semiconductor chips, for creating a semiconductor chip carrier, and for producing a novel semiconductor and combined chip carrier structure.12-11-2008
20080265408Highly Reliable Low Cost Structure for Wafer-Level Ball Grid Array Packaging - Methods, systems, and apparatuses for wafer-level integrated circuit (IC) packages are described. An IC package includes an IC chip, an insulating layer on the IC chip, a plurality of vias, a plurality of routing interconnects, and a plurality of bump interconnects. The IC chip has a plurality of terminals configured in an array on a surface of the IC chip. A plurality of vias through the insulating layer provide access to the plurality of terminals. Each of the plurality of routing interconnects has a first portion and a second portion. The first portion of each routing interconnect is in contact with a respective terminal of the plurality of terminals though a respective via, and the second portion of each routing interconnect extends over the insulating layer. Each bump interconnect of the plurality of bump interconnects is connected to the second portion of a respective routing interconnect of the plurality of routing interconnects.10-30-2008
20090108440SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.04-30-2009
20110024897METHOD OF ASSEMBLING SEMICONDUCTOR DEVICES WITH LEDS - Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package.02-03-2011
20100164094Multi-Chip Package Memory Device - Provided is a multi-chip package memory device. The multi-chip package memory device may include a transmission memory chip and a plurality of memory chips that are stacked on the transmission memory chip. The transmission memory chip may include a temporary storage unit, and may transmit a received command or received data to a corresponding memory chip, or to an external element. Each of the memory chips may include a memory core, and may delay the received command according to the properties of the memory chips and then may output delay commands. The transmission memory chip may store the received data in different portions of the temporary storage unit when the delay commands are respectively received.07-01-2010
20100213607INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple Microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the Microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate. Molding material is applied over the top surface of the substrate and the Microsystems to form a molded structure. Portions of the substrate can be removed. The molded structure can be singulated to form individual integrated circuit packages. Each of the integrated circuit packages contains at least one microsystem. Various embodiments involve forming conductive pads on the top surface of the substrate instead of the metal vias.08-26-2010
20090218683Semiconductor Device - The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.09-03-2009
20090218682SEMICONDUCTOR CHIP - An integrated circuit package comprising at least one semiconductor chip of a first material, wherein the semiconductor chip comprises an active part and a passive part that is connected to each other, the passive part comprises at least one cavity, the at least one cavity is filled with a filler of a second material, and the thermal conductivity of the second material is higher than the thermal conductivity of the first material.09-03-2009
20110074011MECHANICAL COUPLING IN A MULTI-CHIP MODULE USING MAGNETIC COMPONENTS - A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates.03-31-2011
20090001563INTEGRATED CIRCUIT PACKAGE IN PACKAGE SYSTEM WITH ADHESIVELESS PACKAGE ATTACH - An integrated circuit package in package system includes a package in package lead with a package in package lead surface substantially planar, attaching a first integrated circuit package having a first encapsulant surface substantially coplanar with the package in package lead surface, attaching a second integrated circuit near the first integrated circuit package, and forming a package in package encapsulant over the first integrated circuit package and the second integrated circuit.01-01-2009
20100244238SEMICONDUCTOR DEVICE - There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips are disposed in an alternating sequence.09-30-2010
20080251912Multi-Chip Module - A multi-chip module includes at least one integrated circuit chip that is electrically connected to first external terminals of the multi-chip module and at least one power semiconductor chip that is electrically connected to second external terminals of the multi-chip module. All first external terminals of the multi-chip module are arranged in a contiguous region of an terminal area of the multi-chip module.10-16-2008
20110068464INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a component over the base substrate; attaching a component interconnect to the base substrate and a perimeter of the component; mounting a stack device over the component; attaching a base exposed interconnect directly on the component and next to the component interconnect; and forming a base encapsulation over the base substrate, the component, and the component interconnect, the base exposed interconnect partially exposed from the base encapsulation.03-24-2011
20080217765SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component comprising two stacked semiconductor dice and a method of manufacture. A leadframe having an active area that includes leadframe leads and a cavity is mounted to a support material such as an adhesive tape. A packaged semiconductor die that includes a first semiconductor die mounted to a support structure and encapsulated within a mold compound is mounted on the adhesive tape. A second semiconductor die is mounted to the packaged semiconductor die. Bond pads on the second semiconductor die are electrically connected to the leadframe, the support structure on which the first semiconductor die is mounted, or both. A mold compound is formed around the second semiconductor die, portions of the leadframe, and the packaged semiconductor die. The adhesive tape is removed and the leadframe is singulated to form multi-chip packages.09-11-2008
20110147921Flange for Semiconductor Die - A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.06-23-2011
20120146211SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.06-14-2012
20080211089Interposer for die stacking in semiconductor packages and the method of making the same - Methods and apparatus for improved electrical, mechanical and thermal performance of stacked IC packages are described. An IC package comprises a substrate, a first die, a second die, and an interposer with an opening in a first surface of the interposer configured to accommodate the first die. The first IC die is attached a first surface of the substrate. The interposer is mounted on the first surface of the substrate such that the first IC die is placed within the opening in the interposer. The second die is mounted on a second surface of the interposer. Wire bonds couple bond pads on the first surfaces of IC die are coupled to the first surface of the substrate. A mold compound encapsulates the first IC die, the second IC die, the interposer and the wire bonds.09-04-2008
20090174066SEMICONDUCTOR DEVICE - In a multi-chip package semiconductor device, a drive chip having an analog circuit and a logic chip having a digital circuit are mounted within the same package. The driver chip includes a logic-chip power-supply circuit that makes up a logic-chip power supply for the logic chip and a group of operational amplifiers that amplify detection signals from a plurality of sensors. The driver chip has the shape of a square as a whole, and the plurality of operational amplifiers and the logic-chip power-supply circuit are disposed in diagonally opposed positions.07-09-2009
20110115072ULTRAVIOLET ENERGY CURABLE TAPE AND METHOD OF MAKING A SEMICONDUCTOR CHIP USING THE TAPE - There is provided a UV energy curable tape comprising an adhesive material including a UV energy curable oligomer, a UV energy initiator, and a material which emits optical light when the tape composition is substantially fully cured. A semiconductor chip made using the tape is also provided.05-19-2011
20120146210COMPLIANT INTERCONNECTS IN WAFERS - A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.06-14-2012
20080217766ACOUSTIC TRANSDUCER MODULE09-11-2008
20090134512METHOD OF PRODUCING MULTIPLE SEMICONDUCTOR DEVICES - A method for producing multiple semiconductor devices. An electrically conductive layer is applied onto a semiconductor wafer. The semiconductor wafer is structured to produce multiple semiconductor chips. The electrically conductive layer is structured to produce multiple semiconductor devices.05-28-2009
20110180926Microelectromechanical Systems Embedded in a Substrate - An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device.07-28-2011
20090057885SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a semiconductor chip having a main surface, wherein a first molding compound accommodates the semiconductor chip. The first molding compound has a surface that is substantially coplanar to the main surface of the semiconductor chip. A second molding compound is arranged in a space between the first molding compound and the semiconductor chip.03-05-2009
20120241944MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The structure includes a lid encapsulating at least one chip mounted on a chip carrier; at least one seal shim fixed between the lid and the chip carrier, the at least one seal shim forming a gap between pistons of the lid and respective ones of the chips; and thermal interface material within the gap and contacting the pistons of the lid and respective ones of the chips.09-27-2012
20080237848SEMICONDUCTOR DEVICE - There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips are disposed in an alternating sequence.10-02-2008
20080224305METHOD, APPARATUS, AND SYSTEM FOR PHASE CHANGE MEMORY PACKAGING - According to one embodiment, a die assembly is disclosed, comprising a package substrate and a plurality of stacked die on the package substrate, the plurality of stacked die including at least an uppermost die, a lowermost die, and at least one phase change memory die between the uppermost die and the lowermost die, wherein the uppermost die and lowermost die are non-functional spacer die.09-18-2008
20080197485Module comprising a semiconductor chip comprising a movable element - The invention relates to a module comprising a carrier, a first semiconductor chip applied to the carrier and having a movable element and a second semiconductor chip applied to the first semiconductor chip, wherein an active first main surface of the first semiconductor chip faces the carrier and a first cavity is formed between the two semiconductor chips.08-21-2008
20080197484Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package - In a method of manufacturing an electronic component package, first, there is fabricated a wafer incorporating a plurality of sets of external connecting terminals corresponding to a plurality of electronic component packages, and a retainer for retaining the plurality of sets of external connecting terminals, the wafer including a plurality of pre-base portions that will be separated from one another later to be bases of the electronic component packages. Next, at least one electronic component chip is bonded to each of the pre-base portions of the wafer. Next, electrodes of the electronic component chips are connected to the external connecting terminals. Next, the electronic component chips are sealed. Next, the wafer is cut so that the pre-base portions are separated from one another and the plurality of bases are thereby formed.08-21-2008
20100025845MICROMECHANICAL HOUSING COMPRISING AT LEAST TWO CAVITIES HAVING DIFFERENT INTERNAL PRESSURE AND/OR DIFFERENT GAS COMPOSITIONS AND METHOD FOR THE PRODUCTION THEREOF - The present application relates to a multiple component which is to be subsequently individualized by forming components containing active structures, in addition to a corresponding component which can be used in microsystem technology systems. The multiple component and/or component comprises a flat substrate and also a flat cap structure which are bound to each other such that they surround at least one first and one second cavity per component, which are sealed against each other and towards the outside. The first of the two cavities is provided with getter material and due to the getter material has a different internal pressure and/or a different gas composition than the second cavity. The present application also relates to a method for producing the type of component and/or components for which gas mixtures of various types of gas have a different absorption ratio in relation to the getter material.02-04-2010

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