Entries |
Document | Title | Date |
20080237843 | Microelectronic package including thermally conductive sealant between heat spreader and substrate - A microelectronic package. The package includes a substrate; a die mounted onto the substrate; an integrated heat spreader mounted onto the substrate, and thermally coupled to a backside of the die; and a sealant material bonding the integrated heat spreader to the substrate, the sealant material having a bulk thermal conductivity above about 1 W/m/° C. and a modulus of elasticity lower than a modulus of elasticity of solder. | 10-02-2008 |
20080237844 | Microelectronic package and method of manufacturing same - A microelectronic package includes a package substrate ( | 10-02-2008 |
20080258295 | Self-Contained Cooling Mechanism for Integrated Circuit Using a Reversible Endothermic Chemical Reaction - A package for a semiconductor chip or other heat producing device has a supporting substrate to which the devices mount and electrically connect. An enclosure is formed over the heat producing devices and filled with a working fluid including a chemical compound that reacts endothermically to absorb heat produced by the devices and releases the heat in a reverse reaction to the enclosure. | 10-23-2008 |
20080265406 | APPARATUS AND METHODS FOR COOLING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGES - Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers. | 10-30-2008 |
20080272483 | High power package with dual-sided heat sinking - An assembly includes a semiconductor die disposed between an upper substrate and a lower substrate. A circuit board that defines a through hole is spaced axially below the upper substrate to define a gap between the upper substrate and the circuit board. An upper heat sink is thermally connected to the upper substrate by an upper thermal interface material to transfer heat in a first dissipation path to the upper heat sink. A lower heat sink is thermally connected to the lower substrate by a lower thermal interface material to transfer heat in a second dissipation path to the lower heat sink. A plurality of first interconnectors are disposed in the gap to solder the upper substrate to the circuit board. The assembly is distinguished by a plurality of second interconnectors that are disposed between the upper substrate and the lower substrate to position the lower substrate in the through hole of the circuit board. | 11-06-2008 |
20080277778 | Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby - A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements. | 11-13-2008 |
20080290502 | INTEGRATED CIRCUIT PACKAGE WITH SOLDERED LID FOR IMPROVED THERMAL PERFORMANCE - An integrated circuit die includes a circuit surface and a back surface opposite the circuit surface. An underbump metallurgy is formed on a back surface. A layer of solder is formed on the underbump metallurgy. | 11-27-2008 |
20080290503 | Compliant thermal contactor - One embodiment of the present invention is a compliant thermal contactor that includes a resilient metal film having a plurality of first thermally conductive, compliant posts disposed in an array on a top side thereof and a plurality of second thermally conductive, compliant posts disposed in an array on a bottom side thereof. | 11-27-2008 |
20080290504 | Compliant thermal contactor - One embodiment of the present invention is a compliant thermal contactor that includes a resilient metal film having a plurality of first thermally conductive, compliant posts disposed in an array on a top side thereof and a plurality of second thermally conductive, compliant posts disposed in an array on a bottom side thereof. | 11-27-2008 |
20080290505 | MOLD DESIGN AND SEMICONDUCTOR PACKAGE - A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation. | 11-27-2008 |
20080296756 | HEAT SPREADER COMPOSITIONS AND MATERIALS, INTEGRATED CIRCUITRY, METHODS OF PRODUCTION AND USES THEREOF - Near net shape heat spreader components are disclosed that comprise at least one pressure-treated powder material. Heat spreaders are also described that include at least one near net shape heat spreader component, and at least one additional part. Methods of forming heat spreaders are also described that include: a) forming a base portion comprising a pressure-treated powder material and having a first surface comprising a perimeter region surrounding a heat-receiving surface; b) forming a frame portion comprising a second material; and c) joining the base portion and the frame portion. | 12-04-2008 |
20080296757 | Fluid spreader - A fluid spreader includes a first surface, wherein the first surface has at least one channel that continuously or discontinuously extends to an outer periphery of the first surface, allowing fluid to flow easily and thereby reducing the thickness of the fluid between the fluid spreader and another device or component. | 12-04-2008 |
20080315403 | APPARATUS AND METHODS FOR COOLING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGES - Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers. | 12-25-2008 |
20080315404 | INTEGRATED THERMAL STRUCTURES AND FABRICATION METHODS THEREOF FACILITATING IMPLEMENTING A CELL PHONE OR OTHER ELECTRONIC SYSTEM - Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer. | 12-25-2008 |
20090008771 | SEMICONDUCTOR MODULE DEVICE, METHOD OF MANUFACTURING THE SAME, FLAT PANEL DISPLAY, AND PLASMA DISPLAY PANEL - Metal foil | 01-08-2009 |
20090014866 | MULTICHIP MODULE PACKAGE AND FABRICATION METHOD - A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink. | 01-15-2009 |
20090039501 | INTEGRATED CIRCUIT WITH GALVANICALLY BONDED HEAT SINK - An integrated circuit includes a semiconductor substrate, a first electrical contact formed on the semiconductor substrate, and a first heat sink element bonded to the first electrical contact via a galvanic bond. | 02-12-2009 |
20090057879 | STRUCTURE AND PROCESS FOR ELECTRICAL INTERCONNECT AND THERMAL MANAGEMENT - A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element. The method supplies a fluid through the entrance through-hole, flows the fluid through the coolant channel between the first substrate and second substrates, and removes the fluid from the coolant channel through the exit through-hole. | 03-05-2009 |
20090057880 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, STACKED MODULE, CARD, SYSTEM AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device capable of improving the efficiency of dispersing heat via a dummy pad. The semiconductor device may be included in a semiconductor package, stack module, card, or system. Also disclosed is a method of manufacturing the semiconductor device. In the semiconductor device, a semiconductor substrate has a first surface and a second surface opposite to the first surface, and at least one conductive pad is arranged on a predetermined region of the first surface. At least one dummy pad is arranged on the first or second surface, and is not electrically coupled to the at least one conductive pad. The dummy pad or pads may be used to disperse heat. Accordingly, it is possible to increase the efficiency of dispersing heat of a semiconductor device, thereby improving the yield of semiconductor devices. | 03-05-2009 |
20090072385 | Electronic Assemblies Providing Active Side Heat Pumping and Related Methods and Structures - An electronic assembly may include a packaging substrate, an integrated circuit (IC) semiconductor chip, a plurality of metal interconnection structures, and a thermoelectric heat pump. The integrated circuit (IC) semiconductor chip may have an active side including input/output pads thereon and a back side opposite the active side, and the IC semiconductor chip may be arranged with the active side facing the first surface of the packaging substrate. The plurality of metal interconnection structures may be between the active side of the IC semiconductor chip and the first surface of the packaging substrate, and the plurality of metal interconnection structures may provide mechanical connection between the active side of the IC semiconductor chip and the first surface of the packaging substrate. The thermoelectric heat pump may be coupled to the packaging substrate with the thermoelectric heat pump being configured to actively pump heat between the IC semiconductor chip and the packaging substrate. Related methods and structures are also discussed. | 03-19-2009 |
20090085197 | Method of Fabrication of On-Chip Heat Pipes and Ancillary Heat Transfer Components - The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture. | 04-02-2009 |
20090108437 | WAFER SCALE INTEGRATED THERMAL HEAT SPREADER - Various embodiments are directed to providing an electronic device with an integrated thermal heat spreader. In one embodiment, an electronic device may comprise an integrated circuit fabricated on a substrate and a heat spreader integrated with the electronic device after fabrication of the integrated circuit. The heat spreader may comprise one or more layers of composite plating material including solid particles incorporated into a metal plating material. The composite plating material may be patterned to the substrate to define the heat spreader. Other embodiments are described and claimed. | 04-30-2009 |
20090108438 | Semiconductor device and method of manufacturing the same - Through heat discharge only by wiring connected to a conventional semiconductor chip, sufficient heat discharge performance may not be achieved in a recent semiconductor device. A semiconductor device according to an aspect of the present invention includes: a flexible substrate including a first main surface and a second main surface; a semiconductor chip; a first heat conductive layer formed on the first main surface of the flexible substrate and electrically connected to the semiconductor chip; and a second heat conductive layer formed on the second main surface of the flexible substrate and electrically insulated from the semiconductor chip. | 04-30-2009 |
20090121343 | CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES - Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure. | 05-14-2009 |
20090127701 | Thermal attach for electronic device cooling - Embodiments of thermal cooling devices and systems including dies and thermal attaches having surface features are described in this application. The thermal attach may have a surface feature, such as a pattern, to limit movement of a thermal interface material, such as thermal grease, from between the die and the thermal attachment. The restriction of movement of the thermal interface material may improve the thermal performance of cooling systems for electronic devices over many cycles as opposed to known cooling systems. Other embodiments are described. | 05-21-2009 |
20090127702 | PACKAGE, SUBASSEMBLY AND METHODS OF MANUFACTURING THEREOF - The package ( | 05-21-2009 |
20090152713 | INTEGRATED CIRCUIT ASSEMBLY INCLUDING THERMAL INTERFACE MATERIAL COMPRISED OF OIL OR WAX - Embodiments of a thermal interface material layer comprised of an oil or a wax are disclosed. The thermal interface material may be used to thermally couple an integrated circuit die to a thermal component, such as a heat spreader. Other embodiments are described and claimed. | 06-18-2009 |
20090166854 | Thermal Interface with Non-Tacky Surface - A thermal interface member includes a bulk layer and a surface layer that is disposed on at least a portion of a surface of the bulk layer. The surface layer is highly thermally conductive, has a melting point exceeding a solder reflow temperature, and has a maximum cross-sectional thickness of less than about 10 microns. | 07-02-2009 |
20090184416 | MCM packages - An RF/IPD package with improved thermal management is described. The IPD substrate is attached to a system substrate with a thin RF chip mounted in the standoff between the IPD substrate and the system substrate. RF interconnections are made between the top of the RF chip and the bottom of the IPD substrate. Heat sinking is provided by bonding a heat sink layer on the RF chip to a heat sink layer on the system substrate. The heat sink may also serve as a ground plane connection. Combinations of other types of integrated devices may be fabricated using this approach. | 07-23-2009 |
20090189276 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor chip, including: a substrate including an front surface; an integrated circuit formed on the front surface and including a plurality of semiconductor elements; and a heat-radiating plug formed in a region of the substrate corresponding to at least one of the semiconductor elements. The heat-radiating plug is made of a material having a thermal conductivity greater than that of the substrate formed in a non-penetrating hole having its opening on a reverse surface of the substrate. | 07-30-2009 |
20090218681 | Carbon nanotube and metal thermal interface material, process of making same, packages containing same, and systems containing same - A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used. | 09-03-2009 |
20090224400 | SEMICONDUCTOR ASSEMBLY HAVING REDUCED THERMAL SPREADING RESISTANCE AND METHODS OF MAKING SAME - Semiconductor assemblies having reduced thermal spreading resistance and methods of making the same are described. In an example, a semiconductor device includes a primary integrated circuit (IC) die and at least one secondary IC die mounted on the primary IC die. A heat extraction element includes a base mounted to the semiconductor device such that each of the at least one secondary IC die is between the primary IC die and the heat extraction element. At least one dummy fill is adjacent the at least one secondary IC die, and each thermally couples the primary IC die to the heat extraction element. | 09-10-2009 |
20090236733 | BALL GRID ARRAY PACKAGE SYSTEM - A ball grid array package system comprising: forming a package base including: fabricating a heat spreader having an access port, attaching an integrated circuit die to the heat spreader, mounting a substrate around the integrated circuit die, and coupling an electrical interconnect between the integrated circuit die and the substrate; and coupling a second integrated circuit package to the substrate through the access port. | 09-24-2009 |
20090250808 | RELIABILITY IMPROVEMENT IN A COMPOUND SEMICONDUCTOR MMIC - A semiconductor package (M) includes a semiconductor substrate layer ( | 10-08-2009 |
20090283902 | Semiconductor Package Structures Having Liquid Coolers Integrated with First Level Chip Package Modules - Semiconductor package structures are provided which are designed to have liquid coolers integrally packaged with first level chip modules. In particular, apparatus for integrally packaging a liquid cooler device within a first level chip package structure include structures in which a liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate. The liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate. | 11-19-2009 |
20090294954 | 3-D ICs WITH MICROFLUIDIC INTERCONNECTS AND METHODS OF CONSTRUCTING SAME - Three dimensional integrated circuits with microfluidic interconnects and methods of constructing same are provided. According to some embodiments, and microfluidic integrated circuit system can comprise a plurality of semiconductor die wafers each having a top and bottom exterior surface. The semiconductor die wafers can form a stack of die wafers. The die wafers can comprise one or more channels formed through the die wafers. The channels can extend generally between top and bottom exterior surfaces of the semiconductor die wafers. A plurality of micro-pipes can be disposed between adjacent semiconductor die wafers in the stack. The micro-pipes can enable the channels to be in fluid communication with each other. A barrier layer can be disposed within at least one of the channels and the micro-pipes. The barrier layer can be adapted to prevent a coolant flowing through the at least one of the channels and the micro-pipes from leeching into the channels and micro-pipes. Other embodiments are also claimed and described. | 12-03-2009 |
20090294955 | COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE - An integrated circuit package includes: a substrate; an electronic circuit located on the substrate, the electronic circuit comprising a topography of at least one level; a cooling device located over the electronic circuit; a compliant interface disposed between the electronic circuit and the cooling device, wherein the compliant interface comprises a first surface and a second surface and wherein the first surface is in thermal contact with the electronic circuit, and wherein the compliant interface is preformed from a compliant material such that the first surface substantially conforms to the topography of the electronic circuit. | 12-03-2009 |
20090302461 | SYSTEMS, DEVICES, AND METHODS FOR SEMICONDUCTOR DEVICE TEMPERATURE MANAGEMENT - Devices, systems, and methods for semiconductor die temperature management are described and discussed herein. An IC device is described that includes at least one intra-die cooling structure. In an embodiment, the IC device includes a semiconductor die formed of integral device layers and further includes at least one coolant reservoir and at least one coolant channel. In an embodiment, the at least one coolant reservoir and at least one coolant channel are disposed wholly within the semiconductor die. In various embodiments, at least one coolant reservoir and at least one coolant channel are constructed and arranged to circulate coolant fluid in proximity to at least one IC device structure in order to decrease and or normalize an operating temperature of the IC device. In other embodiments, systems and methods for designing and/or fabricating IC die that include at least one intra-die cooling structure are provided herein. | 12-10-2009 |
20090315173 | HEAT-TRANSFER STRUCTURE - An apparatus | 12-24-2009 |
20100019379 | EXTERNAL HEAT SINK FOR BARE-DIE FLIP CHIP PACKAGES - An integrated circuit package includes a substrate having opposing first and second surfaces, a flip chip integrated circuit die, and a heat sink. A first surface of die is mounted to the first surface of the substrate by a plurality of electrically conductive solder bumps. The heat sink has a first surface that includes a recessed region extending along a length of the heat sink in the first surface and that includes first and second supporting portions separated by the recessed region. The first and second supporting portions are attached to the first surface of the substrate such that the die is positioned in the recessed region. A second surface of the die is attached to a surface of the recessed region. | 01-28-2010 |
20100044855 | INTEGRATED THERMAL STRUCTURES AND FABRICATION METHODS THEREOF FACILITATING IMPLEMENTING A CELL PHONE OR OTHER ELECTRONIC SYSTEM - Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer. | 02-25-2010 |
20100059880 | SEMICONDUCTOR MODULE AND AN ELECTRONIC SYSTEM INCLUDING THE SAME - A three-dimensional semiconductor module and an electronic system including the same are provided. The semiconductor module includes a module substrate, a logic device formed on a part of the module substrate, and a plurality of memory devices formed on another part of the module substrate, wherein the plurality of memory devices are disposed perpendicular to the logic device, and the module substrate on which the plurality of memory devices are formed is supported by a supporter. The electronic system includes the semiconductor module. | 03-11-2010 |
20100078807 | POWER SEMICONDUCTOR MODULE ASSEMBLY WITH HEAT DISSIPATING ELEMENT - A power semiconductor module assembly is disclosed including a power semiconductor module comprising a load terminal electrically conductively joined to a contact conductor. Part of the heat materializing during operation of the power semiconductor module in the load terminal is dissipated by using a heat dissipating element. | 04-01-2010 |
20100109153 | HIGH BANDWIDTH PACKAGE - Method and apparatus for constructing and operating a high bandwidth package in an electronic device, such as a data storage device. In some embodiments, a high bandwidth package comprises a first known good die that has channel functions, a second known good die that has a controller function, and a third known good die that has a buffer function. Further in some embodiments, the high bandwidth package has pins that connect to each of the first, second, and third dies. | 05-06-2010 |
20100109154 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - At least a part of a heat radiation member ( | 05-06-2010 |
20100140792 | GRAPHITE NANOPLATELETS FOR THERMAL AND ELECTRICAL APPLICATIONS - This disclosure concerns a procedure for bulk scale preparation of high aspect ratio, 2-dimensional nano platelets comprised of a few graphene layers, G | 06-10-2010 |
20100148357 | METHOD OF PACKAGING INTEGRATED CIRCUIT DIES WITH THERMAL DISSIPATION CAPABILITY | 06-17-2010 |
20100181663 | LOW COMPRESSIVE FORCE, NON-SILICONE, HIGH THERMAL CONDUCTING FORMULATION FOR THERMAL INTERFACE MATERIAL AND PACKAGE - An improved thermal interface material for semiconductor devices is provided. More particularly, low compressive force, non-silicone, high thermal conductivity formulations for thermal interface material is provided. The thermal interface material comprises a composition of non-silicone organics exhibiting thermal conductivity of approximately 5.5 W/mK or greater and a compressed bond-line thickness of approximately 100 microns or less using a compressive force of approximately 100 psi or less. | 07-22-2010 |
20100181664 | INTEGRATED CIRCUIT CHIP PACKAGE MODULE - An integrated circuit (IC) package module includes a carrier, an IC chip, a number of wires, a number of pins, a seal member, and a thermal conductor. The IC chip is attached on a top surface of the carrier. The number of pins is connected to the IC chip via the number of wires. The seal member contains the carrier, the IC chip, and the number of wires. The thermal conductor is located over or located on a top surface of the IC chip. Parts of each of the number of pins and the thermal conductor are projected out of the seal member. | 07-22-2010 |
20100187682 | ELECTRONIC PACKAGE AND METHOD OF ASSEMBLING THE SAME - An electronic package ( | 07-29-2010 |
20100187683 | 3-D ICs EQUIPPED WITH DOUBLE SIDED POWER, COOLANT, AND DATA FEATURES - Three dimensional integrated circuits with double sided power, coolant, and data features and methods of constructing same are provided. According to some embodiments, an integrated circuit package can generally comprise one or more semiconductor wafers and opposing end substrates. The semiconductor wafers can each have a top exterior surface and a bottom exterior surface. The plurality of semiconductor wafers can form a multi-dimensional wafer stack of die wafers such that adjacent wafers have facing surfaces. Each of the semiconductor wafers can comprise one or more channels formed through the wafers. A portion of the channels can extend generally between the top and bottom exterior surfaces of the semiconductor wafers. A portion of the channels can carry conductors for coupling the wafers and/or coolant for cooling the wafers. The opposing end substrates can be disposed proximate opposing ends of the multi-dimensional stack. The opposing end substrates can be configured to supply power, coolant, and data signals to opposing ends of the multi-dimensional wafer stack. Other embodiments are also claimed and described. | 07-29-2010 |
20100193942 | Thermally Enhanced Semiconductor Package - Disclosed are systems and methods for improving the thermal performance of integrated circuit packages. Aspects of the present invention include improved thermal package structures and methods for producing the same through the application of one or more thermal spreaders in the package. In embodiments, a thermal spreader is incorporated in a semiconductor chip package between a semiconductor die and its die pad. By including a thermal spreader in an IC package, the package can handle higher levels of power while maintaining approximately the same temperature of the package or can reduce the temperature of the package when operating at the same power level, as compared to a package without a thermal spreader. | 08-05-2010 |
20100224991 | INTEGRATED CIRCUIT HEAT SPREADER STACKING SYSTEM - An integrated circuit heat spreader stacking system includes: an integrated circuit on a substrate; a heat spreader having a heat sink dome; a stacking stand-off for the heat spreader; and the heat spreader mounted with the heat sink dome over the integrated circuit. | 09-09-2010 |
20100244236 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SPREADER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate; mounting an integrated circuit die on the package substrate; and attaching a heat spreader assembly, having a thermal adhesive layer formed therein, to the package substrate and the integrated circuit die. | 09-30-2010 |
20100283143 | Die Exposed Chip Package - This disclosure describes a chip package. In one embodiment, a semiconductor chip package includes a thermal dissipater placed on top of an integrated-circuit die, the thermal dissipater having a same or similar coefficient of thermal expansion as that of the integrated-circuit die. | 11-11-2010 |
20100301470 | STUD BUMPS AS LOCAL HEAT SINKS DURING TRANSIENT POWER OPERATIONS - A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate. | 12-02-2010 |
20110012257 | HEAT SPREADER FOR SEMICONDUCTOR PACKAGE - A semiconductor package including a substrate, a die attached to the substrate and a heat spreader. The heat spreader has a heat dissipating portion with an upper surface, a lower surface and a perimeter. The lower surface overlies and is spaced apart from the die to provide a clearance therebetween. Supports are spaced about the perimeter of the heat dissipating portion and depend downwardly therefrom. Each support is located on the substrate to establish an opening between adjacent supports. | 01-20-2011 |
20110018126 | LOW NOISE HIGH THERMAL CONDUCTIVITY MIXED SIGNAL PACKAGE - An improved microelectronic assembly ( | 01-27-2011 |
20110031612 | POWER SEMICONDUCTOR CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - A power semiconductor circuit device and a method for manufacturing the same, both of which are provided with: a base board on which at least a power semiconductor element is mounted; a resin which molds the base board and the power semiconductor element in a state where partial surfaces of the base board, including a base board surface opposite to a surface on which the power semiconductor element is mounted, are exposed; and a heat dissipating fin joined to the base board by a pressing force. A groove is formed in the base board at a portion to be joined to the heat dissipating fin, and the heat dissipating fin is joined by caulking to the groove. | 02-10-2011 |
20110037167 | METHOD AND PACKAGE FOR CIRCUIT CHIP PACKAGING - A method of assembling a bent circuit chip package and a circuit chip package having a bent structure. The circuit chip package includes: a substrate having a first coefficient of thermal expansion (CTE); a circuit chip, having a second CTE, mounted onto the substrate; a metal foil disposed on the circuit chip in thermal contact with the chip; a metal lid having (i) a third CTE that is different from the first CTE and (ii) a bottom edge region, where the metal lid is disposed on the metal foil in thermal contact with the metal foil; and an adhesive layer along the bottom edge of the metal lid, cured at a first temperature, bonding the lid to the substrate, producing an assembly which, at a second temperature, is transformed to a bent circuit chip package. | 02-17-2011 |
20110037168 | Semiconductor Device and Method of Providing a Thermal Dissipation Path Through RDL and Conductive Via - A semiconductor device has a conductive via formed around a perimeter of the semiconductor die. First and second conductive layers are formed on opposite sides of the semiconductor die and thermally connected to the conductive via. An insulating layer is formed over the semiconductor die. Openings in the insulating layer expose the first conductive layer and a thermal dissipation region of semiconductor die. A thermal via is formed through the insulating layer to the first conductive layer. A thermally conductive layer is formed over the thermal dissipation region and thermal via. A thermal conduction path is formed from the thermal dissipation region through the thermally conductive layer, thermal via, first conductive layer, conductive via, and second conductive layer. The thermal conduction path terminates in an external thermal ground point. The thermally conductive layer provides shielding for electromagnetic interference. | 02-17-2011 |
20110068463 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH QUAD FLAT NO-LEAD PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base array having terminals and an open region; attaching a coverlay layer directly on the base array; placing a component in the open region and directly on the coverlay layer; forming an encapsulation over the base array and the component; removing the coverlay layer to leave a plane of the terminals and a plane of the component partially exposed and substantially coplanar; and removing a portion of the base array between the terminals, the terminals electrically isolated. | 03-24-2011 |
20110156244 | HEAT SINK AND INTEGRATED CIRCUIT ASSEMBLY USING THE SAME - An integrated circuit assembly includes a heat sink and a substrate coupled to the heat sink. The heat sink includes a base and a plurality of fins disposed on the base, the base has an intermediate portion and two side portions connected to the intermediate portion, the intermediate portion has a first width and the side portions has a second width smaller than the first width, and the fins are disposed on the side portions of the base. The substrate is made of ceramic material and has an upper surface with an opening and a lower surface with a groove, the groove matches the intermediate portion of the heat sink, and the opening is configured to expose a portion of the intermediate portion to receive an integrated circuits package. | 06-30-2011 |
20110180925 | Microfabricated Pillar Fins For Thermal Management - An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided. | 07-28-2011 |
20110298121 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device according to the present invention includes a heat sink made of Cu and having a thickness of 2 to 3 mm, an insulating substrate bonded on the heat sink with interposition of a first bonding layer (under-substrate solder), and a power semiconductor element mounted on the insulating substrate. In the heat sink, a buffer slot is formed at a periphery of a region bonded to the insulating substrate. | 12-08-2011 |
20110316142 | SEMICONDUCTOR MODULE WITH RESIN-MOLDED PACKAGE OF HEAT SPREADER AND POWER SEMICONDUCTOR CHIP - A semiconductor module is provided which includes a resin molded package which is made by a resinous mold assembly. The resin molded package is clamped by covers through a fastener to make the semiconductor module. The resinous mold assembly has formed therein a coolant path that is a portion of a coolant passage through which a coolant flows to coal a semiconductor chip embedded in the resin molded package. The resinous mold assembly is made up of a first mold and a second mold. The first mold has the semiconductor chip, heat spreaders, and electric terminals embedded therein. The second mold is wrapped around an outer periphery of the first mold. The second mold is made of resin which is lower in softening temperature than that of the first mold, thereby facilitating ease of removing the first mold from the resin molded package for reusing the resin molded package. | 12-29-2011 |
20110316143 | SEMICONDUCTOR MODULE WITH COOLING MECHANISM AND PRODUCTION METHOD THEREOF - A semiconductor module is provided which includes a semiconductor unit which is made by a resin mold. The resin mold has formed therein a coolant path through which a coolant flows to cool a semiconductor chip embedded in the resin mold. The resin mold also includes heat spreaders, and electric terminals embedded therein. Each of the heat spreaders has a fin heat sink exposed to the flow of the coolant. The fin heat sink is welded to a surface of each of the heat spreaders through an insulator, thus minimizing an electrical leakage from the heat spreader to the coolant. | 12-29-2011 |
20120001318 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package and a cooler. The semiconductor package includes a semiconductor element, a metal member, and a molding member for encapsulating the semiconductor element and the metal member. The metal member has a metal portion thermally connected to the semiconductor element, an insulating layer on the metal portion, and a conducting layer on the insulating layer. The conducting layer is at least partially exposed outside the molding member and serves as a radiation surface for radiating heat of the semiconductor element. The cooler has a coolant passage through which a coolant circulates to cool the conducting layer. The conducting layer and the cooler are electrically connected together. | 01-05-2012 |
20120018873 | METHOD AND PACKAGE FOR CIRCUIT CHIP PACKAGING - A method and a package for circuit chip package having a bent structure. The circuit chip package includes: a substrate having a first coefficient of thermal expansion (CTE); a circuit chip, having a second CTE, mounted onto the substrate; a metal foil disposed on the circuit chip in thermal contact with the chip; a metal lid having (i) a third CTE that is different from the first CTE and (ii) a bottom edge region, where the metal lid is disposed on the metal foil in thermal contact with the metal foil; and an adhesive layer along the bottom edge of the metal lid, cured at a first temperature, bonding the lid to the substrate, producing an assembly which, at a second temperature, is transformed to a bent circuit chip package. | 01-26-2012 |
20120061818 | 3-D Integrated Semiconductor Device Comprising Intermediate Heat Spreading Capabilites - In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips. | 03-15-2012 |
20120080785 | SEMICONDUCTOR COOLING APPARATUS - In some embodiments, a semiconductor cooling apparatus includes a monolithic array of cooling elements. Each cooling element of the monolithic array of cooling elements is configured to thermally couple to a respective semiconductor element of an array of semiconductor elements. At least two of the semiconductor elements have a different height and each cooling element independently flexes to conform to the height of the respective semiconductor element. | 04-05-2012 |
20120098118 | COMPLIANT HEAT SPREADER FOR FLIP CHIP PACKAGING - An integrated circuit chip package is described. The integrated circuit package comprises a substrate, a chip attached to the substrate, and a heat spreader mounted over the chip for sealing the chip therein. The heat spreader includes a thermally-conductive element having a side opposed to the top of the chip for transmitting heat away from the chip to the heat spreader, and a compliant element having a first portion attached to and positioned around the periphery of the thermally-conductive element and a second portion affixed to a surface of the substrate. | 04-26-2012 |
20120139098 | POWER PACKAGE MODULE - Disclosed herein is a power package module, including: a power package mounted with a plurality of semiconductor chips; a heat radiation module coming into contact with the power package and including a first heat radiation member for discharging heat generated from the power package; and a second heat radiation member, one side of which is connected to the first heat radiation member and the other side of which is connected to the power package. | 06-07-2012 |
20120228757 | COOLING STRUCTURE OF SEMICONDUCTOR DEVICE - A cooling structure of a semiconductor device includes an output electrode, a semiconductor element and a semiconductor element disposed to face each other with the output electrode interposed therebetween, a radiator disposed for the semiconductor element on a side opposite to the output electrode, and a radiator disposed for the semiconductor element on the side opposite to the output electrode. The output electrode includes an element mounting portion and a heat transport portion. The element mounting portion is electrically connected to the semiconductor element and the semiconductor element, and is formed of a conductive material. The heat transport portion is disposed to extend from the element mounting portion toward the radiator and the radiator. With this structure, a cooling structure of a semiconductor device with which excellent cooling efficiency is realized can be provided. | 09-13-2012 |
20120319267 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL DISPERSAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a package stack assembly, having a contact pad, on the base substrate; applying an encapsulation having a cavity with a tapered side directly over the package stack assembly, the contact pad exposed in the cavity; attaching a recessed circuitry unit in the cavity and on the contact pad, a chamber of the cavity formed by the recessed circuitry unit and the tapered side of the cavity; and mounting a thermal structure over the recessed circuitry unit, the cavity, and the encapsulation. | 12-20-2012 |
20130056864 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED THERMAL HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting a bottom integrated circuit on a bottom substrate having a peripheral thermal via connected to a peripheral thermal interconnect; mounting an inner heat shield, having a top planar portion, over the bottom integrated circuit with the inner heat shield connected to the peripheral thermal via; mounting a top integrated circuit over the inner heat shield; and forming a package encapsulation over the bottom integrated circuit, the inner heat shield, and the top integrated circuit with the top planar portion exposed only at each corners of a package topside of the package encapsulation. | 03-07-2013 |
20130075889 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting a device mounting structure over a bottom substrate; mounting a heat spreader having an opening formed by a single integral structure with a dam and a flange, the dam having a dam height greater than a flange height of the flange; and forming a package encapsulation over the device mounting structure and the bottom substrate with the device mounting structure exposed within the opening. | 03-28-2013 |
20130154082 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE - A semiconductor device includes an insulation layer, a first semiconductor element and a second semiconductor element which are disposed within the insulation layer, a frame which has higher thermal conductivity than the insulation layer and surrounds the first semiconductor element and the second semiconductor element via the insulation layer, and a wiring layer which is disposed over the insulation layer and includes an electrode which electrically connects the first semiconductor element and the second semiconductor element. | 06-20-2013 |
20130168846 | UNDERFILL PROCESS AND MATERIALS FOR SINGULATED HEAT SPREADER STIFFENER FOR THIN CORE PANEL PROCESSING - A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed. | 07-04-2013 |
20130187262 | DEVICES INCLUDING COMPOSITE THERMAL CAPACITORS - Embodiments of the present disclosure include devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like. | 07-25-2013 |
20130207257 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - At least a part of a heat radiation member ( | 08-15-2013 |
20130214406 | Flexible Heat Sink With Lateral Compliance - A multi-chip module (MCM) structure comprises more than one semiconductor chip lying in a horizontal plane, the MCM having individual chip contact patches on the chips and a flexible heat sink having lateral compliance and extending in a plane in the MCM and secured in a heat exchange relation to the chips through the contact patches. The MCM has a mismatch between the coefficient of thermal expansion of the heat sink and the MCM and also has chip tilt and chip height mismatches. The flexible heat sink with lateral compliance minimizes or eliminates shear stress and shear strain developed in the horizontal direction at the interface between the heat sink and the chip contact patches by allowing for horizontal expansion and contraction of the heat sink relative to the MCM without moving the individual chip contact patches in a horizontal direction. | 08-22-2013 |
20130249074 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package including a first printed circuit board and a second printed circuit board is provided. The first printed circuit board may include a first surface upon which a first semiconductor chip is mounted and a second surface upon which at least one connecting structure is attached. The first printed circuit board may further include at least one thermal via and a heat sink and the at least one thermal via and the heat sink may be disposed under the first semiconductor chip with the heat sink being disposed between the first surface and the second surface. The second printed circuit board may include a third surface upon which a second semiconductor chip is mounted. The second printed circuit board may be disposed under the first printed circuit board with the at least one connecting structure connecting the first printed circuit board to the second printed circuit board. | 09-26-2013 |
20130256868 | THERMAL INTERFACE MATERIAL FOR SEMICONDUCTOR CHIP AND METHOD FOR FORMING THE SAME - Disclosed is a method for forming a thermal interface material for a semiconductor chip, comprising the steps of forming an initial layer on a substrate, the initial layer including carbon nanotubes and nano metal powder; arranging a semiconductor chip on the initial layer; and heat-treating the initial layer with a sintering temperature of the nano metal powder to obtain a thermal interface material of the carbon nanotubes and the nano metal powder. | 10-03-2013 |
20130256869 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip. | 10-03-2013 |
20130270690 | Methods for Forming Silicon-Based Hermetic Thermal Solutions - A method includes forming a first oxide layer on a surface of an integrated heat spreader, and forming a second oxide layer on top surfaces of fins, wherein the fins are parts of a heat sink. The integrated heat spreader is bonded to the heat sink through the bonding of the first oxide layer to the second oxide layer. | 10-17-2013 |
20130270691 | PACKAGE FOR A MICROELECTRONIC DIE, MICROELECTRONIC ASSEMBLY CONTAINING SAME, MICROELECTRONIC SYSTEM, AND METHOD OF REDUCING DIE STRESS IN A MICROELECTRONIC PACKAGE - A package for a microelectronic die ( | 10-17-2013 |
20130277821 | THERMAL PACKAGE WTH HEAT SLUG FOR DIE STACKS - A semiconductor assembly comprises a package, which in turn comprises at least one substrate, a first die stacked onto the substrate, at least one further die stacked onto the first die, at least one heat spreader in the package, and TSV:s extending through the stacked dies. The ends of the TSV:s are exposed at the further die. | 10-24-2013 |
20130313701 | HIGH-VOLTAGE SWITCH WITH A COOLING DEVICE - A high-voltage switch comprises one or more high-voltage transistors and a cooling substrate which may be manufactured from an electrically insulating material and on and/or through which a cooling medium can flow, wherein the one or more high-voltage transistors are mounted on at least one surface of the cooling substrate. | 11-28-2013 |
20140015118 | SEMICONDUCTOR CHIP INCLUDING HEAT RADIATION PORTION AND METHOD OF FABRICATING THE SEMICONDUCTOR CHIP - A semiconductor chip includes a semiconductor substrate including a first surface and a second surface, an integrated circuit (IC) on the first surface of the semiconductor substrate, and a heat radiation portion on the second surface of the semiconductor substrate. The heat radiation portion includes heat radiation patterns in a direction perpendicular to the second surface, and a heat radiation layer on upper portions of the heat radiation patterns. The heat radiation patterns include a plurality of recesses and a plurality of protrusions and the heat radiation layer includes a metal material and has a flat upper surface. | 01-16-2014 |
20140015119 | SEMICONDUCTOR DEVICE/ELECTRONIC COMPONENT MOUNTING STRUCTURE - To provide a mounting structure of a semiconductor device/electronic component that suppresses temperature rise of a semiconductor device and/or an electronic component having large power consumption due to heat generation thereof, resulting in stable operation. | 01-16-2014 |
20140015120 | SEMICONDUCTOR DEVICE INCLUDING COOLER - A semiconductor device includes a package and a cooler. The semiconductor package includes a semiconductor element, a metal member, and a molding member for encapsulating the semiconductor element and the metal member. The metal member has a metal portion thermally connected to the semiconductor element, an insulating layer on the metal portion, and a conducting layer on the insulating layer. The conducting layer is at least partially exposed outside the molding member and serves as a radiation surface for radiating heat of the semiconductor element. The cooler has a coolant passage through which a coolant circulates to cool the conducting layer. The conducting layer and the cooler are electrically connected together. | 01-16-2014 |
20140042611 | POWER CONVERTER - A power converter including: a plurality of semiconductor devices forming a power conversion circuit; a base section to which the plurality of semiconductor devices are attached; and radiating fins dissipating heat generated from the semiconductor devices into outside air, in the power converter in which the direction of the flow of a refrigerant flowing into the radiating fins changes depending on the operation status of the power conversion circuit, the shape of each radiating fin changes in such a way that the cross-sectional area of a channel of the refrigerant on the outflow side becomes smaller than the cross-sectional area of the channel of the refrigerant on the inflow side in the radiating fins depending on the direction of the flow of the refrigerant. | 02-13-2014 |
20140048924 | RIDGED INTEGRATED HEAT SPREADER - An integrated circuit package is presented. In an embodiment, the integrated circuit package has a package substrate, an integrated circuit die attached to the package substrate, and a package level heat dissipation device, such as an integrated heat spreader, attached to the package substrate encapsulating the integrated circuit die. The package level heat dissipation device has a top side with a ridge formed on top of a perimeter of the top side, and a bottom side that couples to the integrated circuit die. | 02-20-2014 |
20140070400 | SEMICONDUCTOR DEVICE - In a semiconductor device including semiconductor modules, it is possible to average the temperatures of the semiconductor modules. At least two semiconductor modules, wherein a plurality of semiconductor circuits, on which are mounted one or more semiconductor chips having a gate terminal and gate resistors connected to the gate terminals, are disposed in parallel, are disposed above a cooling body so that an array direction of the semiconductor circuits is a direction intersecting a refrigerant flow. At least one temperature detecting resistor is disposed in each semiconductor module, a gate signal is supplied to a gate signal input terminal of one semiconductor module of the at least two semiconductor modules via the temperature detecting resistor of the other semiconductor module, and a gate signal is supplied to a gate signal input terminal of the other semiconductor module via the temperature detecting resistor of the one semiconductor module. | 03-13-2014 |
20140084447 | POWER MODULE PACKAGE - Disclosed herein is a power module package including: a body member having a polyhedral shape and made of a metal material; a semiconductor device mounted on the body member; and a block member formed at an edge region of the body member and made of a metal material. | 03-27-2014 |
20140084448 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. The upper card includes one of a photosensor, light emitting element, radio frequency (RF) antenna, and radio frequency emitter. The lower card includes an area array input/output. | 03-27-2014 |
20140117528 | SEMICONDUCTOR MODULE - A semiconductor module may include a heat-transferring part connecting at least one of a control device, a buffer semiconductor device, and a memory device to a connector. The heat-transferring part may be configured to have a thermal conductivity higher than the substrate. Accordingly, during the operation of the semiconductor module, the connector can have a temperature lower than the devices. | 05-01-2014 |
20140124915 | SEMICONDUCTOR MODULE - A semiconductor module includes an insulating substrate ( | 05-08-2014 |
20140159226 | COMPACT SENSOR MODULE - Various embodiments of a compact sensor module are disclosed herein. The sensor module can include a stiffener and a sensor substrate having a mounting segment and a first wing segment extending from the mounting segment. The first wing segment may be folded around an edge of the stiffener. A sensor die may be mounted on the mounting segment of the sensor substrate. A processor substrate may be coupled to the sensor substrate. A processor die may be mounted on the processor substrate and may be in electrical communication with the sensor die. | 06-12-2014 |
20140167248 | POWER MODULE PACKAGE - An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir. | 06-19-2014 |
20140210071 | INTEGRATED STRUCTURE WITH IMPROVED HEAT DISSIPATION - An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material. | 07-31-2014 |
20140217574 | COMPOSITES COMPRISED OF ALIGNED CARBON FIBERS IN CHAIN-ALIGNED POLYMER BINDER - A method for enhancing internal layer-layer thermal interface performance and a chip stack of semiconductor chips using the method. The method includes adding a thermosetting polymer to the thermal interface material, dispersing a plurality of nanofibers into the thermal interface material, and un-crosslinking the thermosetting polymer in the thermal interface material. The method further includes extruding the thermal interface material through a die to orient the conductive axis of the nanofibers and polymer chains in the desired direction, and re-crosslinking the thermosetting polymer in the thermal interface material. The chip stack includes a first chip with circuitry on a first side, a second chip coupled to the first chip by a grid of connectors, and a thermal interface material pad between the chips. The thermal interface includes nanofibers and a polymer that allows for optimal alignment of the nanofibers and polymer chains. | 08-07-2014 |
20140217575 | 3DIC Package Comprising Perforated Foil Sheet - A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS. | 08-07-2014 |
20140252588 | SEMICONDUCTOR MODULE - According to one embodiment, a semiconductor module has a substrate, two nonvolatile memories disposed on a first surface of the substrate, a controller to control the nonvolatile memories, disposed on the first surface of the substrate and between the two nonvolatile memories, and a plurality of terminals that are electrically connected to the two nonvolatile memories and to the controller, disposed on a second surface of the substrate. | 09-11-2014 |
20140252589 | Charge Dissipation of Cavities - Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates. | 09-11-2014 |
20140264820 | PASTE THERMAL INTERFACE MATERIALS - Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed. | 09-18-2014 |
20140264821 | MOLDED HEAT SPREADERS - Embodiments of the present disclosure describe techniques and configurations for molded heat spreaders. In some embodiments, a heat spreader includes a first insert having a first face and a first side, the first face positioned to form a bottom surface of a first cavity, and a second insert having a second face and a second side, the second face positioned to form a bottom surface of a second cavity. The second cavity may have a depth that is different from a depth of the first cavity. The heat spreader may further include a molding material disposed between the first and second inserts and coupled with the first side and the second side, the molding material forming at least a portion of a side wall of the first cavity and at least a portion of a side wall of the second cavity. Other embodiments may be described and/or claimed. | 09-18-2014 |
20140306335 | THERMAL MANAGEMENT FOR SOLID-STATE DRIVE - An electronic device including a printed circuit board (PCB) including a thermal conduction plane and at least one heat generating component mounted on the PCB and connected to the thermal conduction plane. A frame is connected to the PCB so as to define a first thermally conductive path between at least a portion of the frame and the at least one heat generating component. The electronic device further includes at least one thermally conductive layer between the frame and the at least one heat generating component so as to define a second thermally conductive path between at least a portion of the frame and the at least one heat generating component. | 10-16-2014 |
20140312486 | CHIP-ON-FILM PACKAGE AND DISPLAY DEVICE HAVING THE SAME - A chip-on-film package and a display device, the package including a base film that includes an upper surface and a lower surface, the lower surface facing the upper surface; an integrated circuit chip on the upper surface of the base film; an alignment line on the base film and being spaced apart from the integrated circuit chip; a heat discharge plate on the lower surface of the base film and having a plate shape; and at least one via pattern penetrating through the base film and electrically connecting the alignment line to the heat discharge plate. | 10-23-2014 |
20140312487 | UNDERFILL PROCESS AND MATERIALS FOR SINGULATED HEAT SPREADER STIFFENER FOR THIN CORE PANEL PROCESSING - A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed. | 10-23-2014 |
20140327128 | Cooling System for Molded Modules and Corresponding Manufacturing Methods - A cooling system for molded modules includes a plurality of individual modules each including a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and at least partly uncovered by the mold compound, and a cooling plate at least partly uncovered by the mold compound. A molded body surrounds a periphery of each individual module to form a multi-die module. The leads of each individual module and the cooling plates are at least partly uncovered by the molded body. A lid with a port is attached to a periphery of the molded body at a first side of the multi-die module. The lid seals the multi-die module at the first side to form a cavity between the lid and the molded body for permitting fluid exiting or entering the port to contact the cooling plates of each individual module. | 11-06-2014 |
20140327129 | PACKAGE ON PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a package on package (PoP) device and a method of manufacturing the same. In the PoP device, a thermal interface material layer is interposed between a lower semiconductor chip and an upper package substrate, and a heat sink is disposed on an upper semiconductor package substrate. This maximizes heat release. Accordingly, an operation speed can be improved and malfunction limitation can be solved. | 11-06-2014 |
20140327130 | SEMICONDUCTOR DEVICE PACKAGES INCLUDING THERMALLY INSULATING MATERIALS AND METHODS OF MAKING AND USING SUCH SEMICONDUCTOR PACKAGES - Semiconductor devices may include a first semiconductor die comprising a heat-generating region located at a periphery thereof. A second semiconductor die is attached to the first semiconductor die. At least a portion of the heat-generating region is located laterally outside a footprint of the second semiconductor die. A thermally insulating material is located on a side surface of the second semiconductor die. Methods of forming semiconductor devices may involve attaching a second semiconductor die to a first semiconductor die. The first semiconductor die includes a heat-generating region at a periphery thereof. At least a portion of the heat-generating region is located laterally outside a footprint of the second semiconductor die. A thermally insulating material is located on a side surface of the second semiconductor die. | 11-06-2014 |
20140339692 | SEMICONDUCTOR PACKAGE STACK HAVING A HEAT SLUG - A semiconductor package stack, comprising: a lower semiconductor package including a lower semiconductor chip mounted on a lower package board; an upper semiconductor package stacked on the lower semiconductor package and including an upper semiconductor chip mounted on an upper package board, wherein the upper package board includes an opening configured to expose a lower surface of the upper semiconductor chip; and a first heat slug disposed within the opening, contacting the lower surface of the upper semiconductor chip, and contacting an upper surface of the lower semiconductor chip. | 11-20-2014 |
20140346661 | CHIP PACKAGE STRUCTURE AND CHIP PACKAGING METHOD - Embodiments of the present invention provide a chip package structure and a chip packaging method, which is related to the field of electronic technologies, and can protect chips and effectively dissipate heat for chips. The chip package structure includes a substrate, chips, and a heat dissipating lid, where the chips include at least one master chip disposed on the substrate and at least one slave chip disposed on the substrate; the heat dissipating lid is bonded to the slave chip by using a heat conducting material, and the heat dissipating lid covers the at least one slave chip; and the heat dissipating lid includes a heat dissipating window at a position corresponding to the at least one master chip. The embodiments of the present invention are applicable to multi-chip packaging. | 11-27-2014 |
20140353816 | METHOD OF FORMING A HIGH THERMAL CONDUCTING SEMICONDUCTOR DEVICE PACKAGE - A semiconductor device package ( | 12-04-2014 |
20140353817 | HEAT DISSIPATION DEVICE EMBEDDED WITHIN A MICROELECTRONIC DIE - The subject matter of the present application relates to a heat dissipation device that is embedded within a microelectronic die. The heat dissipation device may be fabricated by forming at least one trench extending into the microelectronic die from a microelectronic die back surface, which opposes an active surface thereof, and filling the trenches with at least one layer of thermally conductive material. In one embodiment, the heat dissipation device may be a thermoelectric cooling device. | 12-04-2014 |
20140367846 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a plurality of power chips sealed in a package to control power and an IC sealed in the package to control each of the power chips. The IC is disposed at the center part of the package in the plan view. The plurality of power chips are disposed so as to surround the IC in the plan view. | 12-18-2014 |
20140374897 | THERMAL INTERFACE MATERIAL FOR INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING THE SAME - In an embodiment, a thermal interface material (TIM) is provided. The TIM comprises first and a second layers of a first transition metal, and a third layer including a plurality of carbon nanotubes supported in a flexible polymer matrix and a second transition metal coupled to sidewalls of carbon nanotubes. The first and second metal layers are in contact with first and second ends of carbon nanotube. The TIM further comprises fourth and fifth layers of an alloy material coupled to the first and second metal layers, respectively. The carbon nanotube based TIM including the layers with transition metal allow improved heat transfer from an integrated circuit die to a heat spreader. | 12-25-2014 |
20150008573 | Bonded Body and Semiconductor Module - Bondability and heat conductivity of a bonded body in which some of metal, ceramic, or semiconductor are bonded to each other are improved. In the bonded body in which a first member and a second member each comprise one of metal, ceramic, or semiconductor are bonded to each other, the second member is bonded to the first member by way of an adhesive member disposed to the surface of the first member, and the adhesive member contains a V | 01-08-2015 |
20150014841 | HEAT-TRANSFER STRUCTURE - An apparatus comprising a first substrate having a first surface, a second substrate having a second surface facing the first surface and an array of metallic raised features being in contact with the first surface to the second surface, a portion of the raised features having a mechanical bend or buckle plastic deformation produced therein via a compressive force. One or more of the metallic raised features has one or more surface singularities therein prior to the mechanical bend or the buckle plastic deformation produced by the compressive force. | 01-15-2015 |
20150048494 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 02-19-2015 |
20150054148 | SEMICONDUCTOR PACKAGES INCLUDING HEAT EXHAUST PART - According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part. | 02-26-2015 |
20150061110 | STACKED CHIP LAYOUT AND METHOD OF MAKING THE SAME - A stacked chip layout includes a central processing chip has a first area and a first active circuit block over the central processing chip, the first active circuit block has a second area. The stacked chip layout further includes a second active circuit block over the first active circuit block, the second active circuit block has a third area, the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The stacked chip layout further includes a third active circuit block over the second active circuit block, the third active circuit block has a fourth area, the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes a portion of the first active circuit block and the second active circuit block. | 03-05-2015 |
20150069598 | HEAT DISSIPATION CONNECTOR AND METHOD OF MANUFACTURING SAME, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME, AND SEMICONDUCTOR MANUFACTURING APPARATUS - In one embodiment, a heat dissipation connector mounted on a semiconductor chip and sealed up with a molding resin along with the semiconductor chip and a lead frame includes a heat dissipation portion configured to have a block shape, and have an upper face exposed out of the molding resin. The connector further includes a connecting portion configured to extend from a first side face of the heat dissipation portion, and electrically connect an electrode arranged on the semiconductor chip to the lead frame. The heat dissipation portion and the connecting portion are integrally made of the same metal sheet. | 03-12-2015 |
20150076686 | Chip Stacking Packaging Structure - A chip stacking packaging structure is provided for achieving high-density stacking and improving a heat dissipation efficiency of the chip stacking packaging structure. The chip stacking packaging structure includes a main substrate and at least one stacking substrate in which a main chip is disposed in the main substrate, at least one stacking chip is disposed on the stacking substrate, and a side edge of the stacking substrate is disposed on the main substrate, so that the stacking chip is connected to the main chip. | 03-19-2015 |
20150076687 | PACKAGING DRAM AND SOC IN AN IC PACKAGE - An integrated circuit package including a first substrate, a first die, a second die, a second substrate, and a system on chip. The first substrate includes a first portion including first connections, a second portion including no connections, a third portion including second connections, a first opening between the first portion and the second portion, and a second opening between the second portion and the third portion. The first die is arranged on the first substrate. The first die includes third connections to connect to the first connections via the first opening. The second die is arranged adjacent to the first die on the first substrate. The second die includes fourth connections to connect to the second connections via the second opening. The second substrate is connected to the first substrate. The system on chip is arranged on the second substrate between the first substrate and the second substrate. | 03-19-2015 |
20150084180 | SEMICONDUCTOR DEVICE INCLUDING HEAT DISSIPATING STRUCTURE - A semiconductor device includes a substrate serving as a base and having a surface on which electrodes are provided, a semiconductor chip mounted to the surface of the substrate, a sealing portion sealing the semiconductor chip and the surface of the substrate, first vias each penetrating the sealing portion in a thickness direction of the sealing portion to reach the electrodes on the surface of the substrate, external terminals connected to the first vias, and second vias provided near the semiconductor chip, extending to such a depth that the second vias do not penetrate the sealing portion, and insulated from the substrate and the semiconductor chip. | 03-26-2015 |
20150084181 | 3DIC Package Comprising Perforated Foil Sheet - A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS. | 03-26-2015 |
20150091156 | Three-Dimensional Silicon Structure For Integrated Circuits And Cooling Thereof - Embodiments of a three-dimensional silicon structure for integrated circuits and cooling thereof are described. In one aspect, a device includes a silicon substrate having a first primary side and a second primary side opposite the first primary side. The first primary side includes a circuit structure disposed thereon. The second primary side includes a plurality of fins monolithically formed thereon. | 04-02-2015 |
20150097280 | HEAT CONDUCTIVE SUBSTRATE FOR INTEGRATED CIRCUIT PACKAGE - An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment. | 04-09-2015 |
20150108630 | ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device includes a first circuit board; a heat sink fixed to the first circuit board to form a cavity between the heat sink and the first circuit board; and a plurality of electronic components fixed to a surface of the heat sink facing the first circuit board inside the cavity, the plurality of electric components having heights different from each other, wherein each of the plurality of electronic components is electrically coupled to the first circuit board by a second circuit board and being different from the first circuit board. | 04-23-2015 |
20150108631 | 3DIC Packages with Heat Dissipation Structures - A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion not overlapped by the first die. A first Thermal Interface Material (TIM) is over and contacting a top surface of the first die. A heat dissipating lid has a first bottom surface contacting the first TIM. A second TIM is over and contacting the second portion of the second die. A heat dissipating ring is over and contacting the second TIM. | 04-23-2015 |
20150123259 | THERMAL INTERFACE SHEET AND PROCESSOR - A thermal interface sheet includes a peripheral portion, in a surface direction, configured to have a melting point higher than the melting point of a central portion in the surface direction. | 05-07-2015 |
20150130047 | THERMALLY CONDUCTIVE MOLDING COMPOUND STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES - A method of forming a semiconductor package includes forming a thermal conductivity layer and attaching the thermal conductivity layer to a chip. The chip has a first surface and a second surface. The thermal conductivity layer is attached to the first surface of the chip. The thermal conductivity layer provides a path through which heat generated from the chip is dissipated to the ambient. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the thermal conductivity layer. | 05-14-2015 |
20150137345 | SEMICONDUCTOR PACKAGE HAVING HEAT SPREADER - A semiconductor package includes a heat spreader. The semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the first semiconductor chip. The heat spreader may be formed on the first semiconductor chip. A thermal interfacial material (TIM) layer may be formed to be in contact with the first semiconductor chip and the heat spreader and may cover side surfaces of the second semiconductor chip. Heat generated by the first semiconductor chip may be emitted through the TIM layer and the heat spreader. Thermal stress caused by a difference in coefficients of thermal expansion (CTEs) between the substrate and the first semiconductor chip may be distributed to ensure structural stability. | 05-21-2015 |
20150145118 | RIDGED INTEGRATED HEAT SPREADER - An integrated circuit package is presented. In an embodiment, the integrated circuit package has a package substrate, an integrated circuit die attached to the package substrate, and a package level heat dissipation device, such as an integrated heat spreader, attached to the package substrate encapsulating the integrated circuit die. The package level heat dissipation device has a top side with a ridge formed on top of a perimeter of the top side, and a bottom side that couples to the integrated circuit die. | 05-28-2015 |
20150340350 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a substrate, a lead, and a sealing resin member. The semiconductor element has a first electrode and a second electrode located on opposite sides in the thickness direction. The substrate has an insulating base and a conductive plate. The base has first and second surfaces located on opposite sides in the thickness direction. The conductive plate is bonded to the first surface of the base and electrically connected to the second electrode of the semiconductor element. The lead has an island electrically connected to the first electrode. The sealing resin member covers at least the semiconductor element. | 11-26-2015 |
20150357258 | MULTI-COMPONENT INTEGRATED HEAT SPREADER FOR MULTI-CHIP PACKAGES - A multi-component heat spreader comprising a top component having a first surface and an opposing second surface with either a cavity extending therein from the second surface thereof or a projection extending from the second surface thereof. The multi-component heat spreader further includes at least one additional component, such as a footing component or a spacer component, having a first surface and an opposing second surface with either a cavity extending therein from the second surface thereof or a projection extending from the second surface thereof, which is opposite from the top component cavity/projection. The additional component is attached to the top component, such as by brazing, wherein the top component cavity/projection is mated to the additional component cavity/projection. | 12-10-2015 |
20150364344 | Integrated Circuit Packages and Methods of Forming Same - Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a package substrate. A heat dissipation feature is attached on a first side of the first die. A second die is mounted on a second side of the first die, wherein the second die is at least partially disposed in a through hole formed in the package substrate. An encapsulant is formed on the first side of the package substrate around the first die. | 12-17-2015 |
20150380387 | STACKED CHIPS ATTACHED TO A HEAT SINK HAVING BONDING PADS - An integrated circuit comprises a heat sink devoid of electronic components and interposed between a back side of a bottom electronic chip and an upper exterior side of an encapsulation, the sink comprising a front side placed on the back side of the bottom electronic chip. The back side of the bottom electronic chip comprises pads and the front side of the sink comprises pads mechanically fastened to facing pads of the back side of the bottom electronic chip. | 12-31-2015 |
20160005701 | CHIP WITH SHELF LIFE - A semiconductor structure including a recess within a silicon substrate of an integrated circuit (IC) chip, wherein the recess is located near a circuit of the IC chip, and a metal layer in a bottom portion of the recess, wherein a portion of the silicon substrate is located below the metal layer in the bottom portion of the recess and above the circuit. | 01-07-2016 |
20160013114 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND ASSOCIATED SYSTEMS | 01-14-2016 |
20160013115 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND ASSOCIATED METHODS | 01-14-2016 |
20160035644 | EXPOSED, SOLDERABLE HEAT SPREADER FOR INTEGRATED CIRCUIT PACKAGES - An integrated circuit package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit. The heat spreader may be thermally-conductive and may have a first outer surface and a second outer surface substantially parallel to the first outer surface. The first outer surface may be affixed to all portions of a silicon side of the semiconductor die in a thermally-conductive manner. The encapsulation material may be non-electrically conductive and may completely encapsulate the semiconductor die and the heat spreader, except for the second surface of the heat spreader. The second surface of the heat spreader may be solderable and may form part of an exterior surface of the integrated circuit package. | 02-04-2016 |
20160035648 | SEMICONDUCTOR DIE ASSEMBLIES WITH HEAT SINK AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface. | 02-04-2016 |
20160043014 | UNDERFILL PROCESS AND MATERIALS FOR SINGULATED HEAT SPREADER STIFFENER FOR THIN CORE PANEL PROCESSING - A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed. | 02-11-2016 |
20160049352 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 02-18-2016 |
20160056038 | Constructions Comprising Rutile-Type Titanium Oxide; And Methods of Forming And Utilizing Rutile-Type Titanium Oxide - Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks. | 02-25-2016 |
20160079140 | COMPUTE INTENSIVE MODULE PACKAGING - A package for a multi-chip module includes a top cold plate and a bottom plate whose perimeters are in thermal communication so the plates together completely encase the module except for a connector passing through the bottom plate. The cold plate has copper tubing pressed into a groove formed in a serpentine pattern. The perimeter of the cold plate has thermal conduction fins which mate with thermal conduction slots in the perimeter of the bottom plate. Thermal interface material is disposed in gaps between the plates and chips on the module, the gaps having dimensions controlled by support ribs of plates which abut the module substrate. The cold plate is used on the hottest side of the module, e.g., the side having computationally-intensive chips such as ASICs. A densely packed array of these packages can be used in a central electronic complex drawer with a shared coolant circulation system. | 03-17-2016 |
20160079141 | METHODS OF FORMING SERPENTINE THERMAL INTERFACE MATERIAL AND STRUCTURES FORMED THEREBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal interface material comprising a thermally conductive serpentine foil located between a first and a second interface material. The serpentine foil may be in a parallel position or a rotated position, in embodiments. | 03-17-2016 |
20160093598 | SEMICONDUCTOR PACKAGE HAVING STACKED SEMICONDUCTOR CHIPS - A semiconductor package includes a package base substrate, at least one first semiconductor chip disposed on the package base substrate, and at least one stacked semiconductor chip structure disposed on the package base substrate adjacent to the at least one first semiconductor chip. The at least one stacked semiconductor chip includes a plurality of second semiconductor chips. A penetrating electrode region including a plurality of penetrating electrodes is disposed adjacent to an edge of the at least one stacked semiconductor chip structure. | 03-31-2016 |
20160118315 | Heat Sink Coupling Using Flexible Heat Pipes for Multi-Surface Components - An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first heat exchanger disposed on the primary device and having an opening over an area corresponding to the at least one secondary device; a second heat exchanger disposed in the opening on the at least one secondary device; at least one heat pipe coupled to the first heat exchanger and the second heat exchanger. A method including placing a heat exchanger on a multi-chip package, the heat exchanger including a first portion, a second portion and at least one heat pipe coupled to the first portion and the second portion; and coupling the heat exchanger to the multi-chip package. | 04-28-2016 |
20160155729 | PROXIMITY COUPLING OF INTERCONNECT PACKAGING SYSTEMS AND METHODS | 06-02-2016 |
20160172267 | CIRCUIT DEVICE AND METHOD OF MANUFACTURING A CIRCUIT DEVICE FOR CONTROLLING A TRANSMISSION OF A VEHICLE | 06-16-2016 |
20160190029 | METHOD OF MAKING AN ELECTRONIC DEVICE INCLUDING TWO-STEP ENCAPSULATION AND RELATED DEVICES - A method of making an electronic device may include positioning an integrated circuit (IC) die on an upper surface of a grid array substrate having connections on a lower surface thereof and coupling respective bond pads of the IC die to the grid array with bond wires. The method may also include forming a first encapsulating layer over the IC die and bond wires and positioning a heat spreader on the substrate above the first encapsulating layer after forming the first encapsulating layer. The method may further include forming a second encapsulating layer over the first encapsulating layer and embedding the heat spreader in the second encapsulating layer. | 06-30-2016 |
20180025961 | Power Conversion Device Including Semiconductor Module Provided with Laminated Structure | 01-25-2018 |
20190148257 | SEMICONDUCTOR PACKAGES RELATING TO THERMAL REDISTRIBUTION PATTERNS | 05-16-2019 |
20190148260 | ELECTRONIC PACKAGE WITH TAPERED PEDESTAL | 05-16-2019 |
20190148262 | Integrated Fan-Out Packages and Methods of Forming the Same | 05-16-2019 |
20190148337 | ELECTRONIC DEVICE INCLUDING SEMICONDUCTOR DEVICE PACKAGE | 05-16-2019 |
20220139802 | ADHESIVE AND THERMAL INTERFACE MATERIAL ON A PLURALITY OF DIES COVERED BY A LID - Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM. | 05-05-2022 |