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With specific electrical feedthrough structure

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257678000 - HOUSING OR PACKAGE

257690000 - With contact or lead

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257699000 Housing entirely of metal except for feedthrough structure 6
Entries
DocumentTitleDate
20120286413INTEGRATED CIRCUIT PACKAGE AND PACKAGING METHODS - An integrated circuit package includes a package module formed from successive build-up layers which define circuit interconnections, a cavity formed on a top-side of the package module, a chip having a front side with forward contacts and having a back-side, the chip disposed such that in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and a top layer coupled to the back-side of the chip covering at least a part of the chip and the top-side of the package module.11-15-2012
20110193216PACKAGE STRUCTURE - The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes an dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying with the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.08-11-2011
20100078804Apparatus with Side Mounted Microchip - In accordance with one embodiment of the invention, a packaged microchip has 1) a base with a mounting surface having a given electrical interconnector, and 2) a microchip with a plurality of side surfaces, a top surface, a bottom surface, and a given electrical pad on at least one of the top and bottom surfaces. The packaged microchip also has 3) a given solder ball secured to one of the top and bottom surfaces of the microchip. The given solder ball also is connected to the given electrical interconnector to electrically connect the given electrical pad and the given electrical interconnector. At least one side surface of the microchip is generally parallel with the mounting surface of the base.04-01-2010
20130032934PACKAGED MICROELECTRONIC ELEMENTS HAVING BLIND VIAS FOR HEAT DISSIPATION - System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having a top surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation. Specifically, heat generated by the semiconductor device thermally conducts from the semiconductor element, and is further distributed, transferred and/or dissipated through the one or more first blind vias to other connecting components.02-07-2013
20100038773BOND PAD FOR WAFER AND PACKAGE FOR CMOS IMAGER - An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seat between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.02-18-2010
20090184414WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME - A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.07-23-2009
201300823763D INTEGRATED ELECTRONIC DEVICE STRUCTURE INCLUDING INCREASED THERMAL DISSIPATION CAPABILITIES - A microelectronic device structure including increased thermal dissipation capabilities. The structure including a three-dimensional (3D) integrated chip assembly that is flip chip bonded to a substrate. The chip assembly including a device substrate including an active device disposed thereon. A cap layer is phsyically bonded to the device substrate to at least partially define a hermetic seal about the active device. The microelectronic device structure provides a plurality of heat dissipation paths therethrough to dissipate heat generated therein.04-04-2013
20090045504SEMICONDUCTOR PACKAGE THROUGH-ELECTRODE SUITABLE FOR A STACKED SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the first electrode. The first electrode of the semiconductor package through-electrode includes a first metal having a first hardness, and a second electrode comprises a second metal having a second hardness lower than the first hardness. The through-electrode passes through the semiconductor chip body and may be formed with the first metal having the first hardness and/or a first melting point and the second metal having the second hardness and/or a second melting point which are lower than the first hardness and/or the first melting point. This through-electrode allows a plurality of semiconductor packages to be easily stacked.02-19-2009
20100133682SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, an electrically insulating element separated from the semiconductor chip by a space, and encapsulation material disposed in the space. The semiconductor chip includes a first face having a contact, and the electrically insulating element defines at least one through-hole. The encapsulation material is disposed around the semiconductor chip and around the electrically insulating element. Electrically conducting material is deposited in the through-hole of the electrically insulating element and communicates with the contact.06-03-2010
20090302455SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to increase resistance against an electrostatic breakdown and to increase resistance to an external stress. Another object is to reduce cost by simplifying the manufacturing process. In a step in which an element formation layer is provided between a first organic resin layer provided with a first conductive film on its surface and a second organic resin layer provided with a second conductive film on its surface to electrically connect the first conductive film and the second conductive film with a contact conductor formed in each of the organic resin layers, the contact conductor provided in each of the first organic resin layer and the second organic resin layer is manufactured by making paste penetrate before an organic resin is cured and then curing the organic resin layer.12-10-2009
20090302454Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer - The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.12-10-2009
20120112336ENCAPSULATED DIE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF MANUFACTURING SAID MICROELECTRONIC PACKAGE - An encapsulated die (05-10-2012
200902672203-D STACKING OF ACTIVE DEVICES OVER PASSIVE DEVICES - Single-die or multi-die packaged modules that incorporate three-dimensional integration of active devices with discrete passive devices to create a package structure that allows active devices (such as, silicon or gallium-arsenide devices) to share the same footprint area as an array of passive surface mount components. In one example, a module includes at least one active device stacked on top of an array of passive surface mount components on a substrate. A conductive or non-conductive adhesive can be used to adhere the active device to the array of passive devices.10-29-2009
20110012253Semiconductor Package Having Discrete Components And System Containing The Package - A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.01-20-2011
20110012252POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a power semiconductor module. The module includes metal plates each having a first through hole, with an anodic oxidation layer formed on a surface of metal plates and an interior of the first through hole. A cooling member has a second through hole at a position corresponding to the first through hole, and the metal plates are attached to both sides of the cooling member. A circuit layer is formed on the anodic oxidation layer and performs an interlayer connection through a via formed in the first and second through holes. A power device is connected to the circuit layer. A resin encapsulant encloses the circuit layer and the power device. A housing is installed to each of the metal plates to form a sealing space for the resin encapsulant.01-20-2011
20120286414INTEGRATED CIRCUIT PACKAGE AND PACKAGING METHODS - An integrated circuit packaging method includes fabricating a package module from successive build-up layers which define circuit interconnections, forming a cavity on a top-side of the package module, attaching a metalized back-side of a chip onto a metallic layer, the chip having a front-side with at least one forward contact, disposing the chip in the cavity such that at least one forward contact is electrically connected to at least one of the circuit interconnections of the package module, and coupling the metallic layer that is attached to the chip onto the top-side of the package module.11-15-2012
20090212416INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURING SAME - An integrated circuit package includes a substrate (08-27-2009
20110298120Apparatus for Thermally Enhanced Semiconductor Package - A semiconductor package includes a semiconductor die having contact pads. An encapsulant is disposed around the semiconductor die, and conductive vias are disposed in the encapsulant. Electrically conductive traces are disposed between the contact pads and conductive vias, a thermally conductive channel is disposed in the encapsulant separate from the conductive vias, and a thermally conductive layer is disposed over an area of heat generation of the semiconductor die. A thermally conductive trace is disposed between the thermally conductive layer and thermally conductive channel. The thermally conductive layer, thermally conductive trace, and thermally conductive channel are electrically isolated from the contact pads of the semiconductor die and the electrically conductive traces. The semiconductor package further comprises broad thermal traces disposed over the encapsulant, and a thermally conductive material interconnecting the broad thermal traces and the thermally conductive layer.12-08-2011
20090166846PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.07-02-2009
20090283899Semiconductor Device - According to one embodiment of the present invention, a semiconductor device is provided, that includes a semiconductor carrier; a cavity formed within the semiconductor carrier, the cavity extending from the top surface of the semiconductor carrier into the semiconductor carrier; and at least one semiconductor chip provided within the cavity.11-19-2009
20090189275INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFER SCALE HEAT SLUG - An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.07-30-2009
20090085190Semiconductor Device and Method for Making Same - A method for making a semiconductor device includes creating conductive structures on a substrate. Contact pads of a semiconductor die are connected to first ends of conductive structures. The semiconductor die is encapsulated or embedded and the substrate is removed such that second ends of the conductive structures are exposed to the exterior.04-02-2009
20090206471Electronic parts packaging structure and method of manufacturing the same - An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.08-20-2009
20090206470SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND WIRING BOARD - In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.08-20-2009
20090140414Semiconductor device - A semiconductor device includes a resin case, a plurality of external connection terminals fixedly provided on the resin case, and at least one semiconductor element provided in the resin case. At least one terminal block has at least one wiring terminal for electrically connecting the semiconductor element and the external connection terminals.06-04-2009
20090091019Memory Packages Having Stair Step Interconnection Layers - Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.04-09-2009
20090283898DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.11-19-2009
20090283900SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device comprises: (a) a wiring board having front surface lands disposed on a front surface and rear surface lands disposed on a rear surface; (b) a semiconductor chip formed with an integrated circuit and electrode terminals electrically connected to the integrated circuit; and (c) a sealing resin that covers a front side of the wiring board when the semiconductor chip is mounted on the front side of the wiring board such that the front surface lands and the rear surface lands are electrically connected to the electrode terminals, wherein (d) holes having a shape and dimensions that allow projecting electrodes of the other semiconductor device to be inserted therein are formed in the sealing resin such that the front surface lands disposed further toward an inner side than a front surface of the semiconductor chip are exposed.11-19-2009
20090294952CHIP PACKAGE CARRIER AND FABRICATION METHOD THEREOF - The present invention discloses a chip package carrier and a fabrication method, which have the advantages of high reliability, thickness reduction and the scale reduction. The carrier and the method uses blind holes., which penetrates the substrate but external traces and external bonding pads, which cover the external traces. A chip can be installed and encapsulated directly on a first surface.12-03-2009
20120193775SEMICONDUCTOR STRUCTURE WITH LOW RESISTANCE OF SUBSTRATE AND LOW POWER CONSUMPTION - A semiconductor structure comprising a semiconductor unit, a first conductive structure, a first conductive plug, and a second conductive structure is provided. The semiconductor unit has a substrate on a first side of the semiconductor unit. The substrate has at least a hole. The first conductive plug is in the hole and the hole may be full of the conductive plug. The first conductive structure is on the surface of the semiconductor unit. The surface is at the first side of the semiconductor unit. The second conductive structure is on a surface at a second side of the substrate of the semiconductor unit.08-02-2012
20110266666CIRCUIT BOARD WITH BUILT-IN SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME - A circuit board includes an insulating member and a semiconductor chip encapsulated with the thermoplastic resin portion of the insulating member. A wiring member is located in the insulating member and electrically connected to first and second electrodes on respective sides of the semiconductor chip. The wiring member includes a pad, an interlayer connection member, and a connection portion. A diffusion layer is located between the first electrode and the connection portion between the pad and the connection portion, and between the second electrode and the interlayer connection member. At least one element of the interlayer connection member has a melting point lower than a glass-transition point of the thermoplastic resin portion. The connection portion is made of material having a melting point higher than a melting point of the thermoplastic resin portion.11-03-2011
20090166847SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package is provided. The semiconductor chip package comprises a package substrate having a first surface and a second surface opposite to the first surface. A through hole extends through the package substrate. A semiconductor chip is disposed on the first surface of the package substrate, wherein a bottom surface of the semiconductor chip covers one end of the through hole. At least two bonding fingers are disposed on the second surface of the package substrate and arranged on sides of the through hole. A conductive line is disposed on the second surface of the package substrate and between the two bonding fingers and the through hole, wherein two terminals of the conductive line are electrically connected to the two bonding fingers, respectively.07-02-2009
20080277775Ultra-thin near-hermetic package based on rainier - A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.11-13-2008
20120292757SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT - In various embodiments, a semiconductor component may include a semiconductor layer having a front side and a back side; at least one electronic element formed at least partially in the semiconductor layer; at least one via formed in the semiconductor layer and leading from the front side to the back side of the semiconductor layer; a front side metallization layer disposed over the front side of the semiconductor layer and electrically connecting the at least one electronic element to the at least one via; a cap disposed over the front side of the semiconductor layer and mechanically coupled to the semiconductor layer, the cap being configured as a front side carrier of the semiconductor component; a back side metallization layer disposed over the back side of the semiconductor layer and electrically connected to the at least one via.11-22-2012
20090146287Semiconductor device having a chip-size package - Disclosed are a semiconductor device, a method for manufacturing the same, and a method for mounting the same. The method for manufacturing a semiconductor device includes the steps of: preparing a package film having a planar configuration whose region is divided into a device-mounting film portion having a device hole forming therein, an external-connection film portion, and a bent portion located between the device-mounting film portion and the external-connection film portion, an external electrode pad being formed on the external-connection film portion on a first surface side of the package film, an inner lead being formed in such a manner as to lead from the device hole to the external electrode pad via the bending portion; mounting a semiconductor chip on the device-mounting film portion on the first surface side by bonding the inner lead to an electrode pad of the semiconductor chip in a region where the device hole is formed; and bending the external-connection film portion at the bending portion 180° toward a second surface side of the package film and fixing the same. The method for mounting a semiconductor device on a mother board in close contact therewith includes the steps of: depositing solder balls on electrode pads of the mother board; and placing the semiconductor device on the mother board and melting the solder balls so as to electrically connect the electrode pads of the mother board and the external electrode pads of the semiconductor device.06-11-2009
20090146288SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor element 06-11-2009
20100140789INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED TERMINAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an inner package so that the lead is peripheral to the inner package, and the inner package having a connection pad; forming an exposed terminal interconnect on the connection pad; and encapsulating the inner package, and partially encapsulating the exposed terminal interconnect with an encapsulation.06-10-2010
20100140790CHIP HAVING THERMAL VIAS AND SPREADERS OF CVD DIAMOND - An integrated circuit chip having a heat spreader comprising CVD diamond extending along the chip support body and thermal vias extending through the support body in regions free of active devices or functional elements. The thermal vias may thermally conductive and electrically conductive or may be thermally conductive and electrically resistive. The integrated circuit chips may be 3D integrated circuit chips.06-10-2010
20100123241SEMICONDUCTOR CHIP WITH THROUGH-SILICON-VIA AND SIDEWALL PAD - Subject matter disclosed herein may relate to packaging for multi-chip semiconductor devices as may be used, for example, in flash memory devices. In an example embodiment, a semiconductor chip may comprise a through-silicon via and a sidewall pad.05-20-2010
20090127697Housing with a Cavity for a Mechanically-Sensitive Electronic Component and Method for Production - An element includes a hollow space for a mechanically sensitive electrical element. The element includes a first housing part and a second housing part rigidly connected to the first housing part via joint surfaces. The element also includes connection surfaces on a base of a recess in the first housing the first housing part being covered by the second housing part to form an enclosed hollow space.05-21-2009
20090127696Piezoelectric Resonator Device - A package inner peripheral face 05-21-2009
20090127698COMPOSITE CONTACT FOR FINE PITCH ELECTRICAL INTERCONNECT ASSEMBLY - An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of composite contacts are positioned in a plurality of the through openings. The composite contacts include a conductive member having a central portion and at least first and second interface portions. One or more polymeric layers extend along at least the central portion conductive member. One or more coupling features on the composite contacts engage with the housing. At least one engagement feature formed in the polymeric layers proximate the first interface portion mechanically couples with the terminals on the first circuit member.05-21-2009
20090140413SEMICONDUCTOR PACKAGE STRUCTURE, APPLICATIONS THEREOF AND MANUFACTURING METHOD OF THE SAME - A semiconductor package structure and the applications thereof and the manufacturing method are disclosed. The semiconductor package structure includes a carrier, a semiconductor device, a first package body, a lid and a second package body. The semiconductor device is electrically connected to the carrier via a first conductive element. The first package body is molded on the carrier to surround the semiconductor device. The lid is disposed on top of the first package body and has at least one protrusion. The second package body is molded on the carrier to encapsulate the protrusion, whereby the protrusion is embedded within the second package body thereby locking the lid in place against the first package body.06-04-2009
20110221056ELECTRODE STRUCTURE AND MICRODEVICE PACKAGE PROVIDED THEREWITH - An electrode structure has a Cu electrode that provided in a surface of a substrate, a diffusion preventing film that is made of a material in which a diffusion coefficient of Sn is equal to or lower than 3×1009-15-2011
20090218679CHIP PACKAGE AND PROCESS THEREOF - A chip package is disclosed. The chip package comprises a chip, a plurality of bond pads, a plurality of connecting lines and a rigid cover. The chip has a plurality of recesses arranged along at least an edge of the chip and also has an active surface and a backside. The bond pads are disposed on the active surface and the bond pads are arranged to be corresponding to the recesses respectively. The connecting lines are disposed on surfaces of the recesses respectively at the edge of the chip. For each of the connecting lines, a first end of the connecting line is connected to one of the bond pads and a second end of the connecting line extends to the backside to be a terminal pad. The rigid cover is located on the active surface without covering the bond pads on the active surface.09-03-2009
20080315399Semiconductor Device Having Through Contacts Through a Plastic Housing Composition and Method for the Production Thereof - The invention relates to a semiconductor device comprising through contacts through a plastic housing composition and a method for the production thereof. For this purpose, the wiring substrate has a solder deposit on which through contact elements are arranged vertically with respect to the wiring substrate and extend as far as the top side of the semiconductor device.12-25-2008
20090096081Semiconductor device - A semiconductor device includes a substrate, at least one semiconductor element mounted on the substrate, a resin housing for housing the semiconductor element, the resin housing having a cover thereon, at least one pin provided and standing in the resin housing, and at least one printed substrate disposed inside the resin housing or outside the resin housing. The printed substrate and the cover of the resin housing are positioned by the pin.04-16-2009
20090256252Semiconductor Die Packages With Multiple Integrated Substrates, Systems Using the Same, and Methods Using the Same - An exemplary semiconductor die package is disclosed having one or more semiconductor dice disposed on a first substrate, one or more packaged electrical components disposed on a second substrate that is electrical coupled to the first substrate, and an electrically insulating material disposed over portions of the substrates. The first substrate may hold power-handling devices and may be specially constructed to dissipation heat and to facilitate fast and inexpensive manufacturing. The second substrate may hold packaged components of control circuitry for the power-handling devices, and may be specially constructed to enable fast and inexpensive wiring design and fast and inexpensive component assembly. The first substrate may be used with different designs of the second substrate.10-15-2009
20090243083Wafer Integrated with Permanent Carrier and Method Therefor - A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.10-01-2009
20100148353Double-Sided Semiconductor Device and Method of Forming Top-Side and Bottom-Side Interconnect Structures - A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect structure is formed over the first insulating layer and first conductive layer. A temporary carrier is mounted to the first interconnect structure. A second active device is formed on a second side of the semiconductor wafer. A second insulating layer is formed over the second side of the wafer. A second conductive layer is formed over the second insulating layer. A second interconnect structure is formed over the second insulating layer and second conductive layer. The temporary carrier is removed, leaving a double-sided semiconductor device. The double-sided semiconductor device is enclosed in a package with the first and second interconnect structures electrically connected.06-17-2010
20090256251Electronic device packages and methods of formation - Provided are electronic device packages and their methods of formation. The electronic device packages include an electronic device mounted on a substrate, a conductive via and a locally thinned region in the substrate. The invention finds application, for example, in the electronics industry for hermetic packages containing an electronic device such as an IC, optoelectronic or MEMS device.10-15-2009
20120193776COMPLIANT SPRING INTERPOSER FOR WAFER LEVEL THREE DIMENSIONAL (3D) INTEGRATION AND METHOD OF MANUFACTURING - The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.08-02-2012
20100264535INTEGRATED CIRCUIT PACKAGE ASSEMBLY AND SUBSTRATE PROCESSING METHOD - An integrated circuit (IC) package assembly includes a substrate and an IC. The substrate defines a plurality of vias. Inner walls of the plurality of vias and surfaces of the substrate are coated with copper. The plurality of vias are filled with an adhesive. The copper coated on surfaces of the substrate among the plurality of vias are etched. The IC is fixed on the substrate by cohesion between the adhesive and the etched surfaces of the substrate.10-21-2010
20110127666CHIP PACKAGE AND FABRICATION METHOD THEREOF - An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.06-02-2011
20100155932BONDED SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING MECHANISM - A bonded substrate comprising two semiconductor substrates is provided. Each semiconductor substrate includes semiconductor devices. At least one through substrate via is provided between the two semiconductor substrates to provide a signal path therebetween. The bottom sides of the two semiconductor substrate are bonded by at least one bonding material layer that contains a cooling mechanism. In one embodiment, the cooling mechanism is a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. In another embodiment, the cooling mechanism is a conductive cooling fin with two end portions and a contiguous path therebetween. The cooling fin is connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate.06-24-2010
20100155931Embedded Through Silicon Stack 3-D Die In A Package Substrate - An integrated circuit package has a die or die stack with through silicon vias embedded in a package substrate. A method of producing an integrated circuit package embeds at least one die with a through silicon via in a package substrate. The package substrate provides a protective cover for the die or die stack.06-24-2010
20100193939WIRING SUBSTRATE, ELECTRONIC DEVICE, AND ELECTRONIC DEVICE MOUNTING STRUCTURE - A wiring substrate includes a silicon substrate, a through hole formed to penetrate the silicon substrate in a thickness direction, an insulating layer formed on both surfaces and side surfaces of the silicon substrate and an inner surface of the through hole, a penetration electrode formed in the through hole, a wiring layer formed on at least one surface of the silicon substrate and connected to the penetration electrode, and a metal wire terminal connected to the wiring layer and formed to extend from one surface of the silicon substrate to a side surface thereof. The metal wire terminal on the side surface of the electronic device is connected to the mounting substrate such that a substrate direction of the electronic device in which an electronic component is mounted on the wiring substrate intersects orthogonally with a substrate direction of the mounting substrate.08-05-2010
20100176506THERMOELECTRIC 3D COOLING - The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips.07-15-2010
20100213603INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.08-26-2010
20110057304METHOD FOR FABRICATING A SEMICONDUCTOR AND SEMICONDUCTOR PACKAGE - A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.03-10-2011
20090184413INSULATIVE WIRING BOARD, SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD FOR PRODUCING THE INSULATIVE WIRING BOARD - The insulative wiring board of the present invention, with its both surfaces being covered with solder resist, includes at least one via hole in a semiconductor chip-mounting area penetrating the insulative wiring board, wherein conductor layers are electrically connected to each other via said at least one via hole. Further, the mounting area is covered with the solder resist, excluding said at least one via hole that penetrates the insulative wiring board. Therefore, it is possible to achieve an insulative wiring board that prevents defects caused by expansion occurred due to heating of moisture absorbed by the board, as well as reducing an area where a wiring cannot be provided.07-23-2009
20090321920Semiconductor device and method of manufacturing the same - A semiconductor device includes: a substrate; a plurality of connection pads provided on the substrate; a semiconductor chip; a plurality of electrode pads provided on the semiconductor chip; a plurality of wires electrically connecting the connection pads and the electrode pads; and a seal covering the semiconductor chip and the wires. The semiconductor chip is distanced from the substrate while being placed inside a periphery of the substrate. The seal intervenes between the semiconductor chip and the substrate.12-31-2009
20090115049SEMICONDUCTOR PACKAGE - A semiconductor package in which an electronic device chip is provided in a cavity of a silicon substrate stacked product constituted by stacking a plurality of silicon substrates.05-07-2009
20100295169SEMICONDUCTOR SUBSTRATE AND METHOD OF CONNECTING SEMICONDUCTOR DIE TO SUBSTRATE - A semiconductor substrate includes a substrate layer and a circuit film formed over the substrate layer. One or more openings are formed in the circuit film and the substrate layer. Conductive plates are formed over the circuit film at the peripheries of the openings. A semiconductor die is attached to the circuit film, below the openings with an adhesive material. A conductive material is disposed in the openings to electrically connect the semiconductor die to the conductive plates.11-25-2010
20100295168SEMICONDUCTOR PACKAGE USING CONDUCTIVE PLUG TO REPLACE SOLDER BALL - Exemplary embodiments provide a semiconductor package and methods for its formation. The disclosed semiconductor package can use conductive plug(s) to replace solder ball(s) of a conventional BGA semiconductor package. In one embodiment, the semiconductor package can include a conductive pad disposed over a first dielectric layer having a conductive plug directly extended from the conductive pad through the first dielectric layer and protruded over a surface of the first dielectric layer from about 0 micron to about 50 microns or greater. In various embodiments, arrays of the conductive plugs can be formed for the semiconductor package and can be further connected to a printed circuit board. Various exemplary methods for forming the semiconductor package can include a through-hole metal deposition to form the conductive plugs.11-25-2010
20110108977PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes a dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.05-12-2011
20110042800PACKAGE STRUCTURE - A package structure includes a first carrier board provided with a through hole, at least a filling hole in communication with the through hole, a semiconductor chip received in the through hole, and a fastening member disposed in the filling hole and abutting against the semiconductor chip so as to secure the semiconductor chip in position, thereby preventing the semiconductor chip in the through hole from displacement under an external force.02-24-2011
20100148354INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING THROUGH SILICON VIA WITH DIRECT INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.06-17-2010
20090085191Environment-Resistant Module, Micropackage And Methods Of Manufacturing Same - An environment-resistant module which provides both thermal and vibration isolation for a packaged micromachined or MEMS device is disclosed. A microplatform and a support structure for the microplatform provide the thermal and vibration isolation. The package is both hermetic and vacuum compatible and provides vertical feedthroughs for signal transfer. A micromachined or MEMS device transfer method is also disclosed that can handle a wide variety of individual micromachined or MEMS dies or wafers, in either a hybrid or integrated fashion. The module simultaneously provides both thermal and vibration isolation for the MEMS device using the microplatform and the support structure which may be fabricated from a thin glass wafer that is patterned to create crab-leg shaped suspension tethers or beams.04-02-2009
20100213602INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed. The integrated circuit is electrically connected to the external package contacts at least partly through one or more of the conductive interconnect layers. Various embodiments pertain to apparatuses that are formed by performing some or all of the aforementioned operations.08-26-2010
20090218677BOARD-ON-CHIP TYPE SUBSTRATES WITH CONDUCTIVE TRACES IN MULTIPLE PLANES, SEMICONDUCTOR DEVICE PACKAGES INCLUDING SUCH SUBSTRATES, AND ASSOCIATED METHODS - A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane. Redistribution elements including these features, as well as semiconductor device assemblies including the redistribution elements and assembly methods, are also disclosed.09-03-2009
20090218678SEMICONDUCTOR IC-EMBEDDED SUBSTRATE AND METHOD FOR MANUFACTURING SAME - A semiconductor IC-embedded substrate suitable for embedding a semiconductor IC in which the electrode pitch is extremely narrow. The substrate comprises a semiconductor IC 09-03-2009
20100038772SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. At least one penetration hole extends from one surface of the semiconductor chip to an opposite surface of the semiconductor chip. A penetration electrode is situated inside the penetration hole without contacting a wall of the penetration hole. The penetration electrode has one end fixed to the one surface of the semiconductor chip and an opposite end protruding from the opposite surface of the semiconductor chip. A connection terminal is formed on the opposite end of the penetration electrode and electrically connected to the wiring board.02-18-2010
20100072609Socket for semiconductor integrated circuit - Provided is a socket for semiconductor integrated circuit allowing a semiconductor integrated circuit to be analyzed easily. The socket for semiconductor integrated circuit according to the invention is used by mounting a package thereon. The socket for semiconductor integrated circuit includes: a socket main body which covers both a front-side surface and a back-side surface of the package and is provided with a window formed above either of the two surfaces of the package; bottom-side socket pins provided corresponding respectively to package balls of the package; upper-side socket pins provided corresponding respectively to the package balls of the package at the time when the package is mounted upside down; and wirings which electrically connect the bottom-side socket pins to the corresponding upper-side socket pins, respectively.03-25-2010
20100065961Electronic Device and Method of Manufacturing Same - This application relates to a method of manufacturing a semiconductor device comprising: providing a metal carrier; placing the metal carrier into a mold for forming a molded structure holding the metal carrier; segmenting the metal carrier into at least two disconnected metal carrier segments; and attaching a semiconductor chip to the molded structure.03-18-2010
20100127386DEVICE INCLUDING A SEMICONDUCTOR CHIP - A device including a semiconductor chip. One embodiment provides a device, including a metal layer having a first layer face. A semiconductor chip includes a first chip face. The semiconductor chip is electrically coupled to and placed over the metal layer with the first chip face facing the first layer face. An encapsulation material covers the first layer face and the semiconductor chip. At least one through-hole extends from the first layer face through the encapsulation material. The at least one through-hole is accessible from outside the device.05-27-2010
20110068459Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die - A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.03-24-2011
20110248397SEMICONDUCTOR DEVICE HAVING STACKED COMPONENTS - A semiconductor device includes at least one first component (10-13-2011
20100244235INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An integrated circuit package includes a first dielectric layer comprising a dielectric film having a first side and a second side. The package also includes a die having an active surface affixed to a contact location of the first side of the dielectric film absent a layer of adhesive therebetween that is distinct from a material of the dielectric film. A die stud is affixed to the active surface of the die and extends through the dielectric film to an interconnect location of the second side of the dielectric film, and a via is formed through the dielectric film by the die stud.09-30-2010
20090102044DEVICE INCLUDING A HOUSING FOR A SEMICONDUCTOR CHIP - A device including a housing for a semiconductor chip is disclosed. One embodiment provides a plurality of leads. A first lead forms an external contact element at a first housing side and extends at the first housing side into the housing in the direction of an opposite second housing side. The length of the first lead within the housing is greater than half the distance between the first and the second housing side.04-23-2009
20080265400Chip-Stacked Package Structure and Applications Thereof - A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, circuit board and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first rear surface is electrically connected to first surface of substrate serving by a flip chip bonding process. The circuit board has a dielectric layer set on the first rear surface and a patterned conductive layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer.10-30-2008
20080265399Low-cost and ultra-fine integrated circuit packaging technique - A semiconductor package structure and the methods for forming the same are provided. The semiconductor package structure includes an interposer; a first plurality of bonding pads on a side of the interposer; a semiconductor chip; and a second plurality of bonding pads on a side of the semiconductor chip. The first and the second plurality of bonding pads are bonded through metal-to-metal bonds.10-30-2008
20110068460INTEGRATION OF SMD COMPONENTS IN AN IC HOUSING - The invention relates to an electronic component having a semiconductor component, particularly a semiconductor chip, and at least one SMD component, a chip carrier with a support platform and with connecting leads. Whereby the semiconductor component, which is connected electrically via chip bonds to bond fingers of the connecting leads is mounted on the support platform and the SMD component connects the support platform to a connecting lead via contact surfaces arranged thereon, a housing, which encloses the semiconductor component, the SMD component, and at least partially the chip carrier. The support platform and the connecting lead in the area of the SMD component are profiled to create barriers in such a way that flowing of a free-flowing material from the contact surfaces connected to the SMD component of the chip carrier both onto the support platform and onto the connecting lead is prevented.03-24-2011
20080203556Through-Wafer Interconnection - A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer. The patterned trench extends in depth from the front side to the backside of the wafer, and has an annular opening generally dividing the conductive wafer into an inner portion and an outer portion whereby the inner portion of the conductive wafer is insulated from the outer portion and serves as a through-wafer conductor. A dielectric material is formed or added into the patterned trench mechanical to support and electrically insulate the through-wafer conductor. Multiple conductors can be formed in an array.08-28-2008
20110163438SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.07-07-2011
20110163437Semiconductor package and method of manufacturing the same - There is provided a semiconductor package. A semiconductor package according to an aspect of the invention may include a core part having a semiconductor chip mounted within a receiving space therein; an insulation part provided on one surface of the core part; and a via part provided by filling a hole-processed surface formed simultaneously through the insulation part and a passivation layer for protecting an electrode pattern part on the semiconductor chip.07-07-2011
20100320595HYBRID HERMETIC INTERFACE CHIP - A hermetically sealed MEMS device package comprises a MEMS device platform, a hermetic interface chip, and an outer seal ring. The MEMS device platform includes a MEMS device surrounded by a continuous outer boundary wall with a top surface. The hermetic interface chip includes a glass substrate and at least one silicon mesa. The glass substrate includes at least one hole and has a lower surface with an inner portion surrounded by an outer portion. The at least one silicon mesa is bonded to the inner portion of the lower surface of the glass substrate, such that the at least one silicon mesa is aligned with the at least one hole in the glass substrate. The outer seal ring bonds the outer portion of the lower surface of the glass substrate to the top surface of the continuous outer boundary wall of the MEMS device platform.12-23-2010
20100213601INTEGRATED CIRCUIT MICRO-MODULE - In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer or electrically conductive vias. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, interconnect layers, conductive vias that electrically connect different components of the package and/or passive devices. In some specific embodiments, the dielectric layers are formed from a suitable epoxy such as SU-8 type. In a method aspect of the invention, the dielectric layers may be formed using a spin-on coating approach and patterned using conventional photolithographic techniques.08-26-2010
20100176507SEMICONDUCTOR-BASED SUBMOUNT WITH ELECTRICALLY CONDUCTIVE FEED-THROUGHS - A submount for a micro-component includes a semiconductor substrate having a cavity defined in a front-side of the substrate in which to mount the micro-component. The submount also includes a thin silicon membrane portion at a bottom of the cavity and thicker frame portions adjacent to sidewalls of the cavity. The substrate includes an electrically conductive feed-through connection extending from a back-side of the substrate at least partially through the thicker silicon frame portion. Electrical contact between the feed-through connection and a conductive layer on a surface of the cavity is made at least partially through a sidewall of the cavity.07-15-2010
20090267221SEMICONDUCTOR DEVICE - An antenna formed on one surface side of a silicon substrate and a semiconductor element provided on the other surface side of the silicon substrate are electrically connected to each other by means of a through via penetrating the silicon substrate. A wiring board is formed separately from the silicon substrate. A passive element is provided on one surface side of the wiring board. A copper core solder ball is provided between the one surface side of the wiring board and the other surface side of the silicon substrate and electrically connects the silicon substrate and the wiring board to each other.10-29-2009
20110186983PACKAGE FOR HOUSING SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE USING THE SAME - According to one embodiment, a package for housing semiconductor element includes: a base plate including a top surface and a recessed portion formed as a downwardly-recessed portion of the top surface; a peripheral wall provided on the top surface of the base plate; a lid provided on an upper side of the peripheral wall and forming a semiconductor element housing space in cooperation with the base plate and the peripheral wall; and a feed-through terminal including a bottom end and fixed to the recessed portion so that the bottom end is located at a lower position than the top surface of the base plate except the recessed portion.08-04-2011
20090057872Through-Chip Via Interconnects for Stacked Integrated Circuit Structures - A stacked IC structure has an integrated circuit (IC) having a front IC side, a back IC side, and a first conductive feature formed on the front IC side. A through-chip via connects to the first conductive feature on the front IC side. A substrate has an external circuit formed on a front surface. The IC attaches to the front surface of the substrate and the through-chip via forms a connection between the first conductive feature and the external circuit.03-05-2009
20090174060HYBRID INTEGRATED CIRCUIT DEVICE, AND METHOD FOR FABRICATING THE SAME, AND ELECTRONIC DEVICE - A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.07-09-2009
20090174062CIRCUIT BOARD, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF CIRCUIT BOARD - A circuit board includes a semiconductor substrate which has a plurality of through holes passing from an upper surface to a lower surface thereof. A plurality of wiring lines are provided on the upper surface of the semiconductor substrate and have bottomed cylindrical portions located within regions corresponding to the through holes. Bottom surfaces of the bottomed cylindrical portions of the wiring lines serve as connection pad portions.07-09-2009
20090174061Semiconductor Device - To prevent peeling-off of a film in a solder connection pad of a semiconductor device, which peeling-off may occur due to thermal load and so on in the manufacture process, a pad structure is adopted in which a Cr film good in adhesiveness to either of a Ti film or Ti compound film and a Ni film (or a Cu film) is interposed between the Ti film or Ti compound film formed on a silicon or silicon oxide film, and the Ni film (or the Cu film) to be connected to solder. Further, to prevent peeling-off at the interface between the Ti film or Ti compound film and the silicon oxide film, the Cr film is formed in a larger area than the Ti film or Ti compound film.07-09-2009
20110115071INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.05-19-2011
20110115070Semiconductor Device and Method of Forming Protective Material Between Semiconductor Die Stacked on Semiconductor Wafer to Reduce Defects During Singulation - A semiconductor wafer contains first semiconductor die. TSVs are formed through the semiconductor wafer. Second semiconductor die are mounted to a first surface of the semiconductor wafer. A first tape is applied to on a second surface of the semiconductor wafer. A protective material is formed over the second die and first surface of the wafer. The protective material can be encapsulant or polyvinyl alcohol and water. The wafer is singulated between the second die into individual die-to-wafer packages each containing the second die stacked on the first die. The protective material protects the wafer during singulation. The die-to-wafer package can be mounted to a substrate. A build-up interconnect structure can be formed over the die-to-wafer package. The protective material can be removed. Underfill material can be deposited beneath the first and second die. An encapsulant is deposited over the die-to-wafer package.05-19-2011
20110304038SEMICONDUCTOR CHIP DESIGNED TO DISSIPATE HEAT EFFECTIVELY, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND STACK PACKAGE USING THE SAME - A semiconductor chip includes a semiconductor chip body having a top surface, a bottom surface, and side surfaces. The bottom surface may have a groove pattern defined by removing a partial thickness of the semiconductor chip body to extend from one or more edges of the semiconductor chip body toward a center portion of the semiconductor chip body. Through electrodes may be formed to extend from the top surface of the semiconductor chip body and pass through the groove pattern defined on the bottom surface. A heat dissipation pattern may fill in the groove pattern defined on the bottom surface and may be connected with the through electrodes.12-15-2011
20110316140MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME - A microelectronic package includes a substrate (12-29-2011
20110156242SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface; (b) forming vias through the silicon wafer in its thickness direction; (c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias; (d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias; (e) dividing the MEMS element wafer into the respective MEMS elements; (f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and (g) dicing the lid and the silicon wafer.06-30-2011
20100019376HIGH FREQUENCY CERAMIC PACKAGE AND FABRICATION METHOD FOR THE SAME - A high frequency ceramic package includes: a first conductive pattern placed on the top surface of a ceramic RF substrate; a second conductive pattern placed on the bottom surface of the ceramic RF substrate; a through hole for passing through the top surface and bottom surface of the ceramic RF substrate; a through hole metal layer which is filled up in the through hole and which connects the first conductive pattern and the second conductive pattern; a ceramic seal ring placed on the ceramic RF substrate; an insulating adhesive bond placed on the ceramic seal ring; and a ceramic cap placed on the insulating adhesive bond, wherein the second conductive pattern is used as an external terminal, and between the ceramic cap and the top surfaces of the ceramic seal ring is sealed with the insulating adhesive bond and it is simple for structure and excellent in high frequency characteristics.01-28-2010
20120061817SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.03-15-2012
20120119347SEMICONDUCTOR DEVICE - A semiconductor device comprises at least a semiconductor module including a semiconductor chip, a heat sink thermally connected to the semiconductor chip and a seal member for covering and sealing the semiconductor chip and the heat sink in such a manner as to expose the heat radiation surface of the heat sink. The radiation surface is cooled by a refrigerant. An opening is formed in a part of the seal member as a refrigerant path through which the refrigerant flows.05-17-2012
20120153452Double-Sided Semiconductor Device and Method of Forming Top-Side and Bottom-Side Interconnect Structures - A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect structure is formed over the first insulating layer and first conductive layer. A temporary carrier is mounted to the first interconnect structure. A second active device is formed on a second side of the semiconductor wafer. A second insulating layer is formed over the second side of the wafer. A second conductive layer is formed over the second insulating layer. A second interconnect structure is formed over the second insulating layer and second conductive layer. The temporary carrier is removed, leaving a double-sided semiconductor device. The double-sided semiconductor device is enclosed in a package with the first and second interconnect structures electrically connected.06-21-2012
20100096744PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - Embodiments of the present invention provide a printed wiring board in which solder bumps of a mounted semiconductor chip are less prone to be ruptured. The printed wiring board includes a coreless substrate which includes: a dielectric layer having a main surface and a connecting pad embedded in the dielectric layer. The connecting pad is shaped like a brimmed hat. That is, the connecting pad includes a plate portion whose diameter φ04-22-2010
20090134510SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME, AND ELECTRONIC DEVICE USING THE SEMICONDUCTOR PACKAGE - A semiconductor package and method of fabricating the same. The semiconductor package includes a first semiconductor package, a second semiconductor package stacked on the first semiconductor package, and a first electrical connector interposed between the first and second semiconductor packages to electrically connect the first and second semiconductor packages.05-28-2009
20120119348Semiconductor Device and Method of Electrically Connecting a Shielding Layer to Ground Through a Conductive Via Disposed in Peripheral Region around Semiconductor Die - A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.05-17-2012
20120168930SEMICONDUCTOR DEVICE - A semiconductor device has high reliability which suppresses a temperature rise of a set housing within an allowable range, and avoids an effect on a wiring on a package substrate due to thermal expansion of a heat dissipating member. The semiconductor device includes a semiconductor element, a package substrate, and a heat dissipating member. A first main surface of the semiconductor element faces an element-mounting surface of the package substrate and is connected to the package substrate. A main surface part of the heat dissipating member contacts a second main surface which is a back surface of first main surface of semiconductor element. A bonding part around a periphery of the main surface part is bonded to a bonding area of the element-mounting surface of the package substrate. A wiring on the package substrate is arranged at a portion other than the element-mounting surface, in a region of the bonding area.07-05-2012
20090032934POTENTIAL-FREE HOUSING LEADTHROUGH - The invention relates to a circuit arrangement with an electronic circuit on a printed circuit board and an electrically screening housing surrounding the circuit board, wherein there are on said circuit board a HF plug-and-socket connector connected to the electronic circuit with an outer conductor part and an inner conductor part, wherein the HF plug-and-socket connector penetrates through an opening in the housing. The outer conductor part of the HF plug-and-socket connector is electrically isolated from the housing, and wherein a tunnel-like screening sleeve surrounds the outer conductor part both axially and circumferentially at least partially, the sleeve being connected electrically to the housing and capacitively to the outer conductor part of the HF plug-and-socket connector.02-05-2009
20090020865Method for Packaging Semiconductor Dies Having Through-Silicon Vias - An integrated circuit structure is provided. The integrated circuit structure includes a die and an anisotropic conducing film (ACF) adjoining the back surface of the die. The die includes a front surface; a back surface on an opposite side of the die than the front surface; and a through-silicon via (TSV) exposed through the back surface of the die.01-22-2009
20120228755SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREOF - A semiconductor module includes a high frequency chip, an insulating cap, a through electrode, interconnections, and an insulating layer. The insulating cap forms a hollow with the chip to cover the chip. The through electrode passes through a first plane of the cap and a second plane of the cap, the first plane facing the chip, the second plane being on a side opposite to the first plane. The interconnections are provided on the cap and connected to the through electrode. The insulating layer is provided on the cap and fills a portion between the interconnections therewith.09-13-2012
20100327429SEMICONDUCTOR PACKAGE STRUCTURE AND PACKAGE METHOD THEREOF - A semiconductor package structure and a package method thereof are provided. The semiconductor package structure includes a substrate, a sensing chip, a first patterned conductive layer and a electrical connection portion. The substrate has an accommodating portion, a first surface and a second surface opposite to the first surface. The accommodating portion are extended to the second surface from the first surface.12-30-2010
20110018124Semiconductor Device Packages, Redistribution Structures, and Manufacturing Methods Thereof - Described herein are semiconductor device packages and redistribution structures including alignment marks and manufacturing methods thereof.01-27-2011
20120319265INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED LASER VIA INTERPOSER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.12-20-2012
20080237836SEMICONDUCTOR CHIP EMBEDDING STRUCTURE - A semiconductor chip embedding structure is disclosed, including a carrier board having a first and an opposed second surfaces and formed with at least a through hole; a semiconductor chip received in the through hole, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is formed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are formed on surfaces of the electrode pads; a buffer layer formed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer formed on the buffer layer; and a first circuit layer formed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures formed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expansion) of the buffer layer is between the CTE of the semiconductor chip and the CTE of the dielectric layer. Thereby, the buffer layer can reduce the stress on the interface between the dielectric layer and the semiconductor chip.10-02-2008
20080237835NON-UNIFORM FEEDTHROUGH AND LEAD CONFIGURATION FOR A TRANSISTOR OUTLINE PACKAGE - A transistor outline package having a feedthrough via and lead configuration that maximizes the amount of usable area on a header of the package is disclosed. In one embodiment, the package includes a header having an interior surface that includes a first and second lead assembly. The first lead assembly includes two vias having a first diameter, with each first via being positioned along a first pin circle imaginarily defined on the interior surface of the header. Each first via also includes first leads received therein. The second lead assembly includes four vias having a second diameter each, with each second via being positioned along a second pin circle that has a diameter greater than that of the first pin circle. Each second via includes second leads received therein. This configuration increases usable area on the header interior surface between the leads, enabling relatively larger submounts to be placed thereon.10-02-2008
20080230891CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS - A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.09-25-2008
20080230890STRUCTURE AND ELECTRONICS DEVICE USING THE STRUCTURE - A structure includes a circuit substrate including a first substrate and a second substrate. The first substrate has a region where an electronic component is to be mounted. The second substrate has a side surface connected to a first side surface of the first substrate. The structure further includes a frame on the circuit substrate, enclosing the region in a plane view. The frame crosses the boundary between the first substrate and the second substrate.09-25-2008
20080224301Lead Structure for a Semiconductor Component and Method for Producing the Same - A lead structure for a semiconductor component includes: external leads for external connections outside a plastic housing composition, internal leads for electrical connections within the plastic housing composition, and a chip mounting island composed of the lead material. While leaving free contact pads of the internal leads, the top sides of the chip mounting island and the internal leads are equipped with nanotubes as an anchoring layer. The plastic housing composition is arranged in the interspaces between the nanotubes arranged on the internal leads, while an adhesive composition for the semiconductor chip is arranged in the interspaces between the nanotubes arranged on the chip mounting island. The adhesive composition and the plastic housing composition fill the interspaces in a manner free of voids.09-18-2008
20110272797SEMICONDUCTOR LIGHT EMITTING DEVICE AND POWER SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a casing, a semiconductor element, a terminal and a screw member. The semiconductor element is housed within the casing. The terminal is electrically connected to the semiconductor element, and has an externally projecting part extending out of the casing. The screw member is movably provided along a surface of the casing between the externally projecting part and the casing, and fixes an external terminal to the externally projecting part.11-10-2011
20130099369Hermetic Surface Mount Packages for Diodes and Transistors - A discrete semiconductor package includes a discrete semiconductor device disposed upon a non-conductive substrate, with via-connected upper and lower conductive ports. By utilizing a plurality of vias to connect the ports within the non-conductive substrate, and by depositing metals directly upon the surface of the substrate, manufacturing of such semiconductor packages is cheaper and more effective.04-25-2013
20080197481Semiconductor sensor having flat mounting plate - A semiconductor sensor for detecting a rotational speed of a rotor is contained in a cylindrical housing, an opening of which is closed with a cover member. The cover member includes a mounting plate integrally molded therewith. Components including a bare sensing chip and other circuit chips are directly mounted on a flat surface of the mounting plate. The components mounted on the flat surface are covered with gel having a high flowability. The gel is prevented from flowing out of the flat surface toward the cover member by banks formed at both sides of the flat surface. On an inner wall of the bank, curved surfaces and depressions are formed to surely suppress creeping up of the gel and to trap the gel therein if it creeps up the inner wall of the bank. Thus, the gel is surely prevented from flowing out even though the banks do not entirely surround the flat mounting surface.08-21-2008
20080197480Semiconductor device package with multi-chips and method of the same - The present invention provides a semiconductor device package with the multi-chips comprising a substrate with a die receiving through hole, a conductive connecting through holes structure and coupled the first contact pads on an upper surface and second contact pads on a lower surface of the substrate through a conductive connecting through holes. A first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though holes of the substrate. Then, a first conductive wire is formed to couple the first bonding pads and the first contact pads. Further, a second die having second bonding pads is attached on the first die. A second conductive wire is formed to couple the second bonding pads and the first contact pads. A plurality of dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.08-21-2008
20080197479SEMICONDUCTOR PACKAGE, INTEGRATED CIRCUIT CARDS INCORPORATING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SAME - One embodiment of a semiconductor package described herein includes a substrate having a first through-hole extending therethrough; a conductive pattern overlying the substrate and extending over the first through-hole; a first semiconductor chip facing the conductive pattern such that at least a portion of the first semiconductor chip is disposed within the first through-hole; and a first external contact terminal within the first through-hole and electrically connecting the conductive pattern to the first semiconductor chip.08-21-2008
20080197478SEMICONDUCTOR DEVICE PACKAGE WITH DIE RECEIVING THROUGH-HOLE AND CONNECTING THROUGH-HOLE AND METHOD OF THE SAME - The present invention provides a semiconductor device package with the die receiving through hole and connecting through holes structure comprising a substrate with a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A die is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Further, a bonding wire is formed to couple and the bonding pads and the first contact pads. A dielectric layer is formed on the bonding wire, the die and the substrate.08-21-2008
20130147026HEATSINK INTERPOSER - According an embodiment, a package-on-package heatsink interposer for use between a top package and a bottom package of a package-on-package device, may include a top heatsink below the top package; an interposer substrate below the top heatsink; a bottom heatsink below the interposer substrate; a first interposer substrate metal layer between the interposer substrate and the top heatsink; a second interposer substrate metal layer between the interposer substrate and the bottom heatsink; and interposer solder balls between the second interposer substrate metal layer and the bottom package.06-13-2013
20100308454POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD - A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.12-09-2010
20100308453Integrated circuit package including a thermally and electrically conductive package lid - An integrated circuit package includes a thermally and electrically conductive package lid. The package lid may be in electrical communication with an electrically conductive pad connected to a power plane, ground plane, or signal route in the integrated circuit. The electrically conductive package lid may provide an electrical connection for electrical power or electrical signals or may serve as an electrical ground. In some embodiments, the package lid may include a thermally and electrically conductive material. In other embodiments, the package lid may include an electrically insulative substrate coated on at least one surface with a layer of metal or another conductive material. The conductive layer may be electrically connected to electrical ground, a reference voltage, or a signal pay by at least one electrically conductive via.12-09-2010
20100314749SEMICONDUCTOR DEVICE HAVING A SEALING RESIN AND METHOD OF MANUFACTURING THE SAME - The semiconductor device 12-16-2010
20090289349HERMETIC SEALING OF MICRO DEVICES - An encapsulated device includes a micro device on a substrate, a micro chamber that encapsulates the micro device on the substrate; and a layer of hermetic-sealing material that provides at least some degree of hermeticity on one or more outer surfaces of the micro chamber to at least partially hermetically seal the micro device in the micro chamber.11-26-2009
20120018871STACK PACKAGE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.01-26-2012
20130193568Terminal Box - A plurality of terminal plates are arranged in a row in the interior of a box body. Neighboring terminal plates are electrically connected by a diode. The diode is provided with a first terminal part that is laid on, soldered to, and electrically connected to the first terminal plate. A slit is provided formed along the outer perimeter of a region on which the first terminal part is laid on the first terminal plate.08-01-2013
20120068330STAGED VIA FORMATION FROM BOTH SIDES OF CHIP - A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.03-22-2012
20120086116ELECTRONIC COMPONENT DEVICE, METHOD OF MANUFACTURING THE SAME AND WIRING SUBSTRATE - An electronic component device includes a substrate, an electrode post made of a metal material, provide to stand on the substrate, and an electronic component whose connection electrode is connected to the electrode post, wherein the connection electrode of the electronic component and the electrode post are joined by an alloy layer including a metal which is different from the metal material of the electrode post.04-12-2012
20130207254SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING A SEMICONDUCTOR CHIP, DEVICE AND METHOD FOR MANUFACTURING A DEVICE - Embodiments of the present invention relate to a semiconductor chip comprising a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.08-15-2013

Patent applications in class With specific electrical feedthrough structure

Patent applications in all subclasses With specific electrical feedthrough structure