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With contact or lead

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257678000 - HOUSING OR PACKAGE

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257692000 With particular lead geometry 396
257698000 With specific electrical feedthrough structure 141
257691000 Having power distribution means (e.g., bus structure) 69
257700000 Multiple contact layers separated from each other by insulator means and forming part of a package or housing (e.g., plural ceramic layer package) 51
Entries
DocumentTitleDate
20130043578PRESSPIN, POWER SEMICONDUCTER MODULE AND SEMICONDUCTER MODULE ASSEMBLY WITH MULTIPLE POWER SEMICONDUCTER MODULES - A first presspin includes a foot, whereby a base of the foot is provided for contacting a contact element of a power semiconductor device, such as within a power semiconductor module including a base plate and at least one power semiconductor device, which is arranged on the base plate and contacted by at least one further presspin. An insulation means is provided for electrically an outer surface of the foot. A power semiconductor module is also provided including a base plate, at least one power semiconductor device arranged on the base plate, and at least one of the aforementioned first presspin provided with the aforementioned insulation means. A power semiconductor module assembly is also provided including multiple power semiconductor modules as specified above, whereby the power semiconductor modules are arranged side by side to each other with electric connections between adjacent power semiconductor modules.02-21-2013
20110198744LAND GRID ARRAY PACKAGE CAPABLE OF DECREASING A HEIGHT DIFFERENCE BETWEEN A LAND AND A SOLDER RESIST - A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.08-18-2011
20090206465SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving electrical connection without using a wire-bonding process includes: a package unit, a semiconductor chip, a first insulative layer, first conductive layers, a second insulative layer, and second conductive layers. The package unit has a receiving groove. The semiconductor chip receives in the receiving groove and has a plurality of conductive pads disposed on its top surface. The first insulative layer is formed among the conductive pads in order to insulate the conductive pads from each other. The first conductive layers are formed on the first insulative layer, and one side of each first conductive layer is electrically connected to the corresponding conductive pad. The second insulative layer is formed among the first conductive layers in order to insulate the first conductive layers from each other. The second conductive layers are respectively formed on the other opposite sides of the first conductive layers.08-20-2009
20090179320INTEGRATED CIRCUIT INCORPORATING WIRE BOND INDUCTANCE - The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package such as a quad flat pack, a ball grid array or hybrid style module. The present invention takes the normally undesirable wire bond inductance and uses it in an operational circuit where positive inductance is required. The circuit in which the wire bond inductance is used is located primarily in the integrated circuit die housed in the integrated circuit package, but may also include off-die components. In one example, a wire bond is used as the required series inductance in a discrete circuit impedance inverter which consists of two shunt-to-ground negative inductances and one series positive inductance. One of the negative inductances is located on-die, while the other is located off-die.07-16-2009
20090194863SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - A semiconductor package includes: a semiconductor substrate; an inner insulator layer formed on the substrate; at least one internal wiring extending from a front side of the substrate along one of lateral sides of the substrate to a rear side of the substrate; a first outer insulator layer disposed at the front side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole; and a second outer insulator layer disposed at the rear side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole which exposes a portion of the internal wiring.08-06-2009
20090194862SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor module having improved heat radiation efficiency. A semiconductor module includes a semiconductor element, a pair of Cu heat radiating plates sandwiching the semiconductor element, insulating and heat radiating plates sandwiching the Cu heat radiating plates, heat radiating fins sandwiching the insulating and heat radiating plates, and solder applied between the Cu heat radiating plates and the insulating and heat radiating plates as well as between the insulating and heat radiating plates and the heat radiating fins.08-06-2009
20130043579POWER SEMICONDUCTOR ARRANGEMENT, POWER SEMICONDUCTOR MODULE WITH MULTIPLE POWER SEMICONDUCTOR ARRANGEMENTS, AND MODULE ASSEMBLY COMPRISING MULTIPLE POWER SEMICONDUCTOR MODULES - A power semiconductor arrangement includes a base plate having a molybdenum layer, and a power semiconductor device mounted to a top side of the base plate and electrically and thermally coupled thereto. The base plate includes a metallic mounting base, which is arranged between the semiconductor device and the molybdenum layer and prevents the molybdenum layer from forming highly resistive intermetallic phases with the semiconductor device. A semiconductor module, such as a power semiconductor module, includes multiple semiconductor arrangements, whereby the base plate of the semiconductor arrangements is a common base plate. A module assembly, such as a power semiconductor module assembly, includes multiple semiconductor modules, whereby the semiconductor modules are arranged side by side to each other with electric connections between adjacent semiconductor modules.02-21-2013
20110186980Wireless Element With Antenna Formed On A Thin Film Substrate For Embedding into Semiconductor packages - In one embodiment, a wireless tag includes a wireless transceiver, a memory and an antenna all formed on a thin film substrate where the substrate includes one or more openings formed thereon. The opening in the substrate enables the flow of encapsulation material when the wireless tag is embedded into a semiconductor package. In another embodiment, a wireless tag is attached to the package substrate of a semiconductor package where the thin film substrate of the wireless tag has an opening sufficient to accommodate the integrated circuit die of the semiconductor package. In another embodiment, a wireless tag is formed using a metal film as the antenna and a wireless element attached to the metal film. The wireless tag is attached to the package substrate of a semiconductor package using a non-conductive adhesive. The metal film includes an opening sufficient to accommodate the die of the semiconductor package.08-04-2011
20100084755Semiconductor Chip Package System Vertical Interconnect - Stacked semiconductor chip package system vertical interconnects and related methods are disclosed. A preferred embodiment of the invention includes a first semiconductor chip with a surface bearing a plurality of first fusible metallic coupling elements. A second semiconductor chip has a plurality of second fusible metallic coupling elements. The first and second fusible metallic coupling elements correspond at the adjoining surfaces of the first and second semiconductor chips when stacked, and are fused to form a gold-tin eutectic alloy fused metallic coupling vertically interconnecting the stacked chips.04-08-2010
20100078799MICROELECTRONIC PACKAGE WITH CARBON NANOTUBES INTERCONNECT AND METHOD OF MAKING SAME - A method of forming a microelectronic package is provided. The method includes providing a silicon substrate having a plurality of carbon nanotubes disposed on a silicon layer and coupling the silicon substrate to a top surface of a packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of substrate pads of the packaging substrate. The method also includes removing the silicon substrate from the packaging substrate and disposing a die adjacent to the top surface of the packaging substrate, wherein the plurality of carbon nanotubes are coupled to a plurality of bump pads of the die.04-01-2010
20100072603SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES WITH EDGE CONTACTS AND SACRIFICIAL SUBSTRATES AND OTHER INTERMEDIATE STRUCTURES USED OR FORMED IN FABRICATING THE ASSEMBLIES OR PACKAGES - A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device.03-25-2010
20080315389Bumpless Flip-Chip Assembly With a Complaint Interposer Contractor - Consistent with an example embodiment, an integrated circuit device (IC) is assembled on a package substrate and encapsulated in a molding compound. There is a semiconductor die having a circuit pattern with contact pads. A package substrate having bump pad landings corresponding to the contact pads of the circuit pattern, has an interposer layer sandwiched between them. The interposer layer includes randomly distributed mutually isolated conductive columns of spherical particles embedded in an elastomeric material, wherein the interposer layer is subjected to a compressive force from pressure exerted upon an underside surface of the semiconductor die. The compressive force deforms the interposer layer causing the conductive columns of spherical particles to electrically connect the contact pads of the circuit pattern with the corresponding bump pad landings of the package substrate. The compressive force may be obtained from forces generated by thermal expansion properties of the molding compound and package substrate, metal clips or combinations, thereof.12-25-2008
20100044852VERTICAL STACK TYPE MULTI-CHIP PACKAGE HAVING IMPROVED GROUNDING PERFORMANCE AND LOWER SEMICONDUCTOR CHIP RELIABILITY - A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire. A mold resin seals the second semiconductor chip and a solder ball is bonded to a solder ball pad below the organic substrate.02-25-2010
20100044851Flip chip packages - Flip chip packages and methods of manufacturing the same are provided, the flip chip packages may include a package substrate, a semiconductor chip, conductive bumps, a ground pattern and an underfilling layer. The semiconductor chip may be over the package substrate. The conductive bumps may be between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The ground pattern may ground one of the package substrate and the semiconductor chip. The underfilling layer may be between the package substrate and the semiconductor chip to surround the conductive bumps. The underfilling layer may have a diode selectively located between the ground pattern and the conductive bumps by electrostatic electricity applied to the underfilling layer to protect the semiconductor chip from the electrostatic electricity.02-25-2010
20100044850ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - An advanced quad flat non-leaded package structure includes a carrier, a chip and a molding compound. The carrier includes a die pad and a plurality of leads. The die pad has a central portion, a peripheral portion disposed around the central portion and a plurality of connecting portions connecting the central portion and the peripheral portion. The central portion, the peripheral portion, and the connecting portions define at least two hollow regions. The leads are disposed around the die pad. The chip is located within the central portion of the die pad and electrically connected to the leads via a plurality of wires. The molding compound encapsulates the chip, the wires, inner leads and a portion of the carrier.02-25-2010
20100096742CUT-OUT HEAT SLUG FOR INTEGRATED CIRCUIT DEVICE PACKAGING - In a package, a heat slug, encapsulated by molding compound, encases an integrated circuit device (IC). In an example embodiment, a semiconductor package structure comprises a substrate having conductive traces and pad landings. The conductive traces have pad landings. An IC is mounted on the substrate. The IC has bonding pads. With conductive wires, the IC bonding pads are connected to the pad landings, which in turn, are connected to the conductive traces. A heat slug, having predetermined height, is disposed on the substrate surface. The heat slug includes a plurality of mounting feet providing mechanical attachment to the substrate. A cavity in the heat slug accommodates the IC. A plurality of first-size openings surrounds the IC. A second-size opening constructed from one of the first size-openings, is larger than the first-size opening. The second size-opening facilitates the introduction of molding compounds into the cavity of the heat slug.04-22-2010
20090160044SEMICONDUCTOR MODULE MOUNTING STRUCTURE - The semiconductor module mounting structure includes a semiconductor module including therein a semiconductor device and electrodes exposed to both surfaces thereof, a wiring substrate having a mounting surface on which the semiconductor module is mounted, and a heat radiating body for dissipating heat from the semiconductor module. The wiring substrate is formed with a ground wiring such that at least a part of the ground wiring is exposed to a back surface thereof opposite to the mounting surface. The exposed surface of the ground wiring exposed to the back surface is in thermal contact with the heat radiating body. At least one of the electrodes exposed to one of the both surfaces opposed to the wiring substrate is in electrical contact with the ground wiring through a through hole formed in the wiring substrate.06-25-2009
20090160043Dice Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration - A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of metal traces is electrically connected to the each pads; a protection layer is provided to cover the active surface and the other ends of the exposed metal traces is electrically connected to the plurality of conductive elements, the characteristic in that the package body is a B-stage material.06-25-2009
20100109142INTERPOSER FOR SEMICONDUCTOR PACKAGE - An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.05-06-2010
20100109144SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including: a semiconductor substrate including an electrode; a resin protrusion formed on the semiconductor substrate; and an interconnect electrically connected to the electrode and formed to extend over the resin protrusion. The interconnect includes a first portion formed on a top surface of the resin protrusion and a second portion formed on a side of a lower portion of the resin protrusion. The second portion has a width smaller than a width of the first portion.05-06-2010
20100109143SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package includes forming a protection layer on a support plate, stacking substrates on the protection layer, electrically connecting the substrates to each other, forming a molding layer on the support plate, and removing the support plate while the protection layer remains on the substrates. The stacked substrates are offset from adjacent substrates.05-06-2010
20100109140FLEXIBLE SEMICONDUCTOR PACKAGE APPARATUS HAVING A RESPONSIVE BENDABLE CONDUCTIVE WIRE MEMBER AND A MANUFACTURING THE SAME - A flexible semiconductor package apparatus having a responsive bendable conductive wire member is presented. The apparatus includes a flexible substrate, semiconductor chips, and conductive wires. The semiconductor chips are disposed on the flexible substrate and spaced apart from each other on the flexible substrate. Each semiconductor chip has bonding pads. The conductive wires are electrically connected to the bonding pads of the semiconductor chip. Each conductive wire has at least one elastic portion. One preferred configuration is that part of the conductive wire is wound to form a coil spring shape so that the coil spring shape of the conductive wire aid in preventing the conductive wire from being separated from the corresponding bonding pad of the semiconductor chip when the flexible substrate on which the semiconductor chips are mounted are bent, expanded or twisted.05-06-2010
20100109141SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY CARD - A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.05-06-2010
20090152708SUBSTRATE FOR HIGH SPEED SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.06-18-2009
20130082373LOW-INDUCTIVE SEMICONDUCTOR MODULE - A semiconductor module includes a module housing, at least one substrate, a number N of at least two controllable power semiconductor chips arranged inside the module housing and one after another in a lateral direction, a single main load terminal arranged outside the module housing and electrically connected to the first main electrodes, and an auxiliary terminal arranged outside the module housing and electrically connected to the first main electrodes via an auxiliary terminal connecting conductor.04-04-2013
20130087902INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL STRUCTURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a thermal attach cluster includes: forming a heat collector having a heat dissipation surface, forming a cluster bridge, having a thermal surface, connected to the heat collector, forming a cluster pad, having an attachment surface, connected to the end of the cluster bridge opposite the heat collector; connecting an integrated circuit to the thermal attach cluster; and forming an encapsulation over the thermal attach cluster with the heat dissipation surface, the thermal surface, and the attachment surface exposed from and coplanar with the encapsulation.04-11-2013
20130087903Electronics Packaging For High Temperature Downhole Applications - A downhole tool is described. The downhole tool includes a work device and an electronics packaging connected to the work device. The electronics packaging comprises a housing, a substrate, at least one first type component, and at least one second type component. The housing defines a void. The substrate is positioned within the void of the housing and forms a first cavity and a second cavity relative to the housing. The first cavity and the second cavity are isolated to form separate atmospheric chambers. The at least one first type component is disposed in the first cavity and connected to the substrate. The at least one second type component is disposed in the second cavity and connected to the substrate. The at least one first type component is different from the at least one second type component.04-11-2013
20100327422SEMICONDUCTOR CHIP, METHOD OF FABRICATING THE SAME, AND STACK MODULE AND MEMORY CARD INCLUDING THE SAME - A semiconductor chip, a method of fabricating the same, and a stack module and a memory card including the semiconductor chip include a first surface and a second surface facing the first surface is provided. At least one via hole including a first portion extending in a direction from the first surface of the substrate to the second surface of the substrate and a second portion that is connected to the first portion and has a tapered shape. At least one via electrode filling the at least one via hole is provided.12-30-2010
20100133679COMPLIANT INTEGRATED CIRCUIT PACKAGE SUBSTRATE - An integrated circuit package may include a plurality of interconnects, and an integrated package substrate coupled to the plurality of interconnects and comprising an integrated circuit package substrate core. A first surface of the integrated circuit package substrate core may define a depression.06-03-2010
20090108434SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, PDP DRIVER, AND PLASMA DISPLAY PANEL - In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved. The conductive leads of a resin package for supplying a power supply section of a semiconductor integrated circuit chip with power from an external power supply are connected with bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires. Furthermore, the conductive leads connected to a GND for supplying the power supply section of the semiconductor integrated circuit chip with a grounding potential are connected with the bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires.04-30-2009
20100102433APPARATUS FOR USE IN SEMICONDUCTOR WAFER PROCESSING FOR LATERALLY DISPLACING INDIVIDUAL SEMICONDUCTOR DEVICES AWAY FROM ONE ANOTHER - A chip-scale or wafer-level package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed package, is provided. The package may be formed by disposing a first passivation layer on the passive or back side surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.04-29-2010
20100102430SEMICONDUCTOR MULTI-CHIP PACKAGE - A semiconductor multichip package includes a substrate having a top surface on which a bonding pad is formed, and a bottom surface opposing the top surface, on which an external connection terminal electrically connected with the bonding pad is formed, a first semiconductor chip mounted on a region of the top surface of the substrate excluding the bonding pad, a ceramic spacer disposed on a top surface of the first semiconductor chip and including a passive device therein, and at least one second semiconductor chip disposed on a top surface of the ceramic spacer. The ceramic spacer includes an interlayer circuit for an electrical connection between the first and second semiconductor chips, and the passive device is electrically connected to at least one of the first and second semiconductor chips. Accordingly, a package with a more compact structure can be realized.04-29-2010
20120217627PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure is provided that includes a metal plate; a semiconductor chip having an active surface, electrode pads disposed on the active surface, conductive bumps disposed on the electrode pads, and an inactive surface opposing the active surface and attached with the metal plate by a thermal conductive adhesive; an encapsulant formed on the metal plate for encapsulating a perimeter of the semiconductor chip, with the active surface of the semiconductor chip being exposed thereon; a first dielectric layer formed on the encapsulant and the active surface of the semiconductor chip, and having wiring trenches for exposing the conductive bumps; and a first wiring layer formed in the wiring trenches of the first dielectric layer and electrically connected to the conductive bumps. The wiring layer, through the electrical connection of the conductive bumps with the semiconductor chip prevents the use of bonding wires as a conductive pathway.08-30-2012
20100084759Die Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration - A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a polymer material with at least one slit is provided to cover the active surface and the pads is exposed from said slits; one ends of a plurality of metal traces is electrically connected to each pads; a protective layer is provided to cover the active surface of the dies and each metal traces, and the other ends of the metal traces being exposed; a plurality of connecting elements is electrically connected other ends of the metal traces, the characterized in that: the package body is a B-stage material.04-08-2010
20090267214ELECTRONIC CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SAME - The electronic circuit device of the present invention includes at least one semiconductor element, a plurality of external connection terminals, a connecting conductor for electrically connecting semiconductor element and external connection terminals, and an insulating resin for covering the semiconductor element and supporting the connecting conductor integrally, in which the semiconductor element is buried in the insulating resin, and the terminal surface of the external connection terminals is exposed from the insulating resin.10-29-2009
20130062749SEMICONDUCTOR MODULE - A semiconductor module that can be connected with simple wiring is provided. A semiconductor device of the semiconductor module is provided with a semiconductor substrate, a first electrode formed on one surface of the semiconductor substrate, and a second electrode formed on a surface of the semiconductor substrate opposite to the one surface. The semiconductor module is provided with a first electrode plate being in contact with the first electrode, a second electrode plate being in contact with the second electrode, and a first wiring member connected to the second electrode plate and penetrating the first electrode plate in a state of being insulated from the first electrode plate. The first electrode plate, the semiconductor device, and the second electrode plate are fixed with each other by an application of a pressure pressurizing the semiconductor device on the first electrode plate and the second electrode plate.03-14-2013
20110012250SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A semiconductor device includes a first die pad, a first semiconductor chip provided on the first die pad, a second die pad, a second semiconductor chip provided on the second die pad, and a sealing resin made of a first resin material, sealing the first die pad, the first semiconductor chip, the second die pad and the second semiconductor chip. A lower surface of the first semiconductor chip is connected to the first die pad. A first portion of a lower surface of the second semiconductor chip is connected to the second die pad, and a second portion not connected to the second die pad of the lower surface of the second semiconductor chip is connected to an upper surface of the first semiconductor chip via a second resin material different from the first resin material.01-20-2011
20090236726PACKAGE-ON-PACKAGE SEMICONDUCTOR STRUCTURE - A semiconductor package that includes a substrate having first and second major surfaces is presented. The package includes a plurality of landing pads and a semiconductor die disposed on the first major surface. A molded cap is disposed on the first surface to encapsulate the die and substrate. The landing pads are covered when the cap is molded. Package interconnects are coupled to the landing pads. The package interconnects are exposed by the cap to facilitate package stacking.09-24-2009
20090236725Solder Preform and Electronic Component - An electronic component having a semiconductor element bonded to a substrate with solder has a decreased bonding strength if there is not a suitable clearance between the semiconductor element and the substrate. Therefore, a solder preform having high melting point metal particles dispersed in solder has been used in the manufacture of electronic components. However, when an electronic component was manufactured using a conventional solder preform, there were cases in which the semiconductor element leaned or the bonding strength was not adequate.09-24-2009
20090236724IC PACKAGE WITH WIREBOND AND FLIPCHIP INTERCONNECTS ON THE SAME DIE WITH THROUGH WAFER VIA - Integrated circuit dies, integrated circuit packages, and methods for assembling the same are provided. An integrated circuit package includes a substrate, an integrated circuit die, a plurality of electrically conductive bump interconnects, an electrically conductive material, and one or more bond wires. The electrically conductive bump interconnects mount a first surface of the die to a first surface of the substrate. The electrically conductive material forms an electrically conductive path from a first electrically conductive feature on the first surface of the die to a second electrically conductive feature on the second surface of the die. The bond wire couples the second electrically conductive feature to a third electrically conductive feature on the first surface of the substrate. In this manner, flip chip bump interconnects and bond wires are available to interface signals of the die with the substrate.09-24-2009
20090026602Method For Manufacturing And Making Planar Contact With An Electronic Apparatus, And Correspondingly Manufactured Apparatus - Reliable electrical contact is made with electronic components and effective electrical isolation is produced between the top and bottom of the electronic components. An electronic component is arranged inside a window in a first layer on a substrate. Next, a second layer is put on such that contact areas on the component and contact points on the first layer are freely accessible. Electrical contacts and electrical connecting lines are produced by electrodeposition. The second layer is used to produce bridges over an interval range between the electronic component and the first layer. The bridges have connecting lines formed on them. The second layer can be removed again. Radio-frequency modules can be produces in compact fashion and can be combined with audio-frequency components.01-29-2009
20110024892THERMALLY ENHANCED HEAT SPREADER FOR FLIP CHIP PACKAGING - A flip chip microelectronic package having a heat spreader is provided. In one embodiment, the microelectronic package comprises a die having a first surface and a second surface, the first surface being coupled to a substrate; a thermal interface material disposed in thermal conductive contact with the second surface of the die; and a heat spreader adapted for dissipating heat from the die, the heat spreader disposed in thermal conductive contact with the thermal interface material. The heat spreader includes a lid having an inner chamber therein defined by a first wall and a second wall, the second wall securely joined to the first wall to seal the chamber, the lid being mounted to the substrate and a wick layer positioned in the chamber.02-03-2011
20090321915System-in-package and manufacturing method of the same - The present invention discloses a structure of package comprising: a substrate with a die receiving through hole and a contact conductive via formed therein, a die disposed within the die receiving through hole, a surrounding material filled in the gap except the die area of the die receiving though hole, a re-distribution layer formed on the substrate and coupled to the contact conductive via, a protection layer formed over the re-distribution layer, a cover material formed over the protection layer; and a terminal contact pad formed on the lower surface of the substrate and under the contact conductive via and the die to couple the contact conductive via.12-31-2009
20090152706INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECT LOCK - An integrated circuit package system includes: mounting a device structure over a package carrier; connecting an internal interconnect between the device structure and the package carrier; forming an interconnect lock over the internal interconnect over the device structure with interconnect lock exposing the device structure; and forming a package encapsulation adjacent to the interconnect lock and over the package carrier.06-18-2009
20100171212SEMICONDUCTOR PACKAGE STRUCTURE WITH PROTECTION BAR - A semiconductor package structure includes a carrier, a chip or multi-chips mounted on a top surface of the carrier, a molding compound encapsulating the top surface and the chips, a plurality of solder balls distributed on a bottom surface of the carrier, and a protection bar formed of thermosetting plastic material formed on the bottom surface.07-08-2010
20100171211SEMICONDUCTOR DEVICE - A semiconductor device is provided by the present invention. The semiconductor device includes a semiconductor die, and the semiconductor die includes a die core having at least two bond pads with voltage level equivalent to each other and electrically connected to each other via at least a bond wire, and an input/output (I/O) periphery. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost.07-08-2010
20090206468Board on chip package and manufacturing method thereof - A method of manufacturing a board on chip package including laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; removing the dry film; laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; mounting a semiconductor chip on the solder ball pad by a flip chip bonding; molding the semiconductor chip with a passivation material; removing the carrier film and the thin metal film; and laminating a lower photo solder resist under the solder ball pad. The board on chip package provides a high density circuit since a circuit pattern is formed using a seed layer.08-20-2009
20080296750SEMICONDUCTOR DEVICE - A semiconductor device comprises a semiconductor chip having a photoelectric conversion function and conductor connecting with the semiconductor chip electrically. The semiconductor chip is sealed by resin. The resin comprises a first sealing resin, second sealing resin and third sealing resin. The second sealing resin has transparency for optical signal to the semiconductor chip and seals one side of the conductor. The third sealing resin seals the other side of the conductor and has a linear thermal expansion coefficient and thickness which may restrain at least a part of flexion of the conductor caused by the linear thermal expansion of the second sealing resin. The first sealing resin seals at least a part of the conductor, is sandwiched between the second sealing resin and the third sealing resin, and has a linear thermal expansion coefficient which may restrain at least a part of the linear thermal expansion of the second sealing resin.12-04-2008
20090091016I/O PAD STRUCTURES FOR INTEGRATED CIRCUIT DEVICES - A semiconductor device, including methods and arrangements for making the same, are described. The device includes an integrated circuit die having a plurality of bond pads. At least one bond pad on the active surface of the die is an extended I/O pad. Each extended I/O pad extends to at least one peripheral side edge of the die.04-09-2009
20100090329HIGH-POWER DEVICE HAVING THERMOCOUPLE EMBEDDED THEREIN AND METHOD FOR MANUFACTURING THE SAME - Provided is a high-power device having a thermocouple (thermoelectric couple) for measuring the temperature of a transistor constituting a high-power device. The high-power device includes a heating element, a thermocouple formed adjacent to the heating element, and a dielectric body formed between the heating element and the thermocouple.04-15-2010
20110291256Method for Fabricating a Semiconductor Chip Package and Semiconductor Chip Package - A semiconductor chip includes a contact pad on a main surface of the chip. An electrically conductive layer is applied onto the contact pad. The main surface of the semiconductor chip is covered with an insulating layer. An electrically conductive contact area is formed within the insulating layer such that the contact area and the insulating layer include coplanar exposed surfaces and the contact area is electrically connected with the electrically conductive layer and includes an extension which is greater than the extension of the electrically conductive layer along a direction parallel to the main surface of the semiconductor chip.12-01-2011
20100213596STACK PACKAGE - A stack package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, a lower stack group, an upper stack group, and connection members. The lower stack group is attached to the upper surface of the substrate and includes at least two semiconductor chips which are stacked in a face-up type to form on or more steps. The upper stack group is disposed over the lower stack group and includes at least two semiconductor chips which are stacked in a face-down type in such a way as to form one or more steps whose direction mirrors the direction of the at least one step of the lower stack group. The connection members electrically connect the semiconductor chips of the lower and upper stack groups to the substrate.08-26-2010
20100078796Semiconductor Device - This application relates to a semiconductor device comprising multiple separate leads molded in a molded structure, and a chip attached to the molded structure over at least two of the multiple separate leads.04-01-2010
20080246137INTEGRATED CIRCUIT DEVICE AND METHOD FOR THE PRODUCTION THEREOF - An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.10-09-2008
20110169156SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF AND ENCAPSULATING METHOD THEREOF - A semiconductor package, a manufacturing method thereof and an encapsulating method thereof are provided. The semiconductor package includes a substrate, a semiconductor chip, a plurality of conductive parts and a sealant. The conductive parts electrically connect an upper surface of the substrate and an active surface of the semiconductor chip. The sealant covers a back surface of the semiconductor chip, wherein the space between the upper surface of the substrate and the active surface of the semiconductor chip is filled with a portion of the sealant. The back surface of the semiconductor is spaced apart from a top surface of the sealant by a first distance, the upper surface of the substrate is spaced apart from the active surface of the semiconductor chip by a second distance, and the ratio of the first distance to the second distance is smaller than or equal to 5.07-14-2011
20100148348PACKAGE SUBSTRATE - A package substrate is disclosed. The package substrate as a printed circuit board, in which a semiconductor chip is mounted on one side thereof and the other side thereof is mounted on a main board, can include a substrate part, a first pad, which is formed on one side of the substrate part such that the first pad is electrically connected to the semiconductor chip, and a first solder resist layer, which is formed on one surface of the substrate part such that the first pad is exposed. Here, the first solder resist layer is divided into a pad portion and a dummy portion, the first pad is exposed in the pad portion, and the dummy portion is thinner than the pad portion. The package substrate can contribute to the formation of a structure in which thermal expansion coefficients are symmetrical between the top and bottom, thus preventing the warpage.06-17-2010
20090212411SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.08-27-2009
20090189273MULTIPHASE SYNCHRONOUS BUCK CONVERTER - Disclosed in this specification is a multiphase buck converter package and process for forming such package. The package includes at least four dice and several parallel leads. The dice are electrically connected through a plurality of die attach pads, thus eliminating the need for wirebonding.07-30-2009
20090189272Wafer Level Chip Scale Packages Including Redistribution Substrates and Methods of Fabricating the Same - Provided are wafer level chip scale packages, each having a redistribution substrate in which a pad pitch is improved, and methods of fabricating the same. An exemplary wafer level chip scale package includes a semiconductor chip and a redistribution substrate. The semiconductor chip includes a plurality of pads arranged with a first pitch on a first surface thereof. The redistribution substrate includes a plurality of connection wires arranged with a second pitch, which is greater than the first pitch, on a first surface thereof. The redistribution substrate expands a pad pitch from the first pitch to the second pitch by electrically connecting the pads to the connection wires.07-30-2009
20090189271PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE, CARD APPARATUS, AND SYSTEM - A printed circuit board providing high reliability using a packaging of high capacity semiconductor chip, a semiconductor package, and a card and a system using the semiconductor package. The semiconductor package includes a substrate having a first surface and a second surface, a semiconductor chip mounted on the first surface of the substrate, at least one land disposed on the second surface of the substrate, and whose circumference includes a plurality of first group arcs, a mask layer covering the second surface of the substrate and including at least one opening that exposes the at least one land, and at least one external terminal disposed on the at least one land, wherein a portion of the at least one land is covered by the mask layer, and a sidewall of another portion of the at least one land is exposed by the at least one opening, and the circumference of the at least one opening includes a plurality of second group arcs, and a radius of the outermost arc from among the plurality of first group arcs is equal to a radius of the outermost arc from among the plurality of second group arcs.07-30-2009
20090189270MANUFACTURING PROCESS AND STRUCTURE FOR EMBEDDED SEMICONDUCTOR DEVICE - A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads.07-30-2009
20090189269Electronic Circuit Package - A electronic circuit package having a flexible substrate with metals layers on one or more of its surfaces forming a wiring pattern and/or surface mount bonding pads. Passive electronic components are integrated onto component packages that are mounted to the flexible substrate and electrically connected with the wiring pattern or bonding pad. An active electronic device is mounted on the flexible substrate or bonding pad.07-30-2009
20090184410SEMICONDUCTOR PACKAGE APPARATUS HAVING REDISTRIBUTION LAYER - Provided is a semiconductor package apparatus having a redistribution layer. The apparatus includes at least one or more semiconductor chips, a packing part protecting the semiconductor chips, and a support part supporting the semiconductor chips. The apparatus also includes external terminals extending outside the packing part, redistribution layers installed between the semiconductor chips and the support part and including redistribution paths, first signal transmitting units, and second signal transmitting units. The first signal transmitting units transmitting electrical signals generated from the semiconductor chips to the redistribution paths of the redistribution layers, and the second signal transmitting units transmit the electrical signals from the redistribution paths to the external terminals. Therefore, a size and a thickness of the semiconductor package apparatus can be reduced, and processes can be simplified to improve productivity.07-23-2009
20090026601SEMICONDUCTOR MODULE - A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to the second main surface, and an electrically insulating material covering the first electrically conductive layer, wherein a surface of the second electrically conductive layer forms an external contact pad and the second electrically conductive layer has a thickness of less than 200 μm.01-29-2009
20090146286DIRECT ATTACH INTERCONNECT FOR CONNECTING PACKAGE AND PRINTED CIRCUIT BOARD - A direct attach interconnect includes a housing and spring contacts. The housing has top and bottom sides lying in parallel planes defined by x and y axes. Passages extend along the z axis between the top and bottom housing sides. Each spring contact has a middle portion and top and bottom ends. The spring contacts are individually disposed within respective passages such that the top ends of the spring contacts extend out through the top housing side and the bottom ends of the spring contacts extend out through the bottom housing side. The middle portion of each spring contact includes a connector which movably connects the middle portion of the spring contact to the passage for the spring contact such that the spring contact is movable along the x, y, and z axes. The top and bottom ends of each spring contact include one of a solder sphere and a solder pad.06-11-2009
20090152709SEMICONDUCTOR DEVICE - A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer.06-18-2009
20090152707METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS - Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.06-18-2009
20080237829High current lead electrode for semiconductor device - A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die.10-02-2008
20080237828SEMICONDUCTOR DEVICE PACKAGE WITH DIE RECEIVING THROUGH-HOLE AND DUAL BUILD-UP LAYERS OVER BOTH SIDE-SURFACES FOR WLP AND METHOD OF THE SAME - The present invention discloses a structure of package comprising a substrate with at least one die receiving through holes, a conductive connecting through holes structure and a contact pads on both side of substrate. At least one die is disposed within the die receiving through holes. A first material is formed under the die and second material is formed filled in the gap between the die and sidewall of the die receiving though holes. Dielectric layers are formed on the surface of both side of the die and the substrate. Redistribution layers (RDL) are formed on the both sides and coupled to the contact pads. A protection bases are formed over the RDLs.10-02-2008
20110210439Semiconductor Package and Manufacturing Method Thereof - A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes a device carrier and a stiffener structure. The device carrier includes at least one insulating layer and at least conductive layer defining at least one trace layout unit. The stiffener structure is disposed on the device carrier, surrounding the periphery of the at least one trace layout unit. The stiffener structure is disposed away from the periphery of the at least one trace layout unit, forming a cavity with the device carrier. The shape and disposition of the stiffener structure enhance the strength of the semiconductor package, impeding flexure to the semiconductor package.09-01-2011
20080265395Semiconductor device and method of fabricating the semiconductor device - A semiconductor device includes: a package substrate that includes a recessed portion, with electrode pads that are electrically connected to electrodes of the semiconductor chip being formed inside the recessed portion; a semiconductor chip that is housed in the recessed portion; terminal-use wires that are formed on the surface of the package substrate and are electrically connected to the electrode pads; external connection pads that are formed on a back surface of the package substrate and are electrically connected to the electrode pads; a sealing resin portion that includes a grinded surface that is parallel to the surface of the package substrate, and seals at least the semiconductor chip by a sealing resin; rewiring pads that are formed on the grinded surface; and connecting wires that are formed on the grinded surface and electrically interconnect the terminal-use wires and the rewiring pads.10-30-2008
20080265393STACK PACKAGE WITH RELEASING LAYER AND METHOD FOR FORMING THE SAME - The present invention provides a structure and a of stacked dice package and a process for forming the same, wherein an elastic adhesive layer applied on the first die covering all top surface of the first die and forming rims at the peripheral edges of the first die except the openings formed on the first contacting pads. With this shape of the elastic adhesive layer, the present invention can avoid micro crack happens in the die while performing wire bonding on the contacting pad of the die.10-30-2008
20090001546Ultra-thick thick film on ceramic substrate - An electrically isolated and thermally conductive double-sided pre-packaged integrated circuit component exhibiting excellent heat dissipative properties, durability and strength, and which can be manufactured at a low cost includes electrically insulated and thermally conductive substrate members having outer surfaces, ultra-thick thick film materials secured to the outer surfaces of the substrate members and a lead member and a transistor member positioned between the substrate members.01-01-2009
20090001545INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SIDE SUBSTRATE - An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit over the package substrate; and attaching a side substrate adjacent the integrated circuit over the package substrate.01-01-2009
20100123238Packaging structure of sip and a manufacturing method thereof - A manufacturing method for a packaging structure of SIP (system in package) includes the following steps. First step is providing a substrate having electronic devices thereon. Second step is covering the electronic devices by a mixture of a molding compound and a conductive polymer precursor so as to form a molding structure, wherein the substrate, the electronic devices and the molding structure forms a collective electronic module. Third step is separating the collective electronic module into a plurality of individual electronic modules. Fourth step is performing a doping step by using a doping element for transforming the conductive polymer precursor in the mixture into a conductive layer near the surface of the molding structure. Therefore, the manufacturing method is optimized for forming a shielding structure of the SIP module.05-20-2010
20090085188POWER SEMICONDUCTOR MODULE - A power semiconductor module comprising: a power semiconductor element; a case for receiving the power semiconductor element; a control terminal which is connected to a control electrode of the power semiconductor element, the control terminal is installed in a state of protruding from an upper surface of the case; and a conductive spring which is inserted into the control terminal so that an inner surface of the spring makes contact with at least a part of the side surface of the control terminal, the conductive spring is electrically connected to a printed substrate placed as opposed to the upper surface of the case by making pressurization contact with the printed substrate.04-02-2009
20090309211Compliant Wirebond Pedestal - A wire bonder (12-17-2009
20090309210SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.12-17-2009
20090309209Die Rearrangement Package Structure and the Forming Method Thereof - A die rearrangement package structure is provided, which includes an active surface of die with the pads; a first polymer material is covered on the active surface of die and the pads is to be exposed; the conductive posts is disposed among the first polymer material and is electrically connected to the pads; an encapsulated structure is covered the die and the first polymer material and the conductive posts is to be exposed; a second polymer material is covered on the first polymer material and the encapsulated structure to expose the conductive posts; the fan-out patterned metal traces are disposed on the second polymer material and one ends of each fan-out patterned metal traces is electrically connected to the conductive posts; and the conductive elements is electrically connected to another ends of the patterned metal traces.12-17-2009
20100084758Semiconductor package - Provided is a semiconductor package including a mark pattern and a method of manufacturing the same. The semiconductor package may include at least one semiconductor chip including a circuit region, a protection layer covering the circuit region, a molding portion sealing the protection layer and the at least one semiconductor chip, the molding portion having an exposed top surface on the circuit region, and a mark pattern at the top surface of the molding portion. A method of fabricating the semiconductor package may include providing at least one semiconductor chip including a circuit region, forming a protection layer covering the circuit region, forming a molding portion sealing the protection layer and the at least one semiconductor chip, the molding portion having an exposed top surface on the circuit region, and forming a mark pattern at the top surface of the molding portion using a laser.04-08-2010
20100078798INSULATION COVERING STRUCTURE FOR A SEMICONDUCTOR ELEMENT WITH A SINGLE DIE DIMENSION AND A MANUFACTURING METHOD THEREOF - An insulation covering structure for a semiconductor element with a single die dimension includes: a semiconductor element with a single die dimension and an insulation covering layer. The semiconductor element has a front side surface, a rear side surface, a left side surface, a right side surface, a bottom surface, and a top surface. The top surface of the semiconductor element has two metal pads. The insulation covering layer covers the front side surface, the rear side surface, the left side surface, the right side surface, and the bottom surface of the semiconductor element. A manufacturing process for covering the semiconductor element with a single die dimension is also disclosed.04-01-2010
20100084757CONDUCTIVE COMPOSITIONS AND METHODS OF USING THEM - A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.04-08-2010
20100078795ELECTRONIC DEVICE - The electronic device comprises a semiconductor substrate (04-01-2010
20100078797SYSTEM AND METHOD FOR PRE-PATTERNED EMBEDDED CHIP BUILD-UP - A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.04-01-2010
20110062575Semiconductor Device and Method of Forming Cavity in PCB Containing Encapsulant or Dummy Die Having CTE Similar to CTE of Large Array WLCSP - A semiconductor device has a PCB with a cavity formed in a first surface of the PCB. A stress compensating structure, such as an encapsulant or dummy die, is disposed in the cavity. An insulating layer is formed over the PCB and stress compensating structure. A portion of the insulating layer is removed to expose the stress compensating structure. A conductive layer is formed over the stress compensating structure. A solder masking layer is formed over the conductive layer with openings to the conductive layer. A semiconductor package is mounted over the cavity. The semiconductor package is a large array WLCSP. Bumps electrically connect the semiconductor package and conductive layer. The semiconductor package is electrically connected to the conductive layer. The CTE of the stress compensating structure is selected substantially similar to or matching the CTE of the semiconductor package to reduce stress between the semiconductor package and PCB.03-17-2011
20090206466SEMICONDUCTOR DEVICE - A semiconductor device is provided that can further reduce the thickness of an electronic device and that can reduce its own mounting area and development period. This semiconductor device has a first semiconductor chip and a second semiconductor chip, and is formed in a WLCSP type package. On the upper surface of the first semiconductor chip, an integrated circuit is formed and, in a region other than where it is formed, a recess is formed. An integrated circuit is formed on the second semiconductor chip. The second semiconductor chip is provided in the recess of the first semiconductor chip such that the upper surface of the first semiconductor chip is level with that of the second semiconductor chip.08-20-2009
20100127375WAFER LEVEL CHIP SCALE SEMICONDUCTOR PACKAGES - Wafer-level chip scale (WLCSP) semiconductor packages and methods for making and using the same are described. The WLCSP semiconductor packages contain a grid array of land pads rather than solder balls or solder bumps. The land pads can be provided directly on a semiconductor wafer by using a leadframe interconnect structure that has been formed from a leadframe. The land pads can be used to mount the WLCSP to a circuit board. Such a configuration allows the formation of a thinner chip scale semiconductor package using a simpler manufacturing process, thereby reducing costs and improving performance. Other embodiments are described.05-27-2010
20090102042Semiconductor device and method of fabricating semiconductor device - A semiconductor device including a semiconductor chip having external connecting terminals formed on one side is restrained to cause chipping in ridge line portion of semiconductor chip. A cover layer 04-23-2009
20090278249Printed circuit board and method thereof and a solder ball land and method thereof - A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance. A second example method may include first treating a solder ball land to increase a first type of resistance and second treating the solder ball land to increase a second type of resistance other than the first type of resistance.11-12-2009
20110198743Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device - A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.08-18-2011
20080211080Package structure to improve the reliability for WLP - The present invention provides a package structure to improve the reliability for WLP (Wafer Level Package). The package structure includes at least two areas. One area is harder than another. The hard area sustains more shears resulting from board drop test than the soft area in order to disperse the shear in the soft area to avoid the peeling of the buffer layers within the soft area.09-04-2008
20090166841PACKAGE SUBSTRATE EMBEDDED WITH SEMICONDUCTOR COMPONENT - A package substrate embedded with a semiconductor component includes a substrate, a semiconductor chip, a first dielectric layer, a first circuit layer and first conductive vias. The substrate is formed with an opening for allowing the semiconductor chip to be secured therein. The semiconductor chip has an active surface and an inactive surface, wherein a plurality of electrode pads are formed on the active surface thereof and a passivation layer disposed thereon. The first dielectric layer is disposed both on the substrate and the passivation layer, wherein vias are formed at locations corresponding to those of the electrode pads and penetrating the dielectric layer and the passivation layer to expose the electrode pads therefrom. The first circuit layer is disposed on the first dielectric layer and electrically connected to the first conductive vias. The first conductive vias are disposed in the openings of the dielectric and passivation layers and the first circuit layer is electrically connected to the electrode pads, thereby allowing the first conductive vias to be electrically connected to the electrode pads of the chip.07-02-2009
20090278248SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - A semiconductor device includes a first die pad, a first semiconductor chip provided on the first die pad, a second die pad, a second semiconductor chip provided on the second die pad, and a sealing resin made of a first resin material, sealing the first die pad, the first semiconductor chip, the second die pad and the second semiconductor chip. A lower surface of the first semiconductor chip is connected to the first die pad. A first portion of a lower surface of the second semiconductor chip is connected to the second die pad, and a second portion not connected to the second die pad of the lower surface of the second semiconductor chip is connected to an upper surface of the first semiconductor chip via a second resin material different from the first resin material.11-12-2009
20090283891ELASTICALLY DEFORMABLE INTEGRATED-CIRCUIT DEVICE - The present invention relates to an integrated-circuit device comprising a multitude of separate rigid substrate islands (11-19-2009
20090283892Design method of semiconductor package substrate - When the impedance of a first circuit is deviated from a standard value, a second circuit is designed for generating a second reflected wave to cancel a first reflected wave generated by the first circuit. Individual structural parts in a transmission line are intentionally designed to be deviated from a standard impedance reversely under a fine control. By this method, the impedance matching between the input and output impedance of the semiconductor element and the transmission line is achieved. As a result, the terminal impedance of the component of the semiconductor circuit and the semiconductor package substrate is adjusted to 50 Ohm, so that a good signal property can be obtained.11-19-2009
20090289346Structure and manufacturing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.11-26-2009
20090289345ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package and a fabrication method thereof are provided. The fabrication method includes providing a semiconductor substrate containing a plurality of chips having a first surface and an opposite second surface. A plurality of conductive electrodes is disposed on the first surface and the conductive electrodes of the two adjacent chips are arranged asymmetrically along side direction of the chip. A plurality of contact holes is formed in each chip, apart from the side of the chip, to expose the conductive electrodes.11-26-2009
20090289344Semiconductor device - A semiconductor device includes an insulating substrate; at least one semiconductor element mounted on a first principal surface of the insulating substrate; and a heat radiator joined through a solder member to a second principal surface of the insulating substrate opposite to the first principal surface on which the semiconductor element is mounted. The solder member contains at least tin and antimony, and the antimony content of the solder member is in a range of from 7% by weight to 15% by weight, both inclusively. Thus, reliability of the semiconductor device is improved.11-26-2009
20090289342Semiconductor Device and Semiconductor Device Manufacturing Method - In an inventive semiconductor device production method, a one-side metal layer is first formed in a region located across a predetermined section line on one surface of a substrate. Further, an other-side metal layer is formed on the other surface of the substrate in a position opposed to the one-side metal layer. In turn, a continuous through-hole extending continuously through the other-side metal layer and the substrate is formed in a position located across the section line. Thereafter, a metal plating layer is formed on a surface of the other-side metal layer, an inner surface of the continuous through-hole and a portion of the one-side metal layer exposed to the continuous through-hole. Before the resulting substrate is cut into separate support boards, a portion of the other-side metal layer present on the section line and a portion of the metal plating layer present on this other-side metal layer portion are removed.11-26-2009
20090294950SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.12-03-2009
20090294949MOLDED SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip and at least one metal line over a first side of the semiconductor chip. The semiconductor device includes a molded body covering at least a second side of the semiconductor chip. The molded body includes at least one recess.12-03-2009
20090261469SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Manufacturing a semiconductor package includes preparing a semiconductor chip having a top surface with bumps electrically connected to bonding pads, a bottom surface opposite to the top surface and side surfaces joining the top surface to the bottom surface. The bottom surface of the semiconductor chip is attached to a base substrate. A heat pressure process is performed to form a wiring support member on the base substrate to cover the top surface and the side surfaces of the semiconductor chip while exposing each of the bumps. Wirings are formed to be electrically connected to the bumps on the wiring support member. The base substrate is removed from the semiconductor chip and the wiring support member.10-22-2009
20090261468SEMICONDUCTOR MODULE - A semiconductor module. One embodiment provides at least two semiconductor chips placed on a carrier. The at least two semiconductor chips are then covered with a molding material to form a molded body. The molded body is thinned until the at least two semiconductor chips are exposed. Then, the carrier is removed from the at least two semiconductor chips. The at least two semiconductor chips are singulated.10-22-2009
20090008765CHIP EMBEDDED SUBSTRATE AND METHOD OF PRODUCING THE SAME - A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.01-08-2009
20090008764Ultra-Thin Wafer-Level Contact Grid Array - Wafer-level chip-scaled packaging (WLCSP) features are described in a semiconductor die having a plurality of lands providing electrical connection between a surface of the semiconductor die and an active layer of the semiconductor die. Each of the plurality of lands rises above the surface no more than 10 μm. The device also has a plurality of solder bars at corners of the semiconductor die, the plurality of solder bars also rising above the surface no more than 10 μm. The solder bars add overall contiguous surface area to the solder joints between the die package and its final attachment.01-08-2009
20110204506Thermal Interface Material Design for Enhanced Thermal Performance and Improved Package Structural Integrity - An electronic package 08-25-2011
20090039495WIRING SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME - An active matrix substrate includes a first substrate and a driving integrated circuit chip mounted on the first substrate. A support member is provided between the active matrix substrate and the driving IC chip so as to be in contact with both the active matrix substrate and the driving IC chip.02-12-2009
20100102431POWER MODULE AND INVERTER FOR VEHICLES - According to the present invention, a power module in which the thermal stress between a semiconductor chip and a substrate is relaxed by liquefaction of a solder layer, by which the semiconductor chip is positioned on the substrate, such that generation of cracks between the semiconductor chip and the substrate can be prevented and bonding strength is ensured is provided. Further, the following is provided: a power module 04-29-2010
20100102432SEMICONDUCTOR PACKAGE - A semiconductor package has an interconnection substrate including a first conductive lead and a second longer conductive lead, and a semiconductor chip including a first cell region, a second cell region, a first conductive pad electrically connected to the first cell region and a second conductive pad electrically connected to the second cell region. The semiconductor chip is mounted to the interconnection substrate with the first and second conductive pads both disposed on and connected to the second conductive lead.04-29-2010
20100102429FLIP-CHIP PACKAGE STRUCTURE WITH BLOCK BUMPS AND THE WEDGE BONDING METHOD THEREOF - A flip-chip block structure with block bumps comprises a die, a substrate, a first block bump, and a second block bump. The die comprises an active side and a backside, a first die pad and a second die pad are disposed on the active surface, and an electrode layer is disposed on the backside. The first die pad and the second die pad are connected to the pattern side of the substrate via the first block bump and the second block bump respectively. Besides, the first block bump and the second block bump are formed by a wedge bonding method, therefore, the block bumps are more easily formed into larger sizes, which enhance electrical performance and thermal dissipation performance of the flip-chip structure due to a lower contact resistance and a larger contact area between the die and the substrate.04-29-2010
20100102434SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED VOLTAGE TRANSMISSION PATH AND DRIVING METHOD THEREOF - Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.04-29-2010
20080246138Packed System of Semiconductor Chips Having a Semiconductor Interposer - A semiconductor system (10-09-2008
20100127377Method for Producing a MEMS Package - A carrier substrate has a mounting location with a number of electrical connection pads on a top side and external contacts connected thereto on an underside. A metal frame encloses the connection pads of the mounting location. A MEMS chip has electrical contacts on an underside. The MEMS chip is placed on the mounting location of the carrier substrate in such a way that the MEMS chip is seated with an edge region of its underside on the metal frame. Using a flip-chip process, the electrical contacts of the MEMS chip are connected to the connection pads of the carrier substrate by means of bumps the metal frame is connected to the MEMS chip such that a closed cavity is formed between MEMS chip and carrier substrate.05-27-2010
20090174056SEMICONDUCTOR MODULE - A semiconductor module is disclosed. One embodiment provides a first semiconductor chip having a first contact pad on a first main surface and a second contact pad on a second main surface, a first electrically conductive layer applied to the first main surface, a second electrically conductive layer applied to the second main surface, and an electrically insulating material covering the first electrically conductive layer, wherein a surface of the second electrically conductive layer forms an external contact pad and the second electrically conductive layer has a thickness of less than 200 μm.07-09-2009
20080277772Methods of Packaging a Semiconductor Die and Package Formed by the Methods - A method of packaging a semiconductor die (11-13-2008
20080277771Electronic Device Package Manufacturing Method and Electronic Device Package - By joining a lid member to a base member, internal electrodes put in contact with the lid member and an electronic device connected to the internal electrodes are placed in an internal space located in between the base member and the lid member. Then, by performing etching from a surface of the lid member on the side opposite from the base member by a prescribed method, through holes that reach the surface of the internal electrodes are formed. A conductive material is given to the through holes, and external electrodes connected to the internal electrodes are formed in a plane, completing a thin type electronic device package.11-13-2008
20080283996SEMICONDUCTOR PACKAGE USING CHIP-EMBEDDED INTERPOSER SUBSTRATE - A semiconductor package using a chip-embedded interposer substrate is provided. The chip-embedded interposer substrate includes a chip including a plurality of chip pads; a substrate having the chip mounted thereon and including a plurality of redistribution pads for redistributing the chip pads; bonding wires for connecting the chip pads to the redistribution pads; a protective layer having via holes for exposing the redistribution pads while burying the chip and the substrate; and vias connected to the redistribution pads through the via holes. The semiconductor package including chips of various sizes is fabricated using the chip-embedded interposer substrate.11-20-2008
20080283995COMPACT MULTI-PORT CAM CELL IMPLEMENTED IN 3D VERTICAL INTEGRATION - A multi-ported CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-ported CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the multi-port CAM can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-port CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays. Each compare match line and data bit line has the length associated with a simple two-dimensional Static Random Access Memory (SRAM) cell array.11-20-2008
20080290494Backside release and/or encapsulation of microelectromechanical structures and method of manufacturing same - There are many inventions described and illustrated herein. In one aspect, the present inventions relate to devices, systems and/or methods of encapsulating and fabricating electromechanical structures or elements, for example, accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), filter or resonator. The fabricating or manufacturing microelectromechanical systems of the present invention, and the systems manufactured thereby, employ backside substrate release and/or seal or encapsulation techniques.11-27-2008
20080303133INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONTOURED DIE - An integrated circuit package system is provided including forming an external interconnect, providing a contoured integrated circuit die having both an extension and a base portion with the extension extending beyond the base portion, placing the contoured integrated circuit die with the base portion coplanar with the external interconnect and the extension overhanging the external interconnect, connecting the contoured integrated circuit die and the external interconnect, and forming a package encapsulation over the contoured integrated circuit die and the external interconnect with both partially exposed.12-11-2008
20080308922METHOD FOR PACKAGING SEMICONDUCTORS AT A WAFER LEVEL - A method for packaging a plurality of semiconductor devices formed in a surface portion of a semiconductor wafer. The method includes: lithographically forming in a material disposed on the surface portion of the semiconductor wafer device-exposing openings to exposed the devices and electrical contacts pads openings to expose electrical contact pads for devices; mounting a rigid dielectric layer over the formed material, such rigid material being suspended over the device exposing openings in the material and over the electrical contacts pads openings in the material; and forming electrical contact pad openings in portions of the rigid dielectric layer disposed over electrical contact pads of the devices with other portions of the rigid dielectric layer remaining suspended over the device exposing openings in the material.12-18-2008
20100127376SYSTEM AND METHOD TO PROVIDE RF SHIELDING FOR A MEMS MICROPHONE PACKAGE - A semiconductor package has a substrate. An opening is formed through the substrate. A first RF shield is formed around a perimeter of the opening. A first die is attached to the first surface of the substrate and positioned over the opening.05-27-2010
20080272479INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DEVICE CAVITY - An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.11-06-2008
20080283997Electronic Device and Pressure Sensor - An electronic device requires an electronic component to be mounted for the purpose of static shielding. The mounting of such an electronic component raises a problem of avoiding thermal stresses and cracks generated due to the difference between the coefficients of linear expansion of component materials. A positioning recess, a joining-substance thickness ensuring recess, a joining-substance thickness ensuring projection, etc. are formed in a combined manner in an electronic component mount portion of each of leads, whereby spreading of cracks generated in the joining substance can be suppressed and reliability can be improved. Filling a sealing material so as to seal and restrain the electronic component mounted in the electronic component mount portion without leaving voids contributes to further suppressing spreading of cracks generated in the joining substance and ensuring more improved reliability of the joining substance.11-20-2008
20100140778PACKAGE, METHOD OF MANUFACTURING THE SAME AND USE THEREOF - The flexible package (06-10-2010
20130119527SEMICONDUCTOR DIE ASSEMBLIES WITH ENHANCED THERMAL MANAGEMENT, SEMICONDUCTOR DEVICES INCLUDING SAME AND RELATED METHODS - A semiconductor die assembly comprises a plurality of semiconductor dice in a stack. Another semiconductor die is adjacent to the stack and has a region, which may comprise a relatively higher power density region, extends peripherally beyond the stack. Conductive elements extend between and electrically interconnect integrated circuits of semiconductor dice in the stack and of the other semiconductor die. Thermal pillars are interposed between semiconductor dice of the stack, and a heat dissipation structure, such as a lid, is in contact with an uppermost die of the stack and the high power density region of the other semiconductor die. Other die assemblies, semiconductor devices and methods of managing heat transfer within a semiconductor die assembly are also disclosed.05-16-2013
20090051025FAN OUT TYPE WAFER LEVEL PACKAGE STRUCTURE AND METHOD OF THE SAME - To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.02-26-2009
20080258291Semiconductor Packaging With Internal Wiring Bus - A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies.10-23-2008
20080258290Semiconductor device and method for manufacturing the same - A COF which can effectively dissipate the heat by using a simple structure and its manufacturing method. A semiconductor device of COF, which is formed over the main surface of a flexible substrate having no device hole and where a semiconductor chip is mounted over the inner lead interconnection, is characterized by forming a first resin layer over the second main surface of the flexible substrate opposite the side where the semiconductor chip is mounted and at the position corresponding to the semiconductor chip.10-23-2008
20080258289INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING - An integrated circuit package system comprising: forming an area array substrate; mounting surface conductors on the area array substrate; forming a molded package body on the area array substrate and the surface conductors; providing a step in the molded package body; and exposing a surface conductor by the step.10-23-2008
20100200978SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes placing a chip on a carrier, and applying an electrically conducting layer to the chip and the carrier. The method additionally includes converting the electrically conducting layer into an electrically insulating layer.08-12-2010
20100200977Layered chip package and method of manufacturing same - A layered chip package has a main body including a plurality of pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The plurality of pairs of layer portions include at least one specific pair of layer portions consisting of a first-type layer portion and a second-type layer portion. The first-type layer portion includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. A layered substructure formed of a stack of two substructures each of which includes a plurality of preliminary layer portions aligned is used to fabricate a stack of a predetermined two or greater number of pairs of layer portions, and the main body is fabricated by stacking an additional first-type layer portion together with the stack, the number of the additional first-type layer portion being equal to the number of the specific pair(s) of layer portions included in the stack.08-12-2010
20090085186Semiconductor Device and Methods of Manufacturing Semiconductor Devices - This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements.04-02-2009
20100140781QUAD FLAT NON-LEADED PACKAGE AND MANUFACTURING METHOD THEREOF - A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.06-10-2010
20090072378MEMORY DEVICE SYSTEM WITH STACKED PACKAGES - An integrated circuit package system includes: providing a base package of an elongated rectangular-box shape containing first electrical circuitry and including: forming a rectangular contact strip on and adjacent to a first end of the base package; and forming a base contact pad on and adjacent to a second end of the base package for connection to an electrical interconnect.03-19-2009
20090127690Package and Manufacturing Method for a Microelectronic Component - The present invention relates to A package (05-21-2009
20090283893INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SLOTTED DIE PADDLE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system including: providing a selective slot die paddle having selective slots and edge pieces around the perimeter; providing extended leads protruding into the selective slots; mounting an integrated circuit die on the selective slot die paddle; and coupling bond wires between the integrated circuit die, the edge pieces, the extended leads, or a combination thereof.11-19-2009
20090140410ELECTRONIC PART AND METHOD OF PRODUCING THE SAME - It is an object of the invention to provide an electronic part capable of forming an accurate gap between opposing substrates while also capable of decreasing the area of the electronic part, and a method of producing the same. A second electrode portion (06-04-2009
20090321916SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PACKAGE - A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of the silicon substrate is removed to form a ring hole and a silicon pillar surrounded by the silicon pillar. Then, a photosensitive material is disposed in the ring hole, wherein the photosensitive material is insulating. After that, the silicon pillar is removed, such that the ring hole forms a through hole and the photosensitive material covers a lateral wall of the through hole. Lastly, the conductive material is disposed in the through hole, wherein the outer surface of the conductive material is surrounded by the photosensitive material.12-31-2009
20090321914PRODUCTION OF INTEGRATED CIRCUIT CHIP PACKAGES PROHIBITING FORMATION OF MICRO SOLDER BALLS - Methods for making, and structures so made for producing integrated circuit (IC) chip packages without forming micro solder balls. In one embodiment, a method may include placing a solid grid made from an organic material between the IC chip and the substrate. The grid provides a physical barrier between each of a plurality of Controlled Collapse Chip Connections, and thereby prevents the formation of micro solder balls between them, thus improving chip performance and reliability.12-31-2009
20090321913INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LOCKING TERMINAL - An integrated circuit package system includes: forming a first locking terminal having a first terminal recess with a top portion of the first terminal recess narrower than a bottom portion of the first terminal recess; connecting an integrated circuit and the first locking terminal; and forming a package encapsulation over the integrated circuit and in the first locking terminal.12-31-2009
20090032931Power semiconductor module with connecting devices - A power semiconductor module having a housing with first connecting devices for arrangement on an external cooling component, at least one substrate carrier with power-electronics circuit arrangements constructed thereon and electrical terminal elements extending therefrom to second connecting devices for connection to external power lines, wherein the first and/or the second connecting devices are constructed as essentially hollow cylindrical metallic molded die-cast parts which are connected to the housing by injection molding.02-05-2009
20110140260CHIP ASSEMBLY WITH CHIP-SCALE PACKAGING - A chip assembly may comprise a substrate having a top surface and a bottom surface. The chip assembly may comprise a first die having a circuit surface and a connecting surface, the circuit surface comprising one or more integrated circuits. The chip assembly may comprise a chip-scale frame having an inside surface, an outside surface, and a well region, the well region having an opening within the inside surface, the well region having a wall, the well region housing the first die, the first die attached to the wall by a first coupling mechanism, the inside surface coupled to the top surface of the substrate by a second coupling mechanism. The chip assembly may comprise a heat sink coupled to the outside surface of the chip-scale frame using a third coupling mechanism.06-16-2011
20090065925DUAL-SIDED CHIP ATTACHED MODULES - An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.03-12-2009
20120104590Semiconductor Device and Method of Forming Penetrable Film Encapsulant Around Semiconductor Die and Interconnect Structure - A semiconductor device has a plurality of bumps formed over a carrier. A semiconductor die is mounted to the carrier between the bumps. A penetrable film encapsulant layer having a base layer, first adhesive layer, and second adhesive layer is placed over the semiconductor die and bumps. The penetrable film encapsulant layer is pressed over the semiconductor die and bumps to embed the semiconductor die and bumps within the first and second adhesive layers. The first adhesive layer and second adhesive layer are separated to remove the base layer and first adhesive layer and leave the second adhesive layer around the semiconductor die and bumps. The bumps are exposed from the second adhesive layer. The carrier is removed. An interconnect structure is formed over the semiconductor die and second adhesive layer. A conductive layer is formed over the second adhesive layer electrically connected to the bumps.05-03-2012
20090194861Hermetically-packaged devices, and methods for hermetically packaging at least one device at the wafer level - A plurality of devices are hermetically packaged at the wafer level by 1) providing a substrate wafer having a plurality of at least partially-formed devices thereon; 2) forming separation walls on the substrate wafer, around different ones of the at least partially-formed devices; and 3) wafer bonding a cap wafer to the separation walls, to form a plurality of hermetic packages.08-06-2009
20090102040POWER SEMICONDUCTOR MODULE - An apparatus includes a housing with a plurality of restraining elements and at least one supporting element. A cover is elastically deformed by the plurality of restraining elements and the at least one supporting means. At least one substrate carrying at least one semiconductor chip is provided within the housing.04-23-2009
20090102043Semiconductor package and manufacturing method thereof - A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.04-23-2009
20090102041Electrical connection device and assembly method thereof - An electrical connection device and assembly method thereof includes a substrate with a plurality of contacting portions arranged on a surface thereof; a chip module having a plurality of terminals inclining in one direction and compressed and contacted with the contacting portions correspondingly; at least one restricting structure which restricts the chip module to move a distance relative to the substrate depending on the compression deformation of the terminals when the terminals are contacted with the contacting portions; and at least one elastic element just producing deformation when the chip module moves the distance. When the terminals are compressed and contacted with the contacting portions, the restricting structure restricts the chip module to move the distance depending on the compression deformation of the terminals, so that the elastic element just produces deformation, which make the chip module only move in the direction opposite to the deformation direction of the terminals.04-23-2009
20090200654Method of electrically connecting a microelectronic component - A microelectronic assembly is provided which can include an element including a first dielectric layer and a second dielectric layer overlying the first dielectric layer, the second dielectric layer having an exposed surface defining an exposed major surface of the element. A plurality of substantially rigid metal posts can project beyond the exposed surface, the metal posts having ends remote from the exposed surface. The microelectronic assembly can include a microelectronic device which has bond pads and overlies the element. The microelectronic device can have a major surface which confronts the posts. Connections electrically connect the ends of the metal posts with the bond pads of the microelectronic device.08-13-2009
20090200656SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There are constituted by a tab (08-13-2009
20090200655Method of electrically connecting a microelectronic component - A microelectronic unit can include a support structure including a dielectric having oppositely-directed first and second surfaces. A plurality of substantially rigid posts can protrude parallel to one another in a direction beyond the first surface of the support structure. Each post may have a top surface remote from the support structure, and the top surfaces can be substantially coplanar with one another. A microelectronic device having a surface with bond pads can overlie the second surface of the support structure with the bond pad-bearing surface of the microelectronic device facing toward the support structure. Connections can electrically connect the posts with the bond pads.08-13-2009
20090206467INTEGRATED CIRCUIT PACKAGE08-20-2009
20090230539SEMICONDUCTOR DEVICE - In recent years, as electronic equipment becomes thinner, an area for mounting a semiconductor device used in the electronic equipment is required to be smaller, and a thickness of an encapsulating resin for encapsulating a semiconductor substrate having a circuit formed thereon and the like also becomes smaller. The encapsulating resin is marked with a product number, a manufacturer name, or the like. There arises a problem in that, in the marking, an infrared laser beam applied to the encapsulating resin passes through the encapsulating resin, generates heat in the semiconductor substrate, and destructs the formed circuit. By providing a thin film for refracting the infrared laser beam on a rear surface of the semiconductor substrate, the optical path of the infrared laser beam is made longer to reduce heat generated in the semiconductor substrate.09-17-2009
20090230535SEMICONDUCTOR MODULE - A semiconductor module. In one embodiment, at least two semiconductor chips are placed on a carrier. The at least two semiconductor chips are then covered with a molding material. An exposed portion of the at least two semiconductor chips is provided. A first layer of conductive material is applied over the exposed portion of the at least two semiconductor chips to electrically connect to a contact pad on the exposed portion of the at least two semiconductor chips. The at least two semiconductor chips are singulated.09-17-2009
20090243078Power Device Packages Having Thermal Electric Modules Using Peltier Effect and Methods of Fabricating the Same - Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.10-01-2009
20090250802Multilayer wiring substrate, semiconductor package, and methods of manufacturing semiconductor package - A multilayer wiring substrate included in the semiconductor package includes: a first insulating layer and a second insulating layer, in which wiring layers are respectively provided on the upper and the lower surfaces; and; a core layer provided between the first insulating layer and the second insulating layer. The first insulating layer and the second insulating layer are constituted by different materials from each other.10-08-2009
20080315391INTEGRATED STRUCTURES AND METHODS OF FABRICATION THEREOF WITH FAN-OUT METALLIZATION ON A CHIPS-FIRST CHIP LAYER - Electronic modules and methods of fabrication are provided implementing a first metallization level directly on a chips-first chip layer. The chips-first layer includes chips, each with a pad mask over an upper surface and openings to expose chip contact pads. Structural dielectric material surrounds and physically contacts the side surfaces of the chips, and has an upper surface which is parallel to an upper surface of the chips. A metallization layer is disposed over the front surface of the chips-first layer, residing at least partially on the pad masks of the chips, and extending over one or more edges of the chips. Together, the pad masks of the chips, and the structural dielectric material electrically isolate the metallization layer from the edges of the chips, and from one or more electrical structures of the chips in the chips-first layer.12-25-2008
20080315390Chip Scale Package For A Micro Component - A package includes a sensor die with a micro component, such as a MEMS device, coupled to an integrated circuit which may include, for example, CMOS circuitry, and one or more electrically conductive bond pads near the periphery of the sensor die. A semiconductor cap structure is attached to the sensor die. The front side of the cap structure is attached to the sensor die by a seal ring to hermetically encapsulate an area of the sensor die where the micro component is located. The bond pads on the sensor die are located outside the area encapsulated by the seal ring. Electrical leads, which extend along outer side edges of the semiconductor cap structure from its front side to its back side, are coupled to the micro component via the bond pads.12-25-2008
20080315388VERTICAL CONTROLLED SIDE CHIP CONNECTION FOR 3D PROCESSOR PACKAGE - In some embodiments, vertical controlled side chip connection for 3D processor package is presented. In this regard, an apparatus is introduced having a substrate, a substantially horizontal, in relation to the substrate, integrated circuit device coupled to the substrate, and a substantially vertical, in relation of the substrate, integrated circuit device coupled to the substrate and adjacent to one side of the substantially horizontal integrated circuit device. Other embodiments are also disclosed and claimed.12-25-2008
20090096080SEMICONDUCTOR PACKAGE, ELECTRONIC PART AND ELECTRONIC DEVICE - Even when a substrate on which a semiconductor package has been mounted is made curved, stress upon electrical connections is mitigated, thereby eliminating faulty connections and improving connection reliability. A semiconductor chip has electrodes on a second face thereof. Support blocks, capable of bending and flexing, are placed at two locations on a peripheral edge of a first face of the semiconductor chip. An interposer is placed so as to span the support blocks with the support blocks interposed between itself and the semiconductor chip, and has a wiring pattern in a flexible resin film. Two end portions of the interposer are folded back onto the side of the second face of the semiconductor chip, and the wiring pattern thereof is electrically connected to the electrodes of the semiconductor chip.04-16-2009
20090096079SEMICONDUCTOR PACKAGE HAVING A WARPAGE RESISTANT SUBSTRATE - A semiconductor package is presented having a substrate, a semiconductor chip, an under-fill material, and a solder resist pattern. The substrate having a substrate body, wiring lines which are located on a first surface of the substrate body and which have connection pad parts, and ball lands which are located on a second surface of the substrate body, facing away from the first surface, and which are electrically connected with the wiring lines. The semiconductor chip having bumps which are electrically connected with the respective connection pad parts. The under-fill material filling a space between the substrate and the semiconductor chip. The solder resist pattern is located on the first surface and has first openings which expose the connection pad parts and has at least one second opening which exposes a portion of the substrate body to provide an enhancement of adhesion force between the under-fill material and the substrate body.04-16-2009
20090212412SEMICONDUCTOR PACKAGE ACCOMPLISHING FAN-OUT STRUCTURE THROUGH WIRE BONDING - Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.08-27-2009
20110227210CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package, which includes: a substrate having an upper surface and a lower surface; a passivation layer located overlying the upper surface of the substrate; a plurality of conducting pad structures disposed overlying the upper surface of the substrate, wherein at least portions of upper surfaces of the conducting pad structures are exposed; a plurality of openings extending from the upper surface towards the lower surface of the substrate; and a plurality of movable bulks located between the openings and connected with the substrate, respectively, wherein each of the movable bulks is electrically connected to one of the conducting pad structures.09-22-2011
20090243077INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RIGID LOCKING LEAD - An integrated circuit package system includes: providing a protective layer having an opening; forming a conductive layer over the protective layer and filling the opening; patterning a rigid locking lead, having both a lead locking portion and a lead exposed portion, from the conductive layer; connecting an integrated circuit and the rigid locking lead; and forming an encapsulation over the integrated circuit with the lead locking portion in the encapsulation and the lead exposed portion exposed from the encapsulation.10-01-2009
20090250803SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a chip, a laminated wiring structure formed integrally with the chip, a frame disposed to surround the chip and made of a material having stiffness, and a sealing resin formed to bury therein the frame and at least the periphery of the side surface of the chip. The laminated wiring structure includes a required number of wiring layers, which are formed by patterning in such a manner that a wiring pattern directly routed from an electrode terminal of the chip is electrically connected to pad portions for bonding external connection terminals, the pad portions being provided, at a position directly below a mounting area of the chip and at a position directly below an area outside the mounting area, on a surface to which the external connection terminals are bonded.10-08-2009
20100264533SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package is provided. The semiconductor chip package includes a lead frame having a chip carrier. A semiconductor chip is mounted on the chip carrier, having a plurality of bonding pads thereon. A package substrate has a cavity therein to accommodate the chip carrier and the semiconductor chip, wherein at least one of the bonding pads of the semiconductor chip is electrically coupled to the package substrate.10-21-2010
20100155926INTEGRATED CIRCUIT PACKAGING SYSTEM FOR FINE PITCH SUBSTRATES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a substrate including: patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.06-24-2010
20100148351METHOD OF PACKAGING INTEGRATED CIRCUIT DEVICES USING PREFORMED CARRIER - Disclosed is a method of packaging integrated circuit devices using a preformed carrier. In one illustrative embodiment, the method includes providing a carrier having a plurality of pockets formed therein, positioning an integrated circuit chip and a substrate in each of the plurality of pockets and conductively coupling the integrated circuit chip and the substrate in each of the plurality of pockets to one another. Also disclosed is a packaged integrated circuit device including a preformed body and an integrated circuit chip and a substrate positioned within the preformed body, the integrated chip and the substrate being conductively coupled to one another.06-17-2010
20100148350SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.06-17-2010
20100148349Semiconductor Package Having Support Chip And Fabrication Method Thereof - A semiconductor package having a support chip and a fabrication method thereof. The semiconductor package includes a circuit substrate having a conductive pattern on the top surface. A first semiconductor die is attached on top of the circuit substrate. A second semiconductor die is attached on top of the first semiconductor die. Each of the first and second semiconductor dies has a plurality of bond pads on the top surface. A support chip is attached on top of the first semiconductor die and has a plurality of bond pads provided on the top surface. The conductive wires electrically connect the first semiconductor die and the second semiconductor die to the circuit substrate, the second semiconductor die to the support chip, the bond pads of the support chip to each other, and the support chip to the circuit substrate. An encapsulant encloses, as in a capsule, the foregoing components.06-17-2010
20100148347CHIP SCALE PACKAGE STRUCTURE WITH CAN ATTACHMENT - A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.06-17-2010
20100148344INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INPUT/OUTPUT EXPANSION - An integrated circuit package system includes: forming a base stacking package including: fabricating a base substrate, mounting an integrated circuit on the base substrate, positioning an input/output expansion substrate, having access ports around an inner array area, over the integrated circuit, and injecting a molding compound on the base substrate, the integrated circuit, and the input/output expansion substrate; and mounting a top package on the input/output expansion substrate.06-17-2010
20100155924SEMICONDUCTOR MODULE - A semiconductor module includes first and second sub-units, each including at least one semiconductor chip, a first contact element having a first contact side, and a second or third contact element having a second or third contact side, respectively. The semiconductor chip has opposing first and second main electrode sides. The first main electrode side of the chip is thermally connected to the first contact side, and the second main electrode side is thermally connected to the second or third contact side. In the first sub-unit, a first fixation means connects the first and second contact elements and the chip together. In the second sub-unit, a second fixation means connects the first and third contact elements and the chip together. A flexible element, which is arranged between the first contact element and the first contact element, is electrically and thermally connected to the first contact elements.06-24-2010
20100155925RESIN-SEALED PACKAGE AND METHOD OF PRODUCING THE SAME - A method of producing a resin-sealed package is provided with: providing an electronic component which has a plurality of terminals on one face, a first support member and a second support member; temporarily fixing said electronic component to a surface of said first support member by a first adhesive agent layer, to face said terminals with said first support member; fixing said second support member having a second adhesive agent layer to said electronic component while interposing said electronic component between said first support member and said second support member to face said second adhesive agent layer with a back face side of said electronic component; resin sealing said electronic component between said first support member and said second support member; peeling said first support member and said first adhesive agent layer from said electronic component and a sealing resin; and stacking an insulating resin layer and a wiring layer which is electrically connected to said terminals of said electronic component, on said electronic component and said sealing resin.06-24-2010
20100187675SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - This semiconductor device is a semiconductor device in which a semiconductor element is flip-chip mounted onto a circuit substrate and the semiconductor element is covered and sealed with a sealing resin. A recess portion is formed in the sealing resin on a surface opposite to the mounting surface of the semiconductor element. Warping of the semiconductor device is reduced by the action of this recess portion.07-29-2010
20100187672ELECTRONIC APPARATUS AND CIRCUIT BOARD - According to an aspect of the present invention, there is provided an electronic apparatus including: a housing; a circuit board that is housed in the housing; a semiconductor package that includes a first surface on which solder balls are provided and a second surface opposite to the first surface and that is mounted on the circuit board so as to be electrically connected to the circuit board through the solder balls; a protective film that has a water repellency and that is applied on the circuit board so as to expose around the semiconductor package mounted on the circuit board; and a joint member that joins at least a part of a side surface of the semiconductor package and the circuit board.07-29-2010
20100193933SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.08-05-2010
20100176502Wafer level vertical diode package structure and method for making the same - A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.07-15-2010
20090079056LARGE SUBSTRATE STRUCTURAL VIAS - An electronic package and methods by which the package reduces thermal fatigue failure of conductors in the electronic package. The electronic package includes a carrier substrate having first and second surfaces and a plurality of anchor vias having a via material extending from the first surface toward the second surface. The electronic package includes a first conducting layer having a length and a width extending laterally in two dimensions across a major part of the first surface of the carrier substrate. The anchor vias have plural attachments along the length and the width of the first conducting layer to secure the first conducting layer to the carrier substrate.03-26-2009
20130214401System and Method for Fine Pitch PoP Structure - A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.08-22-2013
20130214402SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package improves reliability of heat emitting performance by maintaining a heat emitting lid stacked on a top surface of a semiconductor chip at a tightly adhered state. A highly adhesive interface material and a thermal interface material are applied to the top surface of the semiconductor chip. The highly adhesive interface material insures that the heat emitting lid is bonded to the top surface while the thermal interface material insures excellent heat transfer between the top surface and the heat emitting lid.08-22-2013
20130214403FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.08-22-2013
20100187673ADHESIVE TAPE AND SEMICONDUCTOR PACKAGE USING THE SAME - Provided is an adhesive tape which adheres two members to each other and decreases problems that may occur due to contraction and expansion of the adhered members when the temperature of the adhered two members changes. The adhesive tape includes: a base film having insulating properties; and an adhesive agent that adheres on both sides of the base film, wherein a coefficient of thermal expansion of the base film is 10 ppm or lower, a coefficient of thermal expansion of the adhesive tape is lower than 17 ppm, and an occupation rate of the base film in the adhesive tape exceeds 50%.07-29-2010
20100013080SEMICONDUCTOR DEVICE PACKAGE WITH INSULATOR RING - Embodiments provide a semiconductor device package and a method for fabricating thereof. The package includes a silicon substrate having a semiconductor device and a metal layer thereon; an insulator ring formed in the silicon substrate and surrounding a portion of a silicon material below the metal layer; and a conductive layer disposed below a backside of the silicon substrate and extended to contact the portion of the silicon material surrounded by the insulator ring below the metal layer.01-21-2010
20100213595SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF AND ENCAPSULATING METHOD THEREOF - A semiconductor package, a manufacturing method thereof and an encapsulating method thereof are provided. The semiconductor package includes a substrate, a flip chip, a plurality of conductive parts and a sealant. The substrate has a substrate upper surface. The flip chip has an active surface and a chip surface opposite to the active surface. The conductive parts electrically connect the substrate upper surface and the active surface. The sealant envelops the flip chip, and the space between the substrate upper surface and the active surface is filled with a portion of the sealant. The sealant further has a top surface. wherein, the chip surface is spaced apart from the top surface by a first distance, the substrate upper surface is spaced apart from the active surface by a second distance, and the ratio of the first distance to the second distance ranges from 2 to 5.08-26-2010
20100148345ELECTRONIC DEVICES INCLUDING FLEXIBLE ELECTRICAL CIRCUITS AND RELATED METHODS - A packaged electronic device includes a die, a flexible circuit structure, and a barrier film disposed on the die. The die includes die circuitry and electrical contacts. The flexible circuit structure is bonded directly to the die, and includes electrical conductors encapsulated by structural layers. Each electrical conductor contacts a respective electrical contact. The electronic device is encapsulated by the barrier film and one or more of the structural layers.06-17-2010
20100213597SEMICONDUCTOR ELEMENT MOUNTING BOARD - A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C. is defined as Y GPa, the X and the Y satisfy a relation of 0.5≦X−Y≦13.08-26-2010
20100219524CHIP SCALE PACKAGE AND METHOD OF FABRICATING THE SAME - A chip scale package (CSP) package and method of fabricating the same are provided. The fabricating method includes the following steps. First, a substrate is provided. Next, a chip is disposed on the front surface of the substrate and electrically connected to the substrate. Then, a thermal conductive paste is formed on the surface of the chip. Afterwards, a molding compound for enclosing the chip is formed. Lastly, a milling process is applied to the molding compound so that the height of the molding compound is aligned with that of the thermal conductive paste. The chip can be disposed on the substrate by way of wire bonding or flip-chip bonding. The thermal conductive paste is disposed on the surface of the chip either before or after the milling process is completed.09-02-2010
20100224981ROUTABLE ARRAY METAL INTEGRATED CIRCUIT PACKAGE - An integrated circuit assembly comprises an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area. An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal layer. An overfill material encapsulates at least the integrated circuit die and the plurality of wire bonds, and a plurality of solder balls are formed on the plurality of external connection pads.09-09-2010
20100224980HERMETIC PACKAGING OF INTEGRATED CIRCUIT COMPONENTS - A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.09-09-2010
20100230799SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier, a chip attached to the carrier, and an encapsulation body disposed over the chip and the carrier. An exterior surface of the semiconductor device includes an exposed peripheral edge of at least two of the carrier, the chip, and the encapsulation body.09-16-2010
20100237486SEMICONDUCTOR DEVICE - A semiconductor device including: a base substrate; a frame body mounted on the base substrate and formed with a recessed portion in each of both side faces thereof opposing to each other; a semiconductor chip mounted on the base substrate within an area of the frame body; a dielectric block inserted into the recessed portion in the frame body; a waveguide formed on a surface of the dielectric block and electrically connected with the semiconductor chip; a plurality of protection patterns respectively formed along the waveguide at positions spaced from the waveguide on both sides of the waveguide on the surface of the dielectric block; and a metal layer formed on at least each of the both side faces of the dielectric block opposing to each other by plating.09-23-2010
20120139094STACKED MICROELECTRONIC ASSEMBLY HAVING INTERPOSER CONNECTING ACTIVE CHIPS - A microelectronic assembly can include first and second microelectronic elements each embodying active semiconductor devices adjacent a front surface thereof, and having an electrically conductive pad exposed at the respective front surface. An interposer of material having a CTE less than 10 ppm/° C. has first and second surfaces attached to the front surfaces of the respective first and second microelectronic elements, the interposer having a second conductive element extending within an opening in the interposer. First and second conductive elements extend within openings extending from the rear surface of a respective microelectronic element of the first and second microelectronic elements towards the front surface of the respective microelectronic element. In one example, one or more of the first or second conductive elements extends through the respective first or second pad, and the conductive elements contact the exposed portions of the second conductive element to provide electrical connection therewith.06-07-2012
20100237487METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS - Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.09-23-2010
20100237488INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING - A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts; attaching an integrated circuit to the top surface; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that are over and larger than the electrical contacts.09-23-2010
20100252920Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates - In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.10-07-2010
20100140780Semiconductor Device and Method of Forming an IPD Beneath a Semiconductor Die with Direct Connection to External Devices - A semiconductor device has a conductive layer formed on a substrate. The conductive layer has a first portion constituting contact pads and a second portion constituting an integrated passive device such as an inductor. A spacer is formed on the substrate around the second portion of the conductive layer. The spacer can be insulating material or conductive material for shielding. A semiconductor die is mounted to the spacer. An electrical connection is formed between contact pads on the semiconductor die and the contact pads on the substrate. An encapsulant is formed around the semiconductor die, electrical connections, spacer, and conductive layer. The substrate is removed to expose the conductive layer. An interconnect structure is formed on the backside of the substrate. The interconnect structure is electrically connected to the conductive layer. The semiconductor device can be integrated into a package.06-10-2010
20100140779Semiconductor Package with Semiconductor Core Structure and Method of Forming Same - A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) structure is formed over the temporary carrier. The IPD structure includes an inductor, resistor, and capacitor. Conductive posts are mounted to the IPD structure, and first semiconductor die is mounted to the IPD structure. A wafer molding compound is deposited over the conductive posts and the first semiconductor die. A core structure is mounted to the conductive posts over the first semiconductor die. The core structure includes a semiconductor material. Conductive through silicon vias (TSVs) are formed in the core structure. A redistribution layer (RDL) is formed over the core structure. A second semiconductor die is mounted over the semiconductor device. The second semiconductor die is electrically connected to the core structure.06-10-2010
20110101514VERTICAL SURFACE MOUNT ASSEMBLY AND METHODS - A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradeable.05-05-2011
20100140782PRINTED CIRCUIT BOARD HAVING BUILT-IN INTEGRATED CIRCUIT PACKAGE AND FABRICATION METHOD THEREFOR - A Printed Circuit Board (PCB) is provided in which at least one built-in Integrated Circuit (IC) package has a plurality of conductive bumps on an IC. The plurality of conductive bumps are for external electrical connection. The IC package is accommodated within a core layer of a multi-layer PCB by a connection member on the IC. The connection member is formed between the conductive bumps and the core layer with contact holes in contact with the conductive bumps. The conductive bumps are electrically connected through conductor layers formed in the contact holes.06-10-2010
20130127035THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE - Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and protective layer contacting the polymer layer and covering the cavity.05-23-2013
20100155923Microball assembly methods, and packages using maskless microball assemblies - A method of forming a microball grid array includes adhering a microball precursor material to a transfer medium under conditions to reflect a selective charge pattern. The method includes transferring the microball precursor material from the transfer medium across a gap and to an integrated circuit substrate under conditions to reflect the selective charge pattern. The method includes achieving the microball grid array without the aid of a mask.06-24-2010
20090115047Robust multi-layer wiring elements and assemblies with embedded microelectronic elements - An interconnect element 05-07-2009
20090152710QUAD FLAT NO-LEAD (QFN) PACKAGES - Quad Flat No-Lead (QFN) packages are provided. An embodiment of a QFN package includes a semiconductor chip including an active surface and an inactive surface, a plurality of leads, a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip, and a mold material including a mounting side and having a perimeter. The active surface is oriented toward the mounting side, the plurality of wire bonds are disposed between the active surface and the mounting side within the mold material, and the plurality of leads are exposed on the mounting side and are at least partially encapsulated within the perimeter of the mold material.06-18-2009
20080265394WAFER LEVEL PACKAGE AND FABRICATING METHOD THEREOF - A wafer level semiconductor package and fabricating method thereof are disclosed. A method of fabricating a wafer level package, which includes depositing a first insulation layer on the outermost layer circuit of the a semiconductor chip and then flattening the surface of the first insulation layer; removing a portion of the first insulation layer to expose a chip pad to the outside; depositing a metal layer directly contacting the chip pad onto the chip pad and the first insulation layer and then removing a portion to form a bump metal having a bump pad electrically connected with the chip pad; and depositing a second insulation layer and a coating layer in order onto the bump metal and then removing portions thereof to expose the bump pad to the outside, where all of the operations are performed by semiconductor fabrication (FAB) equipment, not only enables the forming of higher-precision patterns, but also reduces volume.10-30-2008
20090108433MULTILAYER SEMICONDUCTOR DEVICE PACKAGE ASSEMBLY AND METHOD - Methods for assembling multilayer semiconductor device packages are disclosed. A base substrate having device mounting sites is provided. A number of semiconductor devices are connected to the device mounting sites. Upper boards are attached to the base substrate and over each of the coupled devices. The method includes steps of testing one or more of the base substrate, semiconductor device, or upper board, prior to operably connecting one to another.04-30-2009
20090152705Micromechanical Component and Method for Fabricating a Micromechanical Component - A method for fabricating a microelectromechanical or microoptoelectromechanical component. The method includes producing first and second layer composites. The first has a first substrate and a first insulation layer, which covers at least one part of the surface of the first substrate, while the second has a second substrate and a second insulation layer, which covers at least one part of the surface of the second substrate. An at least partly conductive structure layer is applied to the first insulation layers and the second composite is applied to the structure layer so that the second insulation layer adjoins the structure layer. The first and second layer composites and the structure layer are configured so that at least one part of the structure layer that comprises the active area of the microelectromechanical or microoptoelectromechanical component is hermetically tightly sealed by the first and second layer composites. Contact holes are formed for making contact with conductive regions of the structure layer within the first and/or second substrate.06-18-2009
20100308451WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.12-09-2010
20100308449SEMICONDUCTOR PACKAGES AND MANUFACTURING METHOD THEREOF - A manufacturing method of semiconductor package is provided. A carrier is provided. The chips are disposed on the carrier. The chips are encapsulated by a molding compound, so that the molding compound and the chips form a chip-redistribution encapsulant. The carrier is removed, so that the chip-redistribution encapsulant exposes the pads of the chips. The plasma is applied on the pads and the molding compound. A first dielectric layer is formed on the pads and the surface of the molding compound. The plasma is applied on a surface of the first dielectric layer. A patterned conductive layer is formed on the surface of the first dielectric layer. A second dielectric layer is formed on the patterned conductive layer and the first dielectric layer. A plurality of solder balls are formed on the second dielectric layer. The chip-redistribution encapsulant is divided so as to form a plurality of packages.12-09-2010
20130134573SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements.05-30-2013
20100258934ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The advanced quad flat non-leaded package structure includes a carrier having a die pad and a plurality of leads, at least a chip, a plurality of wires, and a molding compound. The rough surface of the carrier enhances the adhesion between the carrier and the surrounding molding compound.10-14-2010
20110127663MAGNETIC PARTICLE-BASED COMPOSITE MATERIALS FOR SEMICONDUCTOR PACKAGES - A semiconductor package is described. The semiconductor package includes a substrate and an integrated heat spreader disposed above and coupled with the substrate. A cavity is disposed between the substrate and the integrated heat spreader. A semiconductor die is disposed above the substrate and in the cavity. An array of first-level solder joints is disposed between the substrate and the semiconductor die. A layer of magnetic particle-based composite material is also disposed in the cavity.06-02-2011
20100193932WAFER LEVEL PACKAGE FOR HEAT DISSIPATION AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate.08-05-2010
20100320586INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture an integrated circuit packaging system includes: providing a substrate; attaching a base component to the substrate by a first interconnect; attaching a stack component connected by a second interconnect to the substrate and partially over the base component, the second interconnect different from the first interconnect; molding an encapsulation over the base component, the first interconnect, the stack component, and the second interconnect; and removing the substrate to partially expose the first interconnect and the second interconnect from the encapsulation.12-23-2010
20100320587INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a device having a conductor with ends exposed on opposite sides of the device; forming a first surface depression on the device around the conductor; connecting a first component over the conductor and surrounded by the first surface depression; and applying a first underfill between the first component and the device, the first underfill substantially filled within a perimeter of the first surface depression.12-23-2010
20100181662STACKABLE LAYER CONTAINING BALL GRID ARRAY PACKAGE - Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.07-22-2010
20110018118Semiconductor Device Packages, Redistribution Structures, and Manufacturing Methods Thereof - Described herein are semiconductor device packages and redistribution structures including alignment marks and manufacturing methods thereof.01-27-2011
20110018116CHIP SCALE SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGE AND PROCESS OF MANUFACTURE - A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.01-27-2011
20110018117SEALED JOINT STRUCTURE OF DEVICE AND PROCESS USING THE SAME - A sealed joint structure of device includes a buffer bump layer, conductive joint portions and a sealed joint portion. The buffer bump layer disposed between a device and a substrate includes first parts and a second part surrounding the first parts. Each of the conductive joint portions includes a first electrode covering each of the first parts and a second electrode on the substrate, and each of the first electrodes is electrically connected to the second electrode. The sealed joint portion includes a joint ring located on the substrate and is jointed with the second part to form a hermetic space between the device and the substrate.01-27-2011
20090065924SEMICONDUCTOR PACKAGE WITH REDUCED VOLUME AND SIGNAL TRANSFER PATH - A semiconductor package includes a first semiconductor chip having a first semiconductor chip body including a first circuit region and peripheral regions arranged around the first circuit region. A first bonding pad group is arranged within the first circuit region and includes a plurality of bonding pads. A first redistribution group including a plurality of redistributions is electrically connected to the respective bonding pads and extends towards the peripheral regions. The package further includes a second semiconductor chip having a second semiconductor chip body including a second circuit region opposing the first circuit region. A second bonding pad group is arranged within the second circuit region and corresponds to the first bonding pad group. A second redistribution group is electrically connected to the respective bonding pads of the second bonding pad group. Redistribution connection members are used to electrically connect the first redistribution group to the second redistribution group.03-12-2009
20110024893STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a stacked semiconductor package and a method for manufacturing the same. The method for manufacturing a stacked semiconductor package includes preparing a substrate formed with a seed metal layer; laminating semiconductor chips having via holes aligned with one another on the seed metal layer to form a semiconductor chip module; and growing a conductive layer inside of the via holes using the seed metal layer to form a conductive growth layer inside of the via holes.02-03-2011
20110031605PACKAGE STRUCTURE AND PACKAGE PROCESS - A package structure and a package process are provided. In the package process, firstly, a first electronic component having a plurality of first conductive bumps at a bottom thereof is provided. Then, a first insulation paste is coated on the first conductive bumps. The first electronic component is disposed on a circuit substrate having a plurality of substrate pads, and the first conductive bumps are respectively situated on the substrate pads. Next, a heating process is performed to both of the first conductive bumps and the first insulation paste, wherein the first conductive bumps is reflowed to bond the first electronic component and the substrate pads, and the first insulation paste is cured.02-10-2011
20110031603SEMICONDUCTOR DEVICES HAVING STRESS RELIEF LAYERS AND METHODS FOR FABRICATING THE SAME - Methods are provided for fabricating a semiconductor device. In accordance with an exemplary embodiment, a method comprises the steps of providing a semiconductor die having a conductive terminal, forming an insulating layer overlying the semiconductor die, and forming a cavity in the insulating layer which exposes the conductive terminal. The method also comprises forming a first stress-relief layer in the cavity, forming an interconnecting structure having a first end electrically coupled to the first stress-relief layer, and having a second end, and electrically and physically coupling the second end of the interconnecting structure to a packaging substrate.02-10-2011
20110031606PACKAGING SUBSTRATE HAVING EMBEDDED SEMICONDUCTOR CHIP - A packaging substrate includes: a core board having opposite first and second surfaces and a cavity penetrating therethrough; a semiconductor chip disposed in the cavity and having an active surface with electrode pads and an opposite inactive surface; a first reinforcing dielectric layer containing a reinforcing material disposed on the first surface and the active surface and filling the gap between the chip and the cavity; a second reinforcing dielectric layer containing a reinforcing material disposed on the second surface and the inactive surface and filling the gap between the chip and the cavity; and first and second wiring layers disposed on the first and second reinforcing dielectric layers respectively and the first wiring layer electrically connecting to the electrode pads. The first and second reinforcing dielectric layers enhance the support force of the entire structure to thereby prevent delamination of the wiring layers from the dielectric layers and increase product yield and reliability.02-10-2011
20110031602METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The method comprises providing multiple chips attached to a first carrier, stretching the first carrier so that the distance between adjacent ones of the multiple chips is increased, and applying a laminate to the multiple chips and the stretched first carrier to form a first workpiece embedding the multiple chips, the first workpiece having a first main face facing the first carrier and a second main face opposite to the first main face.02-10-2011
20110042797SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package.02-24-2011
20100013078ADHESIVE FOR CONNECTION OF CIRCUIT MEMBER AND SEMICONDUCTOR DEVICE USING THE SAME - An adhesive for connecting circuit members, which is interposed between a semiconductor chip having protruding connecting terminals and a board having wiring patterns formed thereon for electrically connecting the connecting terminals and the wiring patterns facing each other and bonding the semiconductor chip and the board by applying pressure/heat, containing a resin composition containing a thermoplastic resin, a crosslinkable resin and a hardening agent for forming a crosslink structure of the crosslinkable resin; and composite oxide particles dispersed in the resin composition.01-21-2010
20090085187LOADING MECHANISM FOR BARE DIE PACKAGES AND LGA SOCKET - Methods and associated apparatus of reducing stress in a package Those methods may comprise providing a package comprising a die coupled to a substrate, wherein the substrate is disposed on an LGA socket, and wherein a TIM is disposed on a top surface of the die, and then attaching a thermal solution to the TIM, wherein at least one standoff is attached between the thermal solution and the substrate.04-02-2009
20110140261INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate external layer having an opening; forming a convex interconnect within the opening with the convex interconnect having a protrusion and a horizontal flange substantially horizontally coplanar with the substrate external layer; forming an insulation layer over the substrate external layer and the convex interconnect; forming a horizontal conductive pathway on the insulation layer; forming a single interlayer conductive connector from the horizontal conductive pathway to the convex interconnect; and connecting an integrated circuit and the horizontal conductive pathway.06-16-2011
20100213598CIRCUIT CARRIER AND SEMICONDUCTOR PACKAGE USING THE SAME - A circuit carrier suitable for being connected with a bump is provided. The circuit carrier includes a substrate and at least one bonding pad. The substrate has a bonding pad disposed on a surface thereof for being connected with the bump. A brown-oxide layer is disposed on a surface of the bonding pad.08-26-2010
20110210438Thermal Vias In An Integrated Circuit Package With An Embedded Die - In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.09-01-2011
20110241195FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.10-06-2011
20100187674PACKAGE SUBSTRATE STRUCTURE AND CHIP PACKAGE STRUCTURE AND MANUFACTURING PROCESS THEREOF - A chip package structure includes a substrate, chips and an elastic element. The substrate has a first surface, a second surface, a first patterned metal layer on the first surface and a second patterned metal layer on the second surface, wherein the substrate is suitable for being clipped between an upper mold chase and a lower mold chase of a package mold. The chips are disposed on the first surface, wherein the chips are suitable for being contained in containing spaces defined by the upper mold chase and the substrate. The elastic element is disposed on the second surface and surrounds the second patterned metal layer, wherein the elastic element is suitable for contacting the lower mold chase and is located between the lower mold chase and the substrate. In addition, a manufacturing process of the chip package and a package substrate structure are also provided.07-29-2010
20110084376MODULAR LOW STRESS PACKAGE TECHNOLOGY - A protective modular package assembly with one or more subassemblies, each having a base element, a sidewall element coupled to the base element, and a semiconductor device disposed within and coupled to the sidewall element and the base element; a protective modular package cover having fastening sections located at opposing ends of the cover, torque elements disposed on the opposing ends and configured to fasten the cover to a core, and subassembly receiving sections disposed between the fastening sections with each subassembly receiving section operable to receive a subassembly and having a cross member along the underside of the cover; and an adhesive layer configured to affix subassemblies to respective subassembly receiving sections. The torque elements are configured to transfer a downward clamping force generated at the fastening elements to a top surface of the subassemblies via the cross member of each of the one or more subassembly receiving sections.04-14-2011
20110084375SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRATED STAND-OFF - A semiconductor device includes a substrate having first and second major surfaces and conductive traces, and solder balls attached to the second major surface of the substrate. A semiconductor die including an integrated circuit (IC) is attached to one of the major surfaces of the substrate. The IC is electrically connected to the solder balls by the conductive traces. The substrate includes an integrally molded stand-off feature that prevents the solder balls near the corners and the sides of the substrate from being knocked off during handling. The stand-off feature also maintains a predetermined distance between the substrate and a printed circuit board (PCB) when the substrate is attached to the PCB, and then a reflow process is performed. The stand-off feature also prevents open connections between the solder balls and the PCB that may be caused by warping of the PCB or the weight of the semiconductor die. The semiconductor device may include a stiffener ring attached to the second major surface of the substrate and surrounding the conductive balls.04-14-2011
20090057867Integrated Circuit Package with Passive Component - The present invention comprises a substrate, an integrated circuit mounted on the substrate, a passive component such as a capacitor mounted on the integrated circuit, and an encapsulation enclosing the integrated circuit and the passive component. The integrated circuit can be mounted in a flip-chip configuration with its active side facing the substrate and the passive component mounted on its backside or with its active side up with its backside on the substrate and the passive component mounted on the active side of the integrated circuit.03-05-2009
20090256250SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD - The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.10-15-2009
20090218672SOLDER RESIST MATERIAL, WIRING BOARD USING THE SOLDER RESIST MATERIAL, AND SEMICONDUCTOR PACKAGE - The present invention provides a solder resist material, which can suppress the warpage of a semiconductor package upon exposure to heat or impact even when used in a thin wiring board and meets a demand for size reduction in electronic devices and a higher level of integration, and a wiring board comprising the solder resist material and a semiconductor package. The solder resist material of the present invention can effectively suppress the warpage of a semiconductor package through a fiber base material-containing layer interposed between resin layers. The fiber base material-containing layer is preferably unevenly distributed in the thickness direction of the solder resist material.09-03-2009
20090218675MULTIPACKAGE MODULE HAVING STACKED PACKAGES WITH ASYMMETRICALLY ARRANGED DIE AND MOLDING - Semiconductor chip packages have die asymmetrically arranged on the respective substrates. Two such packages having complementary arrangements can be stacked, one inverted with respect to the other, such that the two die are situated side-by-side in the space between the two substrates. Also, multipackage modules include stacked packages, each having the die asymmetrically arranged on the substrate. Adjacent stacked packages have complementary asymmetrical arrangements of the die, and one package is inverted with respect to the other in the stack, such that the two die are situated side-by-side in the space between the two substrates. Also, methods are disclosed for making the packages and for making the stacked package modules.09-03-2009
20090218674SEMICONDUCTOR MODULE - A semiconductor module including: a semiconductor chip, an integrated circuit being formed in the semiconductor chip; a plurality of electrodes electrically connected to the integrated circuit; an insulating film formed on the semiconductor chip and having a plurality of openings positioned corresponding to the plurality of electrodes; and a long elastic protrusion extending on the insulating film. A plurality of interconnects respectively extend from over the electrodes to over the elastic protrusion, directions of the interconnects intersecting an axis AX that is parallel to the extending direction of the elastic protrusion. A plurality of leads are respectively in contact with the interconnects in an area positioned on the elastic protrusion. A cured adhesive maintains a space between a surface of the semiconductor chip on which the elastic protrusion is formed and a surface of the elastic substrate on which the leads are formed. A surface of the elastic protrusion except an area on which the interconnects are provided is in close contact with the elastic substrate due to an elastic force.09-03-2009
20090218673Semiconductor package having a bridge plate connection - A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.09-03-2009
20090321917Electrical Component - The invention discloses an electrical component with a carrier substrate, on which at least one semiconductor chip is mounted. Terminal areas are arranged on the underside of the carrier substrate and contact areas designed for the assembly with semiconductor chips are arranged on the upper side. The carrier substrate has a functional area that is divided into sections, wherein each section is assigned at least one function such as, e.g., as a filter, a frequency-separating filter, a balun, etc. A separate area of the carrier substrate is assigned to each section. The following applies to at least one of the sections: the contact area and/or the terminal area that is conductively connected to the section lies outside the base of this section. The connecting line that conductively connects the input or output of the respective section to the contact area and/or the terminal area is preferably shielded from the section by a ground area.12-31-2009
20100013077SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a top surface on which a first conductive pad is disposed, a bottom surface opposite to the top surface, and a side surface connecting the top and bottom surfaces to each other, a first reinforcement layer on the top surface of the semiconductor chip, a first absorption layer between the top surface of the semiconductor chip and the first reinforcement layer to absorb a stress resulting from a difference in thermal expansion coefficient between the first reinforcement layer and the semiconductor chip, and a connection terminal disposed on the first reinforcement layer and electrically connected to the first conductive pad.01-21-2010
20100013079PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE HAVING A PACKAGE SUBSTRATE - A package substrate may include an insulating substrate, a circuit pattern and a mold gate pattern. The insulating pattern may have a mold gate region through which a molding member may pass. The circuit pattern may be formed on the insulating substrate. The mold gate pattern may be formed on the mold gate region of the insulating substrate. The mold gate pattern may include a polymer having relatively strong adhesion strength with respect to the insulating substrate and relatively weak adhesion strength with respect to the molding member. Thus, costs of the package substrate and the semiconductor package may be decreased.01-21-2010
20100032823SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes: a semiconductor substrate having an active area formed on a major surface of the semiconductor substrate; an interlayer insulating film and a wiring layer formed on predetermined regions of the active area; and a sealing resin film covering the interlayer insulating film, the wiring layer, and the major surface of the semiconductor substrate and filling a groove surrounding the active area. The sealing resin film 02-11-2010
20100038770Method of packaging and interconnection of integrated circuits - A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.02-18-2010
20100065958PAD REDISTRIBUTION CHIP FOR COMPACTNESS, METHOD OF MANUFACTURING THE SAME, AND STACKED PACKAGE USING THE SAME - A substrate includes a substrate; a number of pad redistribution chips stacked on the substrate and on one another after being rotated 90° in a predetermined direction relative to one another, the pad redistribution chips having a number of center pads positioned at the center thereof, a number of (+) edge pads positioned on an end thereof while corresponding to those of the center pads lying in (+) direction from a middle center pad located in the middle of the center pads, a number of (−) edge pads positioned on the other end thereof while corresponding to those of the center pads lying in (−) direction with symmetry to those of the center pads lying in the (+) direction, and a number of traces for electrically connecting the center pads to the corresponding (±) edge pads, respectively; a flexible PCB for electrically connecting the substrate to the pad redistribution chips; and an anisotropic dielectric film for electrically connecting the pad redistribution chips to the flexible PCB and the substrate to the flexible PCB.03-18-2010
20120241936INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE-ON-PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base substrate top side; mounting a base integrated circuit over the base substrate top side, the base integrated circuit having an active side opposite an inactive side with the inactive side facing the base substrate top side; attaching a peripheral interconnect to the base substrate top side and a device peripheral pad of the base integrated circuit at the active side; mounting an interposer over the base integrated circuit and the peripheral interconnect, the interposer having an interposer top side and a window; and attaching a central interconnect to the interposer top side and a device central pad of the base integrated circuit at the active side, the central interconnect through the window.09-27-2012
20090072377INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DELAMINATION PREVENTION STRUCTURE - An integrated circuit package system includes: mounting an integrated circuit die over a carrier; attaching a delamination prevention structure over the integrated circuit die; and encapsulating the delamination prevention structure and the integrated circuit die.03-19-2009
20100065957PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE HAVING THE PACKAGE SUBSTRATE - A package substrate includes an insulating substrate having a mount region including external terminals mounted to the insulating substrate and a clamp region having an opening receiving a molding material therein, the clamp region disposed adjacent to the mount region in a first direction, a circuit pattern formed on the insulating substrate, and a blocking member blocking the molding material from moving from the clamp region to the mount region when the package substrate loaded in a mold die is pressurized to form a molding member, wherein the blocking member is disposed on at least one side of the package substrate in the clamp region, and the blocking member receives the molding material therein.03-18-2010
20100065956PACKAGING STRUCTURE, PACKAGING METHOD AND PHOTOSENSITIVE DEVICE - The application provides a packaging structure, a packaging method and a photosensitive device. The packaging structure includes a substrate structure, a chip and a solder bump electrically connecting with a pad on the chip. The solder bump is located on the substrate structure, so that the multilayer coverage structure required when forming a bump on a side of the chip in the prior art packaging structure is avoided. In this way, the thickness of the packaging structure is reduced and the reliably of the packaging structure is improved.03-18-2010
20100123239SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A plurality of semiconductor devices having different thicknesses from each other and having respective electrode terminals are fixed on a surface of the support plate through a resin layer in such a manner that terminal surfaces of the electrode terminals are on the level with each other. An insulating layer covers terminal forming surfaces of the semiconductor devices. At least one tapered bump having a tip surface formed in a smaller area than an area of the terminal surface of the electrode terminal of the semiconductor device is formed on one of the terminal surfaces of the electrode terminals and penetrates the insulating layer in such a manner that the tip surface of the tapered bump is exposed to a surface of the insulating layer. A wiring pattern is formed on the surface of the insulating layer and connected to the tip surface of the tapered bump.05-20-2010
20110101513CHIP ON FILM TYPE SEMICONDUCTOR PACKAGE - A chip on film type semiconductor package includes a film, a plurality of leads formed over the film, a chip formed over the plurality of leads, an under-fill layer filled an space between the chip and the plurality of leads and an insulating heating sheet formed on an opposite side of the film contacting to the plurality of leads, wherein the insulating heating sheet is formed of a compound based on a glass fiber.05-05-2011
20110074004PACKAGE PROCESS AND PACKAGE STRUCTURE - A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the side walls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the side walls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.03-31-2011
20110074003FOIL BASED SEMICONDUCTOR PACKAGE - The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.03-31-2011
20120119346SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - Disclosed are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a package cap which is capable of radiating high temperatures and performs a shield function preventing transmission of electromagnetic waves into and/or out of the semiconductor package. The semiconductor package including the package cap prevents chip malfunctions and improves device reliability. The package cap is positioned to cover first and second semiconductor chips of a semiconductor package.05-17-2012
20110042796CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate and at least one semiconductor chip thereon. The semiconductor chip has a plurality of conductive pads, where a plurality of first redistribution layers (RDLs) is disposed thereon and is electrically connected thereto. A single-layer insulating structure covers the carrier substrate and the semiconductor chip, having a plurality of openings exposing the plurality of first RDLs. A plurality of second RDLs is disposed on the single-layer insulating structure and is electrically connected to the plurality of first RDLs. A passivation layer is disposed on the single-layer insulating structure and the plurality of second RDLs, having a plurality of openings exposing the plurality of second RDLs. A plurality of conductive bumps is correspondingly disposed in the plurality of openings to be electrically connected to the plurality of second RDLs. A fabrication method of the chip package is also disclosed.02-24-2011
20110031604SEMICONDUCTOR PACKAGE REQUIRING REDUCED MANUFACTURING PROCESSES - A semiconductor package includes a semiconductor chip having a first surface, a second surface located opposite the first surface, and side surfaces connecting the first and second surfaces. The semiconductor chip includes bonding pads disposed on the first surface and having a molding member formed to cover the first surface of the semiconductor chip. The molding member is formed so as to expose the side surfaces of the semiconductor chip. The semiconductor chip also includes bonding members having first ends electrically connected to the respective bonding pads and second ends that are connected to and opposite the first ends. The second ends are exposed from side surfaces of the molding member after passing through the molding member so as to allow various electrical connections.02-10-2011
20090321918CHIP PACKAGE - A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.12-31-2009
20090230538SEMICONDUCTOR CHIP PACKAGE STRUCTURE FOR ACHIEVING FACE-UP ELECTRICAL CONNECTION WITHOUT USING A WIRE-BONDING PROCESS AND METHOD FOR MAKING THE SAME - A semiconductor chip package structure for achieving face-up electrical connection without using a wire-bonding process includes a package unit, a semiconductor chip, a substrate unit, a first insulative unit, a first conductive unit, a second conductive unit, and a second insulative unit. The package unit has a central receiving groove and an outer receiving groove formed around the central receiving groove. The semiconductor chip has a plurality of conductive pads. The first insulative unit has a first insulative layer formed between the conductive pads. The first conductive unit has a plurality of first conductive layers. The second conductive unit has a plurality of second conductive layers formed on the first conductive layers. The second insulative unit is formed between the first conductive layers and between the second conductive layers.09-17-2009
20090230537SEMICONDUCTOR DIE PACKAGE INCLUDING EMBEDDED FLIP CHIP - A semiconductor die package. The semiconductor die package includes a leadframe structure, a first semiconductor die comprising a first surface attached to a first side of the leadframe structure, and a second semiconductor die attached to a second side of the leadframe structure. The second semiconductor die comprises an integrated circuit die. A housing material is formed over at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die. An exterior surface of the molding material is substantially coplanar with the first surface of the semiconductor die.09-17-2009
20090230536SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DICE - A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first die attach pad, and a second die attach pad laterally spaced from the first die attach pad, a first side and a second side opposite to the first side. The semiconductor die package further includes a first semiconductor die attached the first die attach pad at the first side of the leadframe structure, and a second semiconductor die attached to the second die attach pad at the second side of the leadframe structure. The semiconductor die package further includes a housing material covering at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die.09-17-2009
20090166842LEADFRAME FOR SEMICONDUCTOR PACKAGE - A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.07-02-2009
20100244224SEMICONDUCTOR CHIP MOUNTING BODY, METHOD OF MANUFACTURING SEMICONDUCTOR CHIP MOUNTING BODY AND ELECTRONIC DEVICE - According to one embodiment, a semiconductor chip mounting body, with an enhanced shock-resistance at portions of the bonding member corresponding to the corners of a semiconductor chip, is provided. The semiconductor chip mounting body includes a circuit board having a circuit pattern formed on a mounting surface thereof, a semiconductor chip mounted on the circuit pattern of the circuit board, and a bonding member arranged at least between the circuit board and the semiconductor chip, and on the sides of the semiconductor chip to fix the semiconductor chip on the circuit board. The bonding member contains thermosetting resin and magnetic powder dispersed in the thermosetting resin. The magnetic powder is locally disposed in portions of the bonding member which is located the corners of the semiconductor chip.09-30-2010
20100244223INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a shielding channel through a substrate first side and a substrate second side; mounting a first shielding interconnect to the shielding channel; mounting an integrated circuit over the substrate and adjacent to the first shielding interconnect; attaching a silicon interposer, having an integral-conductive-shield and a via, to the first shielding interconnect with the integral-conductive-shield over the integrated circuit; grounding the shielding channel at the substrate second side; and forming an encapsulation over the substrate covering the integrated circuit and the first shielding interconnect.09-30-2010
20100244222INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate-interconnect; mounting an internal-interconnect to the substrate-interconnect; mounting a structure having an integral-interposer-structure over the substrate with the integral-interposer-structure connected to the internal-interconnect; mounting an integrated circuit to the substrate and under the integral-interposer-structure; and encapsulating the internal-interconnect and the integrated circuit with an encapsulation.09-30-2010
20080251907Electronic Device With Stress Relief Element - The present invention relates to an electronic device whose component body contains at least one stress relief element (10-16-2008
20110163436WIRING BOARD, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a semiconductor element 07-07-2011
20100320588Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor Die - A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.12-23-2010
20100283141SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package includes a chip; first and second connection pads arranged in a matrix and disposed about the chip, and the first and second connection pads have different bottom surface shapes when viewed from a bottom of the QFN package; bonding pads provided on an active surface of the chip and being electrically connected with corresponding said connection pads through bonding wires; and a package body encapsulating the chip, the bonding wires and an upper portion of each of the connection pads such that a lower portion of each of the connection pads extends outward from a bottom of the package body.11-11-2010
20110186981SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plate-shaped semiconductor element and an electrically insulating resin member. The semiconductor element has a front-surface electrode on its front surface and a back-surface electrode on its back surface. The resin member encapsulates the semiconductor element. The front-surface electrode is exposed to a front side of an outer surface of the resin member. The back-surface electrode is exposed to a back side of the outer surface of the resin member. The resin member has an extension portion that covers the entire side surface of the semiconductor element and extends from the side surface of the semiconductor element in a direction parallel to the front surface of the semiconductor element.08-04-2011
20110133326Reducing Plating Stub Reflections in a Chip Package Using Resistive Coupling - Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A resistor is used to resistively couple the plating stub to a ground layer.06-09-2011
20100117213COIL AND SEMICONDUCTOR APPARATUS HAVING THE SAME - An apparatus to package a semiconductor chip includes a coil configured to use induction heating to reflow a solder ball of the semiconductor chip. The coil includes a first body, a second body parallel to the first body, a third body extending from the first body to the second body. The first and second bodies are symmetrical with respect to a vertical plane disposed therebetween. The first and second bodies have inclined surfaces facing each other, and the inclined surfaces are distant from each other downward.05-13-2010
20110084374SEMICONDUCTOR PACKAGE WITH SECTIONED BONDING WIRE SCHEME - A semiconductor package includes a carrier substrate having thereon at least one bond finger; a semiconductor die mounted on a top surface of the carrier substrate; at least one active bond pad disposed on the semiconductor die; at least one dummy bond pad disposed on the semiconductor die; a first bonding wire extending between the at least one active bond pad and the at least one dummy bond pad; a second bonding wire extending between the at least one dummy bond pad and the at least one bond finger; and a molding compound encapsulating at least the semiconductor die.04-14-2011
20100059874SEMICONDUCTOR CHIP CAPABLE OF INCREASED NUMBER OF PADS IN LIMITED REGION AND SEMICONDUCTOR PACKAGE USING THE SAME - A semiconductor package includes a semiconductor chip including a body unit having one or more circuit units. A first bonding pad is disposed in a first face of the body unit and is connected to a circuit unit. A second bonding pad is disposed in the first face of the body unit in the bonding pad region so as to be positioned in an adjacent surrounding area of the first bonding pad and borders at least one side face of the first bonding pad while being insulated from the first bonding pad. A first connection terminal is attached onto the first bonding pad, and a second connection terminal is attached onto the second bonding pad and is positioned in an adjacent surrounding area of the first connection terminal and borders at least one side face of the first connection terminal while being insulated from the first connection terminal.03-11-2010
20100059875SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved.03-11-2010
20080217754SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor chip 09-11-2008
20080217753SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor element 09-11-2008
20110147913MICROELECTRONIC PACKAGE AND METHOD FOR A COMPRESSION-BASED MID-LEVEL INTERCONNECT - A microelectronic package includes first substrate (06-23-2011
20110215459INTERCONNECT AND TEST ASSEMBLY INCLUDING AN INTERCONNECT - An interconnect includes an elastic body, an electric conductor and a spacer. The elastic body has a first surface, a second surface, a first hole extending from the first surface to the second surface, and a second hole extending from the first surface to the second surface. The electric conductor is disposed in the first hole of the insulating body for contacting one of a plurality of balls of the first integrated circuit package and one of a plurality of conductor pads of the second integrated circuit package. The electric conductor includes an elastic body and electric conductor particles disbursed in the elastic body. The spacer is disposed in the second hole.09-08-2011
20100025839Leadframe, semiconductor device, and method of manufacturing the same - A leadframe has a die pad, first marks, and second marks, and the die pad allows thereon mounting of a first semiconductor chip. The first marks indicate a mounting region for the first semiconductor chip, the second marks indicate a mounting region for the second semiconductor chip, and the first marks and the second marks are different from each other in at least either one of size and geometry.02-04-2010
20100025840EMBEDDED INDUCTOR AND METHOD OF PRODUCING THEREOF - A method of manufacturing an inductor embedded into a semiconductor chip package (02-04-2010
20100019370SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device and manufacturing method. One embodiment provides a semiconductor chip. An encapsulating material covers the semiconductor chip. A metal layer is over the semiconductor chip and the encapsulating material. At least one of a voltage generating unit and a display unit are rigidly attached to at least one of the encapsulating material and the metal layer.01-28-2010
20100019371SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING WARPING IN A WAFER STATE AND MANUFACTURING METHOD THEREOF - In this manufacturing method of a semiconductor device, after a sealing film is applied over an entire surface of a semiconductor wafer and hardened, a second groove for forming a side-section protective film is formed in the sealing film and on the top surface side of the semiconductor wafer. In other words, the sealing film is formed in a state where a groove that causes strength reduction has not been formed on the top surface side of the semiconductor wafer. Since the second groove is formed on the top surface side of the semiconductor wafer after the sealing film is formed, the semiconductor wafer is less likely to warp when the sealing film, made of liquid resin, is hardened.01-28-2010
20100019372SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.01-28-2010
20120146207STACKED STRUCTURE AND STACKED METHOD FOR THREE-DIMENSIONAL CHIP - A stacked structure and a stacked method for a three-dimensional integrated circuit are provided. The provided stacked method includes separating a logic chip into a function chip and an I/O chip; stacking the function chip above the I/O chip; and stacking at least one memory chip between the function chip and the I/O chip.06-14-2012
20120146206PIN ATTACHMENT - A microelectronic package includes a substrate having a first region, a second region, a first surface, and a second surface remote from the first surface. At least one microelectronic element overlies the first region on the first surface. First electrically conductive elements are exposed at one of the first surface and the second surface of the substrate within the second region with at least some of the first conductive elements electrically connected to the at least one microelectronic element. Substantially rigid metal elements overlie the first conductive elements and have end surfaces remote therefrom. A bond metal joins the metal elements with the first conductive elements, and a molded dielectric layer overlies at least the second region of the substrate and has a surface remote from the substrate. The end surfaces of the metal elements are at least partially exposed at the surface of the molded dielectric layer.06-14-2012
20090115048Multipiece Apparatus for Thermal and Electromagnetic Interference (EMI) Shielding Enhancement in Die-Up Array Packages and Method of Making the Same - An integrated circuit (IC) device package is presented. A frame body has opposing first and second surfaces and a central opening that is open at the first and second surfaces. The second frame body surface is mounted to a first stiffener surface. An IC die is mounted to the first stiffener surface within the central opening through the frame body. A planar lid has opposing first and second surfaces. The second lid surface is coupled to the first frame body surface. A first substrate surface is coupled to a second stiffener surface. An array of electrically conductive terminals is coupled to a second substrate surface. The stiffener, frame body, and lid form an enclosure structure substantially enclosing the IC die. The die enclosure spreads heat from the IC die, and shields EMI emanating from and radiating toward the IC die. At least one tab protrudes from the second surface of the frame body. At least one receptacle formed in the first surface of the stiffener corresponding to the at least one tab. The at least one tab is coupled with the at least one corresponding receptacle, whereby structural coupling of said frame body to said stiffener is substantially improved.05-07-2009
20080265396QUAD FLAT NO-LEAD CHIP CARRIER WITH STANDOFF - A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved.10-30-2008
20110018119Semiconductor packages including heat slugs - A semiconductor package may include at least one semiconductor chip mounted on a substrate, a molding layer adapted to mold the at least one semiconductor chip, a heat slug, on the molding layer, having a structure in which a dielectric is provided between conductors, and a through mold via electrically connecting the heat slug to the substrate.01-27-2011
20090174058CHIP SCALE PACKAGE - A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.07-09-2009
20090174057SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD - The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.07-09-2009
20090174055Leadless Semiconductor Packages - An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice (07-09-2009
20090174054Module with Flat Construction and Method for Placing Components - A module for electrical components is proposed in which connection surfaces that can be bonded are provided on a multi-layer substrate with integrated wiring; a component chip is bonded on the top that has bond pads on its surface pointing upward and that contacts the substrate by means of bonding wires. Here, the wire guide of the bonding wires is so that they are each bonded with a ball on a connection surface and with the wedge directly on one of the bond pads.07-09-2009
20090174053Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device - A substrate 07-09-2009
20090174052ELECTRONIC COMPONENT, SEMICONDUCTOR PACKAGE, AND ELECTRONIC DEVICE - In a conventional UBM made of, for example, Cu, Ni, or NiP, there has been a problem that when an electronic component is held in high-temperature conditions for an extended period, the barrier characteristic of the UBM is lost and the bonding strength decreases due to formation of a brittle alloy layer at a bonding interface. The present invention improves the problem of decrease in long-term connection reliability of a solder connection portion after storage at high temperatures. An electronic component comprises the electronic component includes an electrode pad formed on a substrate or a semiconductor element and a barrier metal layer formed to cover the electrode pad and the barrier metal layer comprises a CuNi alloy layer on the side opposite the side in contact with the electrode pad, the CuNi alloy layer containing 15 to 60 at % of Cu and 40 to 85 at % of Ni.07-09-2009
20110115068Power Semiconductor Module and Method for Operating a Power Semiconductor Module - A power semiconductor module includes a circuit carrier including an insulation carrier having a top side on which a metallization layer is arranged. A power semiconductor chip is arranged on a side of the metallization layer facing away from the insulation carrier, and which has on a top side of the power semiconductor chip facing away from the circuit carrier an upper chip metallization composed of copper or a copper alloy having a thickness of greater than or equal to 1 μm. An electrical connection conductor composed of copper or a copper alloy is connected to the upper chip metallization at a connecting location. A potting compound extends from the circuit carrier to at least over the top side of the power semiconductor chip and completely covers the top side of the power semiconductor chip, encloses the connection conductor at least in the region of the connecting location, and has a penetration of less than or equal to 30 according to DIN ISO 2137 at a temperature of 25° C.05-19-2011
20110115067SEMICONDUCTOR CHIP PACKAGE WITH MOLD LOCKS - A semiconductor chip package includes a base comprising a die attach region and a mold-lock forming region surrounding the die attach region; a die mounted onto the base within the die attach region; a plurality of line-shaped trenches in the mold-lock forming region; a mold body encapsulating the die; and a mold lock inlaid in each of the line-shaped trenches to securely interlock the mold body to the base.05-19-2011
20110115066SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a circuit substrate, an electronic device, an encapsulant, and a conductive layer. The substrate includes a carrying surface, an opposing bottom surface, and a pad. The device is disposed adjacent to the carrying surface and is electrically connected to the substrate. The encapsulant is disposed adjacent to the carrying surface, encapsulates the device, and includes a center portion and a surrounding peripheral portion that is less thick than the center portion. An opening exposing the pad is formed in the peripheral portion. The conductive layer conformally covers the encapsulant and traverses the opening to connect to the pad.05-19-2011
20110115065INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a planar support structure having a cavity; forming a terminal within the cavity with the terminal coplanar with the planar support structure; forming a conductive pathway on the terminal and the planar support structure with the conductive pathway having a route portion and an interconnect attach portion at the end of the route portion; connecting a device and the interconnect attach portion with the interconnect attach portion towards the device; and forming an encapsulation over the planar support structure covering the conductive pathway and the device.05-19-2011
20110147914Clad Solder Thermal Interface Material - A clad solder thermal interface material is described. In one example the material has a a first layer of solder having a melting temperature lower than a temperature of a particular solder reflow furnace, a second layer of solder clad to the first layer of solder, the second layer having a melting temperature higher than the temperature of the solder reflow furnace, and a third layer of solder clad to the second layer of solder opposite the first layer, the third layer having a melting temperature lower than the temperature of the solder reflow furnace.06-23-2011
20100207263SEMICONDUCTOR DEVICE - A semiconductor device includes a first chip coupled to an electrical insulator, and a sintered heat conducting layer disposed between the electrical insulator and the first chip.08-19-2010
20110089554INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CAVITY AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting a substrate-less integrated circuit package, having a terminal having characteristics of an intermetallic compound, over a substrate; connecting the substrate and the substrate-less integrated circuit package; and forming a base encapsulation over the substrate-less integrated circuit package with the terminal exposed.04-21-2011
20110108974POWER AND SIGNAL DISTRIBUTION OF INTEGRATED CIRCUITS - A packaged integrated circuit is provided comprising a first semiconductor die, a second semiconductor die, and a bonding wire. The first semiconductor die has a first internal bonding pad electrically connected to the package. The second semiconductor die has a second internal bonding pad located in an internal portion of the second semiconductor die. The second internal bonding pad is electrically connected to the first internal bonding pad through the first bonding wire.05-12-2011
20120098115Semiconductor device and method of manufacturing the same - A semiconductor device has a substrate, a semiconductor chip mounted on the substrate, an encapsulating body encapsulating the semiconductor chip on the substrate, and a plurality of heat sink plates embedded in the encapsulating body so as to have a surface that is exposed to an exterior of the encapsulating body and positioned on the same plane. The heat sink plates are spaced from each other.04-26-2012
20110316138HIGH FREQUENCY FAST RECOVERY DIODE - A high-frequency fast recovery diode that includes a diode chip set, solder lugs, lead wires, lead terminals, a silicone coating layer and a plastic package body. The diode chip set includes n-diode chips arranged in the same polarity order sequentially, a part of the n-diode chips can be fast recovery diode chips and others can be conventional. Solder lugs are placed on both sides of, and connected with, each diode chip. Lead wires are connected with the solder lugs on the ends of the diode chip set, respectively. The silicone coating layer is provided around the diode chip set and the lugs. The plastic package body is provided around the lead terminals and the silicone coating layer. The shape of the plastic package body can be a cylindrical or square column. The reverse recovery time of the high-frequency fast recovery diode can be shortened, and the voltage resistance performance improved.12-29-2011
20120001316Package for High Power Devices - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.01-05-2012
20120001314MULTI-CHIP PACKAGE WITH THERMAL FRAME AND METHOD OF ASSEMBLING - A semiconductor device includes a substrate having a plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice are stacked on the bonding surface of the substrate to form a die stack. Each die has a plurality of die bonding pads arranged along at least one bonding edge thereof. The remaining edges of each die are non-bonding edges. A plurality of bonding wires each electrically connects one of the die bonding pads to one of the substrate bonding pads. At least one thermally conductive layer is disposed between two adjacent semiconductor dice. At least one thermally conductive lateral portion is in thermal contact with the at least one layer of thermally conductive material. Each thermally conductive lateral portion is arranged along a non-bonding edge of the die stack.01-05-2012
20120001317POWER SEMICONDUCTOR MODULE HAVING LAYERED INSULATING SIDE WALLS - A power semiconductor module includes at least two interconnected power semiconductor units having actuatable power semiconductors, a module housing in which the power semiconductor units are disposed and which has an electrically insulating side wall, and at least one connection bus extended through the side wall and connected to at least one of the power semiconductor units. High explosion resistance and particularly inexpensive production are provided by forming the insulating side wall as a stack of insulating and partial elements constructed as a single piece, in which contact areas of the partial elements contact each other.01-05-2012
20120001315SEMICONDUCTOR DEVICE - A semiconductor package includes a print circuit part, a lower chip, an upper chip, a thermal conductivity part, and an encapsulation resin. The lower chip and the upper chip are mounted on the print circuit part through wire bonding connection. The thermal conductivity part efficiently dissipates heat from the chips to the outside of the package. The encapsulation resin entirely seals the package while exposing the thermal conductivity part. A adhesive sheet is hardened to form a bonding layer between the thermal conductivity part and the upper chip, a bonding layer between the semiconductor chips, and a bonding layer between the semiconductor chip and the wired component. The configuration contributes to miniaturization, high integration, and heat resistance reduction of a semiconductor package using high-heat-generating ICs.01-05-2012
20110156236THERMALLY ENHANCED EXPANDED WAFER LEVEL PACKAGE BALL GRID ARRAY STRUCTURE AND METHOD OF MAKING THE SAME - A thermally enhanced expanded wafer level ball grid array package. The expanded wafer level ball grid array package includes an integrated thermally conductive heat dissipater. In one embodiment the heat dissipater is positioned in close proximity to a non-active face of a die and is separated from the non-active face by a thermal interface material. In another embodiment the heat dissipater includes legs that displace the heat dissipater a short distance from the non-active die face, with the intervening space occupied by encapsulation material. In yet another embodiment, the thermal interface material exists between the non-active die face and the heat dissipater, but extends beyond the edge of the semiconductor die to also cover a portion of the encapsulation material. Methods for making the various embodiments of the expanded wafer level ball grid array package are also shown.06-30-2011
20110156235FLIP CHIP PACKAGE HAVING ENHANCED THERMAL AND MECHANICAL PERFORMANCE - A flip chip semiconductor package is provided. In one embodiment, the flip chip semiconductor package comprises a first substrate having a first surface and a second surface opposite the first surface, a semiconductor chip mounted on the first surface of the first substrate by solder bumps, a thermally-conductive stiffener mounted above the first surface of the first substrate and around the chip to define a cavity region therebetween, one or more molding compound material disposed in the cavity region, and a second substrate mounted to the second surface of the first substrate by solder balls.06-30-2011
20100289132SUBSTRATE HAVING EMBEDDED SINGLE PATTERNED METAL LAYER, AND PACKAGE APPLIED WITH THE SAME, AND METHODS OF MANUFACTURING OF THE SUBSTRATE AND PACKAGE - A substrate having single patterned metal layer applied in a package is provided. The substrate includes a first patterned dielectric layer, a patterned metal layer and a second patterned dielectric layer, wherein the patterned metal layer is embedded in the first patterned dielectric layer. Also, the top surfaces of the patterned metal layer and the first patterned dielectric layer lie in the same plane. At least part of the patterned metal layer are exposed from the holes formed on the lower surface of the first patterned dielectric layer, so as to form plural first contact pads for electrical connection downwardly. The second patterned dielectric layer, formed above the patterned metal layer and the first patterned dielectric layer, at least exposes part of the patterned metal layer to form plural second contact pads at the top surface of the patterned metal layer for electrical connection upwardly.11-18-2010
20110049697ELECTRONIC PACKAGE SYSTEM - Disclosed herein is an electronic package system utilizing a module having a liquid contact material to prevent mechanically and thermally induced strains in an electrical joint. The conductivity of the liquid contact material provides electrical communication between the required electronic components of the package system. The ability of the liquid contact material to flow prevents the creation of stresses and affords an electronic package design tolerant of small displacements or torsions. Thus, the liquid contact material enables a floating contact with high electrical reliability.03-03-2011
20120153451SEMICONDUCTOR DEVICE - A semiconductor device of the present invention comprises a semiconductor element, a main electrode connected to the semiconductor element, and a case for sealing the semiconductor element. The main electrode is provided, extending outside of the case from the inside thereof, and an external thread or an internal thread to be fastened to an external terminal is provided integrally on an extended portion of the main electrode, which extends outside of the case.06-21-2012
20120119345INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DEVICE MOUNT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base bottom side and a base top side; mounting an integrated circuit perpendicular to the base top side, the integrated circuit having a first conductor partially exposed at a first end facing and connected to the base top side; and forming an encapsulation over the integrated circuit.05-17-2012
20110074005SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND LEAD FRAME, COMPRISING A BENT CONTACT SECTION - The invention relates to a semiconductor device having an integrated circuit die and a housing. The housing includes a base surface and at least one lateral surface which extends across to the base surface. In particular, this semiconductor device can be an electronic chip card, such as a universal integrated circuit card (UICC). The semiconductor device includes at least one electrical contact for electrically connecting the integrated circuit die with an abutting counter contact of a connecting device. The electrical contact has first and second mating sections, which are arranged on the base surface and lateral surface, respectively, and are connected to each other through a bent section.03-31-2011
20090134509INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CARRIER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a carrier having a top side and a bottom side; forming an edge terminal pad on the top side and an inner terminal pad on the bottom side; connecting an integrated circuit die to an inner portion of the edge terminal pad; and encapsulating the integrated circuit die and the inner portion of the edge terminal pad with the outer portion of the edge terminal pad exposed.05-28-2009
20110089555AREA REDUCTION FOR SURFACE MOUNT PACKAGE CHIPS - Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.04-21-2011
20120211878CHIP PACKAGE WITH PLANK STACK OF SEMICONDUCTOR DIES - In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.08-23-2012
20120126388STACKABLE SEMICONDUCTOR ASSEMBLY WITH BUMP/FLANGE HEAT SPREADER AND DUAL BUILD-UP CIRCUITRY - A stackable semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive, a plated through-hole, first build-up circuitry and second build-up circuitry. The heat spreader includes a bump and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the first build-up circuitry and thermally connected to the bump. The bump extends into an opening in the adhesive and the flange extends laterally from the bump at the cavity entrance. The first build-up circuitry and the second build-up circuitry extend beyond the semiconductor device in opposite vertical directions. The plated through-hole extends through the adhesive and provides signal routing between the first build-up circuitry and the second build-up circuitry. The heat spreader provides heat dissipation for the semiconductor device.05-24-2012
20120126387ENHANCED HEAT SPREADER FOR USE IN AN ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - An electronic device includes an integrated circuit (IC) die attached to a substrate, and electrical conductors connecting the IC die to the substrate. The electronic device also includes a heat spreader located over the IC die and having a concaved portion located over the IC die along with a lateral portion extending from the concaved portion. The lateral portion has a surface area greater than a surface area of the concaved portion. A support member is further included that extends from the lateral portion to and contacts the substrate. An encapsulant covers the support member leaving the lateral and concaved portions exposed on outer sides thereof. In another aspect, a method of manufacturing an electronic device is also included.05-24-2012
20120161306Semiconductor Package - In one embodiment, a semiconductor package comprising a metal base coupled to one or more pins, a semiconductor body having a top side and a bottom side, the top side comprising an integrated circuit and one or more metal surfaces for coupling the integrated circuit to the one more pins with one or more bonding wires, the bottom side non-positively coupled to the metal base, a disk having a top area and a base area, the base area coupled to the top side of the semiconductor body and at least partially covering the integrated circuit, the disk being electrically insulated from the semiconductor body, and a plastic compound completely enclosing the one or more bonding wires, and at least partially enclosing the top side of the integrated circuit, the top area of the disk, and the one or more pins.06-28-2012
20120161307CHIP SCALE SURFACE MOUNTED SEMICONDUCTOR DEVICE PACKAGE AND PROCESS OF MANUFACTURE - A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.06-28-2012
20100207264SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MOUNTED STRUCTURE - A module substrate has an interconnection electrode that is exposed at a side end face thereof. A semiconductor component including an IC chip is mounted on the module substrate. A molded part comprising a resin is formed so as to cover at least a part of the semiconductor component. A coating with higher heat conductivity than the molded part is formed on the surface of the molded part by applying a paste made of material with higher heat conductivity than the molded part. This improves heat dissipation. The coating can be formed such that it extends to the surface of the main substrate on which the module substrate with the semiconductor component is mounted and comes into contact with the interconnection electrode on the surface of the main substrate. This further improves heat dissipation.08-19-2010
20110180920CO-AXIAL RESTRAINT FOR CONNECTORS WITHIN FLIP-CHIP PACKAGES - An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions 07-28-2011
20110180919MULTI-TIERED INTEGRATED CIRCUIT PACKAGE - An integrated circuit package base includes a plurality of tiers. In some examples, an integrated circuit package encloses a plurality of stacked integrated circuits that are each electrically coupled to an electrical contact located on a respective tier of the package base. The tiers of the integrated circuit package can have different elevations relative to a bottom surface of the integrated circuit package.07-28-2011
20090057868Wafer Level Chip Size Package For MEMS Devices And Method For Fabricating The Same - The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.03-05-2009
20090057866Microelectronic Package Having Second Level Interconnects Including Stud Bumps and Method of Forming Same - A microelectronic package and a method of forming the package. The microelectronic package includes a first level package including: a package substrate having a die side and a carrier side a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects etectrically coupling the die to the package substrate. The microelectronic package further includes: a carrier having a substrate side, the first level package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the first level package to the carrier, each of the second level interconnects including a stud bump made substantially of Au.03-05-2009
20110186979SEMICONDUCTOR PACKAGE AND HIGH-FREQUENCY SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor package includes: a base substrate made of a metal; a frame body made of a dielectric, placed on a surface of the base substrate, and including an opening portion in its center portion; a seal member placed on an upper surface of the frame body, and including an opening portion in its center portion; and a lid portion placed on an upper surface of the seal member. The thickness of the seal member is substantially equal to that of the base substrate, and a coefficient of linear expansion of the seal member is substantially equal to that of the base substrate. The base substrate, the first frame body, the second frame body, the seal member and the lid portion form a space.08-04-2011
20100052146SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product.03-04-2010
20100052145SEMICONDUCTOR PACKAGE AND METHOD THEREFOR - In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.03-04-2010
20100052144SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD, IN PARTICULAR FOR MEMS DEVICES - A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.03-04-2010
20100052143Electronic packaging structure and a manufacturing method thereof - A packaging structure includes a main substrate having a plurality of circuit lines thereon, and an electronic module having at least one conductive pad at the bottom thereof and having a plurality of conductive lines on the sides thereof. The pad and the conductive circuits are connected electrically to the circuits on the main substrate when the electronic module is disposed on the main substrate. As above-mentioned, one electronic module can be stacked on top of another so that the integrity of the packaging structure is improved.03-04-2010
20100052142SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a first electrode and a second electrode of a semiconductor element, the first electrode and the second electrode being configured on a first surface and a second surface of the semiconductor chip, an encapsulating material encapsulating the semiconductor chip, the surface portion being other than regions, each of the regions connecting with the first second electrodes, each of inner electrodes being connected with the first or the second electrodes, a thickness of the inner electrode from the first surface or the second surface being the same thickness as the encapsulating material from the first surface or the second surface, respectively, outer electrodes, each of the outer electrodes being formed on the encapsulating material and connected with the inner electrode, a width of the outer electrode being at least wider than a width of the semiconductor chip, and outer plating materials, each of the outer plating materials covering five surfaces of the outer electrode other than one surface of the outer electrode being connected with the inner electrode.03-04-2010
20100052141QFN PACKAGE - An improved Quad Flat No-Lead package is described. The package is formed by encapsulating a die mounted on a leadframe with a moulding compound using a mould chase. The mould chase comprises a number of internal projections which form openings in the mould compound to expose regions of the leadframe. These exposed regions of the leadframe may then be used for soldering the package to a substrate. The arrangement of the openings may be designed such that each aperture is the same shape and size and/or that the apertures are arranged in multiple rows on the underside of the package.03-04-2010
20100052140PACKAGE STRUCTURE - In the specification and drawing a package structure is described and shown with a first die including a high side driver, a second die including a low side driver and at least one conducting wire, wherein the conducting wire is coupled with the first die and the second die.03-04-2010
20120175762SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other: and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed.07-12-2012
20100032822CHIP PACKAGE STRUCTURE - A chip package structure including a first substrate, a chip, a second substrate, a plurality of conductive wires, a plurality of solder balls and a molding compound is provided. The chip is disposed on the first substrate. The second substrate disposed on the chip has an upper surface and a lower surface, in which a distance of the lower surface relative to the chip is smaller than that of the upper surface relative to the chip. The upper surface has a ball mounting surface and a wire bonding surface. A distance between the wire bonding surface and the first substrate is smaller than that between the ball mounting surface and the first substrate. The conductive wires connect the wire bonding surface to the first substrate. The solder balls are disposed on the ball mounting surface. The molding compound is disposed on the first substrate.02-11-2010
20100270668Dual Interconnection in Stacked Memory and Controller Module - A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.10-28-2010
20100007004WAFER AND SEMICONDUCTOR PACKAGE - A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.01-14-2010
20100007003SEMICONDUCTOR DEVICE - A semiconductor device includes: a GaAs chip; and a resin sealing the GaAs chip. The GaAs chip includes: a p-type GaAs layer; an n-type GaAs layer on the p-type GaAs layer; a metal electrode located on the n-type GaAs layer along an edge of the GaAs chip and to which a positive voltage is applied; a device region located in a central portion of the GaAs chip; a semi-insulating region located between the metal electrode and the device region and extending in the p-type GaAs layer and the n-type GaAs layer; and a connecting portion disposed outside the semi-insulating region and electrically connecting the p-type GaAs layer to the metal electrode.01-14-2010
20100327423SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application provides a method and semiconductor packaging structure comprising a conductive substrate having a first surface, a first lateral surface and a second lateral surface adjacent to the first surface. A first electrode line with two ends are provided on the first surface and the first lateral surface, and a second electrode line with two ends are provided on the first surface and a second lateral surface respectively. A semiconductor device is provided on the first surface of the conductive substrate which electrically connected to the first electrode line and the second electrode line, a protective plate with through holes covers the first surface, and a sheathing overlays the semiconductor device.12-30-2010
20120261810INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFERSCALE SPACER - An integrated circuit packaging system is provided including: a first device having a first backside and a first active side; and a waferscale spacer having an exact fit at all four corners adjacent to an edge of the first device and a recess along the edge of the first device.10-18-2012
20110037160MICROELECTRONIC DEVICE AND FABRICATING METHOD THEREOF AND MEMS PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF - A fabricating method of a microelectronic device including the following steps is provided. First, a substrate is provided. Second, a semi-conductor element is formed in a CMOS circuit region of the substrate. Next, a plurality of metallic layer, a plurality of contact plugs and a plurality of oxide layer are formed on the substrate. The metallic layers and the oxide layers are interlaced with each other and the contact plugs are formed in the oxide layers and connected with the metallic layers correspondingly so as to form a micro electromechanical system (MEMS) structure within a MEMS region and an interconnecting structure within the CMOS circuit region. Then, a first protective layer is formed on at least one of the oxide layers and a second protective layer is formed on the interconnecting structure. Predetermined portions of the oxide layers located within the MEMS region are removed and thereby the MEMS structure is partially suspended above the substrate. The present invention also provides a microelectronic device, a MEMS package structure and a fabricating method thereof02-17-2011
20120319264SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member.12-20-2012
20120319263INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTRA SUBSTRATE DIE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a through hole; mounting an integrated circuit in the through hole, the integrated circuit having an inactive side and a vertical side; connecting a first interconnect in direct contact with the integrated circuit and the substrate; applying a wire-in-film adhesive around and above the integrated circuit leaving a portion of the vertical side and the inactive side exposed and covering a portion of the first interconnect; and mounting a chip above the integrated circuit and in direct contact with the wire-in-film adhesive.12-20-2012
20110215460STACKED SEMICONDUCTOR CHIPS - Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.09-08-2011
20120080783THIN FLIP CHIP PACKAGE STRUCTURE - A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.04-05-2012
20100230798SEMICONDUCTOR DEVICE INCLUDING SPACER ELEMENT - A semiconductor device includes a metal carrier and a spacer element attached to the metal carrier. The semiconductor device includes a first sintered metal layer on the spacer element and a semiconductor chip on the first sintered metal layer.09-16-2010
20120326292ELECTRONIC CONTROL UNIT - An electronic control unit includes a substrate, a semiconductor module, a heat storage body, an insulator, and a heat sink. The substrate includes a wiring and a land. The semiconductor module includes a semiconductor chip working as a switching element, a terminal electrically coupled with the semiconductor chip and the wiring, a molded resin sealing the semiconductor chip and the terminal, and a heat radiation plate having a surface exposed from the molded resin and transferring heat generated at the semiconductor chip. The heat storage body has a heat capacity required to store the heat generated at the semiconductor chip. The heat storage body is coupled with the heat radiation plate. The insulator is in contact with the heat storage body or the semiconductor module. The heat sink is in contact with the insulator.12-27-2012
20120326293SEMICONDUCTOR PACKAGE HAVING ELECTRODE ON SIDE SURFACE, AND SEMICONDUCTOR DEVICE - A semiconductor package includes a substrate, a semiconductor chip disposed on the substrate, and a connection wiring connected electrically to the semiconductor chip. The semiconductor package further includes a sidewall formed of an insulator, an inner electrode formed on a first surface of the sidewall that faces the substrate, and a sidewall external electrode formed on a second surface of the sidewall different from the first surface. The inner electrode and the sidewall external electrode are connected electrically, and the inner electrode is connected to the connection wiring. With this configuration, it is possible to suppress the semiconductor package from being large due to an increase in the number of sidewall external electrodes formed on the side surfaces of the semiconductor package, and to shorten a connection distance between the semiconductor packages by connecting the sidewall external electrodes.12-27-2012
20120139095LOW-PROFILE MICROELECTRONIC PACKAGE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC ASSEMBLY CONTAINING SAME - A low-profile microelectronic package includes a die (06-07-2012
20100148346SEMICONDUCTOR DIE PACKAGE INCLUDING LOW STRESS CONFIGURATION - A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.06-17-2010
20080251908Semiconductor device package having multi-chips with side-by-side configuration and method of the same - The present invention provides a semiconductor device package with the die receiving through hole and connecting through hole structure comprising a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad. A die is disposed within the die receiving through hole. An adhesion material is formed under the die and filled in the gap between the die and sidewall of the die receiving though hole. Further, a wire bonding is formed to couple to the bonding pads and the first contact pad. A dielectric layer is formed on the wire bonding, the die and the substrate. A second contact pad is formed at the lower surface of the substrate and under the connecting through hole structure.10-16-2008
20080237830Semiconductor device - There is provided a semiconductor device whose cost is low and whose case is restrained from breaking. In the semiconductor device having a semiconductor sensor chip, a signal processing circuit for processing signals output from the semiconductor sensor chip and a hollow case for mounting the semiconductor sensor chip and the signal processing circuit therein, the case is constructed by bonding a concave bottom member whose one end is opened with a plate-like lid member that covers the opening of the bottom member. Then, the bottom and lid members are both made of a semiconductor material and are bonded by means of anode bonding or metal bonding for example.10-02-2008
20080224298APPARATUS FOR PACKAGING SEMICONDUCTOR DEVICES, PACKAGED SEMICONDUCTOR COMPONENTS, METHODS OF MANUFACTURING APPARATUS FOR PACKAGING SEMICONDUCTOR DEVICES, AND METHODS OF MANUFACTURING SEMICONDUCTOR COMPONENTS - Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals electrically coupled to the die contacts, arrays of second backside terminals, and a plurality of individual package areas that have an array of the die contacts, an array of the first backside terminals, and an array of the second backside terminals. The apparatus further includes a second board having a first side laminated to the front side of the first board, a second side, openings through the second board aligned with individual package areas that define die cavities, and arrays of front contacts at the second side electrically coupled to the second backside terminals by interconnects extending through the first board and the second board.09-18-2008
20080224297Apparatus comprising a device and method for producing it - An apparatus comprises a device layer structure, a device integrated into the device layer structure, an insulating carrier substrate and an insulating layer being continuously positioned between the device layer structure and the insulating carrier substrate, the insulating layer having a thickness which is less than 1/10 of a thickness of the insulating carrier substrate. An apparatus further comprises a device integrated into a device layer structure disposed on an insulating layer, a housing layer disposed on the device layer structure and housing the device, a contact providing an electrical connection between the device and a surface of the housing layer opposed to the device layer structure and a molding material surrounding the housing layer and the insulating layer, the molding material directly abutting on a surface of the insulating layer being opposed to the device layer structure.09-18-2008
20130181336SEMICONDUCTOR PACKAGE WITH IMPROVED THERMAL PROPERTIES - A semiconductor package, comprises an encapsulant which contains a semiconductor substrate, the package lower side being mountable on a surface. The semiconductor substrate backside is in close proximity of the semiconductor package lower side for improved thermal conductivity to the surface. The active side of the semiconductor substrate, facing the upper side of the semiconductor package, has a plurality of die contacts. A plurality of electrically conductive interconnects are connected to the die contacts and extend to the lower side of the semiconductor package for connecting the die contacts to the surface.07-18-2013
20130168842INTEGRATED CIRCUIT PACKAGES HAVING REDISTRIBUTION STRUCTURES - A semiconductor package includes a semiconductor chip stack disposed between first and second leads near first and second sides of the package and including a plurality of semiconductor chips, and a redistribution structure disposed on the semiconductor chip stack. At least one semiconductor chip of the semiconductor chip stack includes a plurality of first chip pads disposed near or closer to a third side of the package. The redistribution structure includes a first redistribution pad disposed near or closer to the first side and electrically connected to the first lead, a second redistribution pad disposed near or closer to the second side and electrically connected to the second lead, and a third redistribution pad disposed near or closer to the third side and electrically connected to a first one of the first chip pads and the first redistribution pad.07-04-2013
20100084756DUAL OR MULTIPLE ROW PACKAGE - A dual or multiple row package (04-08-2010
20130134571POWER MODULE PACKAGE - Disclosed herein is a power module package including: a first heat dissipation plate including a first flow path, a second flow path, and a third flow path which are sequentially formed, the first flow path and the third flow path being formed to have a step therebetween; and a second heat dissipation plate formed under the first heat dissipation plate, having one face and the other face, having a semiconductor device mounting groove formed in the one face thereof, and including a fourth flow path having one end connected to the second flow path and the other end connected to the third flow path, wherein a cooling material introduced through the first flow path is distributed to the third flow path and the fourth flow path based on the second flow path.05-30-2013
20130134572SEMICONDUCTOR DEVICE INCLUDING CLADDED BASE PLATE - A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1.05-30-2013
20110210437INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED CONDUCTOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a component connector on the substrate; forming a resist layer on the substrate with the component connector exposed; forming a vertical insertion cavity in the resist layer, the vertical insertion cavity isolated from the component connector or a further vertical insertion cavity, the vertical insertion cavity having a cavity side that is orthogonal to the substrate; forming a rounded interconnect in the vertical insertion cavity, the rounded interconnect nonconformal to the vertical insertion cavity; and mounting an integrated circuit device on the component connector.09-01-2011
20080197477Flip-Chip Grid Ball Array Strip and Package - The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. The use of a retention wall of a stiffener layer over an expensive substrate layer allows for the use of disposable edges around the strip including indexing holes or other holding mechanisms. What is also contemplated is a method of manufacture of a compact strip, matrix, or array comprised of a plurality of integrated circuit packages where no waste or additional cuts are needed to produce individual integrated circuit packages.08-21-2008
20080197476SEMICONDUCTOR DEVICE - The bump diameter of a bump electrode is reduced. An external connection substrate is bonded to a semiconductor chip, and is provided with, at an edge portion thereof, an external connection electrode protruding from the semiconductor chip, and continuing on both principal surfaces of the external connection substrate. The external connection electrode on a principal surface side of the external connection substrate is connected to the bump electrode through an opening in a resin layer covering the external connection electrode. The external connection electrode on the other principal surface is connected to a conductive path of a mounting board. The chip and the external connection substrate are fixed together by an underfill material. The external connection electrode and the conductive path are fixed together by solder. The bonding strength can be improved even with a reduced bump diameter so that the chip can be reduced in size.08-21-2008
20080197475Packaging conductive structure and method for forming the same - A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure.08-21-2008
20080197474Semiconductor device package with multi-chips and method of the same - The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.08-21-2008
20080197473CHIP HOLDER WITH WAFER LEVEL REDISTRIBUTION LAYER - A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.08-21-2008
20090289343Semiconductor package having an antenna - The present invention relates to a semiconductor package having an antenna. The semiconductor package includes a substrate, a chip, a molding compound and an antenna. The substrate has a first surface and a second surface. The chip is disposed on the first surface of the substrate, and electrically connected to the substrate. The molding compound encapsulates the whole or a part of the chip. The antenna is disposed on the molding compound, and electrically connected to the chip. The antenna is disposed on the molding compound that has a relatively large area, so that the antenna will not occupy the space for the substrate.11-26-2009
20100308450INTEGRATED PACKAGE - A device substrate has a device major surface, a semiconductor element on the device major surface, and electrically conductive device connectors extending across the device major surface. An interconnection substrate has an interconnection substrate having an interconnection major surface, the interconnection substrate defining at least one sealing recess recessed from the interconnection major surface, the sealing recess being surrounded by a sealing ring. The device substrate is mounted on the interconnection substrate with the interconnection major surface facing the device major surface, the sealing ring around the semiconductor element and with the device major surface sealed against the sealing ring so that the recess forms a sealed cavity containing the semiconductor element. Electrical interconnects extend across the interconnection major surface. Interconnection bumps are provided outside the sealing ring to electrically connect the device to the interconnect substrate.12-09-2010
20110233750Arrangement of Two Substrates having an SLID Bond and Method for Producing such an Arrangement - An arrangement having a first and a second substrate is disclosed, wherein the two substrates are connected to one another by means of an SLID (Solid Liquid InterDiffusion) bond. The SLID bond exhibits a first metallic material and a second metallic material, wherein the SLID bond comprises the intermetallic Al/Sn-phase.09-29-2011
20110233749SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.09-29-2011
20110233748INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an interposer having an interposer first side and an interposer second side opposing the interposer first side; mounting an integrated circuit to the interposer first side, the integrated circuit having a non-active side and an active side with the non-active side facing the interposer; connecting first interconnects between the active side and the interposer first side, the first interconnects having a first density on the interposer first side; mounting the interposer over a package carrier with the interposer first side facing the package carrier; connecting second interconnects between the package carrier and the interposer second side, the second interconnects having a second density on the interposer second side, the second density that is approximately the same as the first density; and forming an encapsulation over the package carrier covering the interposer and the second interconnects.09-29-2011
20100314744SUBSTRATE HAVING SINGLE PATTERNED METAL LAYER EXPOSING PATTERNED DIELECTRIC LAYER, CHIP PACKAGE STRUCTURE INCLUDING THE SUBSTRATE, AND MANUFACTURING METHODS THEREOF - A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.12-16-2010
20100314743INTEGRATED CIRCUIT PACKAGE HAVING A CASTELLATED HEATSPREADER - In one aspect, an embodiment of an IC package includes an IC chip electrically connected to a substrate, a heatspreader disposed over the IC chip, wherein the heatspreader does not directly contact the IC chip, and an encapsulant material encapsulating at least a portion of the IC chip and a portion of the heatspreader such that a top portion of the heatspreader is exposed to the surroundings of the IC package. In another embodiment, the heatspreader comprises at least one castellation to improve adhesion to the encapsulation compound. A method of manufacturing such IC package is also disclosed.12-16-2010
20100314742SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having two or more regions that partially overlap so as to define an overlapping region. Through-holes are defined through the two or more partially overlapping regions. One or more first electrodes are disposed on inner surfaces of the semiconductor chip within the through-holes. One or more second electrodes are disposed so as to be insulated from the first electrodes. The one or more second electrodes are at least partially disposed in the overlapping region. Insulation members are disposed in the through-holes.12-16-2010
20130119528STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AND ASSOCIATED SYSTEMS AND METHODS - Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.05-16-2013
20120018869MOLD DESIGN AND SEMICONDUCTOR PACKAGE - A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.01-26-2012
20120032319HIGH-VOLTAGE PACKAGED DEVICE - Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described.02-09-2012

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