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HOUSING OR PACKAGE

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257690000 With contact or lead 1038
257685000 Multiple housings 544
257712000 With provision for cooling the housing or its contents 323
257701000 Insulating material 177
257723000 For plural devices 93
257680000 With window means 59
257687000 Housing or package filled with solid or liquid electrically insulating material 38
257679000 Smart (e.g., credit) card package 34
257684000 With semiconductor element forming part (e.g., base, of housing) 29
257682000 With desiccant, getter, or gas filling 23
257729000 Portion of housing of specific materials 18
257728000 For high frequency (e.g., microwave) device 12
257708000 Entirely of metal except for feedthrough 9
257688000 With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element, e.g., ring 5
20080265392SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.10-30-2008
20090115046Micro-electro-mechanical system device and method for making same - According to the present invention, a method for making a micro-electro-mechanical system (MEMS) device comprises: providing a substrate with devices and interconnection formed thereon, the substrate having a to-be-etched region; depositing and patterning an etch stop layer; depositing and patterning metal and via layers to form an MEMS structure, the MEMS structure including an isolation region between MEMS parts, an isolation region exposed upwardly, and an isolation region exposed downwardly, wherein the isolation region exposed downwardly is in contact with the etch stop layer; masking the isolation region exposed upwardly, and removing the isolation region between MEMS parts; and removing the etch stop layer.05-07-2009
20100244221INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a device through via and a device interconnect, over a substrate with the device through via traversing the integrated circuit and the device interconnect attached to the device through via; attaching a conductive support over the substrate with the conductive support adjacent to the integrated circuit; providing a pre-formed interposer, having an interposer through via and a pre-attached interconnect, with the pre-attached interconnect attached to the interposer through via; mounting the pre-formed interposer over the integrated circuit and the conductive support with the pre-attached interconnect over the device through via; and forming an encapsulation over the substrate covering the integrated circuit, the conductive support, and partially covering the pre-formed interposer.09-30-2010
20090134508Integrated circuit with flexible planar leads - A microelectronic device including a microelectronic circuit and at least one planar flexible lead. These planar flexible leads are adapted to bend and flex during mechanical stress, allowing direct mounting of the device to a member and able withstand extreme thermal cycling between −20° C. to +80° C. encountered in terrestrial applications. Advantageously, the microelectronic device is adapted to be both weldable and solderable. The invention may comprise a solar cell diode, which is flexible and so thin that it can be affixed directly to the solar panel proximate the solar cell.05-28-2009
20080237827Integrated circuit with flexible planer leads - A microelectronic device including a microelectronic circuit and at least one planar flexible lead. These planar flexible leads are adapted to bend and flex during mechanical stress allow direct mounting of the device to a member, and withstand extreme thermal cycling, such as −197° C. to +150° C. such as encountered in space.10-02-2008
257727000 Device held in place by clamping 3
20090108441SEMICONDUCTOR CLAMP SYSTEM - A system for clamping a plurality of semiconductors that includes: 1) a first endplate and a second endplate that are substantially parallel and oppose each other across a predetermine distance (the predetermined distance being fixed by one or more tension members that extend between the first endplate and the second endplate); and 2) a screw jack that includes a threaded cylinder that moves through a threaded opening in the first endplate upon being rotated such that the threaded cylinder moves toward the second endplate if rotated one direction and away from the second endplate if rotated the opposite direction.04-30-2009
20080284005FASTENER FOR HEAT SINKS - This invention is related to an improvement in the structure of a fastener which includes a rod and a sleeve, wherein the rod has a flat top for depression and a rod body extending downwardly from the flat top to form three stepped portions. The upper end of the rod body is provided with a circular groove. The sleeve is formed with a through hole and a flange close to its upper end. The inner side of the sleeve is provided above the flange with a first engaging section engageable with the circular groove of the rod. The sleeve is provided with a second engaging section below the flange and a third engaging section at the lower end thereof. By means of the engagement between the circular groove of the rod and the first engaging section of the sleeve, the rod will be prevented from detaching from the sleeve. The second and third engaging sections are used for preventing the fastener from disengaging from a workpiece. By means of the three stepped portions of the elongated body, the rod can be easily inserted into the sleeve thereby fastening the workpiece on the third engaging section of the sleeve. The second stepped portion of the elongated rod is used for expanding the outer end of the sleeve so as to keep the sleeve at a firm position thus preventing the rod from detaching from the sleeve and facilitating the locking operation of the fastener.11-20-2008
20110215463COMPRESSIVE RING STRUCTURE FOR FLIP CHIP PACKAGING - Flip chip packages having warpage control and methods for fabricating such packages are described. In one embodiment, the flip chip package comprises a package substrate; a chip coupled to the package substrate; and a ring structure coupled to the package substrate and positioned laterally around the periphery of the chip so that a surface of the chip is exposed, wherein the ring structure comprises one or more compressive members, each of the one or more compressive members compressively opposed to a surface of the package substrate to counter or absorb stresses in the package substrate.09-08-2011
257730000 Outside periphery of package having specified shape or configuration 2
20090267226HIGH-CONTRAST LASER MARK ON SUBSTRATE SURFACES - As part of a first configured laser operation, a smooth, more reflective marking area is formed at a surface of a substrate (e.g., integral heat spreader, or IHS). In a second configured laser operation, a mark is formed at the surface of the substrate within the marking area. The mark contrasts strongly with the reflective surface of the substrate in the marking area. As a result, the mark may be read with an optoelectronic imaging system with a higher rate of reliability than marks disposed at a substrate surface having a microtopographical profile with greater variation from a nominal surface plane. An IHS with a mark so disposed provides benefits when include as a portion of an integrated circuit package, which in turn provides benefits when included as a portion of an electronic system.10-29-2009
20100314750Integrated circuit package having security feature and method of manufacturingsame - An integrated circuit package comprises a package substrate (12-16-2010
257683000 With means to prevent explosion of package 1
20090250799Power Semiconductor Module Comprising an Explosion Protection System - A power semiconductor module for energy distribution, includes at least one power semiconductor, connection terminals for connecting the power semiconductor module, and a housing, in which protection from explosion is ensured in the module even in the event of electric arcs. Therefore, each power semiconductor and each connection terminal is disposed in the housing, and the housing includes an exhaust gas channel for the controlled withdrawal of hot gases and/or plasma in the event of an explosion.10-08-2009
Entries
DocumentTitleDate
20110175214Power Semiconductor Module With Interconnected Package Portions - A power semiconductor module includes a package having a first package portion and a second package portion. The side of the first package portion facing the second package portion has an anchoring element with a first recess. The second package portion includes a second recess with an indentation which receives the anchoring element. To produce a mechanically firm connection between the first package portion and the second package portion, a plug-in element is inserted in the first recess and the second recess. The plug-in element displaces the anchoring element transversely with respect to the plug-in direction, causing the anchoring element to engage the indentation so that a form-fit connection is produced between the first package portion and the second package portion. The plug-in element prevents the anchoring element from disengaging the indentation.07-21-2011
20100019365DICING/DIE BONDING FILM - The invention relates to a dicing die-bonding film having a pressure-sensitive adhesive layer and a die bonding adhesive layer being sequentially laminated on a supporting substrate, wherein said pressure-sensitive adhesive layer has a thickness of 10 to 80 μm, and has a storage elastic modulus at 23° C. of 1×1001-28-2010
20090194860Chip Housing Having Reduced Induced Vibration - A premold housing for accommodating a chip structure includes a first part of the housing which is connected to the chip structure as well as connected in an elastically deflectable manner to an additional part of the housing which is fastened to the support structure bearing the entire housing. A mechanism is provided for damping the deflection of the first part of the housing which is connected to the chip structure.08-06-2009
20100072594LOW COST DIE PLACEMENT - Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, using a release member having a phase change material. Specifically, IC elements/components can be selectively received, stored, inspected, repaired, and/or released in a scalable manner during the assembly of IC chips by inducing phase change of the phase change material. The release member can be flexible or rigid. In some embodiments, the release member can be used for a low cost placement of the IC elements in combination with an SOI (silicon on insulator) wafer and/or an intermediate transfer member. In other embodiments, the release member can be used for a low cost placement of the IC elements in combination with a release wafer.03-25-2010
20100072595METHOD AND SYSTEM FOR SEALING A SUBSTRATE - A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprises forming a metal seal on the substrate proximate to a perimeter of the MEMS device using a method such as photolithography. The metal seal is formed on the substrate while the MEMS device retains a sacrificial layer between conductive members of MEMS elements, and the sacrificial layer is removed after formation of the seal and prior to attachment of a backplane.03-25-2010
20090160040LOW TEMPERATURE CERAMIC MICROELECTROMECHANICAL STRUCTURES - A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method provides for processing and manufacturing is steps limiting a maximum exposure of an integrated circuit upon which the MEMS is manufactured during MEMS manufacturing to below a temperature wherein CMOS circuitry is adversely affected, for example below 400° C., and sometimes to below 300° C. or 250° C., thereby allowing direct manufacturing of the MEMS devices onto electronic integrated circuits, such as Si CMOS circuits.06-25-2009
20090045494METHOD FOR MANUFACTURING A MICROELECTRONIC PACKAGE - The invention relates to a method of packaging an electronic microsystem (02-19-2009
20090302445Method and Apparatus for Thermally Enhanced Semiconductor Package - A semiconductor package includes a semiconductor die. Encapsulant is flowed around a portion of the semiconductor die. The encapsulant is etched and a conductive material is deposited into the etched portion of the encapsulant to form a thermally conductive structure. In one embodiment, a trench is etched into the encapsulant and a thermally conductive material is deposited into the trench to form a thermal channel. In alternative embodiments, thermally conductive through hole vias (THVs) are formed in the encapsulant. A thermally conductive pad may be formed over the semiconductor die to facilitate removal of heat energy from the hot spots of the semiconductor die. A thermally conductive trace is formed to interconnect the thermal channel and the thermally conductive pad. A heat sink may be deposited over the semiconductor package. The packages are singulated by cutting through the encapsulant or the thermal channel.12-10-2009
20110012247SOCKET TYPE MEMS BONDING - A method for fabricating an integrated circuit device is disclosed. The method includes providing a first substrate; bonding a second substrate to the first substrate, the second substrate including a microelectromechanical system (MEMS) device; and bonding a third substrate to the first substrate.01-20-2011
20090236716RECTIFYING DIODE PACKAGE STRUCTURE - A rectifying diode package structure includes a base which has a holding deck to hold a diode chip and a protective portion on the perimeter of the base to form sealing space filled by a filling material to seal the diode chip in an integrated manner. The diode chip has a conductive element extended outside the sealing space. The holding deck and the protective portion are interposed by a buffer ring embedded in the filling material. The buffer ring has at least one retaining ridge which has at least one first end and one second end of different cross sections formed in an upright manner to form a retaining relationship between the buffer ring and the filling material.09-24-2009
20090236715SEMICONDUCTOR PACKAGE STRUCTURE WITH LAMINATED INTERPOSING LAYER - The invention relates to microelectronic semiconductor chip assemblies having vertically stacked layers. In a disclosed example of a preferred embodiment, a vertically stacked semiconductor chip assembly includes a first semiconductor chip affixed to the surface of a substrate. A laminated interposing layer therebetween includes a first adhesive material and a second adhesive material, at least one of the adhesive materials adapted to capturing debris. Methods are disclosed for making a vertically stacked semiconductor chip assemblies by joining first and second adhesive materials to form a laminated interposing layer between a first chip and second chip or substrate. In preferred embodiments of the invention, the interposing layer includes polyimide film and one adhesive material of relatively low elasticity, and another adhesive material having relatively high elasticity.09-24-2009
20100084751Double Broken Seal Ring - The amount of signal propagation and moisture penetration and corresponding reliability problems due to moisture penetration degradation in an IC can be reduced by fabricating two seal rings with non-adjacent gaps. In one embodiment, the same effect can be achieved by fabricating a wide seal ring with a channel having offset ingress and egress portions. Either of these embodiments can also have grounded seal ring segments which further reduce signal propagation.04-08-2010
20090189265METHOD AND APPARATUS FOR MAKING SEMICONDUCTOR DEVICES INCLUDING A FOIL - A method for manufacturing a semiconductor device including covering a portion of at least one semiconductor device with a foil, including covering at least one target region of the semiconductor device, and illuminating the foil with a laser to singulate from the foil a portion covering the at least one target region of the at least one semiconductor device.07-30-2009
20100038762CIRCUIT BOARD MANUFACTURING METHOD, SEMICONDUCTOR MANUFACTURING APPARATUS, CIRCUIT BOARD AND SEMICONDUCTOR DEVICE - There is provided a circuit board manufacturing method that makes it possible to manufacture a next-generation semiconductor device in a stable manner and improve the yield during secondary mounting processing. A circuit board 02-18-2010
20080265387SMUDGE RESISTANT COATING FOR ELECTRONIC DEVICE DISPLAYS - An apparatus and method is provided for preventing smudges (10-30-2008
20100078786WIRING SUBSTRATE WITH REINFORCEMENT - A wiring substrate assembly includes a resin wiring substrate and a reinforcement member. The resin wiring substrate does not have a core substrate, and includes a substrate main surface, a substrate back surface, a laminate structure comprised of resin insulation layers and conductive layers, and connection terminals disposed on the substrate main surface, to which a chip component is connectable. The reinforcement member is bonded to the substrate main surface and defines an opening portion extending through the reinforcement member so as to expose the main-surface-side connection terminals. The reinforcement member comprises a composite material including a resin material containing an inorganic material.04-01-2010
20090091014Semiconductor Device Having a Flexible Printed Circuit - To provide a thin film device which becomes possible to be formed in the portion which has been considered impossible to be provided with such device by the conventional technique, and to provide a semiconductor device which occupies small space and which has high shock resistance and flexibility, a device formation layer with a thickness of at most 50 μm which was peeled from a substrate by a transfer technique is transferred to another substrate, hence, a thin film device can be formed over various substrates. For instance, a semiconductor device can be formed so as to occupy small space by pasting a thin film device which is transferred to a flexible substrate onto a rear surface of a substrate of a panel, by pasting directly a thin film device onto a rear surface of a substrate of a panel, or by transferring a thin film device to an FPC which is pasted onto a substrate of a panel.04-09-2009
20090289339SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.11-26-2009
20090289338SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.11-26-2009
20100283138Nickel-Based Bonding of Semiconductor Wafers - A nickel-based material is used on one or both wafers to be bonded, and the two wafers are bonded at low temperature and pressure through interdiffusion of the nickel-based material with either another nickel-based material or aluminum. In various embodiments, nickel-based walls are formed on one wafer, and corresponding walls are formed on the other wafer from a nickel-based material or aluminum. The walls of the two wafers are placed in contact with one another under sufficient pressure and temperature to cause bonding of the walls through interdiffusion.11-11-2010
20080246133Flip-chip image sensor packages and methods of fabricating the same - There is provided an imager package including an image sensor die attached to a transparent substrate such that sensitive image sensing components on the sensor die face the transparent substrate. In accordance with an embodiment of the present technique, the imager package may be coupled to an external package via bond wires and other interconnect elements. The sensor die and bond wires may be protected by an encapsulant on which the interconnect elements may be disposed. The bond wires may enable placement of the interconnect elements partially or directly above the sensor die, as opposed to around an outer periphery of the sensor die. There is further provided a method of manufacturing an imager package wherein interconnect elements may be located partially or directly above the sensor die, enabling the manufacture of smaller imager packages than previously envisioned.10-09-2008
20080283987SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing structure for reducing destruction caused by pressure from the outside. A frame of a semiconductor material is provided over a first substrate, which is bonded to a second substrate having a semiconductor element so that the semiconductor element is located inside the frame between the first substrate and the second substrate. The frame may be formed using, as frame members, two L-shaped semiconductor members in combination or four or more stick semiconductor members in combination.11-20-2008
20080308919HOLLOW SEALING STRUCTURE AND MANUFACTURING METHOD FOR HOLLOW SEALING STRUCTURE - A manufacturing method for a hollow sealing structure, includes, a process for filling a recessed portion in a principal surface of a substrate with a first sacrificial layer, a process for forming a functional element portion on the principal surface of the substrate, a process for forming a second sacrificial layer on the functional element portion so as to be connected to a part of the first sacrificial layer, a process for forming a covering portion over respective surfaces of the first and second sacrificial layers, a process for circulating a fluid for sacrificial layer removal through an opening in the covering portion in contact with the first sacrificial layer, thereby removing the first and second sacrificial layers, and a process for closing the opening.12-18-2008
20080308918SEMICONDUCTOR PACKAGE WITH PASSIVE ELEMENTS - The semiconductor package includes a plate having first via patterns formed on a center portion and second via patterns formed on edge portions; a connection wiring formed on a top surface of the plate to connect at least one first via patterns to at least one second via patterns; a plurality of passive elements formed on the top surface of the plate having a connection wiring formed thereon; a semiconductor chip having a plurality of bonding pads attached to a bottom surface of the plate and electrically connected to the first via patterns; and a plurality of external connection terminals each of which being attached to each of the second via pattern on the bottom surface of the plate.12-18-2008
20080251903SEMICONDUCTOR MODULE - A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier.10-16-2008
20100320581Semiconductor device - The invention provides a semiconductor device including a rectangular chip provided on a mounting region of a substrate, a liquid resin layer provided under the rectangular chip and on a side surface of the chip, and a plurality of dams formed on the substrate so as to extend along the side surface of the rectangular chip. The configuration allows the semiconductor device to be provided with the substrate having a reduced size which is achieved by preventing a liquid resin from flowing out.12-23-2010
20080272472Semiconductor packaging device comprising a semiconductor chip including a MOSFET - A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed. The semiconductor device comprises a sealing member, a semiconductor chip positioned within the sealing member, the semiconductor chip having a source electrode and a gate electrode on a first main surface thereof and a drain electrode on a second main surface as a back surface thereof, a first electrode plate (drain electrode plate) having an upper surface and a lower surface, a part of the upper surface of the first electrode plate being exposed to an upper surface of the sealing member and the lower surface portions of end portions of the first electrode plate being exposed to a lower surface of the sealing member, and second electrode plates (source electrode plate and gate electrode plate) each having a lower surface exposed to the lower surface of the sealing member and an upper surface positioned within the sealing member, wherein the drain electrode of the semiconductor chip is electrically connected to the drain electrode plate through an adhesive, one or plural stud type bump electrodes are formed by gold wire on the surface of each of the source electrode and gate electrode of the semiconductor chip, the bump electrode(s) being covered with an electrically conductive adhesive, the bump electrode(s) and the source and gate electrode plates are electrically connected with each other through the adhesive, and the bump electrode(s) and the source and gate electrode plates are not in contact with each other.11-06-2008
20090146281SYSTEM IN PACKAGE AND FABRICATION METHOD THEREOF - There is provided a system-in-package including: a substrate of a sawed base wafer on which a semiconductor circuit is formed; a conductive post formed on a top surface of the substrate; at least one semiconductor chip stacked on the top surface of the substrate; a buried layer formed on the top surface of the substrate so as to cover at least partially the conductive post and the semiconductor chip; and an external connection bump electrically connected to the conductive post. The system-in-package is fabricated by stacking a plurality of semiconductor chips on a top surface of a base wafer, forming a buried layer, realizing an electrical path by a conductive post, and polishing top and bottom surfaces of the package, thereby thinning the thickness of the package. Further, the system-in-package greatly improves electrical operation characteristics and increases productivity.06-11-2009
20080258283WIRING BOARD AND SEMICONDUCTOR PACKAGE USING THE SAME - A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 μm and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as D10-23-2008
20080258282LEAD FRAME FREE PACKAGE AND METHOD OF MAKING - A lead frame free packaged semiconductor device with an exposed heat sink is formed by die bonding the semiconductor device directly to the heat sink and bonding package leads directly to the semiconductor die, and optionally to the heat sink. In an alternative embodiment, a lead frame free packaged semiconductor device with an exposed heat sink is formed by die bonding the semiconductor device directly to the heat sink and wire bonding package leads to the semiconductor die, and optionally to the heat sink.10-23-2008
20100140767Component Stacking Using Pre-Formed Adhesive Films - A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film.06-10-2010
20090267203MULTI-CHIP PACKAGE FOR REDUCING TEST TIME - A multi-chip package is provided. The multi-chip package includes semiconductor chips. The multi-chip package receives selection signals for selecting two or more chips in response to the selection signals. Any number of chips may be simultaneously selected for a test and the test time can be reduced.10-29-2009
20090140404HERMETIC SEAL AND RELIABLE BONDING STRUCTURES FOR 3D APPLICATIONS - A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.06-04-2009
20090212406SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - When manufacturing a semiconductor device by mounting a semiconductor chip 08-27-2009
20090230530SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A back side of the silicon semiconductor substrate is roughly ground and is finishing-ground by using a whetstone having a copper content of less than 1 ppm, the back side being an opposite side of a side on which the semiconductor element is formed. The back side of the silicon semiconductor substrate is cleaned by the silicon chemical etching. A part up to depth of 3 nm from the back side of the silicon semiconductor substrate comprises copper of 1×1009-17-2009
20090243062IC TAG AND MANUFACTURING METHOD OF THE SAME - An IC tag comprises a substrate on which a wiring pattern is formed, an IC chip which is bonded and mounted to the substrate by bringing a bump into press-contact with the wiring pattern, a repulsive member that is arranged on the surface opposite to the surface of the substrate on which surface the IC chip is mounted, and that is made of a material having higher rigidity than the substrate, and an exterior package member which is configured to cover the substrate, the IC chip, and the repulsive member.10-01-2009
20100187668NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.07-29-2010
20100148332SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A semiconductor apparatus includes a first wiring substrate, a second wiring substrate, a semiconductor chip, an adhesive layer and a molding resin. The second wiring substrate is stacked and connected on the first wiring substrate through a bump electrode. The semiconductor chip is mounted on the first wiring substrate by flip chip bonding and received between the first wiring substrate and the second wiring substrate. An upper surface of the semiconductor chip is subject to a mirror treatment. The adhesive layer is formed on the upper surface of the semiconductor chip. The molding resin is filled in a gap between the first wiring substrate and the second wiring substrate.06-17-2010
20090079052Semiconductor package, apparatus and method for manufacturing the semiconductor package, and electronic device equipped with the semiconductor package - Provided is a semiconductor package which includes a substrate that includes a chip region having an active surface and an inactive surface, and a dicing region having an active surface and an inactive surface; connection terminals disposed on the active surface that belongs to the chip region; a first molding layer that covers the active surface that belongs to the chip region and exposes a portion of the connection terminals; and a second molding layer that covers the active region that belongs to the dicing region and is disposed along the dicing region and has a different surface shape from the first molding layer so as to recognize a dicing line dividing the chip regions. The semiconductor package is manufactured using an apparatus for manufacturing a semiconductor package having a mold surface that coincides to surface shapes of the first and second molding layers.03-26-2009
20100187667Bonded Microelectromechanical Assemblies - A MEMS device is described that has a body with a component bonded to the body. The body has a main surface and a side surface adjacent to the main surface and smaller than the main surface. The body is formed of a material and the side surface is formed of the material and the body is in a crystalline structure different from the side surface. The body includes an outlet in the side surface and the component includes an aperture in fluid connection with the outlet.07-29-2010
20100213590Systems and Methods of Tamper Proof Packaging of a Semiconductor Device - A barrier layer can be attached in a semiconductor package to one or more sensitive devices. The barrier layer can be used to obstruct tampering by a malicious agent attempting to access sensitive information on the sensitive device. The barrier layer can cause the sensitive device to become inoperable if physically tampered. Additional other aspects of the protective packaging provide protection against x-ray and thermal probing as well as chemical and electrical tampering attempts.08-26-2010
20090243063PACKAGING METHOD OF MICRO ELECTRO MECHANICAL SYSTEM DEVICE AND PACKAGE THEREOF - Disclosed are a micro electro mechanical system (MEMS) device and a package thereof. The packaging method of a MEMS device comprises: sequentially forming a sacrificial layer, a support layer, and a block copolymer layer on a substrate on which the MEMS device is formed; self-assembling the block copolymer layer formed on the support layer; selectively etching a part of the self-assembled block copolymer layer to form a plurality of nano-pores; forming a plurality of etching holes in the support layer corresponding to the plurality of nano-pores using the block copolymer layer in which the plurality of nano-pores are formed as a mask; removing the sacrificial layer using the etching holes formed in the support layer; and forming a shielding layer on the support layer.10-01-2009
20110018112SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor package which includes: a semiconductor substrate; a functional element that is disposed on one surface of the semiconductor substrate; a protection substrate that is disposed in an opposite side of that surface of the semiconductor substrate with a predetermined gap from a surface of the semiconductor substrate; and a junction member that is disposed to surround the functional element and bonds the semiconductor substrate and the protection substrate together, wherein the functional element has a shape different from a shape of a plane surrounded by the junction member in that surface of the semiconductor substrate, or is disposed in a region deviated from a central region of the plane surrounded by the junction member in that surface of the semiconductor substrate.01-27-2011
20090121334MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS - A required number of wiring layers 05-14-2009
20080230884Semiconductor device package having multi-chips with side-by-side configuration and method of the same - The present invention provides a semiconductor device package having multi-chips with side-by-side configuration comprising a substrate with die receiving through holes, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. A first die having first bonding pads and a second die having second bonding pads are respectively disposed within the die receiving through holes. The first adhesion material is formed under the first and second die and the substrate, and the second adhesion material is filled in the gap between the first and second die and sidewall of the die receiving though holes of the substrate. Further, bonding wires are formed to couple between the first bonding pads and the first contact pads, between the second bonding pads and the first contact pads. A dielectric layer is formed on the bonding wires, the first and second die and the substrate. A build up layer is form on the lower surface of substrate and the back side of first and second die.09-25-2008
20090166830Metallic cover of miniaturization module - A metallic cover of a miniaturization module includes a substrate, a SMD chip unit and a metallic cover, the metallic cover embracing the SMD chip unit and having at least one sizing hole and a plurality of venting holes, the venting holes being disposed around the sizing hole, and the sizing hole and the venting holes being positioned above the SMD chip unit so that glue portions fill up slits between the metallic cover and the SMD chip unit. The venting holes stop the glue portion from running over the second chip unit. The glue-filled slits between the top lid and the SMD chip unit provides a strong support to prevent any deformation of the metallic cover when the metallic cover is tested and processed.07-02-2009
20080283986System-in-package type semiconductor device - A system-in-package type semiconductor device includes a plurality of semiconductor chips, a first semiconductor chip 11-20-2008
20080230885CHIP HERMETIC PACKAGE DEVICE AND METHOD FOR PRODUCING THE SAME - A chip hermetic package device includes a substrate, a chip, a hermetic lid, a hermetic material and a post. The height of the post is larger than the thickness of the hermetic material. A method for producing a chip hermetic package includes the steps of: mounting the chip on the substrate; disposing the post and the hermetic material between the substrate and the hermetic lid; disposing the hermetic lid on the substrate to form a chamber, the post supporting the hermetic lid on the substrate to form an air passage; and performing a sealing step in an atmosphere of inert gas. The present invention utilizes the post to form the air passage between the substrate and the hermetic lid. Therefore, only is the sealing step performed in the atmosphere of nitrogen, and present invention needs a reduced number of equipment. Therefore, the present invention has a low cost, simplifies the packaging process and improves efficiency.09-25-2008
20100019366Package for an Integrated Circuit - According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of alignment features disposed thereon, the monolithic frame having a mounting surface disposed thereon for the integrated circuit, the monolithic frame also having a thermal interface area disposed thereon for the integrated circuit. The device also includes an electrical interface capable of providing an electrical connection for the integrated circuit, the plurality of alignment features being substantially independent of the electrical interface, and an adhesive layer disposed between the monolithic frame and the electrical interface.01-28-2010
20100019364SAW DEBRIS REDUCTION IN MEMS DEVICES - An improved MEMS device and method of making. Channels are formed in a first substrate around a plurality of MEMS device areas previously formed on the first substrate. Then, a plurality of seal rings are applied around the plurality of MEMS device areas and over at least a portion of the formed channels. A second substrate is attached to the first substrate, then the seal ring surrounded MEMS device areas are separated from each other. The channels include first and second cross-sectional areas. The first cross-sectional area is sized to keep saw debris particles from entering the MEMS device area.01-28-2010
20090184407METHOD TO RECOVER UNDERFILLED MODULES BY SELECTIVE REMOVAL OF DISCRETE COMPONENTS - Methods and reworked intermediate and resultant electronic modules made thereby, whereby a component in need of rework is located and removed from the module to reveal encapsulated solder connections residing within an underfill matrix. Heights of both the solder connections and underfill matrix are reduced, followed by etching the solder out of the solder connections to form openings within the underfill matrix. The underfill material is then removed to expose metallurgy of the substrate. A blank having a release layer with an array of solder connections is aligned with the exposed metallurgy, and this solder array is transferred from the blank onto the metallurgy. The transferred solder connections are then flattened using heat and pressure, followed by attaching solder connections of a new component to the flattened solder connections and underfilling these reworked solder connections residing between the new chip and substrate.07-23-2009
20090121333Flexible substrates having a thin-film barrier - Methods and apparatus provide for: applying an inorganic barrier layer to at least a portion of a flexible substrate, the barrier layer being formed from a low liquidus temperature (LLT) material; and sintering the inorganic barrier layer while maintaining the flexible substrate below a critical temperature.05-14-2009
20090152698INTEGRATED MATCHING NETWORKS AND RF DEVICES THAT INCLUDE AN INTEGRATED MATCHING NETWORK - An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a power amplifier, a second die having a capacitor, and a metal interconnect coupled to the power amplifier and the first capacitor. The metal interconnect has an inductance. The capacitor and metal interconnect form a shunt impedance.06-18-2009
20110068452LOW COST DIE PLACEMENT - Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, using a release member having a phase change material. Specifically, IC elements/components can be selectively received, stored, inspected, repaired, and/or released in a scalable manner during the assembly of IC chips by inducing phase change of the phase change material. The release member can be flexible or rigid. In some embodiments, the release member can be used for a low cost placement of the IC elements in combination with an SOI (silicon on insulator) wafer and/or an intermediate transfer member. In other embodiments, the release member can be used for a low cost placement of the IC elements in combination with a release wafer.03-24-2011
20110089550PRODUCTION DEVICE, PRODUCTION METHOD, TEST APPARATUS AND INTEGRATED CIRCUIT PACKAGE - Provided is a manufacturing apparatus that manufactures an integrated circuit package by packaging an integrated circuit chip, the manufacturing apparatus comprising a flattening section that flattens the integrated circuit chip; a holding section that holds a base substrate; a transporting section that transports the flattened integrated circuit chip to load the integrated circuit chip on the base substrate held by the holding section; and a packaging section that packages the integrated circuit chip and the base substrate as the integrated circuit package.04-21-2011
20120161305TECHNIQUES FOR BONDING SUBSTRATES USING AN INTERMEDIATE LAYER - A method includes depositing a thin film on a first surface of a first substrate and moving a second surface of a second substrate into contact with the thin film such that the thin film is located between the first and second surfaces. The method further includes generating electromagnetic (EM) radiation of a first wavelength, the first wavelength selected such that the thin film absorbs EM radiation at the first wavelength. Additionally, the method includes directing the EM radiation through one of the first and second substrates and onto a region of the thin film until the first and second substrates are fused in the region.06-28-2012
20100207261CHIP ATTACH ADHESIVE TO FACILITATE EMBEDDED CHIP BUILD UP AND RELATED SYSTEMS AND METHODS - Present embodiments are directed to an adhesive and method for assembling a chip package. The adhesive may be used to couple a chip to a substrate, and the adhesive may include an epoxy-based dielectric material, an epoxy resin, a photoacid generator, an antioxidant, and a cold catalyst corresponding to the photoacid generator.08-19-2010
20080211073AIRTIGHT PACKAGE - An airtight sealed package with a device sealed therein in an airtight manner under vacuum, the device being placed in a space defined in the airtight sealed package by a lid and a substrate, includes at least one pressure adjustment unit provided on at least one of the lid and the substrate, and configured to receive energy from an outside of the airtight sealed package, with the device sealed in the airtight manner in the airtight sealed package, to adjust pressure in the space. An energy transmission member transmits the energy to the pressure adjustment unit.09-04-2008
20100006998LIQUID RESIN COMPOSITION, SEMICONDUCTOR WAFER HAVING ADHESIVE LAYER, SEMICONDUCTOR ELEMENT HAVING ADHESIVE LAYER, SEMICONDUCTOR PACKAGE, PROCESS FOR MANUFACTURING SEMICONDUCTOR ELEMENT AND PROCESS FOR MANUFACTURING SEMICONDUCTOR PACKAGE - A liquid resin composition of the present invention is a liquid resin composition for bonding a semiconductor element on a support, exhibiting a tackiness of 0.05 N or less after heating at 120° C. for 10 min and a tackiness of 1 N or more at 80° C. A semiconductor wafer having an adhesive layer of the present invention is a semiconductor wafer having an adhesive layer in which the adhesive layer is formed from the above liquid resin composition. A process for manufacturing a semiconductor element of the present invention has the application step of applying an adhesive as a liquid resin composition containing a thermosetting resin and a solvent to one side of a wafer; the evaporation step of evaporating said solvent while substantially maintaining a molecular weight of said liquid resin composition to form an adhesive layer; the bonding step of bonding a dicing sheet on one side of said wafer; and the cutting step of cutting said wafer into pieces.01-14-2010
20100006999SUBSTRATE BONDING METHOD AND ELECTRONIC COMPONENT THEREOF - A substrate bonding method has a film forming step of forming an insulating film for bonding in such a manner that an SiO01-14-2010
20120319261HERMETICALLY SEALED WAFER PACKAGES - Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.12-20-2012
20100224973Semiconductor memory device and method of fabricating the same - Provided is a semiconductor device and method of fabricating the semiconductor memory device. The semiconductor device may be formed by forming a first welding groove along outside edges of one case of a pair of upper and lower cases, forming a first welding protrusion along outside edges of the other case, the first welding protrusion being formed to correspond to the first welding groove and having a volume larger than a volume of the first welding groove. The method may further include inserting the first welding protrusion into the first welding groove to enclose a memory module in an inner accommodating space of the upper and lower cases, melting the first welding protrusion so that a first portion of the first welding protrusion fills the first welding groove and a second portion of the first welding protrusion fills a space between welding portions of the upper case and the lower case, and solidifying the first and second portions of the first welding protrusion.09-09-2010
20100230793SEMICONDUCTOR APPARATUS PACKAGING STRUCTURE, SEMICONDUCTOR APPARATUS PACKAGING METHOD, AND EMBOSSED TAPE - A TAB tape (09-16-2010
20130020693CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost.01-24-2013
20080237821Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a shielding plate, a first chip, a first sealant, a second chip and a second sealant. The substrate has a lower surface and an upper surface on which the shielding plate is disposed. The first chip disposed on the shielding plate is electrically connected to the substrate. The first sealant disposed on the upper surface encapsulates the shielding plate and the first chip. The second chip disposed on the lower surface is electrically connected to the substrate. The second sealant disposed on the lower surface encapsulates the second chip.10-02-2008
20080237820Package structure and method of manufacturing the same - A package structure including a substrate, a shielding element, a chip, a sealant layer and a semiconductor device is provided. The substrate has a first surface and a second surface opposite to the first surface. The shielding element is disposed on the first surface. The chip is disposed on the shielding element and is electrically connected to the substrate. The sealant layer is disposed on the first surface, and encapsulates the chip and the shielding element. The semiconductor device is disposed on the second surface.10-02-2008
20080230883INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLDED STRIP PROTRUSION - An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.09-25-2008
20080224291PACKAGED SEMICONDUCTOR COMPONENTS HAVING SUBSTANTIALLY RIGID SUPPORT MEMBERS AND METHODS OF PACKAGING SEMICONDUCTOR COMPONENTS - Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.09-18-2008
20110309486Method of Etching and Singulating a Cap Wafer - A method of forming a capped die forms a cap wafer having a top side and a bottom side. The bottom side is formed with 1) a plurality of device cavities having a first depth, and 2) a plurality of second cavities that each have a greater depth than the first depth. At least some of the plurality of second cavities each generally circumscribe at least one of the device cavities. The method then secures the cap wafer to a device wafer in a manner that causes a plurality of the device cavities each to circumscribe at least one of circuitry and structure on the device wafer. Next, the method removes at least a portion of the top side of the cap wafer to expose the second cavities. This forms a plurality of caps that each protect the noted circuitry and structure.12-22-2011

Patent applications in class HOUSING OR PACKAGE

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