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LEAD FRAME

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257676000 With structure for mounting semiconductor chip to lead frame (e.g., configuration of die bonding flag, absence of a die bonding flag, recess for LED) 663
257675000 With heat sink means 141
257670000 With separate tie bar element or plural tie bars 72
257673000 With bumps on ends of lead fingers to connect to semiconductor 55
257668000 On insulating carrier other than a printed circuit board 43
257669000 With stress relief 27
257667000 With dam or vent for encapsulant 19
257677000 Of specified material other than copper (e.g., Kovar (T.M.)) 18
257674000 With means for controlling lead tension 4
20090146277SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor module case; a metal terminal externally extending from within the case; a semiconductor element disposed within the case and electrically connected to the metal terminal; and a printed wiring board having a wiring pattern formed on a surface thereof, the printed wiring board being connected to the semiconductor element through the metal terminal; wherein the external portion of the metal terminal includes a joining portion and a resilient portion, the joining portion being in surface contact with an external surface of the case, the resilient portion facing and being spaced from the joining portion; wherein the printed wiring board is inserted between the joining portion and the resilient portion; and wherein the wiring pattern on the printed wiring board is pressure-welded to the joining portion.06-11-2009
20130168840SEMICONDUCTOR INTEGRATED DEVICE WITH MECHANICALLY DECOUPLED ACTIVE AREA AND RELATED MANUFACTURING PROCESS - A semiconductor integrated device is provided with: a die having a body of semiconductor material with a front surface, and an active area arranged at the front surface; and a package having a support element carrying the die at a back surface of the body, and a coating material covering the die. The body includes a mechanical decoupling region, which mechanically decouples the active area from mechanical stresses induced by the package; the mechanical decoupling region is a trench arrangement within the body, which releases the active area from an external frame of the body, designed to absorb the mechanical stresses induced by the package.07-04-2013
20120280375SEMICONDUCTOR PACKAGE AND RADIATION LEAD FRAME - In a package wherein a lead part coupled to a semiconductor element by wire bonding, an element retention member to retain the semiconductor element on the top face side and radiate heat on the bottom face side, and an insulative partition part to partition the lead part from the element retention member with an insulative resin appear, a creeping route ranging from the top face to retain the semiconductor element to a package bottom face on a boundary plane between the element retention member and an insulative partition part includes a bent route having a plurality of turns. Consequently, it is possible to inhibit an encapsulation resin to seal a region retaining the semiconductor element from exuding toward the bottom face side of the package.11-08-2012
20120086112Multi-Component Electronic System Having Leadframe with Support-Free Cantilever Leads04-12-2012
257672000 Small lead frame (e.g., "spider" frame) for connecting a large lead frame to a semiconductor chip 4
20100140761Quad Flat Package - A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.06-10-2010
20110095406TECHNOLOGY OF REDUCING RADIATION NOISE OF SEMICONDUCTOR DEVICE - A first lead frame group is constituted by a plurality of lead frames that are connected to the first circuit, terminals of the plurality of lead frames being provided on a first side of the semiconductor device. A second lead frame group is constituted by a plurality of lead frames that are connected to the second circuit, terminals of the plurality of lead frames being provided on a second side of the semiconductor device. A suspension lead for suspending a die pad that supports the semiconductor chip, the suspension lead being arranged from a corner portion that is formed by the first side and the second side toward the semiconductor chip. Among a group of the terminals of the first lead frame group that are provided on the first side, a terminal on the corner portion side is a terminal for inputting or outputting a signal with a high frequency.04-28-2011
20090001531INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE - An integrated circuit package system includes: fabricating a lead frame including: providing inner leads having an inner lead pitch of progressive length, forming a lead shoulder, on the inner leads, having a shoulder height of a progressive height, and forming outer leads coupled to the lead shoulder and the inner leads; mounting an integrated circuit die on the lead frame; and molding a package body on the lead frame and the integrated circuit die.01-01-2009
20080203548High current semiconductor power device soic package - A high current semiconductor power SOIC package is disclosed. The package includes a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, the lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die soldered thereto; a pair of lead bonding areas being disposed in a same plane of a top surface of the die; large diameter bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum; and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.08-28-2008
Entries
DocumentTitleDate
20130043571POWER OVERLAY STRUCTURE WITH LEADFRAME CONNECTIONS - A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.02-21-2013
20090218663LEAD FRAME BASED SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package, where the package includes a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface. The method is characterised in that it comprises the step of patterning one or more channels on the surface which channels extend away from the joint area towards an edge of the surface. Also the method has the step of applying a compound to one or more channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the interaction defines one or more paths in the connective material. These correspond to the one or more channels on the surface and allow the passage of waste material away from the joint area to the outer edge of the surface.09-03-2009
20090194855FOLDED LEADFRAME MULTIPLE DIE PACKAGE - A multiple die package includes a folded leadframe for interconnecting at least two die attached to another leadframe. In a synchronous voltage regulator the folded leadframe, which is formed from a single piece of material, connects the high side switching device with the low side switching device to provide a low resistance, low inductance connection between the two devices.08-06-2009
20100052118MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGES - Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame with a customized array of lands at the bottom of the package. The lands are connected to a series of leads that are located within the perimeter of the lands. The leads can be routed according to the requirements of each specific IC die which they support and therefore can support both a single die and multiple die in the semiconductor package. Such a configuration provides a flexible routing for optimized layout, a maximized package density, and a higher input/output capability with a smaller package size. Other embodiments are also described.03-04-2010
20100127362SEMICONDUCTOR PACKAGE HAVING ISOLATED INNER LEAD - A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip. A jumping wire electrically connecting the isolated inner lead and the external lead is adjacent to the second side to achieve the redistribution of pin assignments without affecting wire-bonding. Especially, this package can be applied for multi-chip stacking.05-27-2010
20110193205SEMICONDUCTOR DEVICE PACKAGES HAVING STACKING FUNCTIONALITY AND INCLUDING INTERPOSER - A semiconductor device package with an interposer, which serves as an intermediate or bridge circuit of various electrical pathways in the package to electrically connect any two or more electrical contacts, such as any two or more electrical contacts of a substrate and a chip. In particular, the interposer provides electrical pathways for simplifying a circuit layout of the substrate, reducing the number of layers of the substrate, thereby reducing package height and manufacturing cost. Furthermore, the tolerance of the circuit layout can be increased or maintained, while controlling signal interference between adjacent traces and accommodating high density circuit designs. Moreover, the package is suitable for a PoP process, where a profile of top solder balls on the substrate and a package body can be varied according to particular applications, so as to expose at least a portion of each of the top solder balls and electrically connect the package to another device through the exposed, top solder balls.08-11-2011
20110193204SEMICONDUCTOR DEVICE - A semiconductor package includes a substrate including a substrate body which has an upper surface and a lower surface facing away from the upper surface, first connection pads which are formed on the upper surface, and a second connection pad which is formed on the upper surface to be separated from the first connection pads, a semiconductor chip including first bonding pads and a second bonding pad, connection members connecting the first connection pads and the first bonding pads, and a resistor member connecting the second connection pad and the second bonding pad.08-11-2011
20090294932LEADFRAME HAVING DELAMINATION RESISTANT DIE PAD - A lead frame (12-03-2009
20100072584COPPER ALLOY SHEET FOR ELECTRIC AND ELECTRONIC PARTS - A Cu—Fe—P alloy sheet that is provided with the high strength and with the improved resistance of peel off of oxidation film, in order to deal with problems such as package cracks and peeling, is provided. A copper alloy sheet for electric and electronic parts according to the present invention is a copper alloy sheet containing Fe: 0.01 to 0.50 mass % and P: 0.01 to 0.15 mass %, respectively, with the remainder of Cu and inevitable impurities. A centerline average roughness Ra is 0.2 μm or less and a maximum height Rmax is 1.5 μm or less, and Kurtosis (degree peakedness) Rku of roughness curve is 5.0 or less, in measurement of the surface roughness of the copper alloy sheet in accordance with JIS B0601.03-25-2010
20130075880PACKAGING STRUCTURE - A packaging structure comprises a first leadframe, a second leadframe, two grounding pins, two first pins, a plurality of first wires, a plurality of second wires, and a package body. The second leadframe is coupled to the drains of a first power transistor and a second power transistor. The two grounding pins are adjacent together and coupled to the first leadframe. The two first pins are coupled to the source of the second power transistor. The two first pins are connected together through a conductive region for increasing capability of loading current. The plurality of first wires is coupled between the source of the second power transistor and the first pin to decrease the internal resistance of the second power transistor. The plurality of second wires is coupled between the first leadframe and the source of the first power transistor to decrease the internal resistance of the first power transistor.03-28-2013
20130032932BONDED WIRE SEMICONDUCTOR DEVICE - A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.02-07-2013
20130082370COMPONENT BUILT-IN WIRING BOARD AND MANUFACTURING METHOD OF COMPONENT BUILT-IN WIRING BOARD - Disclosed is a component built-in wiring board, including a first insulating layer; a second insulating layer positioned in a laminated state on the first insulating layer; a semiconductor element buried in the second insulating layer, having a semiconductor chip with terminal pads and having surface mounting terminals arrayed in a grid shape connected electrically with the terminal pads; an electric/electronic component further buried in the second insulating layer; a wiring pattern sandwiched between the first insulating layer and the second insulating layer, including a first mounting land for the semiconductor element and a second mounting land for the electric/electronic component; a first connecting member connecting electrically the surface mounting terminal of the semiconductor element with the first mounting land; and a second connecting member connecting electrically the terminals of the electric/electronic component with the second mounting land, made of a same material as a material of the first connecting member.04-04-2013
20090121327Semiconductor device having spacer formed on semiconductor chip connected with wire - A semiconductor device includes a semiconductor chip, a supporting body that is disposed below the semiconductor chip and supports the semiconductor chip, a spacer that is fixed onto the first semiconductor chip, and a substrate that is located below the first semiconductor chip and electrically connected to the semiconductor chip with a wire. At least a part of the peripheral portion of the semiconductor chip is an overhang portion that projects more laterally than the peripheral portion of the supporting body. A covering portion that covers a part of the upper surface of the overhang portion is formed in the spacer. The wire is connected to a region in the upper surface of the overhang portion, the region being lateral to the outermost periphery of the covering portion of the spacer and not being covered with the covering portion of the spacer. A height of an apex of the wire from the upper surface of the first semiconductor chip as a reference, is greater than a height, from the reference, of at least a portion in the outermost periphery of the covering portion of the spacer, the portion having the wire arranged at its lateral side.05-14-2009
20090121326SEMICONDUCTOR PACKAGE MODULE - A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.05-14-2009
20090160037METHOD OF PACKAGING INTEGRATED CIRCUITS - A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead.06-25-2009
20090160036PACKAGE WITH MULTIPLE DIES - A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package.06-25-2009
20090146273SEMICONDUCTOR DEVICE - There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions.06-11-2009
20130082369CURABLE RESIN COMPOSITION, CURABLE RESIN COMPOSITION TABLET, MOLDED BODY, SEMICONDUCTOR PACKAGE, SEMICONDUCTOR COMPONENT AND LIGHT EMITTING DIODE - The present invention aims to provide a curable resin composition which gives a cured product having a low linear expansion coefficient. The curable resin composition of the present invention contains, as essential components, (A) an organic compound having at least two carbon-carbon double bonds reactive with SiH groups per molecule, (B) a compound containing at least two SiH groups per molecule, (C) a hydrosilylation catalyst, (D) a silicone compound having at least one carbon-carbon double bond reactive with a SiH group per molecule, and (E) an inorganic filler.04-04-2013
20100025828SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND LEAD FRAME - To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part.02-04-2010
20100148325Semiconductor Dice with Backside Trenches Filled With Elastic Material For Improved Attachment, Packages Using the Same, and Methods of Making the Same - Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.06-17-2010
20130087898Semiconductor Device and Method of Forming Prefabricated Multi-Die Leadframe for Electrical Interconnect of Stacked Semiconductor Die - A prefabricated multi-die leadframe having a plurality of contact pads is mounted over a temporary carrier. A first semiconductor die is mounted over the carrier between the contact pads of the leadframe. A second semiconductor die is mounted over the contact pads of the leadframe and over the first die. An encapsulant is deposited over the leadframe and first and second die. The carrier is removed. A first interconnect structure is formed over the leadframe and the first die and a first surface of the encapsulant. A channel is cut through the encapsulant and leadframe to separate the contact pads. A plurality of conductive vias can be formed through the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive vias.04-11-2013
20090045489MICROELECTRONIC DIE PACKAGES WITH LEADFRAMES, INCLUDING LEADFRAME-BASED INTERPOSER FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.02-19-2009
20130049179LOW COST HYBRID HIGH DENSITY PACKAGE - A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.02-28-2013
20100001382MANUFACTURING METHOD FOR INTEGRATING A SHUNT RESISTOR INTO A SEMICONDUCTOR PACKAGE - An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.01-07-2010
20090321899INTEGRATED CIRCUIT PACKAGE SYSTEM STACKABLE DEVICES - An integrated circuit package system includes: providing a finger lead having a side with an outward exposed area and an inward exposed area separated by a lead cavity; positioning a chip adjacent the finger lead and connected to the finger lead; and a stack encapsulant encapsulating the chip and the finger lead with the outward exposed area and the inward exposed area of the finger lead substantially exposed.12-31-2009
20100133665INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; and removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed.06-03-2010
20100133666DEVICE INCLUDING A SEMICONDUCTOR CHIP AND METAL FOILS - A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.06-03-2010
20090302441COL (CHIP-ON-LEAD) MULTI-CHIP PACKAGE - A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, tile thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant. Therefore, the internal leads of the leads without downset bends in the encapsulant can balance the upper and lower mold flows and carry more chips without shifting nor tilting.12-10-2009
20120217626SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes: placing a seal layer including a connection conductive film on the surface so that the connection conductive film is in contact with an electrode of a semiconductor element and a lead; electrically coupling the electrode and the lead through the connection conductive film; and sealing the semiconductor element by the seal layer.08-30-2012
20110006409NICKEL-TITANUM CONTACT LAYERS IN SEMICONDUCTOR DEVICES - Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds (or alloys) and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit having a drain on the backside of the substrate, a TiNi contact layer contacting the drain on the backside of the substrate, a soldering layer on the contact layer, an oxidation reducing layer on the soldering layer, a solder bump on the soldering layer, and a lead frame attached to the solder bump. The combination of the Ti and Ni materials in the contact layer exhibits many features not found in the Ti and Ni materials alone, such as reduced backside on-resistance, ability to form a silicide with the Si substrate at lower temperatures, reduced wafer warpage, increased ductility for improved elasticity, and good adhesion properties. Other embodiments are described.01-13-2011
20130069212SEMICONDUCTOR DEVICE - A semiconductor device in which a flip chip is mounted which can change a potential of a specific terminal without changing a design of a package external. The semiconductor device includes an IC chip having a bump for an external terminal, and a package in which the IC chip is mounted. The package includes an inner lead portion that supplies a first signal or a second signal to the external terminal. The inner lead portion has a pattern of an inner lead that can change a signal to be supplied to the external terminal to the first signal or the second signal according to a position at which the IC chip is mounted.03-21-2013
20130069210POWER MODULE PACKAGE - Disclosed herein is a power module package including: a first substrate having one surface and the other surface; a second substrate contacting one side of one surface of the first substrate; and a first lead frame contacting the other side of one surface of the first substrate. The power module package further includes: a first metal layer formed on one side of one surface of the first substrate; a first bonding layer formed on the first metal layer and contacting a lower surface of the second substrate; a second metal layer formed on the other side of one surface of the first substrate; and a second bonding layer formed on the second metal layer and contacting a lower surface of the first lead frame.03-21-2013
20130069211DEVICE INCLUDING A SEMICONDUCTOR CHIP AND METAL FOILS - A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.03-21-2013
20120112329CHIP PACKAGE - An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof.05-10-2012
20090065911SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a carrier, at least one chip, an encapsulation, and a patterned conductive film. The carrier has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the carrier and electrically connected to the carrier. The encapsulation encapsulates the chip and at least a portion of the first surface of the carrier. The patterned conductive film is disposed on the encapsulation to electrically connect to the carrier. A manufacturing method of the semiconductor package is also disclosed.03-12-2009
20130062741Semiconductor Devices and Methods of Manufacturing and Packaging Thereof - Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.03-14-2013
20130062742Spot Plated Leadframe and IC Bond Pad Via Array Design for Copper Wire - There is provided a system and method for a spot plated leadframe and an IC bond pad via array design for copper wire. There is provided a semiconductor package comprising a leadframe having a pre-plated finish and a spot plating on said pre-plated finish, a semiconductor die including a bond pad on a top surface thereof, and a copper wire bonded to said spot plating and to said bond pad. Optionally, a novel corner via array design may be provided under the bond pad for improved package performance while maintaining the integrity of the copper wire bond. The semiconductor package may provide several advantages including high MSL ratings, simplified assembly cycles, avoidance of tin whisker issues, and low cost compared to conventional packages using gold wire bonds.03-14-2013
20110012240Multi-Connect Lead - This disclosure describes a multi-connect lead providing multiple connections using one external pin. In one embodiment, a lead frame for a lead-frame-based chip package includes a multi-connect lead that uses one external pin and enables multiple electrical connections to an integrated circuit die.01-20-2011
20090236703Chip package structure and the method thereof - A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces.09-24-2009
20090236702SiP SUBSTRATE - Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.09-24-2009
20100200969SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion.08-12-2010
20080290479Wafer level device package with sealing line having electroconductive pattern and method of packaging the same - Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.11-27-2008
20120001307Lead Frame and Method For Manufacturing the Same - A lead frame comprises: a base metal layer; a copper plating layer, including one of a copper layer and an alloy layer including a copper, configured to plate the based metal layer to make a surface roughness; and an upper plating layer, including at least one plating layer including at least one selected from the group of a nickel, a palladium, a gold, a silver, a nickel alloy, a palladium alloy, a gold alloy, and a silver alloy, configured to plate the copper plating layer.01-05-2012
20110284998INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE - An integrated circuit package system provides a leadframe having a short lead finger and a long lead finger, and the long lead finger and the short lead finger reside substantially within the same horizontal plane. A first die is placed in the leadframe. A second die is offset from the first die. The offset second die is attached over the first die and the long lead finger with an adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant.11-24-2011
20110284997Chip-Exposed Semiconductor Device and Its Packaging Method - A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chi on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.11-24-2011
20090091007Semiconductor Device Having Grooved Leads to Confine Solder Wicking - A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 μm deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 μm deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions.04-09-2009
20100219515LEAD FRAME - A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a coefficient of thermal expansion similar to that of inner leads. An adhesive layer is disposed between the base layer and the plurality of leads to fix the plurality of leads and adhere the base layer to the leads. At least one line electrically connects the semiconductor chip to the base layer of the lead lock. Since regions for bus bars are replaced by the lead lock and are removed, the lead frame can be miniaturized and has superior thermal stability and dimension stability.09-02-2010
20090072359STACKED SYNCHRONOUS BUCK CONVERTER - A multichip module buck converter 03-19-2009
20120098110Supporting Body for a Semiconductor Component, Semiconductor Element and Method for Production of a Supporting Body - A carrier body for a semiconductor component, in particular for an optoelectronic semiconductor component, is specified. Said carrier body has a connecting layer and a conductor layer, which are connected to one another via main areas facing one another. The connecting layer, the conductor layer or both the connecting layer and the conductor layer has/have at least one thinned region in which the layer thickness of said layer(s) is less than the maximum layer thickness of said layer(s). The connecting layer is either completely electrically conductive and electrically insulated at least from parts of the conductor layer or it is electrically insulating at least in parts. Furthermore, a semiconductor component comprising the electrical connection conductor and also a method for producing the carrier body are specified.04-26-2012
20090189259ELECTRONIC DEVICE AND METHOD OF MANUFACTURING - An electronic device and method of manufacturing. One embodiment includes attaching a first semiconductor chip to a first metallic clip. The first semiconductor chip is placed over a leadframe after the attachment of the first semiconductor chip to the first metallic clip.07-30-2009
20100078782COATING COMPOSITION AND A METHOD OF COATING - A coating composition including a compound having a first molecular group or a first combination of atoms, the first molecular group or the first combination of atoms capable of bonding to an oxidizable metal or a metal oxide, and a second molecular group or a second combination of atoms, the second molecular group or the second combination of atoms capable of interacting with a precursor of a polymer so the compound and the polymer are bound together.04-01-2010
20090146274INTEGRATED CIRCUIT PACKAGES INCLUDNG SINUOUS LEAD FRAMES - Integrated circuit packages include an integrated circuit mounting substrate having a hole that defines an inner wall of the integrated circuit mounting substrate. An integrated circuit is provided in the hole. A sinuous lead frame extends from the integrated circuit and is connected to the inner wall. The sinuous lead frame extends back and forth along a given direction, and may include a U- and/or V-shape, and round and/or jagged portions. Related packaging methods are also disclosed.06-11-2009
20090146271INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM - An integrated circuit package-in-package system is provided including mounting first integrated circuits stacked in a first offset configuration over a die-attach paddle having a first edge and a second edge, opposing the first edge; connecting the first integrated circuits and a second edge lead adjacent the second edge; mounting second integrated circuits stacked in a second offset configuration, below and to the die-attach paddle; connecting the second integrated circuits and a first edge lead adjacent to the first edge; and encapsulating the first integrated circuits, second integrated circuits, and the die-attach paddle, with the first edge lead and the second edge lead partially exposed.06-11-2009
20100084748THIN FOIL FOR USE IN PACKAGING INTEGRATED CIRCUITS - Methods for minimizing warpage of a welded foil carrier structure used in the packaging of integrated circuits are described. Portions of a metallic foil are ultrasonically welded to a carrier to form a foil carrier structure. The ultrasonic welding helps define a panel in the metallic foil that is suitable for packaging integrated circuits. Warpage of the thin foil can be limited in various ways. By way of example, an intermittent welding pattern that extends along the edges of the panel may be formed. Slots may be cut to define sections in the foil carrier structure. Materials for the metallic foil and the carrier may be selected to have similar coefficients of thermal expansion. An appropriate thickness for the metallic foil and the carrier may be selected, such that the warpage of the welded foil carrier structure is limited when the foil carrier structure is subjected to large increases in temperature. Foil carrier structures for use in the above methods are also described.04-08-2010
20110062564SEMICONDUCTOR DIE CONTAINING LATERAL EDGE SHAPES AND TEXTURES - Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described.03-17-2011
20100006991PACKAGING INTEGRATED CIRCUITS FOR HIGH STRESS ENVIRONMENTS - One aspect of the invention pertains to a semiconductor package suitable for use in high stress environments, such as ones involving high pressures, temperatures and/or corrosive substances. In this aspect, a die and leadframe are fully encapsulated in a first plastic casing. The first plastic casing is fully encapsulated in turn with a second plastic casing. The two casings have different compositions. The first plastic casing, for example, may be made of a thermoset plastic material and the second plastic casing may be made of a thermoplastic material. The first plastic casing may have recesses, indentations and/or slots suitable for securing it to the second plastic casing. In some embodiments, a corrosion resistant coating is added to the second plastic casing. Methods for forming semiconductor packages suitable for use in high stress environments are also described.01-14-2010
20090206456MODULE INCLUDING A SINTERED JOINT BONDING A SEMICONDUCTOR CHIP TO A COPPER SURFACE - A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.08-20-2009
20090206457RESIN MOLDING PART AND MANUFACTURING METHOD THEREOF - A primary molding product is formed by integrally forming a first lead frame and a second lead frame with a primary molding resin portion. In addition, in order to prevent separation of the first lead frame and the second lead frame from the primary molding resin portion, a hook-and-hold portion for preventing separation of the first lead frame from the primary molding resin portion and separation of the second lead frame from the primary molding resin portion is provided on an outer surface of each of the first lead frame and the second lead frame. Thus, a resin molding part capable of achieving suppression of increase in a thickness thereof without deformation or displacement of a lead frame and a manufacturing method thereof can be provided.08-20-2009
20100127361ENCAPSULANT INTERPOSER SYSTEM WITH INTEGRATED PASSIVE DEVICES AND MANUFACTURING METHOD THEREFOR - A method of manufacturing a semiconductor package system including: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.05-27-2010
20110198738METHOD FOR MANUFACTURING A MICROELECTRONIC PACKAGE COMPRISING AT LEAST ONE MICROELECTRONIC DEVICE - A method for manufacturing a microelectronic package (08-18-2011
20090091008Semiconductor device - A semiconductor device for programmable logic or operation processing includes a semiconductor chip; a first connecting terminal for electrically connecting the semiconductor device to a printed circuit board on which the semiconductor device is to be mounted; a second connecting terminal for electrically connecting the semiconductor device to another semiconductor device; and a packaging material for sealing the semiconductor chip, the first connecting terminal, and the second connecting terminal. Then, the first connecting terminal is formed of the lead frame, and the second connecting terminal is formed on the wiring board.04-09-2009
20110169145MANUFACTURING METHOD OF LEAD FRAME SUBSTRATE AND SEMICONDUCTOR APPARATUS - A lead frame substrate, including: a metal plate with a first surface and a second surface; a connection post formed on the first surface; wiring formed on the second surface; and a pre-molding resin layer, in which a thickness of the pre-molding resin layer is the same as a height of the connection post.07-14-2011
20080211068METHOD FOR MANUFACTURING LEADFRAME, PACKAGING METHOD FOR USING THE LEADFRAME AND SEMICONDUCTOR PACKAGE PRODUCT - A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.09-04-2008
20080211069SEMICONDUCTOR PACKAGE CONFIGURATION WITH IMPROVED LEAD PORTION ARRANGEMENT - A semiconductor device with improved reliability is provided. The semiconductor device in a QFN package configuration has a semiconductor chip mounted on a tab, leads which are alternately arranged around the tab and electrically connected to the electrodes of the semiconductor chip via bonding wires, and an encapsulating resin portion for encapsulating therein the semiconductor chip and the bonding wires. The lower exposed surfaces of the leads are exposed at the outer peripheral portion of the back surface of the encapsulating resin portion to form external terminals. The lower exposed surfaces of the leads are exposed at the portion of the back surface of the encapsulating resin portion which is located inwardly of the lower exposed surface of the leads to also form external terminals. The cut surfaces of the leads are exposed at the cut surfaces of the encapsulating resin portion, while the upper exposed surfaces of the leads are exposed from the portion of the encapsulating resin portion which is proximate to the cut surfaces thereof. Each of the upper exposed surfaces of the leads has a width smaller than the width of each of the lower exposed surfaces thereof.09-04-2008
20090273064Semiconductor device and inspection method therefor - A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for said circuit block, and a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and electrically connected to a lead frame by a bonding wire, the laterally offset bonding pad thereby functioning as a substitute wire bonding pad for the circuit block.11-05-2009
20090273063SEMICONDUCTOR DEVICE - One embodiment provides a semiconductor device including a carrier, a first chip attached to the carrier, a structured dielectric coupled to the chip and to the carrier, and a conducting element electrically connected with the chip and extending over a portion of the structured dielectric. The conducting element includes a sintered region.11-05-2009
20090294933Lead Frame and Chip Package Structure and Method for Fabricating the Same - The present invention discloses a lead frame and chip package structure, which comprises a plurality of leads including a plurality of inner leads and a plurality of outer leads; a plurality of chips arranged on a portion of the inner leads; a plurality of connecting wires electrically connecting the chips to the other inner leads; a support member arranged on the lower surface of the inner leads and having a fillister with an opening, wherein the backside of the opening faces the inner leads; and a resin encapsulant covering the leads, the chips, the connecting wires and the support member, and filling up the fillister with a portion of the outer leads and a portion of the surface of the support member being revealed. Further, the present invention also discloses a method for fabricating a lead frame and chip package structure, whereby the quality of a chip package is promoted.12-03-2009
20120193773Adhesion Promoting Composition for Metal Leadframes - A process for increasing the adhesion of a polymeric material to a metal surface, the process comprising contacting the metal surface with an adhesion promoting composition comprising: 1) an oxidizer; 2) an inorganic acid; 3) a corrosion inhibitor; and 4) an organic phosphonate; and thereafter b) bonding the polymeric material to the metal surface. The organic phosphonate aids in stabilizing the oxidizer and organic components present in the bath and prevents decomposition of the components, thereby increasing the working life of the bath, especially when used with copper alloys having a high iron content.08-02-2012
20120193772STACKED DIE PACKAGES WITH FLIP-CHIP AND WIRE BONDING DIES - The present technology discloses a stacked die package. In one embodiment, a package comprises a first die, a second die, and a leadframe. The first die is electrically coupled to the bottom surface of the leadframe through contact bump/bumps. The second die is electrically coupled to the top surface of the leadframe through wirebond/wires. The second die is mounted on the top surface of the first die.08-02-2012
20090261461SEMICONDUCTOR PACKAGE WITH LEAD INTRUSIONS - Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead fingers may have a lead intrusion disposed on the external exposed lower surface of the lead finger. The lead intrusion may have a height that is about ⅕ to about ½ the height of a lead finger, a width that is about ⅕ to about 1/2 the width of a lead finger, and a depth that is about ¼ to about ¾ the length of the externally exposed lower surface of a lead finger. The lead intrusion increases the area on the lead finger that contacts a bond material, such as solder, and therefore increase the strength of the joint between the semiconductor package and an external surface to which the lead finger is connected (i.e., a PCB). The lead intrusion allows out gassing during reflow of the bond material which may reduce voiding. The lead intrusion can also increase bond joint reliability by providing longer crack propagation length.10-22-2009
20100102422SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes depositing a mask of low melting point material on a surface of the semiconductor device; depositing a layer to be structured relative to the mask; and removing the mask of low melting point material.04-29-2010
20080283977STACKED PACKAGED INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and second packaged integrated circuit devices to one another. A method is also disclosed which includes conductively coupling a plurality of extensions on a leadframe to each of a pair of stacked packaged integrated circuit devices and cutting the leadframe to singulate the extensions from one another.11-20-2008
20080290477Semiconductor Device - A semiconductor device having a plurality of semiconductor chips mounted on a lead frame (11-27-2008
20080303122INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADED PACKAGE - An integrated circuit package system includes: providing a frame; attaching a leaded package having leads adjacent the frame wherein the leads extend towards a side opposite the frame; and applying a package encapsulant over the leaded package having the leads partially exposed opposite the frame.12-11-2008
20080308913STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A stacked semiconductor package includes a first semiconductor package, a second semiconductor package and a conductive connection member. The first semiconductor package includes a first semiconductor chip, a first lead frame having first outer leads that are electrically connected to the first semiconductor chip, and a first molding member formed on the first semiconductor chip and the first lead frame to expose the first outer leads. The second semiconductor package includes a second semiconductor chip, a second lead frame formed on the first molding member and having second outer leads that may be electrically connected to the second semiconductor chip, and a second molding member formed on the second semiconductor chip and the second lead frame to expose the second outer leads. The conductive connection member may electrically connect the first outer leads and the second outer leads to each other. Further, the conductive connection member may have a crack-blocking groove.12-18-2008
20080251897SEMICONDUCTOR DEVICE - The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved.10-16-2008
20090032916SEMICONDUCTOR PACKAGE APPARATUS - A semiconductor package apparatus and a method of fabricating the semiconductor package apparatus. The semiconductor package apparatus includes: semiconductor chips comprising active and inactive surfaces and protected by a packing portion; a substrate on which the semiconductor chips are installed; leads comprising front portions electrically coupled to the active surfaces of the semiconductor chips and rear portions extending substantially to the substrate; and bonding materials bonded between ends of the rear portions of the leads and the substrate to electrically couple the leads to the substrate. Ends of the rear portions of the leads may stand on the substrate. Thus, solder joint reliability can be improved, and a wetting characteristic of solder can be improved during surface installation. Also, semiconductor package apparatuses having similar attributes can easily be multilayered. In addition, a foot print of the semiconductor package apparatus can be reduced to enable high-density installation. Moreover, shapes of the bonding materials (solder) can be controlled to optimize bonding strength of the leads, quantity of the bonding materials, or the like.02-05-2009
20090032915TFCC (TM) & SWCC (TM) thermal flex contact carriers - Two groups of interconnection devices and methods are described. Both provide columns between electronic packages and boards or between chips and substrates or the like. In the first group, called Thermal Flex Contact Carrier (TFCC), the column elements are carved out of a flat laminated structure and then formed to suit. In the second group, the carrier, which carries the connecting elements, is made out of a soluble or removable material, which acts at the same time, as a solder mask, to prevent the solder from wicking along the stem of the elements.02-05-2009
20090014849INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE MOLDING - An integrated circuit package system is provided forming a lead from a padless lead frame, and encapsulating the lead for supporting an integrated circuit die with a first molding compound for encapsulation with a second molding compound.01-15-2009
20090014848Mixed Wire Semiconductor Lead Frame Package - One embodiment includes an encapsulated semiconductor package having a lead frame with die pad surrounded by a plurality of first and second leadfingers. A semiconductor chip including chip contact pads on its upper active surface is attached to the die pad. A plurality of first bond wires, including a first electrically conductive material, extend between the chip contact pads and the plurality of first leadfingers. A plurality of second bond wires, including a second electrically conductive material, extend between a chip contact pad and a second leadfinger. The semiconductor package further includes a plurality of electrically conducting means attached to the second leadfingers.01-15-2009
20080272470Same Size Through-Hole Via Die Stacked Package - A semiconductor package includes a substrate or leadframe structure. A plurality of interconnected dies, each incorporating a plurality of through-hole vias (THVs) disposed along peripheral surfaces of the plurality of dies, are disposed over the substrate or leadframe structure. The plurality of THVs are coupled to a plurality of bond pads through a plurality of a metal traces. A top surface of a first THV is coupled to a bottom surface of a second THV. An encapsulant is formed over a portion of the substrate or leadframe structure and the plurality of dies.11-06-2008
20090146272ELECTRONIC DEVICE - Embodiments provide an electronic device including a carrier defining a first major surface, a chip attached to the first major surface, an array of leads connected to the first major surface, and a thickness of encapsulation material disposed on the first major surface of the carrier. Each lead extends through the thickness of the encapsulation material.06-11-2009
20100270664Epoxy resin composition for encapsulating semiconductor device and semiconductor device using the same - An epoxy resin composition for encapsulating a semiconductor device, the epoxy resin composition including an epoxy resin, a curing agent, and one or more inorganic fillers, the one or more inorganic fillers including prismatic cristobalite, the prismatic cristobalite being present in the epoxy resin composition in an amount of about 1 to about 50% by weight, based on the total weight of the epoxy resin composition.10-28-2010
20080258272ETCHED LEADFRAME STRUCTURE - A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess.10-23-2008
20080258273Package Structure With Flat Bumps For Electronic Device and Method of Manufacture the Same - The invention discloses an ultra thin package structure of leadless electronic device and the packaging method, and includes lead support base adjacent to the chip support base; chip mounted on the chip support base; wires bonded between chip and lead support base; the molded body encapsulating the top surface and side surface of the chip support base, small protrusions of the chip support base and lead support base below the molded body; in the individual package, the number of the chip support base island can be one or more, the lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island.10-23-2008
20090085178INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BASE STRUCTURE DEVICE - An integrated circuit packaging system including: forming a base structure, having an opening; mounting a base structure device in the opening; attaching an integrated circuit device over the base structure device; and molding an encapsulant on the base structure, the base structure device, and the integrated circuit device.04-02-2009
20090085177INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME ARRAY - An integrated circuit package system includes providing an integrated circuit die; attaching the integrated circuit die over a lead grid having lead blocks; and connecting a die interconnect to the integrated circuit die and the lead blocks.04-02-2009
20090127679POP (Package-On-Package) device encapsulating soldered joints between externals leads - A POP (Package-On-Package) semiconductor device with encapsulating protection of soldered joints between the external leads, primarily comprises a plurality of stacked semiconductor packages and dielectric coating. Each semiconductor package includes at least a chip, a plurality of external leads of leadframe, and an encapsulant where the external leads are exposed and extended from a plurality of sides of the encapsulant. Terminals of a plurality external leads of a top semiconductor package are soldered to the soldered regions of the corresponding external leads of a bottom semiconductor package. The dielectric coating is disposed along the sides of the encapsulant of the bottom semiconductor package to connect the soldered points between the external leads and to partially or completely encapsulate the soldering materials so that the stresses between the soldered joints can be dispersed and no electrical shorts happen.05-21-2009
20090127676Back to Back Die Assembly For Semiconductor Devices - Back to back die assemblies used in semiconductor devices and methods for making such devices are described. The die assemblies are made by stacking two dies together so that the back of one die (that does not contain any active electronic components) is attached to the back of another die. At the same time, though, the dies are electrically isolated from each other. This configuration provides a device with a small package size and a small land pattern. As well, a minimum number of metal traces are used in the semiconductor devices, leading to a very low on-resistance (R05-21-2009
20090127677Multi-Terminal Package Assembly For Semiconductor Devices - Semiconductor packages that contain leads with multiple terminals are described. The leads have a side terminal that can extend between a top terminal and a bottom terminal. The multiple terminals in the leads allow the semiconductor package to be connected to more than one external substrate and give the package multiple land pattern options. The semiconductor package can contain one or more dies that are connected to a lead frame in the package without the use of a clip. The back side of the die may be externally exposed from the package to help dissipate heat.05-21-2009
20090140401System and Method for Improving Reliability of Integrated Circuit Packages - An integrated circuit package includes a die, a bump, an underbump metallization layer formed between the bump and the die, a portion of the underbump metallization layer under the bump having a first radius, and a redistribution layer formed between the underbump metallization layer and the die. The redistribution layer has a pad positioned under the underbump metallization layer. The pad has a second radius, and makes contact with the underbump metallization layer. The second radius is less than or equal to the first radius. The integrated circuit package also includes a first dielectric layer disposed between the die and the redistributing layer.06-04-2009
20090001529PACKAGE STACKING USING UNBALANCED MOLDED TSOP - A semiconductor package assembly is disclosed including a pair of stacked leadframe-based semiconductor packages. The first package is encapsulated in a mold compound so that the electrical leads emanate from the sides of the package, near a bottom surface of the package. The first package may be stacked atop the second package by aligning the exposed leads of the first package with the exposed leads of the second package and affixing the respective leads of the two packages together. The vertical offset of leads toward a bottom of the first package provides a greater overlap with leads of the second package, thus allowing a secure bonding of the leads of the respective packages.01-01-2009
20090321900SEMICONDUCTOR DEVICE - A semiconductor device has a substrate, a semiconductor element, an electrode lead, and a sealing resin portion. The substrate has a main surface on which a circuit pattern is formed. The semiconductor element has first and second surfaces, and is arranged on the substrate such that the first surface faces the main surface. The electrode lead has one end joined to the circuit pattern and the other end joined by soldering to the second surface. The other end has a plurality of portions divided from each other. The sealing resin portion seals the semiconductor element and the electrode lead. Thus, there can be provided a semiconductor device that has relieved thermal stress at a joining portion of the electrode lead, and therefore is less subject to fatigue failure.12-31-2009
20120104578Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.05-03-2012
20120104577SEMICONDUCTOR PACKAGE AND ELECTRONIC COMPONENT PACKAGE - A semiconductor package includes an IC chip including a pad array having at least four pads, the pads including a voltage input pad and a voltage output pad disposed at edges of the pad array, a driver transistor disposed between the voltage input pad and the voltage output pad to receive an input voltage from the voltage input pad and output an output voltage to the voltage output pad, disposed in contact with an outer edge of the element arrangement region; and at least four leads on which the IC chip is mounted by flip chip bonding, disposed corresponding to the pads, formed in a lead array, the leads including a voltage input lead electrically connected to the voltage input pad and a voltage output lead electrically connected to the voltage output pad, disposed at edges of the lead array.05-03-2012
20090194854SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE PACKAGE - A method of manufacturing an electronic device is provided. The method comprises providing a carrier sheet, etching the lead frame material sheet to form a recess on a first surface of the lead frame material sheet, placing an electronic chip into the recess of the carrier sheet, and thereafter, selectively etching a second surface of the lead frame material sheet, the second surface being opposite to the first surface.08-06-2009
20090102028METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE THEREFOR - A method for manufacturing a semiconductor component that includes a leadframe having a non-metallic base structure and an intermediate leadframe structure. The non-metallic base structure may be, among other things, paper, cellulose, or plastic. A layer of electrically conductive material is formed over the non-metallic base structure. A circuit element attach structure and a plurality of leadframe leads are formed from the layer of electrically conductive material. A circuit element is coupled to the circuit element attach structure and electrically coupled to the plurality of leadframe leads. The circuit element is encapsulated and at least the non-metallic base structure is removed. Alternatively, a plurality of leadframe leads may be formed on the electrically conductive layer and a circuit element is placed over the electrically conductive layer. The circuit element is electrically coupled to the plurality of leadframe leads and encapsulated. The non-metallic base structure and the electrically conductive layer are removed.04-23-2009
20090230520Leadframe package with dual lead configurations - The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend to reduce the relative capacitance of the signal connectors and thereby improve high speed performance. The fixed voltage connections incorporate configurations of fixed voltage leads and fixed voltage bonding wires that will tend to reduce the inductance of the fixed voltage connector and reduce noise on the fixed voltage connections and improve power delivery characteristics. The configurations of the associated signal and fixed voltage connections will tend to result in signal connections that include signal leads that are shorter, narrower and/or more widely separated from the active surface of the semiconductor chip than the corresponding fixed voltage leads.09-17-2009
20090230519Semiconductor Device - This application relates to a semiconductor device comprising: a carrier comprising a chip island and at least one first external contact element; only one semiconductor chip, wherein the semiconductor chip comprises a first electrode on a first surface and a second electrode on a second surface opposite to the first surface and wherein the first electrode is attached to the chip island; and a metal structure comprising a plate region attached to the second electrode and a connection region attached to the at least one first external contact element, wherein the plate region extends laterally beyond the edges of at least two sides of the second surface of the semiconductor chip.09-17-2009
20090230517INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRATION PORT - An integrated circuit package system comprising: fabricating a package base including: forming a lead frame, coupling a first integrated circuit device under the lead frame, coupling a second integrated circuit device over the first integrated circuit device, and molding an enclosure on the lead frame, the first integrated circuit device, and the second integrated circuit device for forming an integration port; and coupling a third integrated circuit device on the integration port.09-17-2009
20090212403THERMALLY ENHANCED MOLDED LEADLESS PACKAGE - A molded leadless package (MLP) semiconductor device includes a heat spreader with a single connecting projection extending from an edge of a cap of the heat spreader to a leadframe. The heat spreader can include additional projections on its edges that act as heat collectors and help to secure the spreader in the MLP. The connecting projection is attached to a lead of the leadframe so that heat gathered by the cap can be transferred through the connecting projection to the lead and to a printed circuit board to which the lead is connected. In embodiments, the heat spreader includes a central heat collector projection from the cap toward the die, preferably in the form of a solid cylinder, that enhances heat collection and transfer to the cap. The cap can include fins projecting from its top surface to facilitate radiant and convection cooling.08-27-2009
20090243055Leadframe, semiconductor packaging structure and manufacturing method thereof - A semiconductor packaging structure includes a plurality of first inner leads, a plurality of second inner leads, a plurality of first outer leads, a plurality of stacked chips, an encapsulating body, and a plurality of wires. Wherein, a first protrusion portion is protruded from each of the first inner leads and is formed a plurality of contact faces with height differences, a second protrusion portion is protruded from each of the second inner leads. Therefore, the wires connected to the stacked chips, the first protrusion portion of the first inner leads, and the second protrusion portion of the second inner leads can be shorten. And, the wire sweep and short-circuit can be prevented during molding process. In addition, the present invention also discloses a leadframe and manufacturing method for the leadframe and its semiconductor packaging structure.10-01-2009
20100264525INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADED PACKAGE AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a frame; attaching a leaded package having leads adjacent the frame wherein the leads extend towards a side opposite the frame; and applying a package encapsulant over the leaded package having the leads partially exposed opposite the frame.10-21-2010
20090243054I/O CONNECTION SCHEME FOR QFN LEADFRAME AND PACKAGE STRUCTURES - Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.10-01-2009
20090256246SEMICONDUCTOR PACKAGING TECHNIQUES - A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.10-15-2009
20090127678Stacked assembly of semiconductor packages with fastening lead-cut ends of leadframe - A stacked assembly of semiconductor packages primarily comprises a plurality of stacked semiconductor packages. Each semiconductor package includes an encapsulant, at least a chip, and a plurality of external leads of a leadframe, where the external leads are exposed and extended from a plurality of sides of the encapsulant. Each external lead of an upper semiconductor package has a U-shaped cut end when package singulation. The U-shaped cut ends are configured for locking to the soldered portion of a corresponding external lead of a lower semiconductor package where the U-shaped cut ends and the soldered portions by soldering materials. Therefore, the stacked assembly has a larger soldering area and stronger lead reliability to enhance the soldering points to against the effects of impacts, thermal shocks, and thermal cycles.05-21-2009
20110127656SEMICONDUCTOR-DEVICE MOUNTED BOARD AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor-device mounted board, connection terminals are formed on electrode pads on a semiconductor integrated circuit respectively. A first insulating layer is formed to cover the connection terminals. A plate-like medium having a rough surface is disposed on the first insulating layer. The rough surface of the plate-like medium is pressed onto the first insulating layer so that a part of each of the connection terminals is exposed. A semiconductor device is produced by removing the plate-like medium. A second insulating layer is formed to cover side surfaces of the semiconductor device. A wiring pattern is formed to cover surfaces of the first and second insulating layers, the wiring pattern being electrically connected to the exposed connection terminal parts.06-02-2011
20090315160PREFABRICATED LEAD FRAME AND BONDING METHOD USING THE SAME - A prefabricated lead frame to bond a chip and a substrate, and a bonding method using the prefabricated lead frame. The prefabricated lead frame includes an inner ring, an outer ring, and a plurality of wires, wherein inner ends and outer ends of the wires are respectively connected to the inner ring and the outer ring, and the prefabricated lead frame has a wire shape corresponding to a chip and a substrate to be bonded. The prefabricated lead frame may be manufactured in batch production to increase the manufacturing efficiency of semiconductor devices, and the prefabricated lead frame may be used instead of a general wire bonding process.12-24-2009
20090315161DIE ATTACH METHOD AND LEADFRAME STRUCTURE - In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure). The width of at least some of these tailed lead traces in a region that overlies their associated contact post is narrower than their associated contact post. Thus, these narrowed lead traces have extensions that extend beyond their associated contact posts. The extensions provide additional surface area that gives an adhesive applied to the narrowed lead trace (as for example by stamping) room to bleed (flow) along the top surface of the lead trace on both sides of the associated contact pad.12-24-2009
20100148326Thermally Enhanced Electronic Package - According to one embodiment, an electronic package includes a semiconductor die, a heat sink and a metallization layer interposed between the semiconductor die and the heat sink. The metallization layer attaches the semiconductor die to the heat sink. The metallization layer has a thickness of about 5 μm or less and a thermal conductivity of about 60 W/m·K or greater.06-17-2010
20080296745SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR CHIP AND ANTENNA - A semiconductor device comprises a lead frame, an antenna formed at a predetermined position on the lead frame, and a semiconductor chip. The semiconductor chip is mounted on an island of the lead frame through a spacer.12-04-2008
20100155913THERMALLY ENHANCED THIN SEMICONDUCTOR PACKAGE - A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package.06-24-2010
20090079043SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including a semiconductor chip, a film (first film) which is provided so as to cover an active region with a peripheral portion of the semiconductor chip being uncovered, and is made of a dielectric material having a low dielectric constant, and a package molding resin (sealing resin) provided so as to cover the semiconductor chip and the film. As a result, deterioration in contact property with the sealing resin is suppressed and a high frequency characteristic can be enhanced.03-26-2009
20090079046SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor device having a first main surface and a second main surface, a first electrode plate provided on the first main surface, a second electrode plate provided on the second main surface, and a wiring substrate provided between the semiconductor device and the first electrode plate, in which a plurality of opening portions in the side surface of a protruding portion provided on the first electrode plate are engaged respectively with a plurality of engaging portions which face the opening portions and which are provided on the inner side surface of an intrusion opening portion in the wiring substrate into which the protruding portion is intruded.03-26-2009
20100187664ELECTRICAL CONNECTIVITY FOR CIRCUIT APPLICATIONS - According to example configurations herein, a leadframe includes a connection interface. The connection interface can be configured for attaching an electrical circuit to the leadframe. The leadframe also can include a conductive path. The conductive path in the leadframe provides an electrical connection between a first electrical node of the electrical circuit and a second electrical node of the electrical circuit. Prior to making the connection between the electrical circuit and the leadframe, the first electrical node and the second electrical node can be electrically isolated from each other. Subsequent to making connection of the electrical circuit with the leadframe, the conductive path of the leadframe electrically connects the first electrical node and the second electrical node together. Accordingly, the leadframe provides connectivity between nodes of an electrical circuit in lieu of having to provide such connectivity at, for example, a metal interconnect layer of an integrated circuit device.07-29-2010
20100187663METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE THEREFOR - A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.07-29-2010
20100258920MANUFACTURING METHOD OF ADVANCED QUAD FLAT NON-LEADED PACKAGE - The manufacturing method of advanced quad flat non-leaded packages includes performing a pre-cutting process prior to the backside etching process for defining the contact terminals. The pre-cutting process ensures the isolation of individual contact terminals and improves the package reliability.10-14-2010
20100213586SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package is constituted of a semiconductor chip, a rectangular-shaped stage having the semiconductor chip mounted on the surface, a plurality of leads which are aligned in the periphery of the stage and which are electrically connected to the semiconductor chip, and a resin mold which seals the semiconductor chip, the stage, and the leads therein while externally exposing the backside of the stage on the lower surface thereof. In particular, at least one protrusion is further formed on the upper surface or the lower surface of the resin mold at a position within the outer portion of the resin mold disposed outside the sealed portion of the resin mold. The height of the outer portion of the resin mold having the protrusion is larger than the sum of the thickness of the stage and the thickness of the sealed portion of the resin mold.08-26-2010
20100123225Semiconductor Die Structures for Wafer-Level Chipscale Packaging of Power Devices, Packages and Systems for Using the Same, and Methods of Making the Same - Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.05-20-2010
20080230877SEMICONDUCTOR PACKAGE HAVING WIRE REDISTRIBUTION LAYER AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The method includes providing a semiconductor substrate on which a chip pad is formed. A wire redistribution layer connected to the chip pad is formed. An insulating layer which includes an opening exposing a portion of the wire redistribution layer is formed. A metal ink is applied within the opening to thereby form a bonding pad. The applied metal ink within the opening and the insulating layer can be cured simultaneously.09-25-2008
20080290480MICROELECTRONIC ASSEMBLY AND METHOD FOR FORMING THE SAME - A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls (11-27-2008
20090026589SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein.01-29-2009
20090115033Reduction of package height in a stacked die configuration - A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.05-07-2009
20090115032INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL CONNECTIVITY - An integrated circuit package system includes: forming a lead having a both top contact portion and a bottom contact portion; connecting an integrated circuit die and the lead; and forming a package encapsulation, having a top side and a bottom side, over the integrated circuit die. The forming the package encapsulation includes partially exposing the top contact portion at the top side, and partially exposing the bottom contact portion along the bottom side with the bottom contact portion extending beyond a nonhorizontal portion of the package encapsulation.05-07-2009
20080290478LEAD-FRAME ARRAY PACKAGE STRUCTURE AND METHOD - The present invention provides a lead-frame array package structure. The package structure includes a lead-frame, which composed of a plurality of shorter leads and a plurality of longer leads. The first surface and a second surface are composed of the shorter leads and the longer leads. The chip is fixedly connected to the first surface of the lead-frame. The metal pads are positioned on the one side of the active layer of the chip. The metal pads are electrically connected to the leads of the lead-frame via the metal leads. The chip, the metal leads, the first surface and the second surface of the lead-frame is encapsulated by encapsulated material to expose the portion of the metal of the leads. The conductive elements are electrically connected to exposed leads so as to an array arrangement is formed on the second surface of the lead-frame.11-27-2008
20090108420SEMICONDUCTOR DEVICE AND ITS FABRICATION PROCESS - A technique capable of preventing whiskers which are generated in a plating film formed on the surface of each of leads of a semiconductor device is provided. Particularly, a technique capable of preventing generation of whiskers in a plating film containing tin as a primary material and not containing lead is provided. The plating film formed on the surface of the lead is formed so that a particular plane orientation among plane orientations of tin constituting the plating film is parallel to the surface of the lead. Specifically, the plating film is formed so that the (001) plane of tin is parallel to the surface of the lead. Thus, the coefficient of thermal expansion of tin constituting the plating film can be made to be lower than a coefficient of thermal expansion of the copper constituting the lead.04-30-2009
20090108419LEADFRAME FOR LEADLESS PACKAGE - A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, a plurality of connection portions, a plurality of openings, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of slots are disposed around each of the package units. The plurality of connection portions connect the plurality of package areas. The plurality of openings are disposed on the plurality of connection portions, and are aligned with some of the plurality of slots. The tape (film) fixes the plurality of package areas, the plurality of connection portions, the plurality of die pads, and the plurality of leads in place.04-30-2009
20120241926INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEVELING STANDOFF AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an integrated circuit adjacent the lead; molding an encapsulation encapsulating the lead and the integrated circuit; and forming a leveling standoff protruded from the same surface of the encapsulation as the lead with the integrated circuit between the lead and the leveling standoff electrically isolated from the lead and the integrated circuit.09-27-2012
20120241927INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a substrate having a redistribution line thereon; mounting an integrated circuit to the substrate; and molding a transparent encapsulation over the substrate covering the integrated circuit and the redistribution line and the integrated circuit seen through the transparent encapsulation.09-27-2012
20120241925INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacturing of an integrated circuit packaging system includes: providing a base substrate; mounting a first die over the base substrate; mounting a second die over the first die; attaching an interposer substrate over the first die with an attachment adhesive therebetween, the interposer substrate having a central cavity and the second die within the central cavity; attaching a lateral interconnect to a second active side away from the first die of the second die and to the interposer substrate; and encapsulating the first die and the second die.09-27-2012
20090256245Stacked Micro-Module Packages, Systems Using the Same, and Methods of Making the Same - Semiconductor die packages, methods of making said packages, and systems using said packages are disclosed. An exemplary package comprising at least one semiconductor die disposed on one surface of a leadframe and electrically coupled to at least one conductive region of the leadframe, and at least one passive electrical component disposed on the other surface of a leadframe and electrically coupled to at least one conductive region of the leadframe.10-15-2009
20120133034LEAD FRAME FOR ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME - In a lead frame for an electronic component according to the present invention, a metal plate 3 is extended by a punch 5 into a hole 4 formed on a metal plate 2 and the two metal plates are connected on the inner surface of the hole 4, thereby improving a bonding strength while keeping the small size and thickness of the lead frame with a simple method.05-31-2012
20100133668Semiconductor device and manufacturing method thereof - The present invention relates to a semiconductor device, and more particularly to a manufacturing method for said semiconductor device. The semiconductor device comprises a die that connects with a substrate or a lead frame via an adhesion layer, a metal layer, and/or a back metal layer. Furthermore, the adhesion layer can be made of aluminum, and the die can connect with the substrate or the lead frame by ultrasonic bonding technology, which can avoid heat damaging the die during the manufacturing process.06-03-2010
20100133667POWER SEMICONDUCTOR MODULE - A wiring process between the provided power semiconductor module and the external circuit is simple. In the power semiconductor module, a power semiconductor element and a cylindrical conductor are joined to one surface of a lead frame. An opening of the cylindrical conductor is exposed at a surface of transfer molding resin. Sealing with the transfer molding resin is performed such that terminal portions of the lead frame protrude from peripheral side portions of the transfer molding resin. The cylindrical conductor is conductive with a control circuit. The terminal portions of the lead frame are each conductive with a main circuit.06-03-2010
20110241187LEAD FRAME WITH RECESSED DIE BOND AREA - A lead frame having a recessed die bond area. The lead frame has top and bottom surfaces and a first lead frame thickness defined as the distance between the top and bottom surfaces. The lead frame has a die bond area surface located within a reduced die bond area. A second thickness is defined as the distance between the die bond area surface and the bottom surface. The second lead frame thickness is less than the first lead frame thickness such that a semiconductor die disposed and attached to the die bond area surface has a reduced overall package thickness. A side wall formed between the die bond area surface and the top surface contains the adhesive material used to attach the die, which reduces adhesive bleeding and prevents wire bonding contamination.10-06-2011
20110018110ELECTRONIC DEVICE, METHOD OF PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE - A semiconductor device includes n01-27-2011
20090065910SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - While a semiconductor device is provided with a plurality of element electrodes 03-12-2009
20090065912Semiconductor Package and Method of Assembling a Semiconductor Package - A semiconductor package includes a semiconductor component including a circuit carrier with a plurality of inner contact pads, a semiconductor chip, and a plurality of electrical connections. An adhesion promotion layer is disposed on at least areas of the semiconductor component and a plastic encapsulation material encapsulates at least the semiconductor chip, the plurality of electrical connections and the plurality of the inner contact pads. Surface regions of the semiconductor component are selectively activated.03-12-2009
20110024883SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND LEAD FRAME - To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part.02-03-2011
20090079045Package structure and manufacturing method thereof - A quad-flat non-leaded (QFN) multichip package and a multichip package are provided. The QFN multichip package includes a lead frame, a first chip, a second chip and a molding compound. The lead frame has a plurality of first leads and second leads alternately arranged with each other. Each first lead includes a first connection portion and a first contact portion. Each second lead includes a second connection portion, a bending part and a second contact portion. The bending part is bent upward such that an interval is formed between the second contact portion and the first contact portion. The first chip is disposed between the first leads and the second leads. The second chip is disposed above the first chip. The molding compound encloses the first chip, the second chip, the first leads and the second leads, and further exposes the lower surfaces of the first and the second leads.03-26-2009
20090079044SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a lead frame, at least one chip, and an encapsulation. The lead frame has a plurality of leads, and each of the leads includes at least one first conductive part, at least one second conductive part, and at least one third conductive part. The first conductive part is not electrically connected to the second conductive part, and the second conductive part is electrically connected to the third conductive part. The chip is electrically connected to the first conductive part. The encapsulation encapsulates the chip and at least a portion of the lead frame, and forms a first surface and a second surface opposite to the first surface. The first conductive part and the third conductive part are exposed from the first surface, and the second conductive part is exposed from the second surface.03-26-2009
20110084369DEVICE INCLUDING A SEMICONDUCTOR CHIP AND A CARRIER AND FABRICATION METHOD - A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier.04-14-2011
20110210432SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes: a lead group including a plurality of leads; a plurality of semiconductor memory chips stacked in a step shape on the lead group; and a resin mold section that seals the semiconductor memory chips. One end of a third lead and the other end of a second lead is connected by a metal wire for relay crossing over a first lead section included in the lead group. The metal wire for relay is provided in a space between the semiconductor memory chips stacked in the step shape and the lead group.09-01-2011
20090309198INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes a leadframe with leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to the down set inner leads. Depositing an encapsulating material to prevent exposure of the down set inner leads.12-17-2009
20100032816Electronic Device and Method of Manufacturing Same - This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the insulating foil.02-11-2010
20090020857SYSTEM AND METHOD FOR ROUTING SUPPLY VOLTAGES OR OTHER SIGNALS BETWEEN SIDE-BY-SIDE DIE AND A LEAD FRAME FOR SYSTEM IN A PACKAGE (SIP) DEVICES - An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame. The integrated circuit further includes a redistribution layer formed on the first die to couple selected bond fingers of the lead frame to selected bonding pads of the first and second die. The selected bond fingers may correspond to bond fingers that receive a first supply voltage or the first supply voltage and a second supply voltage.01-22-2009
20110068443Thermally Improved Semiconductor QFN/SON Package - A semiconductor device without cantilevered leads uses conductive wires (03-24-2011
20110068442RESIN-SEALED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a resin-sealed semiconductor device, an inner lead including a bend portion formed by lifting has a protruding shape located on one side and an inclined vertical surface shape located on the other side (inside) in an external connection terminal direction. A cutaway portion is provided along the bend portion and an external connection terminal. A height of an upper surface portion of the inner lead is higher than a height of an upper surface of a semiconductor element. The inner lead is provided in a substantially central portion of a die pad so that the inclined vertical surface shape is parallel to a side of a die pad which includes a thin portion located in a side surface portion and an exposure portion located on a bottom surface.03-24-2011
20110037152DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing an integrated circuit; mounting a lead on the periphery of the integrated circuit; connecting the integrated circuit to the lead with an interconnect; and forming a conformable material by pressing the conformable material on the integrated circuit, the lead, and the interconnect.02-17-2011
20090091006Dual Capillary IC Wirebonding - The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual capillary bond head. The separate wires are preferably non-identical, for example, being of different gauges and/or material composition. According to a preferred embodiment of the invention, dual capillary bond head apparatus includes a rotatable ultrasonic horn with a pair of capillaries for selectably dispensing separate strands of bond wire and for forming bonds on bond targets. According to another aspect of the invention, a method is provided for dual capillary IC wirebonding including steps for using two dual capillary bond heads for contemporaneously attaching non-identical bond wires to selected bond targets on one or more IC package assemblies.04-09-2009
20090108418Non-leaded semiconductor package structure - A non-leaded semiconductor package structure is proposed, in which the structure of a lead frame is improved to let the lower surface of a die paddle of the lead frame be used to carry a die and the upper surface thereof be exposed out of the package structure. Moreover, a plurality of leads of the lead frame is located at the periphery of the lower surface of the die paddle. Each lead has an inner lead and an outer lead, and the outer lead is exposed out of the package structure. The package structure thus formed has a good heat-radiating effect and a reduced chance of leakage current.04-30-2009
20100244209CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are: a circuit device demonstrating an improved connection reliability while being mounted; and a method for manufacturing the same. The circuit device of the present invention includes: an island; leads arranged around the island, each lead having a lower surface and a side surface exposed to the outside; and a semiconductor element mounted on the island and electrically connected to the leads through thin metal wires. Furthermore, the exposed end portion of the lead is formed to spread toward the outside. By forming the lead in this manner, the area where the lead comes into contact with a brazing filler material is increased, thus improving the connection strength therebetween.09-30-2010
20080251898Semiconductor device - A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.10-16-2008
20120032314PACKAGE-ON-PACKAGE WITH FAN-OUT WLCSP - A package-on-package includes a package carrier; a semiconductor die assembled face-down to a chip side of the package carrier; a rewiring laminate structure between the semiconductor die and the package carrier; a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and an IC package mounted on the package carrier. The IC package and the semiconductor die are at least partially overlapped.02-09-2012
20080203546QUAD FLAT NO-LEAD CHIP CARRIER WITH STAND-OFF - A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved.08-28-2008
20120267770DEVICE AND METHOD INCLUDING A SOLDERING PROCESS - A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate.10-25-2012
20100320578PACKAGED IC DEVICE COMPRISING AN EMBEDDED FLEX CIRCUIT, AND METHODS OF MAKING THE SAME - A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.12-23-2010
20110062565METHOD FOR MANUFACTURING A MICROELECTRONIC PACKAGE COMPRISING AT LEAST ONE MICROELECTRONIC DEVICE - A method for manufacturing a microelectronic package (03-17-2011
20110133318SiP SUBSTRATE - Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace.06-09-2011
20110169146CONTACTLESS COMMUNICATION MEDIUM - Even when a mold part of an IC module is exposed from an opening provided in a substrate of an inlay, occurrence of malfunction, communication disorders or the like of the IC module due to the influence of an external impact or the like is prevented. By combining a sealing member including an insulating layer and an adhesive layer in a stacked manner to a shape covering a mold part of the IC module, occurrence of malfunction, communication disorders or the like of the IC module is prevented even if there is an influence of an external impact or the like. Meanwhile, by providing a sealing member, concentration of stress on the mold part in a line pressure test is alleviated by limiting the size of the sealing member, and also occurrence of cracks in the mold part can be prevented.07-14-2011
20110169144DIE PACKAGE INCLUDING MULTIPLE DIES AND LEAD ORIENTATION - A semiconductor die package and method of making the package. The package may have four semiconductor dies with one or more internally connected switch nodes, and may form a dual output or phase synchronous buck converter. The package may have control leads at opposite sides of the package from each other. Furthermore, the package may contain high side semiconductor dies that are oriented perpendicular to low side semiconductor dies.07-14-2011
20120146199SUBSTRATE FOR INTEGRATED CIRCUIT PACKAGE WITH SELECTIVE EXPOSURE OF BONDING COMPOUND AND METHOD OF MAKING THEREOF - A substrate for integrated circuit package is disclosed. The substrate comprises an electrically conductive leadframe having a first side and an opposing second side. The substrate has a first bonding compound disposed in a first recessed portion of the first side and a second bonding compound disposed in at least a portion of a second recessed portion of the leadframe, selectively exposing a selected area of the leadframe on the second side. In an exemplary embodiment, the second bonding compound is a photolithographic material. A method of manufacturing a substrate for integrated circuit package is also disclosed.06-14-2012
20110095405LEAD FRAME AND INTERMEDIATE PRODUCT OF SEMICONDUCTOR DEVICE - In a lead frame used for manufacturing a semiconductor device by forming a circuit pattern group including unit lead frames having plural upper side terminal parts in the periphery of a semiconductor element mounting region in one line or plural lines and an outer frame surrounding the circuit pattern group in a state of having a gap in a lead frame material and then mounting a semiconductor element every the unit lead frame and carrying out necessary wiring and enclosing the entire surface of the circuit pattern group in which the semiconductor element is mounted and a part of the outer frame with a resin from an upper surface side and further etching from a lower surface side and forming lower side terminal parts joined to the upper side terminal parts of the circuit pattern group, the circuit pattern group and the outer frame are had and the inner edge of the outer frame is formed in an uneven portion in plan view and bonding between the resin and the outer frame is enhanced.04-28-2011
20110215452SEMICONDUCTOR PACKAGE, SUBSTRATE, ELECTRONIC COMPONENT, AND METHOD OF MOUNTING SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor device and a substrate over which the semiconductor device is mounted, wherein the substrate includes: an internal ground electrode, formed in the one side of the substrate, which is connected to the semiconductor device; two external ground electrodes, located at the opposite side of the substrate opposite to the one side of the substrate, which are electrically connected to the internal ground electrode; at least one sub-ground electrode, located between the two external ground electrodes, when seen in a plan view, and located at the opposite side of the substrate, which is electrically connected to the internal ground electrode; an internal input electrode, formed in the one side of the substrate, which is connected to the semiconductor device; and an internal output electrode, formed in the one of the substrate, which is connected to the semiconductor device.09-08-2011
20090166820TSOP LEADFRAME STRIP OF MULTIPLY ENCAPSULATED PACKAGES - A method of fabricating a semiconductor leadframe package from a strip including multiply encapsulated leadframe packages, and a leadframe package formed thereby are disclosed. An entire row or column of leadframes gets encapsulated together. Encapsulating an entire row or column reduces the keep-out area between adjacent leadframe packages, which allows the internal leads of each leadframe and the semiconductor die coupled thereto to be lengthened.07-02-2009
20090174042RADIO FREQUENCY OVER-MOLDED LEADFRAME PACKAGE - An over-molded leadframe (e.g., a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300 GHz and a method of making the over-molded leadframe package are disclosed. The over-molded leadframe package includes a capacitance lead configured to substantially reduce and/or offset the inductance created by one or more wirebonds used to connect an integrated circuit (IC) chip on the package to an input/output (I/O) lead. The IC chip is connected to the capacitance lead via one or more wirebonds, and the capacitance lead is then connected to the I/O lead via at least a second wirebond. Thus, inductance created by the one or more wirebonds on the package is substantially reduced and/or offset by the capacitance lead prior to a signal being output by the package and/or received by the IC chip.07-09-2009
20090230518SEMICONDUCTOR DIE PACKAGE INCLUDING IC DRIVER AND BRIDGE - A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe.09-17-2009
20090057850Surface Mountable Semiconductor Package with Solder Bonding Features - A packaged circuit element such as an LED and a method for making the same are disclosed. The packaged circuit element includes a lead frame, a molded body, and a die containing the circuit element. The lead frame has first and second leads, each lead having first and second portions. The molded body surrounds the first portion of each lead, and the die is connected electrically to the first and second leads on the first portions of the first and second leads. The second portion of each of the first and second leads is substantially parallel to opposing side surfaces of the body and include a feature that inhibits molten solder from wetting a portion of the second section of each lead between the feature and the first portion of that lead while allowing the molten solder to wet the remaining surfaces of the second portions.03-05-2009
20110304031SEMICONDUCTOR DEVICE EQUIPPED WITH BONDING WIRES AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE EQUIPPED WITH BONDING WIRES - Disclosed is a semiconductor device including a printed-circuit board which includes a plurality of first electrodes, a plurality of second electrodes and a semiconductor chip on which a plurality of first connection pads are aligned in a first line being disposed along an outer circumference side of a top surface and a plurality of second connection pads are aligned in a second line being disposed inside of and apart from the first line, when the semiconductor chip is seen from above, and any of the plurality of first connection pads are used for a power voltage terminal and a system reset terminal of the semiconductor device.12-15-2011
20090315159LEADFRAMES HAVING BOTH ENHANCED-ADHESION AND SMOOTH SURFACES AND METHODS TO FORM THE SAME - Example leadframes having both rough surfaces to enhance adhesion to molding compounds and selectively smoothed surfaces to enhance bonding wire performance, and methods to form the same are disclosed. A disclosed example packaged integrated circuit chip includes a bond wire, a leadframe having a die pad coupled to a carrier rail, and an inner lead coupled to an outer lead via a dam bar, the inner lead having a first portion having a rough surface and a second portion having a smoothed surface, a first end of the bond wire attached to the second portion of the inner lead, an integrated circuit attached to the die pad, a second end of the bond wire attached to a pad disposed on the integrated circuit, and a molding compound to encapsulate the inner lead, the integrated circuit and the bond wire.12-24-2009
20110062563NON-VOLATILE MEMORY WITH REDUCED MOBILE ION DIFFUSION - Mobile ion diffusion causes a shift in the threshold voltage of non-volatile storage elements in a memory chip, such as during an assembly process of the memory chip. To reduce or avoid such shifts, a coating can be applied to a printed circuit board substrate or a leader frame to which the memory chip is surface mounted. An acrylic resin coating having a thickness of about 10 μm may be used. A memory chip is attached to the coating using an adhesive film. Stacked chips may be used as well. Another approach provides metal barrier traces over copper traces of the printed circuit board, within a solder mask layer. The metal barrier traces are fabricated in the same pattern as the copper traces but are wider so that they at least partially envelop and surround the copper traces. Corresponding apparatuses and fabrication processes are provided.03-17-2011
20120153444SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.06-21-2012
20110316130THIN SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a thin semiconductor package includes providing a lead frame with a removable substrate that has an attaching surface attached to a first surface of the lead frame. The lead frame is formed from an electrically conductive sheet and has leads that extend inwardly from a lead frame boundary towards a central region of the lead frame. A semiconductor die is mounted on the removable substrate at the central region. The semiconductor die has a connection pad surface with die pads on it, and the connection pad surface is attached to the attaching surface of the removable substrate. The lead frame and die are encapsulated with a first encapsulant so that the lead frame is sandwiched between the first encapsulant and the removable substrate. The removable substrate is removed from the lead frame to expose the first surface of the lead frame and then the die pads are electrically connected to respective ones of the leads. The die and lead frame then are encapsulated with a second encapsulant so that the lead frame and die are sandwiched between the first and second encapsulants. Part of the first encapsulant is then removed to reduce the thickness of the package and expose the leads.12-29-2011
20110031596NICKEL-TITANUM SOLDERING LAYERS IN SEMICONDUCTOR DEVICES - Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds or alloys and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit, a contact layer contacting the substrate, a TiNi-containing soldering layer on the contact layer, an oxidation prevention layer on the soldering layer, a solder bump on the soldering layer, and a lead frame or PCB attached to the solder bump. The combination of the Ti and Ni materials in the soldering layer exhibits many features not found in the Ti and Ni materials alone, such as reduced wafer warpage, increased ductility for improved elasticity, decreased consumption of the Ni in the soldering layer, and decreased manufacturing costs. Other embodiments are described.02-10-2011
20120001306SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.01-05-2012
20110049686SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package is provided. The semiconductor package includes a carrier, a die, a metal sheet and a molding compound. The die is disposed on the carrier. The metal sheet has a first portion and a second portion, wherein a receiving space is defined by the first portion and the second portion, and the second portion is electrically connected to the carrier. The molding compound covers the die and the receiving space is filled by at least part of the molding compound.03-03-2011
20120018859SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires.01-26-2012
20120025357LEADFRAME FOR IC PACKAGE AND METHOD OF MANUFACTURE - A leadframe for use in an integrated circuit (IC) package comprising a metal strip partially etched on a first side. In some embodiments, the leadframe may be selectively plated on the first side and/or on a second side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of electrical contacts to be electrically coupled to the leadframe and the IC chip.02-02-2012
20120061809METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a substrate for a semiconductor element, the manufacturing method including the steps of: providing a first photosensitive resin layer at a first surface of a metal plate; providing a second photosensitive resin layer at a second surface of the metal plate different from the first surface; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring post on the second surface of the metal plate; forming the connection post by performing an etching on the first surface of the metal plate from a first surface side to a midway of the metal plate; applying a premold resin in liquid form to the first surface of the metal plate which underwent the etching on the first surface; forming a premold resin layer by solidifying the premold resin in liquid form being applied; and forming a wiring pattern by performing an etching on the second surface of the metal plate from a second surface side.03-15-2012
20120061808SEMICONDUCTOR PACKAGES HAVING INCREASED INPUT/OUTPUT CAPACITY AND RELATED METHODS - A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.03-15-2012
20100096734THERMALLY IMPROVED SEMICONDUCTOR QFN/SON PACKAGE - A semiconductor device without cantilevered leads uses conductive wires (04-22-2010
20090134501DEVICE AND METHOD INCLUDING A SOLDERING PROCESS - A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate.05-28-2009
20090134502LEADFRAME BASED FLASH MEMORY CARDS - A leadframe design for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts.05-28-2009
20110089544PACKAGE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE - A package for mounting a semiconductor chip is provided. The package includes a frame member including an aperture, a first lead including a portion connectable to the semiconductor chip and a portion projecting outside from an outer sidewall of the frame member, and a second lead including a portion connectable to the semiconductor chip and a portion projecting inside the aperture from an inner sidewall of the frame member.04-21-2011
20100289127SEMICONDUCTOR DEVICE - A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.11-18-2010
20120126383METHOD FOR SEMICONDUCTOR LEADFRAMES IN LOW VOLUME AND RAPID TURNAROUND - An apparatus comprising a metallic leadframe including a pad and a plurality of leads. Each having a first and a parallel second surface and sidewalls normal to the surfaces. The pad and each lead having a core of a first metal and layers of a second metal different from the first metal on each surface. The first metal exposed at the sidewalls and at portions of the first surface of the pad. A semiconductor chip is assembled on the leadframe. Portions of the assembled chip and the leadframe are packaged in a polymeric encapsulation compound.05-24-2012
20110001223LEADFRAME, LEADFRAME TYPE PACKAGE AND LEAD LANE - A leadframe for a leadframe type package includes a chip base, and leads constituting lead lanes. One lead lane includes a pair of first differential signal leads, a pair of second differential signal leads, a pair of third differential signal leads between which and the pair of first differential signal leads is arranged the pair of second differential signal leads, a first power lead arranged between the pair of first and second differential signal leads, a second power lead arranged between the pair of second and third differential signal leads, and a third power lead between which and the second power lead is the pair of third differential signal leads. A voltage provided by the first power lead is less than a voltage provided by the second power lead, and the voltage provided by the second power lead is substantially equal to a voltage provided by the third power lead.01-06-2011
20110001224LEAD FRAME ROUTED CHIP PADS FOR SEMICONDUCTOR PACKAGES - A redistributed lead frame for use in a molded plastic semiconductor package is formed from an electrically conductive substrate by a sequential metal removal process. The process includes patterning a first side of the substrate to form an array of lands separated by channels; disposing a first molding compound within those channels; patterning a second side of the substrate to form an array of chip attach sites and routing circuits electrically interconnecting the array of lands and the array of chip attach sites; directly electrically interconnecting input/output pads on a semiconductor device to the chip attach sites; and encapsulating the semiconductor device, the array of chip attach sites and the routing circuits with a second molding compound. This process is particularly suited for the manufacture of chip scale packages and very thin packages.01-06-2011
20120161301SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.06-28-2012
20120133033INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-ROW LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base structure having an intermediate lead with an intermediate concave side and an intermediate convex side, a peripheral lead with a peripheral concave side and a peripheral convex side, and a paddle with a paddle concave side and a paddle convex side; applying an inner multi-layer finish directly on the intermediate concave side, the peripheral concave side, and the paddle concave side; applying an outer multi-layer finish directly on the intermediate convex side, the peripheral convex side, and the paddle convex side; mounting an integrated circuit device over the inner multi-layer finish; attaching an interconnect directly to the inner multi-layer finish on the peripheral concave side and directly to integrated circuit device; and applying an encapsulation over the integrated circuit device, the interconnect, and the base structure, with the outer multi-layer finish exposed from the encapsulation.05-31-2012
20110180913METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP - Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer. A corresponding bump may be disposed on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. Other embodiments are also described and claimed.07-28-2011
20090057851METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device including: arranging multiple dies planarly between a first lead frame plate and a second lead frame plate, which face each other, to connect the multiple semiconductor chips to each of the first lead frame plate and the second lead frame plate; filling a resin between the first lead frame plate and the second lead frame plate to seal the multiple dies; performing a first dicing on a laminated body including the first lead frame plate, the resin, and the second lead frame plate, between the adjacent dies, to separate at least the first lead frame plate by cutting; applying plating to the laminated body with at least the first lead frame plate being separated by cutting; and performing a second dicing on a remainder of the laminated body between the adjacent dies, to separate the laminated body into individual semiconductor devices.03-05-2009
20120168917STACK TYPE SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package.07-05-2012
20100052121SEMICONDUCTOR SYSTEM-IN-A-PACKAGE CONTAINING MICRO-LAYERED LEAD FRAME - Semiconductor packages that contain a system-in-a-package and methods for making such packages are described. The semiconductor packages contain a first semiconductor die resting on a middle of a land pad array, a second die disposed over the first die and resting on routing leads that are connected to the land pad array, a third die resting on the backside of the second die and connected to the land pad array by wire bonds, and a passive device and/or a discrete device resting on device pads. The packages also contain thermal pads which operate as a heat sink. The land pad array is formed from etching the leadframe. The semiconductor packages have a full land pad array with a thin package size while having a system-in-a-package design. Other embodiments are also described.03-04-2010
20100052120SEMICONDUCTOR DEVICE HAVING A SUSPENDED ISOLATING INTERCONNECT - A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.03-04-2010
20100052119Molded Ultra Thin Semiconductor Die Packages, Systems Using the Same, and Methods of Making the Same - Disclosed are molded ultra-thin semiconductor die packages, systems that incorporate such packages, and methods of making such packages. An exemplary package comprises a leadframe having an aperture formed between the leadframe's first and second surfaces, and a plurality of leads disposed adjacent to the aperture. The package further comprises a semiconductor disposed in the aperture of the leadframe with its top surface substantially flush with the leadframe's first surface, and at least one gap between at least one side surface of the semiconductor die and at least one lead of the leadframe. A body of electrically insulating material is disposed in the at least one gap. A plurality of conductive members interconnect leads of the leadframe with conductive regions on the die's top surface, with at least one conductive member having a portion disposed over at least a portion of the body of insulating material.03-04-2010
20090096069Cof board - A COF board includes an insulating layer, and a terminal portion formed on the insulating layer. The terminal portion includes a first lead extending in a longitudinal direction, and a second lead extending in the longitudinal direction, and having a smaller length in the longitudinal direction than a length of the first lead in the longitudinal direction. The first leads are arranged in spaced-apart relation in a direction perpendicular to the longitudinal direction. The second leads are arranged in the direction perpendicular to the longitudinal direction to be interposed between the mutually adjacent first leads such that, when the mutually adjacent first leads are projected in an adjacent direction thereof, overlap portions where the second leads overlap with the first leads and non-overlap portions where the second leads do not overlap with the first leads are formed. Dummy leads are provided at the non-overlap portions.04-16-2009
20090096068System and Method for Stabilizing an Amplifier - In one embodiment of the present invention, a semiconductor circuit including an amplifier disposed on a semiconductor substrate is disclosed. A first bond wire coupled to an input of the amplifier, a second bond wire coupled to an output of the amplifier, and a third bond wire coupled in series with the first bond wire. A third bond wire is disposed on the semiconductor substrate so that a mutual inductance between the second bond wire and the third bond wire at least partially cancels a mutual inductance between the first bond wire and the second bond wire.04-16-2009
20100270663Power Lead-on-Chip Ball Grid Array Package - A packaging assembly (10-28-2010
20120181675SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.07-19-2012
20120181674Stacked Half-Bridge Package with a Common Conductive Leadframe - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.07-19-2012
20110121439SEMICONDUCTOR DEVICE WITH PROTRUDING COMPONENT PORTION AND METHOD OF PACKAGING - A semiconductor package device having a protruding component portion and a method of packaging the semiconductor device is disclosed. The semiconductor device has a component, such as a leadframe, and a packaging mold body. The packaging mold body is formed around a portion of the component and a recess is formed in the packaging mold body adjacent the protruding portion of the component to prevent the protruding portion of the component from damaging other adjacent and abutting semiconductor devices.05-26-2011
20120319255Thermal Enhanced High Density Flip Chip Package - Systems and methods according to embodiments of the invention enable flip chip packaging using high density routing while minimizing the thickness and layer count of the flip chip package. By using a photoresist layer to create very fine traces on a metallic base layer, embodiments of the present invention combine advantages of leadframe substrates and laminate substrates by supporting high-density routing while minimizing layer count and manufacturing cost. Additionally, the use of raised metallic pads in a routing layer enables embodiments of the present invention to include highly compact traces that pass over IC die bond pad connection sites without directly coupling to these bond IC die bond pad connection sites. Further, embodiments of the present invention can support multiple thin routing layers without the need for organic (e.g., laminate) material separating these routing layers.12-20-2012
20120261805THROUGH PACKAGE VIA STRUCTURES IN PANEL-BASED SILICON SUBSTRATES AND METHODS OF MAKING THE SAME - The various embodiments of the present invention provide a low cost, low electrical loss, and low stress panel-based silicon interposer with TPVs. The interposer of the present invention has a thickness of about 100 microns to 200 microns and such thickness is achieved without utilizing a carrier and further wherein no grinding, bonding, or debonding methods are utilized, therefore distinguishing the interposer of the present invention from prior art embodiments.10-18-2012
20080290476METHOD FOR MAKING SEMICONDUCTOR CHIPS HAVING COATED PORTIONS - A method for making semiconductor chips having coated portions can include mounting the chips in lead frames, stacking the lead frames in an orientation in which a portion of one lead frame masks a portion of a chip mounted on another lead frame but leaves another portion of the chip mounted on the other lead frame exposed to receive a coating, and depositing a coating on the stacked lead frames using, for example, an evaporative coating machine. In this manner, the coating is deposited on exposed portions of chips, such as its edges, and is not deposited on masked portions of chips, such as bond pads.11-27-2008
20120319257SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor storage device includes an organic board provided with external connection terminals on one surface and formed as an individual piece into a plane shape substantially identical to that of an area where the external connection terminals are provided, a lead frame having a mounting area positioned relative to the organic board, and a semiconductor memory chip bonded to the mounting area.12-20-2012
20120319256SEMICONDUCTOR PACKAGE FOR MEMS DEVICE AND METHOD OF MANUFACTURING SAME - In some embodiments, a semiconductor package can include: (a) a base having a cavity; (b) an interposer coupled to the base and at least partially over the cavity such that the interposer and the base form a back chamber, the interposer has a first opening into the back chamber; (c) a micro-electro-mechanical system device located over the interposer at the first opening; and (d) a lid coupled to the base. Other embodiments also are disclosed.12-20-2012
20110215451Stacked Semiconductor Packages - Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.09-08-2011
20110227204SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. An encapsulating body encapsulates the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location. At least one of the second conducting element, third conducting element, and fourth conducting element extend over the semiconductor chip and the encapsulating body.09-22-2011
20100230790Semiconductor Carrier for Multi-Chip Packaging - A power semiconductor product includes a carrier attached to a leadframe. An insulating layer is formed on the carrier and two or more conductive plates are patterned on the insulating layer. A control IC is attached to one of these conductive plates and a power transistor is attached to the other. Bond wires connect the first conductive plate to a pin on the leadframe. Additional bond wires attach the control IC to pins on the leadframe and form connections between the control IC and the power transistor.09-16-2010
20120286405SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes a substrate, a semiconductor element which is mounted on the substrate, a protecting film which covers at least a part of the semiconductor element, and an encapsulation resin which encapsulates the semiconductor element and the protecting film, wherein between the protecting film and the encapsulation resin, there is at least one gap in which the protecting film does not stick to the encapsulation resin. According to the above mentioned configuration, it is possible to provide a semiconductor device having a superior stress-relief performance.11-15-2012
20120286406SEMICONDUCTOR DEVICE WITH STAGGERED LEADS - A process for assembling a semiconductor device includes providing a lead frame having a native plane and a plurality of leads having a native lead pitch. The process includes trimming and forming a first subset of the plurality of leads to provide a first row of leads. The process includes trimming and forming a second subset of the plurality of leads to provide a second row of leads. At least one subset of leads is formed with an obtuse angle relative to the native plane such that lead pitch associated with the first or second subset of leads is greater than the native lead pitch.11-15-2012
20130009292SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first frame, a semiconductor element fixed to the first frame, a second frame, a third frame and a resin package. The second frame faces the first frame and is away from the first frame, the second frame being electrically connected to the semiconductor element via a metal wire. The resin package covers the semiconductor element, the first frame, and the second frame. The first frame and the second frame are exposed in one major surface of the resin package. The third frame juxtaposed to one of the first frame and the second frame, the third frame being continuously exposed from the major surface of the resin package to a side surface in contact with the major surface.01-10-2013
20130009290POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a power module package including: a first substrate; a second substrate having a pad for connection to the first substrate formed on one side or both sides of one surface thereof and having external connection terminals for connection to the outside formed on the other surface thereof; and a lead frame having one end bonded to the first substrate and the other end bonded to the pad of the second substrate to thereby vertically connect the first and second substrates to each other.01-10-2013
20130009293PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME - A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved.01-10-2013
20130009291POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: a base substrate having grooves formed between a plurality of semiconductor device mounting areas; semiconductor devices mounted on the semiconductor device mounting areas of the base substrate; and a molding formed on the base substrate and in inner portions of the grooves.01-10-2013
20080246128Bent lead transistor - A metal backing tab supports the semiconductor device and has an extending portion extending from an edge. A top leg, a middle leg and a bottom leg are all coupled to the semiconductor device and each has a lead terminal portion extending beyond the boundary of said molded housing. The top leg has a first top leg section that protrudes directly away from the molded housing, a second top leg section that bends toward a direction of a face of the molded housing, and a third top leg section bending downward. The middle leg has a first middle leg section connected to the package that protrudes away from the molded housing, and a middle leg downward section that points downward. The bottom leg has a first bottom leg section that protrudes away from the molded housing face, a second bottom leg section that points away from the molded housing face, and third bottom leg section that points downward.10-09-2008
20080237814ISOLATED SOLDER PADS - An integrated circuit package is described that includes a die and a lead frame that includes recessed regions for preventing the undesired spread of solder during reflow. The die includes a plurality of solder bumps formed on its active surface. The lead frame includes a plurality of leads, each having an associated solder pad. Each solder pad is suitably positioned adjacent and electrically contacting an associated solder bump on the die. Each lead also includes a recessed region in a region adjacent to the solder pad. The recessed region serves to isolate the surface of the solder pad from the other surfaces of the lead. In this manner, the solder of the solder bump that contacts the lead is confined to the surface of the associated solder pad.10-02-2008
20080230876Leadframe Design for QFN Package with Top Terminal Leads - A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead finger. A portion of the second lead finger forms a bottom terminal lead structure. A portion of the second lead finger corresponds to a bottom surface of the semiconductor package. A surface of the substantially flat, top portion corresponds to a top surface of the semiconductor package.09-25-2008
20130140685Electronic Device and a Method for Fabricating an Electronic Device - The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.06-06-2013
20130140686SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar.06-06-2013
20080224281SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device comprises: a semiconductor chip; a first frame; a solder layer which bonds the solder bonding metal layer of the semiconductor chip and the first frame; and a second frame bonded to the rear face of the semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a first metal layer provided on a major surface of the semiconductor substrate and forming a Schottky junction with the semiconductor substrate; a second metal layer provided on the first metal layer and primarily composed of aluminum; a third metal layer provided on the second metal layer and primarily composed of molybdenum or titanium; and a solder bonding metal layer provided on the third metal layer and including at least a forth metal layer which is primarily composed of nickel, ion or cobalt.09-18-2008
20080224280LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted; and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island.09-18-2008
20080224279VERTICAL ELECTRICAL INTERCONNECT FORMED ON SUPPORT PRIOR TO DIE MOUNT - A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into corresponding pedestals. Also, a support has interconnect pedestals. Also, a method for electrically interconnecting a die to a support includes providing a support having interconnect pedestals formed at bond pads on the die mount surface of the support, providing a die having interconnect terminals projecting beyond a die edge, positioning the die in relation to the support such that the terminals are aligned with the corresponding pedestals, and moving the die and the support toward one another so that the terminals contact the respective pedestals.09-18-2008
20080224278CIRCUIT COMPONENT AND METHOD OF MANUFACTURE - An inductor, a semiconductor component including the inductor, and a method of manufacture. A leadframe has a plurality of conductive strips and a flag. A ferrite core is mounted on a die attach material disposed on the conductive strips and a semiconductor die is mounted on a die attach material disposed on the flag. Wire bonds are formed from the conductive strips on one side of the ferrite core to corresponding conductive strips on an opposing side of the ferrite core. The wire bonds and the conductive strips cooperate to form the coil of the inductor. Wire bonds electrically couple one end of the inductor to leadframe leads adjacent the semiconductor die. Wire bonds couple bond pads on the semiconductor die to the leadframe leads coupled to the inductor. An encapsulant is formed around the inductor and the semiconductor die. Alternatively, a stand-alone inductor is manufactured.09-18-2008
20080224277CHIP PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask.09-18-2008
20110260304LEADFRAME FOR ELECTRONIC COMPONENTS - The present invention specifies a leadframe for electronic components and a corresponding manufacturing process, in which the bonding islands are formed by welding individual, prefabricated segments of a bonding-capable material onto a stamped leadframe.10-27-2011
20130200503PROTECTIVE LAYERS IN SEMICONDUCTOR PACKAGING - A semiconductor package includes a semiconductor die having an upper surface with bond pads thereon. A plurality of leads surround sides of the semiconductor die. Bonding wires couple each of the bond pads to a corresponding one of the plurality of leads. An encapsulant covers the upper surface and the sides of the semiconductor die and the bonding wires. The encapsulant also covers a portion of a top of each of the plurality of leads and sides of the plurality of leads that are nearest the semiconductor die. A bottom of each of the plurality of leads and the sides of the plurality of leads that are farthest from the semiconductor die are exposed outside the encapsulant. A protective film covers a lower surface of the semiconductor die and has a bottom that is substantially coextensive with the bottom of each of the plurality of leads.08-08-2013
20130200504ELECTRONIC COMPONENT MODULE AND METHOD FOR PRODUCING SAME - An electronic component module includes a double-sided mounting board having a front surface and a back surface; components mounted on the front surface and the back surface of the double-sided mounting board; an insulating resin sealing the components mounted on the front surface and the back surface; and a lead frame bonded to the back surface of the double-sided mounting board. The back surface of the double-sided mounting board is sealed with the insulating resin such that the lead frame is not covered by the insulating resin, and the thickness of the insulating resin sealing the components mounted on the back surface of the double-sided mounting board is less than or equal to the thickness of the lead frame.08-08-2013
20130181332PACKAGE LEADFRAME FOR DUAL SIDE ASSEMBLY - Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.07-18-2013
20130127028THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING REDUNDANT RELIEF STRUCTURE FOR CHIP BONDING SECTION - A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset.05-23-2013
20080217750Semiconductor device - A plurality of inner leads 09-11-2008
20120248588LEAD FRAME - A lead frame including rails, section bars, and lead frame cells. The rails are respectively arranged at edges of the lead frame extending in a first direction. The section bars extend between the rails in a second direction and are orthogonal to the rails. The lead frame cells are aligned along the section bars. At least one of the section bars includes a rib extending in the second direction and formed through a half blanking process.10-04-2012
20130093069PACKAGE STRUCTURE AND THE METHOD TO FABRICATE THEREOF - The invention discloses a package structure made of the combination of a metallic substrate and a lead frame. In one embodiment, a recess is formed in the metallic substrate and a first conductive element having at least one first I/O terminal is bonded in the recess. A lead frame is formed on the metallic substrate and comprises a plurality of electrical connections to connect with said at least one first I/O terminal of the first conductive element. In another embodiment, another conductive element is disposed in the vacancy of the lead frame. The invention also discloses a method for manufacturing a package structure made of the combination of a metallic substrate and a lead frame.04-18-2013
20130093071OPTICAL MODULE WITH A LENS ENCAPSULATED WITHIN SEALANT AND METHOD FOR MANUFACTURING THE SAME - A method to manufacture an optical module is disclosed, wherein the optical module has an optically active device on a lead frame and a lens co-molded with the active device and the lead frame by a transparent resin as positioning the lens with respect to the lead frame. The molding die of the present invention has a positioning pin to support the lens during the molding. Because the lead frame is aligned with the molding die, the precise alignment between the active device on the lead frame and the lens is not spoiled during the molding.04-18-2013
20130093070SEMICONDUCTOR DEVICE CAPABLE OF SWITCHING OPERATION MODES - A semiconductor device includes a substrate, a first pad that is formed above the substrate, a second pad that is formed above the substrate, an external terminal that is connected with the second pad, and a circuit that judges whether or not the first pad is connected with the external terminal, wherein a distance between the first pad and a side of the substrate opposed to the external terminal is different from a distance between the second pad and the side.04-18-2013
20110272794PRE-MOLDED CLIP STRUCTURE - A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.11-10-2011
20110272793LEAD FRAME, SEMICONDUCTOR APPARATUS USING THIS LEAD FRAME, INTERMEDIATE PRODUCT THEREOF AND MANUFACTURING METHOD THEREOF - In a lead frame for a semiconductor apparatus 10, including plural terminals 13, one portions of the terminals 13 being sealed with a resin, a resin-sealed portion 16 of the terminal 13 has a polygonal columnar shape that is pentagonal or more or a deformed columnar shape having at least one notch or groove part extending vertically in a periphery. This resin-sealed portion 16 is formed by etching processing or press processing, and an exposed portion 18 of lower half of the terminal 13 is formed by the etching processing.11-10-2011
20110272792DIE BACKSIDE STANDOFF STRUCTURES FOR SEMICONDUCTOR DEVICES - Standoff structures that can be used on the die backside of semiconductor devices and methods for making the same are described. The devices contain a silicon substrate with an integrated circuit on the front side of the substrate and a backmetal layer on the backside of the substrate. Standoff structures made of Cu of Ni are formed on the backmetal layer and are embedded in a Sn-containing layer that covers the backmetal layer and the standoff structures. The standoff structures can be isolated from each other so that they are not connected and can also be configured to substantially mirror indentations in the leadframe that is attached to the Sn-containing layer. Other embodiments are described.11-10-2011
20130134567LEAD FRAME AND SEMICONDUCTOR PACKAGE STRUCTURE THEREOF - The present invention relates to the field of semiconductor package structures, and more specifically to a lead frame and a semiconductor package structure thereof. In one embodiment, a lead frame can include a plurality of parallel-arrayed lead fingers with a plurality of grooves situated on surfaces of the lead fingers, where the depths of the grooves can be smaller than the thickness of the lead fingers. In one embodiment, a flip chip semiconductor package structure can include a chip, a group of bumps, and the above-described lead frame. The first surfaces of the bumps can be coupled to the front surface of the chip, and the second surfaces of the bumps can be coupled to the upper surface of the lead frame.05-30-2013
20110215453MICROELECTRONIC DIE PACKAGES WITH LEADFRAMES, INCLUDING LEADFRAME-BASED INTERPOSER FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.09-08-2011
20130127026CONNECTING MATERIAL, METHOD FOR MANUFACTURING CONNECTING MATERIAL AND SEMICONDUCTOR DEVICE - In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material.05-23-2013
20130127027PRE-ENCAPSULATED LEAD FRAMES FOR MICROELECTRONIC DEVICE PACKAGES, AND ASSOCIATED METHODS - Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers.05-23-2013
20080197459ENCAPSULATED CHIP SCALE PACKAGE HAVING FLIP-CHIP ON LEAD FRAME STRUCTURE AND METHOD - In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects.08-21-2008
20080197458Small Outline Package in Which Mosfet and Schottky Diode Being Co-Packaged - The present invention provides a thin small outline package in which MOSPET and Schottky diode being co-packaged, which comprises a electrode S of MOSFET, a electrode 08-21-2008
20110241188GRANULAR EPOXY RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR, SEMICONDUCTOR DEVICE USING THE SAME AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Disclosed is a granular epoxy resin composition for encapsulating a semiconductor used for a semiconductor device obtained by encapsulating a semiconductor element by compression molding, wherein, in the particle size distribution as determined by sieving the whole epoxy resin composition for encapsulating a semiconductor using JIS standard sieves, the ratio of particles having a size of 2 mm or greater is not more than 3% by mass, the ratio of particles having a size of 1 mm or greater, but less than 2 mm is from 0.5% by mass or more to 60% by mass or less, and the ratio of microfine particles having a size of less than 106 μm is not more than 5% by mass.10-06-2011
20110233740PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.09-29-2011
20110233739SEMICONDUCTOR STRUCTURE, MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE - Disclosed is a semiconductor structure including a semiconductor substrate including an electronic circuit which is provided in a predetermined region of the semiconductor substrate, a wiring provided on the semiconductor substrate in a region outside of the predetermined region, an external connection electrode provided on the wiring, a sealing resin which covers a side surface of the external connection electrode and a wall which intervenes between the electronic circuit and the sealing resin.09-29-2011
20110233738SEMICONDUCTOR DEVICE AND LEAD FRAME - A semiconductor device including a semiconductor element, a die pad of a plane size smaller than that of the semiconductor element, a plurality of hanging leads extending from the die pad, and sealing resin for covering the semiconductor element, the die pad, and the hanging leads. The width of a first main surface of each hanging lead, integrated with the mounting surface of the die pad, is smaller than the width of a second main surface thereof, integrated with the opposite surface of the die pad.09-29-2011
20100314728IC PACKAGE HAVING AN INDUCTOR ETCHED INTO A LEADFRAME THEREOF - A leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The leadframe having a spiral inductor etched therein.12-16-2010
20130154067Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnect Structure on Leadframe - A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.06-20-2013
20130187259Electronic Device and a Method for Fabricating an Electronic Device - An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector.07-25-2013
20120018860METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a substrate for a semiconductor element including the steps of: providing a first photosensitive resin layer on a first surface of a metal plate; providing a second photosensitive resin layer on a second surface different from the first surface of the metal plate; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring pattern on the second surface of the metal plate; forming the connection post by performing an etching from the first surface to a midway of the metal plate; filling in a premold resin to a portion of the first surface where the connection post does not exist; processing so that a height of the connection post of the first surface is lower than a height of the premold resin surrounding the connection post; and forming the wiring pattern by performing an etching on the second surface.01-26-2012
20120043650Packaging Integrated Circuits - An integrated circuit 02-23-2012
20130200505PACKAGE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A method for manufacturing a package comprises a first step of forming a metal pattern including a frame and a plurality of leads extending inward from the frame, a second step of molding a resin pattern including a first resin portion which holds the plurality of leads from an inner side thereof, and second resin portions which cover bottom surfaces of peripheral portions, adjacent to portions to be removed, in the plurality of leads while exposing bottom surfaces of the portions to be removed in the plurality of leads, so as to hold the plurality of leads from a lower side thereof, and a third step of cutting the plurality of leads into a plurality of first leads and a plurality of second leads by removing the portions to be removed in the plurality of leads while the resin pattern keeps holding the peripheral portions in the plurality of leads.08-08-2013
20130200502Semiconductor Device and Method of Manufacturing Thereof - A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.08-08-2013
20120299166CONDUCTION PATH, SEMICONDUCTOR DEVICE USING THE SAME, AND METHOD OF MANUFACTURING CONDUCTION PATH, AND SEMICONDUCTOR DEVICE - A conduction path includes a first conduction path forming plate (11-29-2012
20120086111SEMICONDUCTOR DEVICE - The present invention reduces the occurrence of fracture in external terminal connecting sections and improves the reliability of secondary packaging of a semiconductor device. Specifically, the present invention provides a semiconductor device including a wiring board, a semiconductor chip mounted on one surface of the wiring board via a bonding member, and external electrodes formed on the other surface of the wiring board and electrically connected to the semiconductor chip. In the semiconductor device, a peripheral end of the bonding member is arranged in a position where the peripheral end does not overlap the external electrodes.04-12-2012

Patent applications in class LEAD FRAME

Patent applications in all subclasses LEAD FRAME