Entries |
Document | Title | Date |
20080197458 | Small Outline Package in Which Mosfet and Schottky Diode Being Co-Packaged - The present invention provides a thin small outline package in which MOSPET and Schottky diode being co-packaged, which comprises a electrode S of MOSFET, a electrode | 08-21-2008 |
20080197459 | ENCAPSULATED CHIP SCALE PACKAGE HAVING FLIP-CHIP ON LEAD FRAME STRUCTURE AND METHOD - In one embodiment, an encapsulated electronic package includes a semiconductor chip having patterned solderable pads formed on a major surface. During an assembly process, the patterned solderable pads are directly affixed to conductive leads. The assembly is encapsulated using, for example, a MAP over-molding process, and then placed through a separation process to provide individual chip scale packages having flip-chip on lead frame interconnects. | 08-21-2008 |
20080203546 | QUAD FLAT NO-LEAD CHIP CARRIER WITH STAND-OFF - A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved. | 08-28-2008 |
20080211068 | METHOD FOR MANUFACTURING LEADFRAME, PACKAGING METHOD FOR USING THE LEADFRAME AND SEMICONDUCTOR PACKAGE PRODUCT - A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads. | 09-04-2008 |
20080211069 | SEMICONDUCTOR PACKAGE CONFIGURATION WITH IMPROVED LEAD PORTION ARRANGEMENT - A semiconductor device with improved reliability is provided. The semiconductor device in a QFN package configuration has a semiconductor chip mounted on a tab, leads which are alternately arranged around the tab and electrically connected to the electrodes of the semiconductor chip via bonding wires, and an encapsulating resin portion for encapsulating therein the semiconductor chip and the bonding wires. The lower exposed surfaces of the leads are exposed at the outer peripheral portion of the back surface of the encapsulating resin portion to form external terminals. The lower exposed surfaces of the leads are exposed at the portion of the back surface of the encapsulating resin portion which is located inwardly of the lower exposed surface of the leads to also form external terminals. The cut surfaces of the leads are exposed at the cut surfaces of the encapsulating resin portion, while the upper exposed surfaces of the leads are exposed from the portion of the encapsulating resin portion which is proximate to the cut surfaces thereof. Each of the upper exposed surfaces of the leads has a width smaller than the width of each of the lower exposed surfaces thereof. | 09-04-2008 |
20080217750 | Semiconductor device - A plurality of inner leads | 09-11-2008 |
20080224277 | CHIP PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask. | 09-18-2008 |
20080224278 | CIRCUIT COMPONENT AND METHOD OF MANUFACTURE - An inductor, a semiconductor component including the inductor, and a method of manufacture. A leadframe has a plurality of conductive strips and a flag. A ferrite core is mounted on a die attach material disposed on the conductive strips and a semiconductor die is mounted on a die attach material disposed on the flag. Wire bonds are formed from the conductive strips on one side of the ferrite core to corresponding conductive strips on an opposing side of the ferrite core. The wire bonds and the conductive strips cooperate to form the coil of the inductor. Wire bonds electrically couple one end of the inductor to leadframe leads adjacent the semiconductor die. Wire bonds couple bond pads on the semiconductor die to the leadframe leads coupled to the inductor. An encapsulant is formed around the inductor and the semiconductor die. Alternatively, a stand-alone inductor is manufactured. | 09-18-2008 |
20080224279 | VERTICAL ELECTRICAL INTERCONNECT FORMED ON SUPPORT PRIOR TO DIE MOUNT - A die assembly includes a die mounted to a support, in which the support has interconnect pedestals formed at bond pads, and the die has interconnect terminals projecting beyond a die edge into corresponding pedestals. Also, a support has interconnect pedestals. Also, a method for electrically interconnecting a die to a support includes providing a support having interconnect pedestals formed at bond pads on the die mount surface of the support, providing a die having interconnect terminals projecting beyond a die edge, positioning the die in relation to the support such that the terminals are aligned with the corresponding pedestals, and moving the die and the support toward one another so that the terminals contact the respective pedestals. | 09-18-2008 |
20080224280 | LEAD FRAME, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - To solve a problem in that a die processing cost increases when employing a method involving providing a suction hole in the die to fix an island onto a bottom surface, provided is a semiconductor device, which includes: a semiconductor chip, an island having a first surface, on which the semiconductor chip is mounted; and a second surface opposing to the first surface, a hanger pin extended from the island, a branch portion extended from one of the island and the hanger pin, and a resin encapsulating the semiconductor chip, the island, the hanger pin and the brunch portion while exposing the second surface of the island. | 09-18-2008 |
20080224281 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device comprises: a semiconductor chip; a first frame; a solder layer which bonds the solder bonding metal layer of the semiconductor chip and the first frame; and a second frame bonded to the rear face of the semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a first metal layer provided on a major surface of the semiconductor substrate and forming a Schottky junction with the semiconductor substrate; a second metal layer provided on the first metal layer and primarily composed of aluminum; a third metal layer provided on the second metal layer and primarily composed of molybdenum or titanium; and a solder bonding metal layer provided on the third metal layer and including at least a forth metal layer which is primarily composed of nickel, ion or cobalt. | 09-18-2008 |
20080230876 | Leadframe Design for QFN Package with Top Terminal Leads - A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead finger. A portion of the second lead finger forms a bottom terminal lead structure. A portion of the second lead finger corresponds to a bottom surface of the semiconductor package. A surface of the substantially flat, top portion corresponds to a top surface of the semiconductor package. | 09-25-2008 |
20080230877 | SEMICONDUCTOR PACKAGE HAVING WIRE REDISTRIBUTION LAYER AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The method includes providing a semiconductor substrate on which a chip pad is formed. A wire redistribution layer connected to the chip pad is formed. An insulating layer which includes an opening exposing a portion of the wire redistribution layer is formed. A metal ink is applied within the opening to thereby form a bonding pad. The applied metal ink within the opening and the insulating layer can be cured simultaneously. | 09-25-2008 |
20080237814 | ISOLATED SOLDER PADS - An integrated circuit package is described that includes a die and a lead frame that includes recessed regions for preventing the undesired spread of solder during reflow. The die includes a plurality of solder bumps formed on its active surface. The lead frame includes a plurality of leads, each having an associated solder pad. Each solder pad is suitably positioned adjacent and electrically contacting an associated solder bump on the die. Each lead also includes a recessed region in a region adjacent to the solder pad. The recessed region serves to isolate the surface of the solder pad from the other surfaces of the lead. In this manner, the solder of the solder bump that contacts the lead is confined to the surface of the associated solder pad. | 10-02-2008 |
20080246128 | Bent lead transistor - A metal backing tab supports the semiconductor device and has an extending portion extending from an edge. A top leg, a middle leg and a bottom leg are all coupled to the semiconductor device and each has a lead terminal portion extending beyond the boundary of said molded housing. The top leg has a first top leg section that protrudes directly away from the molded housing, a second top leg section that bends toward a direction of a face of the molded housing, and a third top leg section bending downward. The middle leg has a first middle leg section connected to the package that protrudes away from the molded housing, and a middle leg downward section that points downward. The bottom leg has a first bottom leg section that protrudes away from the molded housing face, a second bottom leg section that points away from the molded housing face, and third bottom leg section that points downward. | 10-09-2008 |
20080251897 | SEMICONDUCTOR DEVICE - The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. | 10-16-2008 |
20080251898 | Semiconductor device - A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized. | 10-16-2008 |
20080258272 | ETCHED LEADFRAME STRUCTURE - A leadframe structure is disclosed. The leadframe structure includes a first leadframe structure portion with a first thin portion and a first thick portion, where the first thin portion is defined in part by a first recess. It also includes a second leadframe structure portion with a second thin portion and a second thick portion, where the second thin portion is defined in part by a second recess. The first thin portion faces the second recess, and the second thin portion faces the first recess. | 10-23-2008 |
20080258273 | Package Structure With Flat Bumps For Electronic Device and Method of Manufacture the Same - The invention discloses an ultra thin package structure of leadless electronic device and the packaging method, and includes lead support base adjacent to the chip support base; chip mounted on the chip support base; wires bonded between chip and lead support base; the molded body encapsulating the top surface and side surface of the chip support base, small protrusions of the chip support base and lead support base below the molded body; in the individual package, the number of the chip support base island can be one or more, the lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island. | 10-23-2008 |
20080272470 | Same Size Through-Hole Via Die Stacked Package - A semiconductor package includes a substrate or leadframe structure. A plurality of interconnected dies, each incorporating a plurality of through-hole vias (THVs) disposed along peripheral surfaces of the plurality of dies, are disposed over the substrate or leadframe structure. The plurality of THVs are coupled to a plurality of bond pads through a plurality of a metal traces. A top surface of a first THV is coupled to a bottom surface of a second THV. An encapsulant is formed over a portion of the substrate or leadframe structure and the plurality of dies. | 11-06-2008 |
20080283977 | STACKED PACKAGED INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged integrated circuit device and a plurality of planar conductive members conductively coupling the first and second packaged integrated circuit devices to one another. A method is also disclosed which includes conductively coupling a plurality of extensions on a leadframe to each of a pair of stacked packaged integrated circuit devices and cutting the leadframe to singulate the extensions from one another. | 11-20-2008 |
20080290476 | METHOD FOR MAKING SEMICONDUCTOR CHIPS HAVING COATED PORTIONS - A method for making semiconductor chips having coated portions can include mounting the chips in lead frames, stacking the lead frames in an orientation in which a portion of one lead frame masks a portion of a chip mounted on another lead frame but leaves another portion of the chip mounted on the other lead frame exposed to receive a coating, and depositing a coating on the stacked lead frames using, for example, an evaporative coating machine. In this manner, the coating is deposited on exposed portions of chips, such as its edges, and is not deposited on masked portions of chips, such as bond pads. | 11-27-2008 |
20080290477 | Semiconductor Device - A semiconductor device having a plurality of semiconductor chips mounted on a lead frame ( | 11-27-2008 |
20080290478 | LEAD-FRAME ARRAY PACKAGE STRUCTURE AND METHOD - The present invention provides a lead-frame array package structure. The package structure includes a lead-frame, which composed of a plurality of shorter leads and a plurality of longer leads. The first surface and a second surface are composed of the shorter leads and the longer leads. The chip is fixedly connected to the first surface of the lead-frame. The metal pads are positioned on the one side of the active layer of the chip. The metal pads are electrically connected to the leads of the lead-frame via the metal leads. The chip, the metal leads, the first surface and the second surface of the lead-frame is encapsulated by encapsulated material to expose the portion of the metal of the leads. The conductive elements are electrically connected to exposed leads so as to an array arrangement is formed on the second surface of the lead-frame. | 11-27-2008 |
20080290479 | Wafer level device package with sealing line having electroconductive pattern and method of packaging the same - Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device. | 11-27-2008 |
20080290480 | MICROELECTRONIC ASSEMBLY AND METHOD FOR FORMING THE SAME - A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls ( | 11-27-2008 |
20080296745 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR CHIP AND ANTENNA - A semiconductor device comprises a lead frame, an antenna formed at a predetermined position on the lead frame, and a semiconductor chip. The semiconductor chip is mounted on an island of the lead frame through a spacer. | 12-04-2008 |
20080303122 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADED PACKAGE - An integrated circuit package system includes: providing a frame; attaching a leaded package having leads adjacent the frame wherein the leads extend towards a side opposite the frame; and applying a package encapsulant over the leaded package having the leads partially exposed opposite the frame. | 12-11-2008 |
20080308913 | STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A stacked semiconductor package includes a first semiconductor package, a second semiconductor package and a conductive connection member. The first semiconductor package includes a first semiconductor chip, a first lead frame having first outer leads that are electrically connected to the first semiconductor chip, and a first molding member formed on the first semiconductor chip and the first lead frame to expose the first outer leads. The second semiconductor package includes a second semiconductor chip, a second lead frame formed on the first molding member and having second outer leads that may be electrically connected to the second semiconductor chip, and a second molding member formed on the second semiconductor chip and the second lead frame to expose the second outer leads. The conductive connection member may electrically connect the first outer leads and the second outer leads to each other. Further, the conductive connection member may have a crack-blocking groove. | 12-18-2008 |
20090001529 | PACKAGE STACKING USING UNBALANCED MOLDED TSOP - A semiconductor package assembly is disclosed including a pair of stacked leadframe-based semiconductor packages. The first package is encapsulated in a mold compound so that the electrical leads emanate from the sides of the package, near a bottom surface of the package. The first package may be stacked atop the second package by aligning the exposed leads of the first package with the exposed leads of the second package and affixing the respective leads of the two packages together. The vertical offset of leads toward a bottom of the first package provides a greater overlap with leads of the second package, thus allowing a secure bonding of the leads of the respective packages. | 01-01-2009 |
20090014848 | Mixed Wire Semiconductor Lead Frame Package - One embodiment includes an encapsulated semiconductor package having a lead frame with die pad surrounded by a plurality of first and second leadfingers. A semiconductor chip including chip contact pads on its upper active surface is attached to the die pad. A plurality of first bond wires, including a first electrically conductive material, extend between the chip contact pads and the plurality of first leadfingers. A plurality of second bond wires, including a second electrically conductive material, extend between a chip contact pad and a second leadfinger. The semiconductor package further includes a plurality of electrically conducting means attached to the second leadfingers. | 01-15-2009 |
20090014849 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE MOLDING - An integrated circuit package system is provided forming a lead from a padless lead frame, and encapsulating the lead for supporting an integrated circuit die with a first molding compound for encapsulation with a second molding compound. | 01-15-2009 |
20090020857 | SYSTEM AND METHOD FOR ROUTING SUPPLY VOLTAGES OR OTHER SIGNALS BETWEEN SIDE-BY-SIDE DIE AND A LEAD FRAME FOR SYSTEM IN A PACKAGE (SIP) DEVICES - An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame. The integrated circuit further includes a redistribution layer formed on the first die to couple selected bond fingers of the lead frame to selected bonding pads of the first and second die. The selected bond fingers may correspond to bond fingers that receive a first supply voltage or the first supply voltage and a second supply voltage. | 01-22-2009 |
20090026589 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein. | 01-29-2009 |
20090032915 | TFCC (TM) & SWCC (TM) thermal flex contact carriers - Two groups of interconnection devices and methods are described. Both provide columns between electronic packages and boards or between chips and substrates or the like. In the first group, called Thermal Flex Contact Carrier (TFCC), the column elements are carved out of a flat laminated structure and then formed to suit. In the second group, the carrier, which carries the connecting elements, is made out of a soluble or removable material, which acts at the same time, as a solder mask, to prevent the solder from wicking along the stem of the elements. | 02-05-2009 |
20090032916 | SEMICONDUCTOR PACKAGE APPARATUS - A semiconductor package apparatus and a method of fabricating the semiconductor package apparatus. The semiconductor package apparatus includes: semiconductor chips comprising active and inactive surfaces and protected by a packing portion; a substrate on which the semiconductor chips are installed; leads comprising front portions electrically coupled to the active surfaces of the semiconductor chips and rear portions extending substantially to the substrate; and bonding materials bonded between ends of the rear portions of the leads and the substrate to electrically couple the leads to the substrate. Ends of the rear portions of the leads may stand on the substrate. Thus, solder joint reliability can be improved, and a wetting characteristic of solder can be improved during surface installation. Also, semiconductor package apparatuses having similar attributes can easily be multilayered. In addition, a foot print of the semiconductor package apparatus can be reduced to enable high-density installation. Moreover, shapes of the bonding materials (solder) can be controlled to optimize bonding strength of the leads, quantity of the bonding materials, or the like. | 02-05-2009 |
20090045489 | MICROELECTRONIC DIE PACKAGES WITH LEADFRAMES, INCLUDING LEADFRAME-BASED INTERPOSER FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads. | 02-19-2009 |
20090057850 | Surface Mountable Semiconductor Package with Solder Bonding Features - A packaged circuit element such as an LED and a method for making the same are disclosed. The packaged circuit element includes a lead frame, a molded body, and a die containing the circuit element. The lead frame has first and second leads, each lead having first and second portions. The molded body surrounds the first portion of each lead, and the die is connected electrically to the first and second leads on the first portions of the first and second leads. The second portion of each of the first and second leads is substantially parallel to opposing side surfaces of the body and include a feature that inhibits molten solder from wetting a portion of the second section of each lead between the feature and the first portion of that lead while allowing the molten solder to wet the remaining surfaces of the second portions. | 03-05-2009 |
20090057851 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device including: arranging multiple dies planarly between a first lead frame plate and a second lead frame plate, which face each other, to connect the multiple semiconductor chips to each of the first lead frame plate and the second lead frame plate; filling a resin between the first lead frame plate and the second lead frame plate to seal the multiple dies; performing a first dicing on a laminated body including the first lead frame plate, the resin, and the second lead frame plate, between the adjacent dies, to separate at least the first lead frame plate by cutting; applying plating to the laminated body with at least the first lead frame plate being separated by cutting; and performing a second dicing on a remainder of the laminated body between the adjacent dies, to separate the laminated body into individual semiconductor devices. | 03-05-2009 |
20090065910 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - While a semiconductor device is provided with a plurality of element electrodes | 03-12-2009 |
20090065911 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a carrier, at least one chip, an encapsulation, and a patterned conductive film. The carrier has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the carrier and electrically connected to the carrier. The encapsulation encapsulates the chip and at least a portion of the first surface of the carrier. The patterned conductive film is disposed on the encapsulation to electrically connect to the carrier. A manufacturing method of the semiconductor package is also disclosed. | 03-12-2009 |
20090065912 | Semiconductor Package and Method of Assembling a Semiconductor Package - A semiconductor package includes a semiconductor component including a circuit carrier with a plurality of inner contact pads, a semiconductor chip, and a plurality of electrical connections. An adhesion promotion layer is disposed on at least areas of the semiconductor component and a plastic encapsulation material encapsulates at least the semiconductor chip, the plurality of electrical connections and the plurality of the inner contact pads. Surface regions of the semiconductor component are selectively activated. | 03-12-2009 |
20090072359 | STACKED SYNCHRONOUS BUCK CONVERTER - A multichip module buck converter | 03-19-2009 |
20090079043 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including a semiconductor chip, a film (first film) which is provided so as to cover an active region with a peripheral portion of the semiconductor chip being uncovered, and is made of a dielectric material having a low dielectric constant, and a package molding resin (sealing resin) provided so as to cover the semiconductor chip and the film. As a result, deterioration in contact property with the sealing resin is suppressed and a high frequency characteristic can be enhanced. | 03-26-2009 |
20090079044 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a lead frame, at least one chip, and an encapsulation. The lead frame has a plurality of leads, and each of the leads includes at least one first conductive part, at least one second conductive part, and at least one third conductive part. The first conductive part is not electrically connected to the second conductive part, and the second conductive part is electrically connected to the third conductive part. The chip is electrically connected to the first conductive part. The encapsulation encapsulates the chip and at least a portion of the lead frame, and forms a first surface and a second surface opposite to the first surface. The first conductive part and the third conductive part are exposed from the first surface, and the second conductive part is exposed from the second surface. | 03-26-2009 |
20090079045 | Package structure and manufacturing method thereof - A quad-flat non-leaded (QFN) multichip package and a multichip package are provided. The QFN multichip package includes a lead frame, a first chip, a second chip and a molding compound. The lead frame has a plurality of first leads and second leads alternately arranged with each other. Each first lead includes a first connection portion and a first contact portion. Each second lead includes a second connection portion, a bending part and a second contact portion. The bending part is bent upward such that an interval is formed between the second contact portion and the first contact portion. The first chip is disposed between the first leads and the second leads. The second chip is disposed above the first chip. The molding compound encloses the first chip, the second chip, the first leads and the second leads, and further exposes the lower surfaces of the first and the second leads. | 03-26-2009 |
20090079046 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor device having a first main surface and a second main surface, a first electrode plate provided on the first main surface, a second electrode plate provided on the second main surface, and a wiring substrate provided between the semiconductor device and the first electrode plate, in which a plurality of opening portions in the side surface of a protruding portion provided on the first electrode plate are engaged respectively with a plurality of engaging portions which face the opening portions and which are provided on the inner side surface of an intrusion opening portion in the wiring substrate into which the protruding portion is intruded. | 03-26-2009 |
20090085177 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME ARRAY - An integrated circuit package system includes providing an integrated circuit die; attaching the integrated circuit die over a lead grid having lead blocks; and connecting a die interconnect to the integrated circuit die and the lead blocks. | 04-02-2009 |
20090085178 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BASE STRUCTURE DEVICE - An integrated circuit packaging system including: forming a base structure, having an opening; mounting a base structure device in the opening; attaching an integrated circuit device over the base structure device; and molding an encapsulant on the base structure, the base structure device, and the integrated circuit device. | 04-02-2009 |
20090091006 | Dual Capillary IC Wirebonding - The invention discloses apparatus and methods for the formation of bond wires in integrated circuit assemblies by attaching two separate wires using a dual capillary bond head. The separate wires are preferably non-identical, for example, being of different gauges and/or material composition. According to a preferred embodiment of the invention, dual capillary bond head apparatus includes a rotatable ultrasonic horn with a pair of capillaries for selectably dispensing separate strands of bond wire and for forming bonds on bond targets. According to another aspect of the invention, a method is provided for dual capillary IC wirebonding including steps for using two dual capillary bond heads for contemporaneously attaching non-identical bond wires to selected bond targets on one or more IC package assemblies. | 04-09-2009 |
20090091007 | Semiconductor Device Having Grooved Leads to Confine Solder Wicking - A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 μm deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 μm deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions. | 04-09-2009 |
20090091008 | Semiconductor device - A semiconductor device for programmable logic or operation processing includes a semiconductor chip; a first connecting terminal for electrically connecting the semiconductor device to a printed circuit board on which the semiconductor device is to be mounted; a second connecting terminal for electrically connecting the semiconductor device to another semiconductor device; and a packaging material for sealing the semiconductor chip, the first connecting terminal, and the second connecting terminal. Then, the first connecting terminal is formed of the lead frame, and the second connecting terminal is formed on the wiring board. | 04-09-2009 |
20090096068 | System and Method for Stabilizing an Amplifier - In one embodiment of the present invention, a semiconductor circuit including an amplifier disposed on a semiconductor substrate is disclosed. A first bond wire coupled to an input of the amplifier, a second bond wire coupled to an output of the amplifier, and a third bond wire coupled in series with the first bond wire. A third bond wire is disposed on the semiconductor substrate so that a mutual inductance between the second bond wire and the third bond wire at least partially cancels a mutual inductance between the first bond wire and the second bond wire. | 04-16-2009 |
20090096069 | Cof board - A COF board includes an insulating layer, and a terminal portion formed on the insulating layer. The terminal portion includes a first lead extending in a longitudinal direction, and a second lead extending in the longitudinal direction, and having a smaller length in the longitudinal direction than a length of the first lead in the longitudinal direction. The first leads are arranged in spaced-apart relation in a direction perpendicular to the longitudinal direction. The second leads are arranged in the direction perpendicular to the longitudinal direction to be interposed between the mutually adjacent first leads such that, when the mutually adjacent first leads are projected in an adjacent direction thereof, overlap portions where the second leads overlap with the first leads and non-overlap portions where the second leads do not overlap with the first leads are formed. Dummy leads are provided at the non-overlap portions. | 04-16-2009 |
20090102028 | METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE THEREFOR - A method for manufacturing a semiconductor component that includes a leadframe having a non-metallic base structure and an intermediate leadframe structure. The non-metallic base structure may be, among other things, paper, cellulose, or plastic. A layer of electrically conductive material is formed over the non-metallic base structure. A circuit element attach structure and a plurality of leadframe leads are formed from the layer of electrically conductive material. A circuit element is coupled to the circuit element attach structure and electrically coupled to the plurality of leadframe leads. The circuit element is encapsulated and at least the non-metallic base structure is removed. Alternatively, a plurality of leadframe leads may be formed on the electrically conductive layer and a circuit element is placed over the electrically conductive layer. The circuit element is electrically coupled to the plurality of leadframe leads and encapsulated. The non-metallic base structure and the electrically conductive layer are removed. | 04-23-2009 |
20090108418 | Non-leaded semiconductor package structure - A non-leaded semiconductor package structure is proposed, in which the structure of a lead frame is improved to let the lower surface of a die paddle of the lead frame be used to carry a die and the upper surface thereof be exposed out of the package structure. Moreover, a plurality of leads of the lead frame is located at the periphery of the lower surface of the die paddle. Each lead has an inner lead and an outer lead, and the outer lead is exposed out of the package structure. The package structure thus formed has a good heat-radiating effect and a reduced chance of leakage current. | 04-30-2009 |
20090108419 | LEADFRAME FOR LEADLESS PACKAGE - A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, a plurality of connection portions, a plurality of openings, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of slots are disposed around each of the package units. The plurality of connection portions connect the plurality of package areas. The plurality of openings are disposed on the plurality of connection portions, and are aligned with some of the plurality of slots. The tape (film) fixes the plurality of package areas, the plurality of connection portions, the plurality of die pads, and the plurality of leads in place. | 04-30-2009 |
20090108420 | SEMICONDUCTOR DEVICE AND ITS FABRICATION PROCESS - A technique capable of preventing whiskers which are generated in a plating film formed on the surface of each of leads of a semiconductor device is provided. Particularly, a technique capable of preventing generation of whiskers in a plating film containing tin as a primary material and not containing lead is provided. The plating film formed on the surface of the lead is formed so that a particular plane orientation among plane orientations of tin constituting the plating film is parallel to the surface of the lead. Specifically, the plating film is formed so that the (001) plane of tin is parallel to the surface of the lead. Thus, the coefficient of thermal expansion of tin constituting the plating film can be made to be lower than a coefficient of thermal expansion of the copper constituting the lead. | 04-30-2009 |
20090115032 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL CONNECTIVITY - An integrated circuit package system includes: forming a lead having a both top contact portion and a bottom contact portion; connecting an integrated circuit die and the lead; and forming a package encapsulation, having a top side and a bottom side, over the integrated circuit die. The forming the package encapsulation includes partially exposing the top contact portion at the top side, and partially exposing the bottom contact portion along the bottom side with the bottom contact portion extending beyond a nonhorizontal portion of the package encapsulation. | 05-07-2009 |
20090115033 | Reduction of package height in a stacked die configuration - A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material. | 05-07-2009 |
20090121326 | SEMICONDUCTOR PACKAGE MODULE - A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module. | 05-14-2009 |
20090121327 | Semiconductor device having spacer formed on semiconductor chip connected with wire - A semiconductor device includes a semiconductor chip, a supporting body that is disposed below the semiconductor chip and supports the semiconductor chip, a spacer that is fixed onto the first semiconductor chip, and a substrate that is located below the first semiconductor chip and electrically connected to the semiconductor chip with a wire. At least a part of the peripheral portion of the semiconductor chip is an overhang portion that projects more laterally than the peripheral portion of the supporting body. A covering portion that covers a part of the upper surface of the overhang portion is formed in the spacer. The wire is connected to a region in the upper surface of the overhang portion, the region being lateral to the outermost periphery of the covering portion of the spacer and not being covered with the covering portion of the spacer. A height of an apex of the wire from the upper surface of the first semiconductor chip as a reference, is greater than a height, from the reference, of at least a portion in the outermost periphery of the covering portion of the spacer, the portion having the wire arranged at its lateral side. | 05-14-2009 |
20090127676 | Back to Back Die Assembly For Semiconductor Devices - Back to back die assemblies used in semiconductor devices and methods for making such devices are described. The die assemblies are made by stacking two dies together so that the back of one die (that does not contain any active electronic components) is attached to the back of another die. At the same time, though, the dies are electrically isolated from each other. This configuration provides a device with a small package size and a small land pattern. As well, a minimum number of metal traces are used in the semiconductor devices, leading to a very low on-resistance (R | 05-21-2009 |
20090127677 | Multi-Terminal Package Assembly For Semiconductor Devices - Semiconductor packages that contain leads with multiple terminals are described. The leads have a side terminal that can extend between a top terminal and a bottom terminal. The multiple terminals in the leads allow the semiconductor package to be connected to more than one external substrate and give the package multiple land pattern options. The semiconductor package can contain one or more dies that are connected to a lead frame in the package without the use of a clip. The back side of the die may be externally exposed from the package to help dissipate heat. | 05-21-2009 |
20090127678 | Stacked assembly of semiconductor packages with fastening lead-cut ends of leadframe - A stacked assembly of semiconductor packages primarily comprises a plurality of stacked semiconductor packages. Each semiconductor package includes an encapsulant, at least a chip, and a plurality of external leads of a leadframe, where the external leads are exposed and extended from a plurality of sides of the encapsulant. Each external lead of an upper semiconductor package has a U-shaped cut end when package singulation. The U-shaped cut ends are configured for locking to the soldered portion of a corresponding external lead of a lower semiconductor package where the U-shaped cut ends and the soldered portions by soldering materials. Therefore, the stacked assembly has a larger soldering area and stronger lead reliability to enhance the soldering points to against the effects of impacts, thermal shocks, and thermal cycles. | 05-21-2009 |
20090127679 | POP (Package-On-Package) device encapsulating soldered joints between externals leads - A POP (Package-On-Package) semiconductor device with encapsulating protection of soldered joints between the external leads, primarily comprises a plurality of stacked semiconductor packages and dielectric coating. Each semiconductor package includes at least a chip, a plurality of external leads of leadframe, and an encapsulant where the external leads are exposed and extended from a plurality of sides of the encapsulant. Terminals of a plurality external leads of a top semiconductor package are soldered to the soldered regions of the corresponding external leads of a bottom semiconductor package. The dielectric coating is disposed along the sides of the encapsulant of the bottom semiconductor package to connect the soldered points between the external leads and to partially or completely encapsulate the soldering materials so that the stresses between the soldered joints can be dispersed and no electrical shorts happen. | 05-21-2009 |
20090134501 | DEVICE AND METHOD INCLUDING A SOLDERING PROCESS - A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate. | 05-28-2009 |
20090134502 | LEADFRAME BASED FLASH MEMORY CARDS - A leadframe design for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts. | 05-28-2009 |
20090140401 | System and Method for Improving Reliability of Integrated Circuit Packages - An integrated circuit package includes a die, a bump, an underbump metallization layer formed between the bump and the die, a portion of the underbump metallization layer under the bump having a first radius, and a redistribution layer formed between the underbump metallization layer and the die. The redistribution layer has a pad positioned under the underbump metallization layer. The pad has a second radius, and makes contact with the underbump metallization layer. The second radius is less than or equal to the first radius. The integrated circuit package also includes a first dielectric layer disposed between the die and the redistributing layer. | 06-04-2009 |
20090146271 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM - An integrated circuit package-in-package system is provided including mounting first integrated circuits stacked in a first offset configuration over a die-attach paddle having a first edge and a second edge, opposing the first edge; connecting the first integrated circuits and a second edge lead adjacent the second edge; mounting second integrated circuits stacked in a second offset configuration, below and to the die-attach paddle; connecting the second integrated circuits and a first edge lead adjacent to the first edge; and encapsulating the first integrated circuits, second integrated circuits, and the die-attach paddle, with the first edge lead and the second edge lead partially exposed. | 06-11-2009 |
20090146272 | ELECTRONIC DEVICE - Embodiments provide an electronic device including a carrier defining a first major surface, a chip attached to the first major surface, an array of leads connected to the first major surface, and a thickness of encapsulation material disposed on the first major surface of the carrier. Each lead extends through the thickness of the encapsulation material. | 06-11-2009 |
20090146273 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. | 06-11-2009 |
20090146274 | INTEGRATED CIRCUIT PACKAGES INCLUDNG SINUOUS LEAD FRAMES - Integrated circuit packages include an integrated circuit mounting substrate having a hole that defines an inner wall of the integrated circuit mounting substrate. An integrated circuit is provided in the hole. A sinuous lead frame extends from the integrated circuit and is connected to the inner wall. The sinuous lead frame extends back and forth along a given direction, and may include a U- and/or V-shape, and round and/or jagged portions. Related packaging methods are also disclosed. | 06-11-2009 |
20090160036 | PACKAGE WITH MULTIPLE DIES - A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package. | 06-25-2009 |
20090160037 | METHOD OF PACKAGING INTEGRATED CIRCUITS - A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead. | 06-25-2009 |
20090166820 | TSOP LEADFRAME STRIP OF MULTIPLY ENCAPSULATED PACKAGES - A method of fabricating a semiconductor leadframe package from a strip including multiply encapsulated leadframe packages, and a leadframe package formed thereby are disclosed. An entire row or column of leadframes gets encapsulated together. Encapsulating an entire row or column reduces the keep-out area between adjacent leadframe packages, which allows the internal leads of each leadframe and the semiconductor die coupled thereto to be lengthened. | 07-02-2009 |
20090174042 | RADIO FREQUENCY OVER-MOLDED LEADFRAME PACKAGE - An over-molded leadframe (e.g., a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300 GHz and a method of making the over-molded leadframe package are disclosed. The over-molded leadframe package includes a capacitance lead configured to substantially reduce and/or offset the inductance created by one or more wirebonds used to connect an integrated circuit (IC) chip on the package to an input/output (I/O) lead. The IC chip is connected to the capacitance lead via one or more wirebonds, and the capacitance lead is then connected to the I/O lead via at least a second wirebond. Thus, inductance created by the one or more wirebonds on the package is substantially reduced and/or offset by the capacitance lead prior to a signal being output by the package and/or received by the IC chip. | 07-09-2009 |
20090189259 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING - An electronic device and method of manufacturing. One embodiment includes attaching a first semiconductor chip to a first metallic clip. The first semiconductor chip is placed over a leadframe after the attachment of the first semiconductor chip to the first metallic clip. | 07-30-2009 |
20090194854 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE PACKAGE - A method of manufacturing an electronic device is provided. The method comprises providing a carrier sheet, etching the lead frame material sheet to form a recess on a first surface of the lead frame material sheet, placing an electronic chip into the recess of the carrier sheet, and thereafter, selectively etching a second surface of the lead frame material sheet, the second surface being opposite to the first surface. | 08-06-2009 |
20090194855 | FOLDED LEADFRAME MULTIPLE DIE PACKAGE - A multiple die package includes a folded leadframe for interconnecting at least two die attached to another leadframe. In a synchronous voltage regulator the folded leadframe, which is formed from a single piece of material, connects the high side switching device with the low side switching device to provide a low resistance, low inductance connection between the two devices. | 08-06-2009 |
20090206456 | MODULE INCLUDING A SINTERED JOINT BONDING A SEMICONDUCTOR CHIP TO A COPPER SURFACE - A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface. | 08-20-2009 |
20090206457 | RESIN MOLDING PART AND MANUFACTURING METHOD THEREOF - A primary molding product is formed by integrally forming a first lead frame and a second lead frame with a primary molding resin portion. In addition, in order to prevent separation of the first lead frame and the second lead frame from the primary molding resin portion, a hook-and-hold portion for preventing separation of the first lead frame from the primary molding resin portion and separation of the second lead frame from the primary molding resin portion is provided on an outer surface of each of the first lead frame and the second lead frame. Thus, a resin molding part capable of achieving suppression of increase in a thickness thereof without deformation or displacement of a lead frame and a manufacturing method thereof can be provided. | 08-20-2009 |
20090212403 | THERMALLY ENHANCED MOLDED LEADLESS PACKAGE - A molded leadless package (MLP) semiconductor device includes a heat spreader with a single connecting projection extending from an edge of a cap of the heat spreader to a leadframe. The heat spreader can include additional projections on its edges that act as heat collectors and help to secure the spreader in the MLP. The connecting projection is attached to a lead of the leadframe so that heat gathered by the cap can be transferred through the connecting projection to the lead and to a printed circuit board to which the lead is connected. In embodiments, the heat spreader includes a central heat collector projection from the cap toward the die, preferably in the form of a solid cylinder, that enhances heat collection and transfer to the cap. The cap can include fins projecting from its top surface to facilitate radiant and convection cooling. | 08-27-2009 |
20090218663 | LEAD FRAME BASED SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor package, where the package includes a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface. The method is characterised in that it comprises the step of patterning one or more channels on the surface which channels extend away from the joint area towards an edge of the surface. Also the method has the step of applying a compound to one or more channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the interaction defines one or more paths in the connective material. These correspond to the one or more channels on the surface and allow the passage of waste material away from the joint area to the outer edge of the surface. | 09-03-2009 |
20090230517 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRATION PORT - An integrated circuit package system comprising: fabricating a package base including: forming a lead frame, coupling a first integrated circuit device under the lead frame, coupling a second integrated circuit device over the first integrated circuit device, and molding an enclosure on the lead frame, the first integrated circuit device, and the second integrated circuit device for forming an integration port; and coupling a third integrated circuit device on the integration port. | 09-17-2009 |
20090230518 | SEMICONDUCTOR DIE PACKAGE INCLUDING IC DRIVER AND BRIDGE - A semiconductor die package. Embodiments of the semiconductor die package are usable in backlight circuitry. Systems in packages may include a bridge circuit or a part thereof, and a integrated circuit die, such as a driver die, encapsulated by a molding material or other package. The bridge circuit may be stacked on opposing surfaces of a leadframe. | 09-17-2009 |
20090230519 | Semiconductor Device - This application relates to a semiconductor device comprising: a carrier comprising a chip island and at least one first external contact element; only one semiconductor chip, wherein the semiconductor chip comprises a first electrode on a first surface and a second electrode on a second surface opposite to the first surface and wherein the first electrode is attached to the chip island; and a metal structure comprising a plate region attached to the second electrode and a connection region attached to the at least one first external contact element, wherein the plate region extends laterally beyond the edges of at least two sides of the second surface of the semiconductor chip. | 09-17-2009 |
20090230520 | Leadframe package with dual lead configurations - The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend to reduce the relative capacitance of the signal connectors and thereby improve high speed performance. The fixed voltage connections incorporate configurations of fixed voltage leads and fixed voltage bonding wires that will tend to reduce the inductance of the fixed voltage connector and reduce noise on the fixed voltage connections and improve power delivery characteristics. The configurations of the associated signal and fixed voltage connections will tend to result in signal connections that include signal leads that are shorter, narrower and/or more widely separated from the active surface of the semiconductor chip than the corresponding fixed voltage leads. | 09-17-2009 |
20090236702 | SiP SUBSTRATE - Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace. | 09-24-2009 |
20090236703 | Chip package structure and the method thereof - A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces. | 09-24-2009 |
20090243054 | I/O CONNECTION SCHEME FOR QFN LEADFRAME AND PACKAGE STRUCTURES - Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost. | 10-01-2009 |
20090243055 | Leadframe, semiconductor packaging structure and manufacturing method thereof - A semiconductor packaging structure includes a plurality of first inner leads, a plurality of second inner leads, a plurality of first outer leads, a plurality of stacked chips, an encapsulating body, and a plurality of wires. Wherein, a first protrusion portion is protruded from each of the first inner leads and is formed a plurality of contact faces with height differences, a second protrusion portion is protruded from each of the second inner leads. Therefore, the wires connected to the stacked chips, the first protrusion portion of the first inner leads, and the second protrusion portion of the second inner leads can be shorten. And, the wire sweep and short-circuit can be prevented during molding process. In addition, the present invention also discloses a leadframe and manufacturing method for the leadframe and its semiconductor packaging structure. | 10-01-2009 |
20090256245 | Stacked Micro-Module Packages, Systems Using the Same, and Methods of Making the Same - Semiconductor die packages, methods of making said packages, and systems using said packages are disclosed. An exemplary package comprising at least one semiconductor die disposed on one surface of a leadframe and electrically coupled to at least one conductive region of the leadframe, and at least one passive electrical component disposed on the other surface of a leadframe and electrically coupled to at least one conductive region of the leadframe. | 10-15-2009 |
20090256246 | SEMICONDUCTOR PACKAGING TECHNIQUES - A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die. | 10-15-2009 |
20090261461 | SEMICONDUCTOR PACKAGE WITH LEAD INTRUSIONS - Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead fingers may have a lead intrusion disposed on the external exposed lower surface of the lead finger. The lead intrusion may have a height that is about ⅕ to about ½ the height of a lead finger, a width that is about ⅕ to about 1/2 the width of a lead finger, and a depth that is about ¼ to about ¾ the length of the externally exposed lower surface of a lead finger. The lead intrusion increases the area on the lead finger that contacts a bond material, such as solder, and therefore increase the strength of the joint between the semiconductor package and an external surface to which the lead finger is connected (i.e., a PCB). The lead intrusion allows out gassing during reflow of the bond material which may reduce voiding. The lead intrusion can also increase bond joint reliability by providing longer crack propagation length. | 10-22-2009 |
20090273063 | SEMICONDUCTOR DEVICE - One embodiment provides a semiconductor device including a carrier, a first chip attached to the carrier, a structured dielectric coupled to the chip and to the carrier, and a conducting element electrically connected with the chip and extending over a portion of the structured dielectric. The conducting element includes a sintered region. | 11-05-2009 |
20090273064 | Semiconductor device and inspection method therefor - A semiconductor device includes a circuit block formed in a peripheral edge portion of a semiconductor chip, a circuit block pad formed on the circuit block providing an electrical connection for said circuit block, and a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and electrically connected to a lead frame by a bonding wire, the laterally offset bonding pad thereby functioning as a substitute wire bonding pad for the circuit block. | 11-05-2009 |
20090294932 | LEADFRAME HAVING DELAMINATION RESISTANT DIE PAD - A lead frame ( | 12-03-2009 |
20090294933 | Lead Frame and Chip Package Structure and Method for Fabricating the Same - The present invention discloses a lead frame and chip package structure, which comprises a plurality of leads including a plurality of inner leads and a plurality of outer leads; a plurality of chips arranged on a portion of the inner leads; a plurality of connecting wires electrically connecting the chips to the other inner leads; a support member arranged on the lower surface of the inner leads and having a fillister with an opening, wherein the backside of the opening faces the inner leads; and a resin encapsulant covering the leads, the chips, the connecting wires and the support member, and filling up the fillister with a portion of the outer leads and a portion of the surface of the support member being revealed. Further, the present invention also discloses a method for fabricating a lead frame and chip package structure, whereby the quality of a chip package is promoted. | 12-03-2009 |
20090302441 | COL (CHIP-ON-LEAD) MULTI-CHIP PACKAGE - A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, tile thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant. Therefore, the internal leads of the leads without downset bends in the encapsulant can balance the upper and lower mold flows and carry more chips without shifting nor tilting. | 12-10-2009 |
20090309198 | INTEGRATED CIRCUIT PACKAGE SYSTEM - An integrated circuit package system includes a leadframe with leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to the down set inner leads. Depositing an encapsulating material to prevent exposure of the down set inner leads. | 12-17-2009 |
20090315159 | LEADFRAMES HAVING BOTH ENHANCED-ADHESION AND SMOOTH SURFACES AND METHODS TO FORM THE SAME - Example leadframes having both rough surfaces to enhance adhesion to molding compounds and selectively smoothed surfaces to enhance bonding wire performance, and methods to form the same are disclosed. A disclosed example packaged integrated circuit chip includes a bond wire, a leadframe having a die pad coupled to a carrier rail, and an inner lead coupled to an outer lead via a dam bar, the inner lead having a first portion having a rough surface and a second portion having a smoothed surface, a first end of the bond wire attached to the second portion of the inner lead, an integrated circuit attached to the die pad, a second end of the bond wire attached to a pad disposed on the integrated circuit, and a molding compound to encapsulate the inner lead, the integrated circuit and the bond wire. | 12-24-2009 |
20090315160 | PREFABRICATED LEAD FRAME AND BONDING METHOD USING THE SAME - A prefabricated lead frame to bond a chip and a substrate, and a bonding method using the prefabricated lead frame. The prefabricated lead frame includes an inner ring, an outer ring, and a plurality of wires, wherein inner ends and outer ends of the wires are respectively connected to the inner ring and the outer ring, and the prefabricated lead frame has a wire shape corresponding to a chip and a substrate to be bonded. The prefabricated lead frame may be manufactured in batch production to increase the manufacturing efficiency of semiconductor devices, and the prefabricated lead frame may be used instead of a general wire bonding process. | 12-24-2009 |
20090315161 | DIE ATTACH METHOD AND LEADFRAME STRUCTURE - In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure). The width of at least some of these tailed lead traces in a region that overlies their associated contact post is narrower than their associated contact post. Thus, these narrowed lead traces have extensions that extend beyond their associated contact posts. The extensions provide additional surface area that gives an adhesive applied to the narrowed lead trace (as for example by stamping) room to bleed (flow) along the top surface of the lead trace on both sides of the associated contact pad. | 12-24-2009 |
20090321899 | INTEGRATED CIRCUIT PACKAGE SYSTEM STACKABLE DEVICES - An integrated circuit package system includes: providing a finger lead having a side with an outward exposed area and an inward exposed area separated by a lead cavity; positioning a chip adjacent the finger lead and connected to the finger lead; and a stack encapsulant encapsulating the chip and the finger lead with the outward exposed area and the inward exposed area of the finger lead substantially exposed. | 12-31-2009 |
20090321900 | SEMICONDUCTOR DEVICE - A semiconductor device has a substrate, a semiconductor element, an electrode lead, and a sealing resin portion. The substrate has a main surface on which a circuit pattern is formed. The semiconductor element has first and second surfaces, and is arranged on the substrate such that the first surface faces the main surface. The electrode lead has one end joined to the circuit pattern and the other end joined by soldering to the second surface. The other end has a plurality of portions divided from each other. The sealing resin portion seals the semiconductor element and the electrode lead. Thus, there can be provided a semiconductor device that has relieved thermal stress at a joining portion of the electrode lead, and therefore is less subject to fatigue failure. | 12-31-2009 |
20100001382 | MANUFACTURING METHOD FOR INTEGRATING A SHUNT RESISTOR INTO A SEMICONDUCTOR PACKAGE - An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads. | 01-07-2010 |
20100006991 | PACKAGING INTEGRATED CIRCUITS FOR HIGH STRESS ENVIRONMENTS - One aspect of the invention pertains to a semiconductor package suitable for use in high stress environments, such as ones involving high pressures, temperatures and/or corrosive substances. In this aspect, a die and leadframe are fully encapsulated in a first plastic casing. The first plastic casing is fully encapsulated in turn with a second plastic casing. The two casings have different compositions. The first plastic casing, for example, may be made of a thermoset plastic material and the second plastic casing may be made of a thermoplastic material. The first plastic casing may have recesses, indentations and/or slots suitable for securing it to the second plastic casing. In some embodiments, a corrosion resistant coating is added to the second plastic casing. Methods for forming semiconductor packages suitable for use in high stress environments are also described. | 01-14-2010 |
20100025828 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND LEAD FRAME - To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part. | 02-04-2010 |
20100032816 | Electronic Device and Method of Manufacturing Same - This application relates to a semiconductor device, the semiconductor device comprising a metal carrier, an insulating foil partially covering the metal carrier, a first chip attached to the metal carrier over the insulating foil, and a second chip attached to the metal carrier over a region not covered by the insulating foil. | 02-11-2010 |
20100052118 | MICRO-LAYERED LEAD FRAME SEMICONDUCTOR PACKAGES - Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame with a customized array of lands at the bottom of the package. The lands are connected to a series of leads that are located within the perimeter of the lands. The leads can be routed according to the requirements of each specific IC die which they support and therefore can support both a single die and multiple die in the semiconductor package. Such a configuration provides a flexible routing for optimized layout, a maximized package density, and a higher input/output capability with a smaller package size. Other embodiments are also described. | 03-04-2010 |
20100052119 | Molded Ultra Thin Semiconductor Die Packages, Systems Using the Same, and Methods of Making the Same - Disclosed are molded ultra-thin semiconductor die packages, systems that incorporate such packages, and methods of making such packages. An exemplary package comprises a leadframe having an aperture formed between the leadframe's first and second surfaces, and a plurality of leads disposed adjacent to the aperture. The package further comprises a semiconductor disposed in the aperture of the leadframe with its top surface substantially flush with the leadframe's first surface, and at least one gap between at least one side surface of the semiconductor die and at least one lead of the leadframe. A body of electrically insulating material is disposed in the at least one gap. A plurality of conductive members interconnect leads of the leadframe with conductive regions on the die's top surface, with at least one conductive member having a portion disposed over at least a portion of the body of insulating material. | 03-04-2010 |
20100052120 | SEMICONDUCTOR DEVICE HAVING A SUSPENDED ISOLATING INTERCONNECT - A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block. | 03-04-2010 |
20100052121 | SEMICONDUCTOR SYSTEM-IN-A-PACKAGE CONTAINING MICRO-LAYERED LEAD FRAME - Semiconductor packages that contain a system-in-a-package and methods for making such packages are described. The semiconductor packages contain a first semiconductor die resting on a middle of a land pad array, a second die disposed over the first die and resting on routing leads that are connected to the land pad array, a third die resting on the backside of the second die and connected to the land pad array by wire bonds, and a passive device and/or a discrete device resting on device pads. The packages also contain thermal pads which operate as a heat sink. The land pad array is formed from etching the leadframe. The semiconductor packages have a full land pad array with a thin package size while having a system-in-a-package design. Other embodiments are also described. | 03-04-2010 |
20100072584 | COPPER ALLOY SHEET FOR ELECTRIC AND ELECTRONIC PARTS - A Cu—Fe—P alloy sheet that is provided with the high strength and with the improved resistance of peel off of oxidation film, in order to deal with problems such as package cracks and peeling, is provided. A copper alloy sheet for electric and electronic parts according to the present invention is a copper alloy sheet containing Fe: 0.01 to 0.50 mass % and P: 0.01 to 0.15 mass %, respectively, with the remainder of Cu and inevitable impurities. A centerline average roughness Ra is 0.2 μm or less and a maximum height Rmax is 1.5 μm or less, and Kurtosis (degree peakedness) Rku of roughness curve is 5.0 or less, in measurement of the surface roughness of the copper alloy sheet in accordance with JIS B0601. | 03-25-2010 |
20100078782 | COATING COMPOSITION AND A METHOD OF COATING - A coating composition including a compound having a first molecular group or a first combination of atoms, the first molecular group or the first combination of atoms capable of bonding to an oxidizable metal or a metal oxide, and a second molecular group or a second combination of atoms, the second molecular group or the second combination of atoms capable of interacting with a precursor of a polymer so the compound and the polymer are bound together. | 04-01-2010 |
20100084748 | THIN FOIL FOR USE IN PACKAGING INTEGRATED CIRCUITS - Methods for minimizing warpage of a welded foil carrier structure used in the packaging of integrated circuits are described. Portions of a metallic foil are ultrasonically welded to a carrier to form a foil carrier structure. The ultrasonic welding helps define a panel in the metallic foil that is suitable for packaging integrated circuits. Warpage of the thin foil can be limited in various ways. By way of example, an intermittent welding pattern that extends along the edges of the panel may be formed. Slots may be cut to define sections in the foil carrier structure. Materials for the metallic foil and the carrier may be selected to have similar coefficients of thermal expansion. An appropriate thickness for the metallic foil and the carrier may be selected, such that the warpage of the welded foil carrier structure is limited when the foil carrier structure is subjected to large increases in temperature. Foil carrier structures for use in the above methods are also described. | 04-08-2010 |
20100096734 | THERMALLY IMPROVED SEMICONDUCTOR QFN/SON PACKAGE - A semiconductor device without cantilevered leads uses conductive wires ( | 04-22-2010 |
20100102422 | SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes depositing a mask of low melting point material on a surface of the semiconductor device; depositing a layer to be structured relative to the mask; and removing the mask of low melting point material. | 04-29-2010 |
20100123225 | Semiconductor Die Structures for Wafer-Level Chipscale Packaging of Power Devices, Packages and Systems for Using the Same, and Methods of Making the Same - Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention. | 05-20-2010 |
20100127361 | ENCAPSULANT INTERPOSER SYSTEM WITH INTEGRATED PASSIVE DEVICES AND MANUFACTURING METHOD THEREFOR - A method of manufacturing a semiconductor package system including: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer. | 05-27-2010 |
20100127362 | SEMICONDUCTOR PACKAGE HAVING ISOLATED INNER LEAD - A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip. A jumping wire electrically connecting the isolated inner lead and the external lead is adjacent to the second side to achieve the redistribution of pin assignments without affecting wire-bonding. Especially, this package can be applied for multi-chip stacking. | 05-27-2010 |
20100133665 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; and removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed. | 06-03-2010 |
20100133666 | DEVICE INCLUDING A SEMICONDUCTOR CHIP AND METAL FOILS - A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner. | 06-03-2010 |
20100133667 | POWER SEMICONDUCTOR MODULE - A wiring process between the provided power semiconductor module and the external circuit is simple. In the power semiconductor module, a power semiconductor element and a cylindrical conductor are joined to one surface of a lead frame. An opening of the cylindrical conductor is exposed at a surface of transfer molding resin. Sealing with the transfer molding resin is performed such that terminal portions of the lead frame protrude from peripheral side portions of the transfer molding resin. The cylindrical conductor is conductive with a control circuit. The terminal portions of the lead frame are each conductive with a main circuit. | 06-03-2010 |
20100133668 | Semiconductor device and manufacturing method thereof - The present invention relates to a semiconductor device, and more particularly to a manufacturing method for said semiconductor device. The semiconductor device comprises a die that connects with a substrate or a lead frame via an adhesion layer, a metal layer, and/or a back metal layer. Furthermore, the adhesion layer can be made of aluminum, and the die can connect with the substrate or the lead frame by ultrasonic bonding technology, which can avoid heat damaging the die during the manufacturing process. | 06-03-2010 |
20100148325 | Semiconductor Dice with Backside Trenches Filled With Elastic Material For Improved Attachment, Packages Using the Same, and Methods of Making the Same - Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice. | 06-17-2010 |
20100148326 | Thermally Enhanced Electronic Package - According to one embodiment, an electronic package includes a semiconductor die, a heat sink and a metallization layer interposed between the semiconductor die and the heat sink. The metallization layer attaches the semiconductor die to the heat sink. The metallization layer has a thickness of about 5 μm or less and a thermal conductivity of about 60 W/m·K or greater. | 06-17-2010 |
20100155913 | THERMALLY ENHANCED THIN SEMICONDUCTOR PACKAGE - A semiconductor die package is disclosed. The semiconductor die package includes a semiconductor die comprising an input at a first top semiconductor die surface and an output at a second bottom semiconductor die surface. A leadframe having a first leadframe surface and a second leadframe surface opposite the first leadframe surface is in the semiconductor die package and is coupled to the first top semiconductor die surface. A clip having a first clip surface and a second clip surface is coupled to the second bottom semiconductor die surface. A molding material having exterior molding material surfaces covers at least a portion of the leadframe, the clip, and the semiconductor die. The first leadframe surface and the first clip surface are exposed by the molding material, and the first leadframe surface, the first clip surface, and the exterior molding material surfaces of the molding material form exterior surfaces of the semiconductor die package. | 06-24-2010 |
20100187663 | METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE THEREFOR - A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components. | 07-29-2010 |
20100187664 | ELECTRICAL CONNECTIVITY FOR CIRCUIT APPLICATIONS - According to example configurations herein, a leadframe includes a connection interface. The connection interface can be configured for attaching an electrical circuit to the leadframe. The leadframe also can include a conductive path. The conductive path in the leadframe provides an electrical connection between a first electrical node of the electrical circuit and a second electrical node of the electrical circuit. Prior to making the connection between the electrical circuit and the leadframe, the first electrical node and the second electrical node can be electrically isolated from each other. Subsequent to making connection of the electrical circuit with the leadframe, the conductive path of the leadframe electrically connects the first electrical node and the second electrical node together. Accordingly, the leadframe provides connectivity between nodes of an electrical circuit in lieu of having to provide such connectivity at, for example, a metal interconnect layer of an integrated circuit device. | 07-29-2010 |
20100200969 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion. | 08-12-2010 |
20100213586 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package is constituted of a semiconductor chip, a rectangular-shaped stage having the semiconductor chip mounted on the surface, a plurality of leads which are aligned in the periphery of the stage and which are electrically connected to the semiconductor chip, and a resin mold which seals the semiconductor chip, the stage, and the leads therein while externally exposing the backside of the stage on the lower surface thereof. In particular, at least one protrusion is further formed on the upper surface or the lower surface of the resin mold at a position within the outer portion of the resin mold disposed outside the sealed portion of the resin mold. The height of the outer portion of the resin mold having the protrusion is larger than the sum of the thickness of the stage and the thickness of the sealed portion of the resin mold. | 08-26-2010 |
20100219515 | LEAD FRAME - A lead frame includes a plurality of leads electrically connected to a semiconductor chip and a lead lock including a base layer disposed over the plurality of the leads and formed of a material having a coefficient of thermal expansion similar to that of inner leads. An adhesive layer is disposed between the base layer and the plurality of leads to fix the plurality of leads and adhere the base layer to the leads. At least one line electrically connects the semiconductor chip to the base layer of the lead lock. Since regions for bus bars are replaced by the lead lock and are removed, the lead frame can be miniaturized and has superior thermal stability and dimension stability. | 09-02-2010 |
20100230790 | Semiconductor Carrier for Multi-Chip Packaging - A power semiconductor product includes a carrier attached to a leadframe. An insulating layer is formed on the carrier and two or more conductive plates are patterned on the insulating layer. A control IC is attached to one of these conductive plates and a power transistor is attached to the other. Bond wires connect the first conductive plate to a pin on the leadframe. Additional bond wires attach the control IC to pins on the leadframe and form connections between the control IC and the power transistor. | 09-16-2010 |
20100244209 | CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are: a circuit device demonstrating an improved connection reliability while being mounted; and a method for manufacturing the same. The circuit device of the present invention includes: an island; leads arranged around the island, each lead having a lower surface and a side surface exposed to the outside; and a semiconductor element mounted on the island and electrically connected to the leads through thin metal wires. Furthermore, the exposed end portion of the lead is formed to spread toward the outside. By forming the lead in this manner, the area where the lead comes into contact with a brazing filler material is increased, thus improving the connection strength therebetween. | 09-30-2010 |
20100258920 | MANUFACTURING METHOD OF ADVANCED QUAD FLAT NON-LEADED PACKAGE - The manufacturing method of advanced quad flat non-leaded packages includes performing a pre-cutting process prior to the backside etching process for defining the contact terminals. The pre-cutting process ensures the isolation of individual contact terminals and improves the package reliability. | 10-14-2010 |
20100264525 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADED PACKAGE AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a frame; attaching a leaded package having leads adjacent the frame wherein the leads extend towards a side opposite the frame; and applying a package encapsulant over the leaded package having the leads partially exposed opposite the frame. | 10-21-2010 |
20100270663 | Power Lead-on-Chip Ball Grid Array Package - A packaging assembly ( | 10-28-2010 |
20100270664 | Epoxy resin composition for encapsulating semiconductor device and semiconductor device using the same - An epoxy resin composition for encapsulating a semiconductor device, the epoxy resin composition including an epoxy resin, a curing agent, and one or more inorganic fillers, the one or more inorganic fillers including prismatic cristobalite, the prismatic cristobalite being present in the epoxy resin composition in an amount of about 1 to about 50% by weight, based on the total weight of the epoxy resin composition. | 10-28-2010 |
20100289127 | SEMICONDUCTOR DEVICE - A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead. | 11-18-2010 |
20100314728 | IC PACKAGE HAVING AN INDUCTOR ETCHED INTO A LEADFRAME THEREOF - A leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The leadframe having a spiral inductor etched therein. | 12-16-2010 |
20100320578 | PACKAGED IC DEVICE COMPRISING AN EMBEDDED FLEX CIRCUIT, AND METHODS OF MAKING THE SAME - A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material. | 12-23-2010 |
20110001223 | LEADFRAME, LEADFRAME TYPE PACKAGE AND LEAD LANE - A leadframe for a leadframe type package includes a chip base, and leads constituting lead lanes. One lead lane includes a pair of first differential signal leads, a pair of second differential signal leads, a pair of third differential signal leads between which and the pair of first differential signal leads is arranged the pair of second differential signal leads, a first power lead arranged between the pair of first and second differential signal leads, a second power lead arranged between the pair of second and third differential signal leads, and a third power lead between which and the second power lead is the pair of third differential signal leads. A voltage provided by the first power lead is less than a voltage provided by the second power lead, and the voltage provided by the second power lead is substantially equal to a voltage provided by the third power lead. | 01-06-2011 |
20110001224 | LEAD FRAME ROUTED CHIP PADS FOR SEMICONDUCTOR PACKAGES - A redistributed lead frame for use in a molded plastic semiconductor package is formed from an electrically conductive substrate by a sequential metal removal process. The process includes patterning a first side of the substrate to form an array of lands separated by channels; disposing a first molding compound within those channels; patterning a second side of the substrate to form an array of chip attach sites and routing circuits electrically interconnecting the array of lands and the array of chip attach sites; directly electrically interconnecting input/output pads on a semiconductor device to the chip attach sites; and encapsulating the semiconductor device, the array of chip attach sites and the routing circuits with a second molding compound. This process is particularly suited for the manufacture of chip scale packages and very thin packages. | 01-06-2011 |
20110006409 | NICKEL-TITANUM CONTACT LAYERS IN SEMICONDUCTOR DEVICES - Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds (or alloys) and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit having a drain on the backside of the substrate, a TiNi contact layer contacting the drain on the backside of the substrate, a soldering layer on the contact layer, an oxidation reducing layer on the soldering layer, a solder bump on the soldering layer, and a lead frame attached to the solder bump. The combination of the Ti and Ni materials in the contact layer exhibits many features not found in the Ti and Ni materials alone, such as reduced backside on-resistance, ability to form a silicide with the Si substrate at lower temperatures, reduced wafer warpage, increased ductility for improved elasticity, and good adhesion properties. Other embodiments are described. | 01-13-2011 |
20110012240 | Multi-Connect Lead - This disclosure describes a multi-connect lead providing multiple connections using one external pin. In one embodiment, a lead frame for a lead-frame-based chip package includes a multi-connect lead that uses one external pin and enables multiple electrical connections to an integrated circuit die. | 01-20-2011 |
20110018110 | ELECTRONIC DEVICE, METHOD OF PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE - A semiconductor device includes n | 01-27-2011 |
20110024883 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND LEAD FRAME - To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part. | 02-03-2011 |
20110031596 | NICKEL-TITANUM SOLDERING LAYERS IN SEMICONDUCTOR DEVICES - Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds or alloys and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit, a contact layer contacting the substrate, a TiNi-containing soldering layer on the contact layer, an oxidation prevention layer on the soldering layer, a solder bump on the soldering layer, and a lead frame or PCB attached to the solder bump. The combination of the Ti and Ni materials in the soldering layer exhibits many features not found in the Ti and Ni materials alone, such as reduced wafer warpage, increased ductility for improved elasticity, decreased consumption of the Ni in the soldering layer, and decreased manufacturing costs. Other embodiments are described. | 02-10-2011 |
20110037152 | DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing an integrated circuit; mounting a lead on the periphery of the integrated circuit; connecting the integrated circuit to the lead with an interconnect; and forming a conformable material by pressing the conformable material on the integrated circuit, the lead, and the interconnect. | 02-17-2011 |
20110049686 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package is provided. The semiconductor package includes a carrier, a die, a metal sheet and a molding compound. The die is disposed on the carrier. The metal sheet has a first portion and a second portion, wherein a receiving space is defined by the first portion and the second portion, and the second portion is electrically connected to the carrier. The molding compound covers the die and the receiving space is filled by at least part of the molding compound. | 03-03-2011 |
20110062563 | NON-VOLATILE MEMORY WITH REDUCED MOBILE ION DIFFUSION - Mobile ion diffusion causes a shift in the threshold voltage of non-volatile storage elements in a memory chip, such as during an assembly process of the memory chip. To reduce or avoid such shifts, a coating can be applied to a printed circuit board substrate or a leader frame to which the memory chip is surface mounted. An acrylic resin coating having a thickness of about 10 μm may be used. A memory chip is attached to the coating using an adhesive film. Stacked chips may be used as well. Another approach provides metal barrier traces over copper traces of the printed circuit board, within a solder mask layer. The metal barrier traces are fabricated in the same pattern as the copper traces but are wider so that they at least partially envelop and surround the copper traces. Corresponding apparatuses and fabrication processes are provided. | 03-17-2011 |
20110062564 | SEMICONDUCTOR DIE CONTAINING LATERAL EDGE SHAPES AND TEXTURES - Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described. | 03-17-2011 |
20110062565 | METHOD FOR MANUFACTURING A MICROELECTRONIC PACKAGE COMPRISING AT LEAST ONE MICROELECTRONIC DEVICE - A method for manufacturing a microelectronic package ( | 03-17-2011 |
20110068442 | RESIN-SEALED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a resin-sealed semiconductor device, an inner lead including a bend portion formed by lifting has a protruding shape located on one side and an inclined vertical surface shape located on the other side (inside) in an external connection terminal direction. A cutaway portion is provided along the bend portion and an external connection terminal. A height of an upper surface portion of the inner lead is higher than a height of an upper surface of a semiconductor element. The inner lead is provided in a substantially central portion of a die pad so that the inclined vertical surface shape is parallel to a side of a die pad which includes a thin portion located in a side surface portion and an exposure portion located on a bottom surface. | 03-24-2011 |
20110068443 | Thermally Improved Semiconductor QFN/SON Package - A semiconductor device without cantilevered leads uses conductive wires ( | 03-24-2011 |
20110084369 | DEVICE INCLUDING A SEMICONDUCTOR CHIP AND A CARRIER AND FABRICATION METHOD - A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier. | 04-14-2011 |
20110089544 | PACKAGE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE - A package for mounting a semiconductor chip is provided. The package includes a frame member including an aperture, a first lead including a portion connectable to the semiconductor chip and a portion projecting outside from an outer sidewall of the frame member, and a second lead including a portion connectable to the semiconductor chip and a portion projecting inside the aperture from an inner sidewall of the frame member. | 04-21-2011 |
20110095405 | LEAD FRAME AND INTERMEDIATE PRODUCT OF SEMICONDUCTOR DEVICE - In a lead frame used for manufacturing a semiconductor device by forming a circuit pattern group including unit lead frames having plural upper side terminal parts in the periphery of a semiconductor element mounting region in one line or plural lines and an outer frame surrounding the circuit pattern group in a state of having a gap in a lead frame material and then mounting a semiconductor element every the unit lead frame and carrying out necessary wiring and enclosing the entire surface of the circuit pattern group in which the semiconductor element is mounted and a part of the outer frame with a resin from an upper surface side and further etching from a lower surface side and forming lower side terminal parts joined to the upper side terminal parts of the circuit pattern group, the circuit pattern group and the outer frame are had and the inner edge of the outer frame is formed in an uneven portion in plan view and bonding between the resin and the outer frame is enhanced. | 04-28-2011 |
20110121439 | SEMICONDUCTOR DEVICE WITH PROTRUDING COMPONENT PORTION AND METHOD OF PACKAGING - A semiconductor package device having a protruding component portion and a method of packaging the semiconductor device is disclosed. The semiconductor device has a component, such as a leadframe, and a packaging mold body. The packaging mold body is formed around a portion of the component and a recess is formed in the packaging mold body adjacent the protruding portion of the component to prevent the protruding portion of the component from damaging other adjacent and abutting semiconductor devices. | 05-26-2011 |
20110127656 | SEMICONDUCTOR-DEVICE MOUNTED BOARD AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor-device mounted board, connection terminals are formed on electrode pads on a semiconductor integrated circuit respectively. A first insulating layer is formed to cover the connection terminals. A plate-like medium having a rough surface is disposed on the first insulating layer. The rough surface of the plate-like medium is pressed onto the first insulating layer so that a part of each of the connection terminals is exposed. A semiconductor device is produced by removing the plate-like medium. A second insulating layer is formed to cover side surfaces of the semiconductor device. A wiring pattern is formed to cover surfaces of the first and second insulating layers, the wiring pattern being electrically connected to the exposed connection terminal parts. | 06-02-2011 |
20110133318 | SiP SUBSTRATE - Disclosed in this specification is a system-in-a-package substrate that includes an interconnect substrate for permitting finely pitched connections to be made to an integrated circuit. The interconnect substrate includes a central region on its upper surface for receiving the integrated circuit. The interconnect substrate also has interconnections that electrically connect the finely pitched contacts on the upper surface to larger pitched contacts on the lower surface. The larger pitched contacts connect to a conductive trace frame. The resulting assembly is encased in a molding compound along with a plurality of other devices which are configured to interact with one other through the conductive trace. | 06-09-2011 |
20110169144 | DIE PACKAGE INCLUDING MULTIPLE DIES AND LEAD ORIENTATION - A semiconductor die package and method of making the package. The package may have four semiconductor dies with one or more internally connected switch nodes, and may form a dual output or phase synchronous buck converter. The package may have control leads at opposite sides of the package from each other. Furthermore, the package may contain high side semiconductor dies that are oriented perpendicular to low side semiconductor dies. | 07-14-2011 |
20110169145 | MANUFACTURING METHOD OF LEAD FRAME SUBSTRATE AND SEMICONDUCTOR APPARATUS - A lead frame substrate, including: a metal plate with a first surface and a second surface; a connection post formed on the first surface; wiring formed on the second surface; and a pre-molding resin layer, in which a thickness of the pre-molding resin layer is the same as a height of the connection post. | 07-14-2011 |
20110169146 | CONTACTLESS COMMUNICATION MEDIUM - Even when a mold part of an IC module is exposed from an opening provided in a substrate of an inlay, occurrence of malfunction, communication disorders or the like of the IC module due to the influence of an external impact or the like is prevented. By combining a sealing member including an insulating layer and an adhesive layer in a stacked manner to a shape covering a mold part of the IC module, occurrence of malfunction, communication disorders or the like of the IC module is prevented even if there is an influence of an external impact or the like. Meanwhile, by providing a sealing member, concentration of stress on the mold part in a line pressure test is alleviated by limiting the size of the sealing member, and also occurrence of cracks in the mold part can be prevented. | 07-14-2011 |
20110180913 | METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP - Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer. A corresponding bump may be disposed on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. Other embodiments are also described and claimed. | 07-28-2011 |
20110193204 | SEMICONDUCTOR DEVICE - A semiconductor package includes a substrate including a substrate body which has an upper surface and a lower surface facing away from the upper surface, first connection pads which are formed on the upper surface, and a second connection pad which is formed on the upper surface to be separated from the first connection pads, a semiconductor chip including first bonding pads and a second bonding pad, connection members connecting the first connection pads and the first bonding pads, and a resistor member connecting the second connection pad and the second bonding pad. | 08-11-2011 |
20110193205 | SEMICONDUCTOR DEVICE PACKAGES HAVING STACKING FUNCTIONALITY AND INCLUDING INTERPOSER - A semiconductor device package with an interposer, which serves as an intermediate or bridge circuit of various electrical pathways in the package to electrically connect any two or more electrical contacts, such as any two or more electrical contacts of a substrate and a chip. In particular, the interposer provides electrical pathways for simplifying a circuit layout of the substrate, reducing the number of layers of the substrate, thereby reducing package height and manufacturing cost. Furthermore, the tolerance of the circuit layout can be increased or maintained, while controlling signal interference between adjacent traces and accommodating high density circuit designs. Moreover, the package is suitable for a PoP process, where a profile of top solder balls on the substrate and a package body can be varied according to particular applications, so as to expose at least a portion of each of the top solder balls and electrically connect the package to another device through the exposed, top solder balls. | 08-11-2011 |
20110198738 | METHOD FOR MANUFACTURING A MICROELECTRONIC PACKAGE COMPRISING AT LEAST ONE MICROELECTRONIC DEVICE - A method for manufacturing a microelectronic package ( | 08-18-2011 |
20110210432 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes: a lead group including a plurality of leads; a plurality of semiconductor memory chips stacked in a step shape on the lead group; and a resin mold section that seals the semiconductor memory chips. One end of a third lead and the other end of a second lead is connected by a metal wire for relay crossing over a first lead section included in the lead group. The metal wire for relay is provided in a space between the semiconductor memory chips stacked in the step shape and the lead group. | 09-01-2011 |
20110215451 | Stacked Semiconductor Packages - Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device. | 09-08-2011 |
20110215452 | SEMICONDUCTOR PACKAGE, SUBSTRATE, ELECTRONIC COMPONENT, AND METHOD OF MOUNTING SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor device and a substrate over which the semiconductor device is mounted, wherein the substrate includes: an internal ground electrode, formed in the one side of the substrate, which is connected to the semiconductor device; two external ground electrodes, located at the opposite side of the substrate opposite to the one side of the substrate, which are electrically connected to the internal ground electrode; at least one sub-ground electrode, located between the two external ground electrodes, when seen in a plan view, and located at the opposite side of the substrate, which is electrically connected to the internal ground electrode; an internal input electrode, formed in the one side of the substrate, which is connected to the semiconductor device; and an internal output electrode, formed in the one of the substrate, which is connected to the semiconductor device. | 09-08-2011 |
20110215453 | MICROELECTRONIC DIE PACKAGES WITH LEADFRAMES, INCLUDING LEADFRAME-BASED INTERPOSER FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads. | 09-08-2011 |
20110227204 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. An encapsulating body encapsulates the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location. At least one of the second conducting element, third conducting element, and fourth conducting element extend over the semiconductor chip and the encapsulating body. | 09-22-2011 |
20110233738 | SEMICONDUCTOR DEVICE AND LEAD FRAME - A semiconductor device including a semiconductor element, a die pad of a plane size smaller than that of the semiconductor element, a plurality of hanging leads extending from the die pad, and sealing resin for covering the semiconductor element, the die pad, and the hanging leads. The width of a first main surface of each hanging lead, integrated with the mounting surface of the die pad, is smaller than the width of a second main surface thereof, integrated with the opposite surface of the die pad. | 09-29-2011 |
20110233739 | SEMICONDUCTOR STRUCTURE, MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE - Disclosed is a semiconductor structure including a semiconductor substrate including an electronic circuit which is provided in a predetermined region of the semiconductor substrate, a wiring provided on the semiconductor substrate in a region outside of the predetermined region, an external connection electrode provided on the wiring, a sealing resin which covers a side surface of the external connection electrode and a wall which intervenes between the electronic circuit and the sealing resin. | 09-29-2011 |
20110233740 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die. | 09-29-2011 |
20110241187 | LEAD FRAME WITH RECESSED DIE BOND AREA - A lead frame having a recessed die bond area. The lead frame has top and bottom surfaces and a first lead frame thickness defined as the distance between the top and bottom surfaces. The lead frame has a die bond area surface located within a reduced die bond area. A second thickness is defined as the distance between the die bond area surface and the bottom surface. The second lead frame thickness is less than the first lead frame thickness such that a semiconductor die disposed and attached to the die bond area surface has a reduced overall package thickness. A side wall formed between the die bond area surface and the top surface contains the adhesive material used to attach the die, which reduces adhesive bleeding and prevents wire bonding contamination. | 10-06-2011 |
20110241188 | GRANULAR EPOXY RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR, SEMICONDUCTOR DEVICE USING THE SAME AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Disclosed is a granular epoxy resin composition for encapsulating a semiconductor used for a semiconductor device obtained by encapsulating a semiconductor element by compression molding, wherein, in the particle size distribution as determined by sieving the whole epoxy resin composition for encapsulating a semiconductor using JIS standard sieves, the ratio of particles having a size of 2 mm or greater is not more than 3% by mass, the ratio of particles having a size of 1 mm or greater, but less than 2 mm is from 0.5% by mass or more to 60% by mass or less, and the ratio of microfine particles having a size of less than 106 μm is not more than 5% by mass. | 10-06-2011 |
20110260304 | LEADFRAME FOR ELECTRONIC COMPONENTS - The present invention specifies a leadframe for electronic components and a corresponding manufacturing process, in which the bonding islands are formed by welding individual, prefabricated segments of a bonding-capable material onto a stamped leadframe. | 10-27-2011 |
20110272792 | DIE BACKSIDE STANDOFF STRUCTURES FOR SEMICONDUCTOR DEVICES - Standoff structures that can be used on the die backside of semiconductor devices and methods for making the same are described. The devices contain a silicon substrate with an integrated circuit on the front side of the substrate and a backmetal layer on the backside of the substrate. Standoff structures made of Cu of Ni are formed on the backmetal layer and are embedded in a Sn-containing layer that covers the backmetal layer and the standoff structures. The standoff structures can be isolated from each other so that they are not connected and can also be configured to substantially mirror indentations in the leadframe that is attached to the Sn-containing layer. Other embodiments are described. | 11-10-2011 |
20110272793 | LEAD FRAME, SEMICONDUCTOR APPARATUS USING THIS LEAD FRAME, INTERMEDIATE PRODUCT THEREOF AND MANUFACTURING METHOD THEREOF - In a lead frame for a semiconductor apparatus 10, including plural terminals 13, one portions of the terminals 13 being sealed with a resin, a resin-sealed portion 16 of the terminal 13 has a polygonal columnar shape that is pentagonal or more or a deformed columnar shape having at least one notch or groove part extending vertically in a periphery. This resin-sealed portion 16 is formed by etching processing or press processing, and an exposed portion 18 of lower half of the terminal 13 is formed by the etching processing. | 11-10-2011 |
20110272794 | PRE-MOLDED CLIP STRUCTURE - A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed. | 11-10-2011 |
20110284997 | Chip-Exposed Semiconductor Device and Its Packaging Method - A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chi on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices. | 11-24-2011 |
20110284998 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKED DIE - An integrated circuit package system provides a leadframe having a short lead finger and a long lead finger, and the long lead finger and the short lead finger reside substantially within the same horizontal plane. A first die is placed in the leadframe. A second die is offset from the first die. The offset second die is attached over the first die and the long lead finger with an adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant. | 11-24-2011 |
20110304031 | SEMICONDUCTOR DEVICE EQUIPPED WITH BONDING WIRES AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE EQUIPPED WITH BONDING WIRES - Disclosed is a semiconductor device including a printed-circuit board which includes a plurality of first electrodes, a plurality of second electrodes and a semiconductor chip on which a plurality of first connection pads are aligned in a first line being disposed along an outer circumference side of a top surface and a plurality of second connection pads are aligned in a second line being disposed inside of and apart from the first line, when the semiconductor chip is seen from above, and any of the plurality of first connection pads are used for a power voltage terminal and a system reset terminal of the semiconductor device. | 12-15-2011 |
20110316130 | THIN SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a thin semiconductor package includes providing a lead frame with a removable substrate that has an attaching surface attached to a first surface of the lead frame. The lead frame is formed from an electrically conductive sheet and has leads that extend inwardly from a lead frame boundary towards a central region of the lead frame. A semiconductor die is mounted on the removable substrate at the central region. The semiconductor die has a connection pad surface with die pads on it, and the connection pad surface is attached to the attaching surface of the removable substrate. The lead frame and die are encapsulated with a first encapsulant so that the lead frame is sandwiched between the first encapsulant and the removable substrate. The removable substrate is removed from the lead frame to expose the first surface of the lead frame and then the die pads are electrically connected to respective ones of the leads. The die and lead frame then are encapsulated with a second encapsulant so that the lead frame and die are sandwiched between the first and second encapsulants. Part of the first encapsulant is then removed to reduce the thickness of the package and expose the leads. | 12-29-2011 |
20120001306 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface. | 01-05-2012 |
20120001307 | Lead Frame and Method For Manufacturing the Same - A lead frame comprises: a base metal layer; a copper plating layer, including one of a copper layer and an alloy layer including a copper, configured to plate the based metal layer to make a surface roughness; and an upper plating layer, including at least one plating layer including at least one selected from the group of a nickel, a palladium, a gold, a silver, a nickel alloy, a palladium alloy, a gold alloy, and a silver alloy, configured to plate the copper plating layer. | 01-05-2012 |
20120018859 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires. | 01-26-2012 |
20120018860 | METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a substrate for a semiconductor element including the steps of: providing a first photosensitive resin layer on a first surface of a metal plate; providing a second photosensitive resin layer on a second surface different from the first surface of the metal plate; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring pattern on the second surface of the metal plate; forming the connection post by performing an etching from the first surface to a midway of the metal plate; filling in a premold resin to a portion of the first surface where the connection post does not exist; processing so that a height of the connection post of the first surface is lower than a height of the premold resin surrounding the connection post; and forming the wiring pattern by performing an etching on the second surface. | 01-26-2012 |
20120025357 | LEADFRAME FOR IC PACKAGE AND METHOD OF MANUFACTURE - A leadframe for use in an integrated circuit (IC) package comprising a metal strip partially etched on a first side. In some embodiments, the leadframe may be selectively plated on the first side and/or on a second side. The leadframe may be configured for an IC chip to be mounted thereon and for a plurality of electrical contacts to be electrically coupled to the leadframe and the IC chip. | 02-02-2012 |
20120032314 | PACKAGE-ON-PACKAGE WITH FAN-OUT WLCSP - A package-on-package includes a package carrier; a semiconductor die assembled face-down to a chip side of the package carrier; a rewiring laminate structure between the semiconductor die and the package carrier; a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and an IC package mounted on the package carrier. The IC package and the semiconductor die are at least partially overlapped. | 02-09-2012 |
20120043650 | Packaging Integrated Circuits - An integrated circuit | 02-23-2012 |
20120061808 | SEMICONDUCTOR PACKAGES HAVING INCREASED INPUT/OUTPUT CAPACITY AND RELATED METHODS - A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided. | 03-15-2012 |
20120061809 | METHOD FOR MANUFACTURING SUBSTRATE FOR SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a substrate for a semiconductor element, the manufacturing method including the steps of: providing a first photosensitive resin layer at a first surface of a metal plate; providing a second photosensitive resin layer at a second surface of the metal plate different from the first surface; forming a first etching mask for forming a connection post on the first surface of the metal plate; forming a second etching mask for forming a wiring post on the second surface of the metal plate; forming the connection post by performing an etching on the first surface of the metal plate from a first surface side to a midway of the metal plate; applying a premold resin in liquid form to the first surface of the metal plate which underwent the etching on the first surface; forming a premold resin layer by solidifying the premold resin in liquid form being applied; and forming a wiring pattern by performing an etching on the second surface of the metal plate from a second surface side. | 03-15-2012 |
20120086111 | SEMICONDUCTOR DEVICE - The present invention reduces the occurrence of fracture in external terminal connecting sections and improves the reliability of secondary packaging of a semiconductor device. Specifically, the present invention provides a semiconductor device including a wiring board, a semiconductor chip mounted on one surface of the wiring board via a bonding member, and external electrodes formed on the other surface of the wiring board and electrically connected to the semiconductor chip. In the semiconductor device, a peripheral end of the bonding member is arranged in a position where the peripheral end does not overlap the external electrodes. | 04-12-2012 |
20120098110 | Supporting Body for a Semiconductor Component, Semiconductor Element and Method for Production of a Supporting Body - A carrier body for a semiconductor component, in particular for an optoelectronic semiconductor component, is specified. Said carrier body has a connecting layer and a conductor layer, which are connected to one another via main areas facing one another. The connecting layer, the conductor layer or both the connecting layer and the conductor layer has/have at least one thinned region in which the layer thickness of said layer(s) is less than the maximum layer thickness of said layer(s). The connecting layer is either completely electrically conductive and electrically insulated at least from parts of the conductor layer or it is electrically insulating at least in parts. Furthermore, a semiconductor component comprising the electrical connection conductor and also a method for producing the carrier body are specified. | 04-26-2012 |
20120104577 | SEMICONDUCTOR PACKAGE AND ELECTRONIC COMPONENT PACKAGE - A semiconductor package includes an IC chip including a pad array having at least four pads, the pads including a voltage input pad and a voltage output pad disposed at edges of the pad array, a driver transistor disposed between the voltage input pad and the voltage output pad to receive an input voltage from the voltage input pad and output an output voltage to the voltage output pad, disposed in contact with an outer edge of the element arrangement region; and at least four leads on which the IC chip is mounted by flip chip bonding, disposed corresponding to the pads, formed in a lead array, the leads including a voltage input lead electrically connected to the voltage input pad and a voltage output lead electrically connected to the voltage output pad, disposed at edges of the lead array. | 05-03-2012 |
20120104578 | Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. | 05-03-2012 |
20120112329 | CHIP PACKAGE - An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof. | 05-10-2012 |
20120126383 | METHOD FOR SEMICONDUCTOR LEADFRAMES IN LOW VOLUME AND RAPID TURNAROUND - An apparatus comprising a metallic leadframe including a pad and a plurality of leads. Each having a first and a parallel second surface and sidewalls normal to the surfaces. The pad and each lead having a core of a first metal and layers of a second metal different from the first metal on each surface. The first metal exposed at the sidewalls and at portions of the first surface of the pad. A semiconductor chip is assembled on the leadframe. Portions of the assembled chip and the leadframe are packaged in a polymeric encapsulation compound. | 05-24-2012 |
20120133033 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-ROW LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base structure having an intermediate lead with an intermediate concave side and an intermediate convex side, a peripheral lead with a peripheral concave side and a peripheral convex side, and a paddle with a paddle concave side and a paddle convex side; applying an inner multi-layer finish directly on the intermediate concave side, the peripheral concave side, and the paddle concave side; applying an outer multi-layer finish directly on the intermediate convex side, the peripheral convex side, and the paddle convex side; mounting an integrated circuit device over the inner multi-layer finish; attaching an interconnect directly to the inner multi-layer finish on the peripheral concave side and directly to integrated circuit device; and applying an encapsulation over the integrated circuit device, the interconnect, and the base structure, with the outer multi-layer finish exposed from the encapsulation. | 05-31-2012 |
20120133034 | LEAD FRAME FOR ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME - In a lead frame for an electronic component according to the present invention, a metal plate 3 is extended by a punch 5 into a hole 4 formed on a metal plate 2 and the two metal plates are connected on the inner surface of the hole 4, thereby improving a bonding strength while keeping the small size and thickness of the lead frame with a simple method. | 05-31-2012 |
20120146199 | SUBSTRATE FOR INTEGRATED CIRCUIT PACKAGE WITH SELECTIVE EXPOSURE OF BONDING COMPOUND AND METHOD OF MAKING THEREOF - A substrate for integrated circuit package is disclosed. The substrate comprises an electrically conductive leadframe having a first side and an opposing second side. The substrate has a first bonding compound disposed in a first recessed portion of the first side and a second bonding compound disposed in at least a portion of a second recessed portion of the leadframe, selectively exposing a selected area of the leadframe on the second side. In an exemplary embodiment, the second bonding compound is a photolithographic material. A method of manufacturing a substrate for integrated circuit package is also disclosed. | 06-14-2012 |
20120153444 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. | 06-21-2012 |
20120161301 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure. | 06-28-2012 |
20120168917 | STACK TYPE SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A stack type semiconductor package and a method of fabricating the stack type semiconductor package. The stack type semiconductor package includes: a lower semiconductor package including a circuit board, a semiconductor chip which is disposed on an upper surface of the circuit board, via-pads which are arrayed on the upper surface of the circuit board around the semiconductor chip, and an encapsulation layer which encapsulates the upper surface of the circuit board and has via-holes through which the via-pads are exposed; and an upper semiconductor package which is stacked on the encapsulation layer, is electrically connected to the lower semiconductor package, and comprises internal connection terminals which are formed on a lower surface of the upper semiconductor package. | 07-05-2012 |
20120181674 | Stacked Half-Bridge Package with a Common Conductive Leadframe - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. | 07-19-2012 |
20120181675 | SEMICONDUCTOR DIE PACKAGE AND METHOD FOR MAKING THE SAME - Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. | 07-19-2012 |
20120193772 | STACKED DIE PACKAGES WITH FLIP-CHIP AND WIRE BONDING DIES - The present technology discloses a stacked die package. In one embodiment, a package comprises a first die, a second die, and a leadframe. The first die is electrically coupled to the bottom surface of the leadframe through contact bump/bumps. The second die is electrically coupled to the top surface of the leadframe through wirebond/wires. The second die is mounted on the top surface of the first die. | 08-02-2012 |
20120193773 | Adhesion Promoting Composition for Metal Leadframes - A process for increasing the adhesion of a polymeric material to a metal surface, the process comprising contacting the metal surface with an adhesion promoting composition comprising: 1) an oxidizer; 2) an inorganic acid; 3) a corrosion inhibitor; and 4) an organic phosphonate; and thereafter b) bonding the polymeric material to the metal surface. The organic phosphonate aids in stabilizing the oxidizer and organic components present in the bath and prevents decomposition of the components, thereby increasing the working life of the bath, especially when used with copper alloys having a high iron content. | 08-02-2012 |
20120217626 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes: placing a seal layer including a connection conductive film on the surface so that the connection conductive film is in contact with an electrode of a semiconductor element and a lead; electrically coupling the electrode and the lead through the connection conductive film; and sealing the semiconductor element by the seal layer. | 08-30-2012 |
20120241925 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacturing of an integrated circuit packaging system includes: providing a base substrate; mounting a first die over the base substrate; mounting a second die over the first die; attaching an interposer substrate over the first die with an attachment adhesive therebetween, the interposer substrate having a central cavity and the second die within the central cavity; attaching a lateral interconnect to a second active side away from the first die of the second die and to the interposer substrate; and encapsulating the first die and the second die. | 09-27-2012 |
20120241926 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEVELING STANDOFF AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an integrated circuit adjacent the lead; molding an encapsulation encapsulating the lead and the integrated circuit; and forming a leveling standoff protruded from the same surface of the encapsulation as the lead with the integrated circuit between the lead and the leveling standoff electrically isolated from the lead and the integrated circuit. | 09-27-2012 |
20120241927 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a substrate having a redistribution line thereon; mounting an integrated circuit to the substrate; and molding a transparent encapsulation over the substrate covering the integrated circuit and the redistribution line and the integrated circuit seen through the transparent encapsulation. | 09-27-2012 |
20120248588 | LEAD FRAME - A lead frame including rails, section bars, and lead frame cells. The rails are respectively arranged at edges of the lead frame extending in a first direction. The section bars extend between the rails in a second direction and are orthogonal to the rails. The lead frame cells are aligned along the section bars. At least one of the section bars includes a rib extending in the second direction and formed through a half blanking process. | 10-04-2012 |
20120261805 | THROUGH PACKAGE VIA STRUCTURES IN PANEL-BASED SILICON SUBSTRATES AND METHODS OF MAKING THE SAME - The various embodiments of the present invention provide a low cost, low electrical loss, and low stress panel-based silicon interposer with TPVs. The interposer of the present invention has a thickness of about 100 microns to 200 microns and such thickness is achieved without utilizing a carrier and further wherein no grinding, bonding, or debonding methods are utilized, therefore distinguishing the interposer of the present invention from prior art embodiments. | 10-18-2012 |
20120267770 | DEVICE AND METHOD INCLUDING A SOLDERING PROCESS - A device and method of making a device is disclosed. One embodiment provides a substrate. A semiconductor chip is provided having a first surface with a roughness of at least 100 nm. A diffusion soldering process is performed to join the first surface of the semiconductor chip to the substrate. | 10-25-2012 |
20120286405 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes a substrate, a semiconductor element which is mounted on the substrate, a protecting film which covers at least a part of the semiconductor element, and an encapsulation resin which encapsulates the semiconductor element and the protecting film, wherein between the protecting film and the encapsulation resin, there is at least one gap in which the protecting film does not stick to the encapsulation resin. According to the above mentioned configuration, it is possible to provide a semiconductor device having a superior stress-relief performance. | 11-15-2012 |
20120286406 | SEMICONDUCTOR DEVICE WITH STAGGERED LEADS - A process for assembling a semiconductor device includes providing a lead frame having a native plane and a plurality of leads having a native lead pitch. The process includes trimming and forming a first subset of the plurality of leads to provide a first row of leads. The process includes trimming and forming a second subset of the plurality of leads to provide a second row of leads. At least one subset of leads is formed with an obtuse angle relative to the native plane such that lead pitch associated with the first or second subset of leads is greater than the native lead pitch. | 11-15-2012 |
20120299166 | CONDUCTION PATH, SEMICONDUCTOR DEVICE USING THE SAME, AND METHOD OF MANUFACTURING CONDUCTION PATH, AND SEMICONDUCTOR DEVICE - A conduction path includes a first conduction path forming plate ( | 11-29-2012 |
20120319255 | Thermal Enhanced High Density Flip Chip Package - Systems and methods according to embodiments of the invention enable flip chip packaging using high density routing while minimizing the thickness and layer count of the flip chip package. By using a photoresist layer to create very fine traces on a metallic base layer, embodiments of the present invention combine advantages of leadframe substrates and laminate substrates by supporting high-density routing while minimizing layer count and manufacturing cost. Additionally, the use of raised metallic pads in a routing layer enables embodiments of the present invention to include highly compact traces that pass over IC die bond pad connection sites without directly coupling to these bond IC die bond pad connection sites. Further, embodiments of the present invention can support multiple thin routing layers without the need for organic (e.g., laminate) material separating these routing layers. | 12-20-2012 |
20120319256 | SEMICONDUCTOR PACKAGE FOR MEMS DEVICE AND METHOD OF MANUFACTURING SAME - In some embodiments, a semiconductor package can include: (a) a base having a cavity; (b) an interposer coupled to the base and at least partially over the cavity such that the interposer and the base form a back chamber, the interposer has a first opening into the back chamber; (c) a micro-electro-mechanical system device located over the interposer at the first opening; and (d) a lid coupled to the base. Other embodiments also are disclosed. | 12-20-2012 |
20120319257 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor storage device includes an organic board provided with external connection terminals on one surface and formed as an individual piece into a plane shape substantially identical to that of an area where the external connection terminals are provided, a lead frame having a mounting area positioned relative to the organic board, and a semiconductor memory chip bonded to the mounting area. | 12-20-2012 |
20130001755 | STACKED SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR SAME - A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device. | 01-03-2013 |
20130001756 | THREE-DIMENSIONAL PACKAGE STRUCTURE - The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is disposed on the conductive pattern. The first conductive element is electrically connected to the conductive pattern, and the second conductive element is electrically connected to the conductive pattern. In one embodiment, the shielding layer is a portion of the patterned conductive layer. | 01-03-2013 |
20130009290 | POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a power module package including: a first substrate; a second substrate having a pad for connection to the first substrate formed on one side or both sides of one surface thereof and having external connection terminals for connection to the outside formed on the other surface thereof; and a lead frame having one end bonded to the first substrate and the other end bonded to the pad of the second substrate to thereby vertically connect the first and second substrates to each other. | 01-10-2013 |
20130009291 | POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: a base substrate having grooves formed between a plurality of semiconductor device mounting areas; semiconductor devices mounted on the semiconductor device mounting areas of the base substrate; and a molding formed on the base substrate and in inner portions of the grooves. | 01-10-2013 |
20130009292 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a first frame, a semiconductor element fixed to the first frame, a second frame, a third frame and a resin package. The second frame faces the first frame and is away from the first frame, the second frame being electrically connected to the semiconductor element via a metal wire. The resin package covers the semiconductor element, the first frame, and the second frame. The first frame and the second frame are exposed in one major surface of the resin package. The third frame juxtaposed to one of the first frame and the second frame, the third frame being continuously exposed from the major surface of the resin package to a side surface in contact with the major surface. | 01-10-2013 |
20130009293 | PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME - A packaging substrate includes a first dielectric layer; a plurality of first conductive pads embedded in and exposed from a first surface of the first dielectric layer; a first circuit layer embedded in and exposed from a second surface of the first dielectric layer; a plurality of first metal bumps disposed in the first dielectric layer, each of the first metal bumps having a first end embedded in the first circuit layer and a second end opposing the first end and disposed on one of the first conductive pads, a conductive seedlayer being disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump; a built-up structure disposed on the first circuit layer and the first dielectric layer; and a plurality of second conductive pads disposed on the built-up structure. The packaging substrate has an over-warpage problem improved. | 01-10-2013 |
20130032932 | BONDED WIRE SEMICONDUCTOR DEVICE - A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes. | 02-07-2013 |
20130043571 | POWER OVERLAY STRUCTURE WITH LEADFRAME CONNECTIONS - A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure. | 02-21-2013 |
20130049179 | LOW COST HYBRID HIGH DENSITY PACKAGE - A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly. | 02-28-2013 |
20130062741 | Semiconductor Devices and Methods of Manufacturing and Packaging Thereof - Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation. | 03-14-2013 |
20130062742 | Spot Plated Leadframe and IC Bond Pad Via Array Design for Copper Wire - There is provided a system and method for a spot plated leadframe and an IC bond pad via array design for copper wire. There is provided a semiconductor package comprising a leadframe having a pre-plated finish and a spot plating on said pre-plated finish, a semiconductor die including a bond pad on a top surface thereof, and a copper wire bonded to said spot plating and to said bond pad. Optionally, a novel corner via array design may be provided under the bond pad for improved package performance while maintaining the integrity of the copper wire bond. The semiconductor package may provide several advantages including high MSL ratings, simplified assembly cycles, avoidance of tin whisker issues, and low cost compared to conventional packages using gold wire bonds. | 03-14-2013 |
20130069210 | POWER MODULE PACKAGE - Disclosed herein is a power module package including: a first substrate having one surface and the other surface; a second substrate contacting one side of one surface of the first substrate; and a first lead frame contacting the other side of one surface of the first substrate. The power module package further includes: a first metal layer formed on one side of one surface of the first substrate; a first bonding layer formed on the first metal layer and contacting a lower surface of the second substrate; a second metal layer formed on the other side of one surface of the first substrate; and a second bonding layer formed on the second metal layer and contacting a lower surface of the first lead frame. | 03-21-2013 |
20130069211 | DEVICE INCLUDING A SEMICONDUCTOR CHIP AND METAL FOILS - A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner. | 03-21-2013 |
20130069212 | SEMICONDUCTOR DEVICE - A semiconductor device in which a flip chip is mounted which can change a potential of a specific terminal without changing a design of a package external. The semiconductor device includes an IC chip having a bump for an external terminal, and a package in which the IC chip is mounted. The package includes an inner lead portion that supplies a first signal or a second signal to the external terminal. The inner lead portion has a pattern of an inner lead that can change a signal to be supplied to the external terminal to the first signal or the second signal according to a position at which the IC chip is mounted. | 03-21-2013 |
20130075880 | PACKAGING STRUCTURE - A packaging structure comprises a first leadframe, a second leadframe, two grounding pins, two first pins, a plurality of first wires, a plurality of second wires, and a package body. The second leadframe is coupled to the drains of a first power transistor and a second power transistor. The two grounding pins are adjacent together and coupled to the first leadframe. The two first pins are coupled to the source of the second power transistor. The two first pins are connected together through a conductive region for increasing capability of loading current. The plurality of first wires is coupled between the source of the second power transistor and the first pin to decrease the internal resistance of the second power transistor. The plurality of second wires is coupled between the first leadframe and the source of the first power transistor to decrease the internal resistance of the first power transistor. | 03-28-2013 |
20130082369 | CURABLE RESIN COMPOSITION, CURABLE RESIN COMPOSITION TABLET, MOLDED BODY, SEMICONDUCTOR PACKAGE, SEMICONDUCTOR COMPONENT AND LIGHT EMITTING DIODE - The present invention aims to provide a curable resin composition which gives a cured product having a low linear expansion coefficient. The curable resin composition of the present invention contains, as essential components, (A) an organic compound having at least two carbon-carbon double bonds reactive with SiH groups per molecule, (B) a compound containing at least two SiH groups per molecule, (C) a hydrosilylation catalyst, (D) a silicone compound having at least one carbon-carbon double bond reactive with a SiH group per molecule, and (E) an inorganic filler. | 04-04-2013 |
20130082370 | COMPONENT BUILT-IN WIRING BOARD AND MANUFACTURING METHOD OF COMPONENT BUILT-IN WIRING BOARD - Disclosed is a component built-in wiring board, including a first insulating layer; a second insulating layer positioned in a laminated state on the first insulating layer; a semiconductor element buried in the second insulating layer, having a semiconductor chip with terminal pads and having surface mounting terminals arrayed in a grid shape connected electrically with the terminal pads; an electric/electronic component further buried in the second insulating layer; a wiring pattern sandwiched between the first insulating layer and the second insulating layer, including a first mounting land for the semiconductor element and a second mounting land for the electric/electronic component; a first connecting member connecting electrically the surface mounting terminal of the semiconductor element with the first mounting land; and a second connecting member connecting electrically the terminals of the electric/electronic component with the second mounting land, made of a same material as a material of the first connecting member. | 04-04-2013 |
20130087898 | Semiconductor Device and Method of Forming Prefabricated Multi-Die Leadframe for Electrical Interconnect of Stacked Semiconductor Die - A prefabricated multi-die leadframe having a plurality of contact pads is mounted over a temporary carrier. A first semiconductor die is mounted over the carrier between the contact pads of the leadframe. A second semiconductor die is mounted over the contact pads of the leadframe and over the first die. An encapsulant is deposited over the leadframe and first and second die. The carrier is removed. A first interconnect structure is formed over the leadframe and the first die and a first surface of the encapsulant. A channel is cut through the encapsulant and leadframe to separate the contact pads. A plurality of conductive vias can be formed through the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant opposite the first surface of the encapsulant. The second interconnect structure is electrically connected to the conductive vias. | 04-11-2013 |
20130093069 | PACKAGE STRUCTURE AND THE METHOD TO FABRICATE THEREOF - The invention discloses a package structure made of the combination of a metallic substrate and a lead frame. In one embodiment, a recess is formed in the metallic substrate and a first conductive element having at least one first I/O terminal is bonded in the recess. A lead frame is formed on the metallic substrate and comprises a plurality of electrical connections to connect with said at least one first I/O terminal of the first conductive element. In another embodiment, another conductive element is disposed in the vacancy of the lead frame. The invention also discloses a method for manufacturing a package structure made of the combination of a metallic substrate and a lead frame. | 04-18-2013 |
20130093070 | SEMICONDUCTOR DEVICE CAPABLE OF SWITCHING OPERATION MODES - A semiconductor device includes a substrate, a first pad that is formed above the substrate, a second pad that is formed above the substrate, an external terminal that is connected with the second pad, and a circuit that judges whether or not the first pad is connected with the external terminal, wherein a distance between the first pad and a side of the substrate opposed to the external terminal is different from a distance between the second pad and the side. | 04-18-2013 |
20130093071 | OPTICAL MODULE WITH A LENS ENCAPSULATED WITHIN SEALANT AND METHOD FOR MANUFACTURING THE SAME - A method to manufacture an optical module is disclosed, wherein the optical module has an optically active device on a lead frame and a lens co-molded with the active device and the lead frame by a transparent resin as positioning the lens with respect to the lead frame. The molding die of the present invention has a positioning pin to support the lens during the molding. Because the lead frame is aligned with the molding die, the precise alignment between the active device on the lead frame and the lens is not spoiled during the molding. | 04-18-2013 |
20130105953 | POWER MODULE PACKAGE | 05-02-2013 |
20130127026 | CONNECTING MATERIAL, METHOD FOR MANUFACTURING CONNECTING MATERIAL AND SEMICONDUCTOR DEVICE - In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material. | 05-23-2013 |
20130127027 | PRE-ENCAPSULATED LEAD FRAMES FOR MICROELECTRONIC DEVICE PACKAGES, AND ASSOCIATED METHODS - Pre-encapsulated lead frames suitable for use in microelectronic device packages are disclosed. Individual lead frames can include a set of multiple lead fingers arranged side by side with neighboring lead fingers spaced apart from each other by a corresponding gap. An encapsulating compound at least partially encapsulates the set of lead fingers without encapsulating a microelectronic device. The encapsulating compound can generally fill the plurality of gaps between two adjacent lead fingers. | 05-23-2013 |
20130127028 | THREE-DIMENSIONAL INTEGRATED CIRCUIT HAVING REDUNDANT RELIEF STRUCTURE FOR CHIP BONDING SECTION - A chip is layered on a rewiring member. A plurality of connecting members and a plurality of redundant connecting members are arranged in the chip, and electrically connect the chip to the rewiring member. Redundant circuits are embedded in each of the rewiring member and the chip. When one of the connecting members is faulty, the redundant circuits cause one of the redundant connecting members to transmit a signal between the rewiring member and the chip, instead of the faulty connecting member. The connecting members have first and second subsets arranged in first and second regions, respectively. A distance between the rewiring member and the chip exceeds a predetermined threshold value in the first region in contrast to the second region. The first subset has a higher proportion of connecting members that the redundant circuits can replace with a subset of the redundant connecting members than the second subset. | 05-23-2013 |
20130134567 | LEAD FRAME AND SEMICONDUCTOR PACKAGE STRUCTURE THEREOF - The present invention relates to the field of semiconductor package structures, and more specifically to a lead frame and a semiconductor package structure thereof. In one embodiment, a lead frame can include a plurality of parallel-arrayed lead fingers with a plurality of grooves situated on surfaces of the lead fingers, where the depths of the grooves can be smaller than the thickness of the lead fingers. In one embodiment, a flip chip semiconductor package structure can include a chip, a group of bumps, and the above-described lead frame. The first surfaces of the bumps can be coupled to the front surface of the chip, and the second surfaces of the bumps can be coupled to the upper surface of the lead frame. | 05-30-2013 |
20130140685 | Electronic Device and a Method for Fabricating an Electronic Device - The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier. | 06-06-2013 |
20130140686 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar. | 06-06-2013 |
20130154067 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnect Structure on Leadframe - A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure. | 06-20-2013 |
20130181332 | PACKAGE LEADFRAME FOR DUAL SIDE ASSEMBLY - Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe. | 07-18-2013 |
20130187259 | Electronic Device and a Method for Fabricating an Electronic Device - An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector. | 07-25-2013 |
20130200502 | Semiconductor Device and Method of Manufacturing Thereof - A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier. | 08-08-2013 |
20130200503 | PROTECTIVE LAYERS IN SEMICONDUCTOR PACKAGING - A semiconductor package includes a semiconductor die having an upper surface with bond pads thereon. A plurality of leads surround sides of the semiconductor die. Bonding wires couple each of the bond pads to a corresponding one of the plurality of leads. An encapsulant covers the upper surface and the sides of the semiconductor die and the bonding wires. The encapsulant also covers a portion of a top of each of the plurality of leads and sides of the plurality of leads that are nearest the semiconductor die. A bottom of each of the plurality of leads and the sides of the plurality of leads that are farthest from the semiconductor die are exposed outside the encapsulant. A protective film covers a lower surface of the semiconductor die and has a bottom that is substantially coextensive with the bottom of each of the plurality of leads. | 08-08-2013 |
20130200504 | ELECTRONIC COMPONENT MODULE AND METHOD FOR PRODUCING SAME - An electronic component module includes a double-sided mounting board having a front surface and a back surface; components mounted on the front surface and the back surface of the double-sided mounting board; an insulating resin sealing the components mounted on the front surface and the back surface; and a lead frame bonded to the back surface of the double-sided mounting board. The back surface of the double-sided mounting board is sealed with the insulating resin such that the lead frame is not covered by the insulating resin, and the thickness of the insulating resin sealing the components mounted on the back surface of the double-sided mounting board is less than or equal to the thickness of the lead frame. | 08-08-2013 |
20130200505 | PACKAGE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A method for manufacturing a package comprises a first step of forming a metal pattern including a frame and a plurality of leads extending inward from the frame, a second step of molding a resin pattern including a first resin portion which holds the plurality of leads from an inner side thereof, and second resin portions which cover bottom surfaces of peripheral portions, adjacent to portions to be removed, in the plurality of leads while exposing bottom surfaces of the portions to be removed in the plurality of leads, so as to hold the plurality of leads from a lower side thereof, and a third step of cutting the plurality of leads into a plurality of first leads and a plurality of second leads by removing the portions to be removed in the plurality of leads while the resin pattern keeps holding the peripheral portions in the plurality of leads. | 08-08-2013 |
20130221502 | JOINED BODY, POWER SEMICONDUCTOR DEVICE, AND MANUFACTURING METHODS OF JOINED BODY AND POWER SEMICONDUCTOR DEVICE - First, an aqueous solution ( | 08-29-2013 |
20130241040 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes, a chip including a first chip electrode on a first surface on one side, and a second chip electrode on a second surface on the other side, an electrically conductive frame provided on a side periphery of the chip, a rewiring configured to electrically connect the second chip electrode and the electrically conductive frame on the other side of the chip, and an insulation side portion provided between the electrically conductive frame and the side periphery of the chip. | 09-19-2013 |
20130249065 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND LEADFRAME ETCHING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of the integrated circuit die; and removing the mounting structure for exposing the integrated circuit die. | 09-26-2013 |
20130249066 | ELECTROMIGRATION-RESISTANT LEAD-FREE SOLDER INTERCONNECT STRUCTURES - Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal. | 09-26-2013 |
20130264692 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME - An integrated circuit package includes an electronic sensor protected by a lid structure. The electronic sensor includes a transducer placed on a backside surface of a lead frame assembly. The lid structure is placed over the transducer and is attached to the lead frame assembly on the backside surface. The lid can define an air cavity around the transducer, such that mold compound, gel, or other protective chemical material is not placed in contact with the transducer. The transducer is therefore protected without a chemical protectant, lowering the cost of the integrated circuit package and maintaining the sensitivity and performance of the transducer. | 10-10-2013 |
20130270682 | Methods and Apparatus for Package on Package Devices with Reversed Stud Bump Through Via Interconnections - Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed. | 10-17-2013 |
20130277811 | STACKED INTERPOSER LEADFRAMES - A method of manufacturing integrated circuit (IC) devices includes the steps of providing a first frame that has openings each having a perimeter with shaped notches, placing a first die in at least one of the openings, and placing a second frame over the first frame. The second frame has a first partial dam bar with a first shaped tip that fits into a first shaped notch of the first frame. The method also includes the step of placing a third frame over the second frame. The third frame has a second partial dam bars with a second shaped tip that fits into a second shaped notch of the first frame. Each perimeter and the respective first and second partial dam bars cooperate to form a continuous dam completely encircling the die within the respective opening. | 10-24-2013 |
20130277812 | ELECTRONIC ASSEMBLY WITH IMPROVED THERMAL MANAGEMENT - The invention relates to an electronic assembly comprising a leadframe ( | 10-24-2013 |
20130285219 | INTEGRATED CIRCUIT POWER GRID WITH IMPROVED ROUTING RESOURCES AND BYPASS CAPACITANCE - An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal layers having a plurality of metal traces, wherein a plurality of the metal traces on different thin metal layers are connected by at least one via, wherein the at least one via is substantially surrounded by a metal trace on at least one thin metal level connected to a different power supply voltage than a power supply of one or more additional thin metal levels. The via can be positioned, for example, at an intersection of a given standard cell row and a given vertical strap. | 10-31-2013 |
20130292810 | REDISTRIBUTION ELEMENTS AND SEMICONDUCTOR DEVICE PACKAGES INCLUDING SEMICONDUCTOR DEVICES AND REDISTRIBUTION ELEMENTS - A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane. | 11-07-2013 |
20130307129 | WIRING MEMBER AND SEMICONDUCTOR MODULE HAVING THE SAME - A wiring member includes a first leg portion, a second leg portion, a third leg portion, a first connecting wall and a second connecting wall. The first leg portion is electrically connected to a first conductive portion. The second leg portion is electrically connected to a second conductive portion. The third leg portion is electrically connected to a third conductive portion. The first connecting wall connects the first leg portion and the second leg portion. The second connecting wall connects the second leg portion and the third leg portion. The first leg portion, the second leg portion, and the third leg portion are non-linearly arranged. | 11-21-2013 |
20130307130 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, in which a first lead ( | 11-21-2013 |
20130313693 | EPOXY-THIOL COMPOSITIONS WITH IMPROVED STABILITY - A curable one-part epoxy resin composition is described. The composition comprises an epoxy component comprising at least one epoxy compound which has two or more groups per molecule; a latent hardener component; a thixotropy-conferrring component; a polythiol component comprising a polythiol having at least one secondary or tertiary thiol group per molecule; and a stabilising component comprising a solid organic acid. The compositions according to the invention are particularly suitable for use in the field of microelectronics. | 11-28-2013 |
20130313694 | PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE - Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate. | 11-28-2013 |
20130334671 | SEMICONDUCTOR PACKAGE AND LEAD FRAME THEREOF - A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound. | 12-19-2013 |
20130334672 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, semiconductor chips and lead frames are soldered at the same time on an insulating circuit board by one reflow soldering, and the positions of the externally led out lead frames undergo no change. In manufacturing the semiconductor device, after power semiconductor chips and control ICs are mounted on an insulating circuit board, and lead frames are disposed thereon, the semiconductor chips and lead frames are soldered at the same time on the insulating circuit board by one reflow soldering. Furthermore, after a primary bending work is carried out on the lead frames, and a terminal case is mounted over the insulating circuit board, a secondary bending work is carried out on the lead frames. | 12-19-2013 |
20130341774 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including: an insulating layer; a semiconductor element embedded in the insulating layer; an adhesive body embedded in the insulating layer, wherein a portion of the semiconductor element is embedded in the adhesive body; a patterned metal layer embedded in the adhesive body and electrically connected to the semiconductor element; and a redistribution structure formed on the insulating layer and electrically connected to the patterned metal layer. By embedding the semiconductor element in the adhesive body, the present invention can securely fix the semiconductor element at a predetermined position without any positional deviation, thereby improving the product yield. | 12-26-2013 |
20140001611 | SEMICONDUCTOR PACKAGE | 01-02-2014 |
20140021592 | LED LEAD FRAME STRUCTURE AND METHOD OF MANUFACTURING LED LEAD FRAME - A LED lead frame structure and a method of manufacturing LED lead frames are disclosed, in which the LED lead frame structure includes a metal base and insulating casings. The metal base has a plurality of lead areas, and two holes are formed on two opposing sides of each lead area. The insulating casings are formed on the lead areas respectively. | 01-23-2014 |
20140027888 | SYSTEM AND METHOD TO MANUFACTURE AN IMPLANTABLE ELECTRODE - The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason. | 01-30-2014 |
20140035112 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first semiconductor element; a first thick plate portion that is electrically connected to an electrode on a lower surface side of the first semiconductor element, and is formed by a conductor; a second semiconductor element that is arranged such that a main surface of the second semiconductor element faces a main surface of the first semiconductor element; a second thick plate portion that is electrically connected to an electrode on a lower surface side of the second semiconductor element, and is formed by a conductor; a third thick plate portion that is electrically connected to an electrode on an upper surface side of the first semiconductor element, and is formed by a conductor; a fourth thick plate portion that is electrically connected to an electrode on an upper surface side of the second semiconductor element, and is formed by a conductor; a first thin plate portion that is provided on the second thick plate portion, is formed by a conductor, and is thinner than the second thick plate portion; and a second thin plate portion that is provided on the third thick plate portion, is formed by a conductor, and is thinner than the third thick plate portion. The first thin plate portion and the second thin plate portion are fixed together and electrically connected. | 02-06-2014 |
20140042599 | MULTI-CHIP MODULE POWER CLIP - The multi-chip leadless module | 02-13-2014 |
20140042600 | Semiconductor Package and Manufacturing Method Thereof - A semiconductor package and manufacturing method thereof are disclosed and may include a first semiconductor device comprising a first bond pad on a first surface of the first semiconductor device, a first encapsulant material surrounding side edges of the first semiconductor device, and a redistribution layer (RDL) formed on the first surface of the first semiconductor device and on a first surface of the encapsulant material. The RDL may electrically couple the first bond pad to a second bond pad formed above the first surface of the encapsulant material. A second semiconductor device comprising a third bond pad on a first surface of the second semiconductor device may face the first surface of the first semiconductor device and be electrically coupled to the first bond pad on the first semiconductor device. The first surface of the first semiconductor device may be coplanar with the first surface of the encapsulant material. | 02-13-2014 |
20140054757 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. | 02-27-2014 |
20140061878 | INTEGRATED CIRCUITS AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit is provided. The integrated circuit includes: a chip and encapsulation material covering at least three sides of the chip, the encapsulation material being formed from adhesive material. The integrated circuit includes a carrier adhered to the chip by means of the encapsulation material. | 03-06-2014 |
20140061879 | MULTILAYER PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING - One embodiment is a packaged device having multiple layers. Another embodiment is a method of forming a packaged device having multiple layers. Conductive layers and insulating layers can be formed with openings exposing semiconductor devices. The semiconductor devices can be wire-bonded to the conductive layers. In some embodiments, parasitic effects and a relative footprint of the packaged device can be reduced. | 03-06-2014 |
20140061880 | WAFER LEVEL CHIP SCALE PACKAGE - The present disclosure provides a semiconductor device including a semiconductor element having a first surface and a second surface, which is opposite to the first surface, and a conductive via disposed on the semiconductor element. The semiconductor element includes a die; a first redistribution layer positioned on the first surface, wherein the first redistribution layer is configured to fan out the die; and a second redistribution layer positioned on the second surface of the semiconductor element. The conductive via is configured to electrically connect the first redistribution layer and the second redistribution layer, wherein the sizes of the two ends of the conductive via are different and the die can be electrically coupled to another semiconductor device through the conductive via. | 03-06-2014 |
20140061881 | INTEGRATED CIRCUIT - An integrated circuit (IC) includes a packaging body, multiple interface connectors, a functional chip, and an electrostatic discharge (ESD) protection chip. The interface connectors are located on an outer surface of the packaging body. The functional chip has an electronic functional circuit, and the ESD protection chip has an ESD protection circuit. The ESD protection circuit is connected electrically to an interface connector serving as a data exchange path. | 03-06-2014 |
20140061882 | ELECTRONIC SYSTEM MODULES AND METHOD OF FABRICATION - A circuit assembly includes a plurality of integrated circuits having stud bumps at each input/output pad, an interconnection circuit having wells filled with solder, said wells corresponding in a one-to-one relationship with said stud bumps of said integrated circuits, and electrical and mechanical bonding at each of said input/output pads, wherein each of said stud bumps connects with solder in each of said wells to form a permanent connection. | 03-06-2014 |
20140070380 | BRIDGE INTERCONNECT WITH AIR GAP IN PACKAGE ASSEMBLY - Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed. | 03-13-2014 |
20140070381 | SEMICONDUCTOR MEMORY CARD - A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals. | 03-13-2014 |
20140070382 | Pre-Molded MEMS Device Package - A MEMS lead frame package body encloses a MEMS device enclosed in an internal cavity formed by the mold body and cover. To accommodate a MEMS microphone, an acoustic aperture extends through the mold body. In some embodiments, a conductive column extends through the pre-molded body to allow electrical connection from a partially encapsulated lead frame to the conductive cover. Some embodiments may include a multi-tiered cavity within the mold body for mounting an integrated circuit separated by a gap above the MEMS device. | 03-13-2014 |
20140070383 | Pre-Molded MEMS Device Package with Conductive Shell - A MEMS lead frame package body encloses a MEMS device enclosed in an internal cavity formed by the mold body and cover. A conductive internal shell with a connection window sits in the cavity. The MEMS device is mounted in the shell and electrically coupled to the lead frame through wire bonds directed through the connection window. To accommodate a MEMS microphone, an acoustic aperture extends through the mold body aligned with a hole in the internal shell. | 03-13-2014 |
20140070384 | STACKED SEMICONDUCTOR DEVICE AND PRINTED CIRCUIT BOARD - An interposer of a first semiconductor package includes a power supply wiring for a second semiconductor element, the power supply wiring including a land provided in one surface layer, and a power supply pattern provided in an inner layer and electrically connected to the land, the power supply wiring further including a larger number of lands than the land, which are provided in another surface layer and electrically connected in parallel to the power supply pattern. In a stacked semiconductor device, this configuration can improve the quality of power supply to the second semiconductor element to secure signal processing operation while preventing an increase in inductance caused by the bending of a power supply path in a power supply wiring of a printed wiring board or by a deviation of connection intervals. | 03-13-2014 |
20140070385 | FLIP-CHIP PACKAGE STRUCTURE AND METHOD FOR AN INTEGRATED SWITCHING POWER SUPPLY - Disclosed are flip-chip package structures and methods for an integrated switching power supply. In one embodiment, a flip-chip package structure can include: (i) a die with an integrated switching power supply, where a first surface of the die includes first bumps with different polarities; (ii) a redistribution layer including redistribution layer units, each having a first surface to connect bumps with a same polarity from the first bumps, the redistribution layer having a second surface including second bumps to redistribute polarities; (iii) a lead frame having pins, where a first surface of the lead frame can connect bumps with a same polarity from the second bumps; and (iv) a flip-chip package configured to package the die, the redistribution layer, the first and second bumps, and the lead frame, where a second surface of the lead frame provides electrical connectivity between the integrated switching power supply and a PCB. | 03-13-2014 |
20140077346 | METHOD AND SYSTEM FOR PRE-MIGRATION OF METAL IONS IN A SEMICONDUCTOR PACKAGE - Pre-migration of metal ions is achieved in a controlled manner to form a migrated metalover which an inhibitor is applied to prevent further migration. In a semiconductor circuit, pre-migration of metal ions is achieved by exposing a joined metal system to water, oxygen and an electrical field in a controlled manner. Conductors, joined to electrically isolating materials, are exposed to electrical fields in such a manner as to form one or more anodes to corresponding cathodes, thus liberating metal ions. The metal ions are then allowed to migrate in a controlled manner from the anode toward the cathode to form a pre-migrated metal. Finally, an inhibitor is applied on top of the pre-migrated metal to prevent further migration. | 03-20-2014 |
20140084429 | EXTREMELY THIN PACKAGE - Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe or substrate via connections and EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate. | 03-27-2014 |
20140091442 | HIGH DENSITY SECOND LEVEL INTERCONNECTION FOR BUMPLESS BUILD UP LAYER (BBUL) PACKAGING TECHNOLOGY - An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body. | 04-03-2014 |
20140103501 | CIRCUIT BOARD WITH TWINNED CU CIRCUIT LAYER AND METHOD FOR MANUFACTURING THE SAME - A circuit board with twinned Cu circuit layer and a method for manufacturing the same are disclosed, wherein the method comprises the following steps: (A) providing a substrate with a first circuit layer formed thereon, wherein the first circuit layer comprises a conductive pad; (B) forming a first dielectric layer on the surface of the substrate; (C) forming plural openings in the first dielectric layer, wherein each opening penetrates through the first dielectric layer and communicates with the conductive pad to expose the conductive pad; (D) forming a Cu seeding layer in the openings; (E) forming a nano-twinned Cu layer in the openings with an electroplating process; and (F) annealing the substrate to transfer the material of the Cu seeding layer into nano-twinned Cu, wherein the nano-twinned Cu layer and the transferred Cu seeding layer are formed into a second circuit layer. | 04-17-2014 |
20140103502 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor chip held on a substrate and including an expanded portion expanding outward from a side surface of a body of the first semiconductor chip; a first wire connecting the expanded portion of the first semiconductor chip to the substrate; and a second wire connecting the body of the first semiconductor chip to the substrate. | 04-17-2014 |
20140117516 | MULTIPLE DIE IN A FACE DOWN PACKAGE - A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements. | 05-01-2014 |
20140117517 | Power Quad Flat No-Lead (PQFN) Package Having Control and Driver Circuits - According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase power inverter, a control circuit, and a driver circuit. The driver circuit is configured to drive the multi-phase power inverter responsive to a control signal from the control circuit. The multi-phase power inverter, the control circuit, and the driver circuit are each situated on a PQFN leadframe of the PQFN package. The control circuit and the driver circuit can be in a common integrated circuit (IC). Furthermore, the control circuit can be configured to reconstruct at least two phase currents of the multi-phase power inverter from a combined phase current. | 05-01-2014 |
20140117518 | Control and Driver Circuits on a Power Quad Flat No-Lead (PQFN) Leadframe - According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase and W-phase power switches situated on the PQFN leadframe and respectively connected to a U-phase output strip and a W-phase output pad of the PQFN leadframe. The PQFN leadframe further includes a common integrated circuit (IC) including a driver circuit and a control circuit where the common IC is connected to the U-phase output strip and to the W-phase output pad of the PQFN leadframe. The PQFN leadframe can also include a V-phase power switch situated on the PQFN leadframe where the V-phase power switch is connected to a V-phase output strip of the PQFN leadframe. | 05-01-2014 |
20140124909 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first electrical conductor, a second electrical conductor, first and second semiconductors between the first and second electrical conductors, a first power terminal, a second power terminal, a signal terminal, and an insulator which covers the components. The insulator includes a flat bottom surface in which the first and second electrical conductors are exposed, a ceiling surface, a first end surface, and a second end surface. The power terminals and the signal terminal extend outwardly from the first and second end surfaces, and the ceiling surface, respectively. The first end surface, the ceiling surface, and the second end surface are formed with a parting line. | 05-08-2014 |
20140131842 | AXIAL SEMICONDUCTOR PACKAGE - An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component. | 05-15-2014 |
20140131843 | MAGNETICALLY COUPLED GALVANICALLY ISOLATED COMMUNICATION USING LEAD FRAME - An integrated circuit package includes an encapsulation and a lead frame. A portion of the lead frame is disposed within encapsulation. The lead frame includes a first conductor having a first conductive loop disposed substantially within the encapsulation. The lead frame also includes a second conductor that is galvanically isolated from the first conductor. The second conductor includes a second conductive loop that is substantially disposed within the encapsulation proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductors. | 05-15-2014 |
20140131844 | System and Method for an Electronic Package with a Fail-Open Mechanism - A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature. | 05-15-2014 |
20140131845 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a capacitor, a first resin, lead frames and a second resin. The first resin forms a resin molding which covers the semiconductor element and the capacitor. The lead frames are attached to two surfaces of the resin molding and are connected to the semiconductor element and the capacitor. The second resin directly covers the capacitor and has a rigidity lower than a rigidity of the first resin. An outside of the second resin is directly covered with the first resin. | 05-15-2014 |
20140138805 | System for No-Lead Integrated Circuit Packages Without Tape Frame - A system has a leadframe strip and a plurality of integrated circuit dies are each encapsulated in an encapsulant. The encapsulant has a plurality of first cuts and a plurality of second cuts therein. A fixture holds the package in said plurality of first cuts while said plurality of second cuts are made. | 05-22-2014 |
20140138806 | POWER OVERLAY STRUCTURE WITH LEADFRAME CONNECTIONS - A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure. | 05-22-2014 |
20140138807 | POWER OVERLAY STRUCTURE WITH LEADFRAME CONNECTIONS - A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure. | 05-22-2014 |
20140151862 | EMBEDDED INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING AN EMBEDDED INTEGRATED CIRCUIT PACKAGE - A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects. | 06-05-2014 |
20140159212 | STACKED TYPE POWER DEVICE MODULE - The disclosure relates to a stacked type power device module. May use the vertical conductive layer for coupling the stacked devices, the electrical transmission path may be shortened. Hence, current crowding or contact damages by employing the conductive vias or wire bonding may be alleviated. | 06-12-2014 |
20140167233 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region. (FIG. | 06-19-2014 |
20140175624 | METHOD FOR MANUFACTURING A CHIP ARRANGEMENT, AND CHIP ARRANGEMENT - A method for manufacturing a chip arrangement in accordance with various embodiments may include: placing a chip on a carrier within an opening of a metal structure disposed over the carrier; fixing the chip to the metal structure; removing the carrier to thereby expose at least one contact of the chip; and forming an electrically conductive connection between the at least one contact of the chip and the metal structure. | 06-26-2014 |
20140175625 | SEMICONDUCTOR DEVICE INCLUDING AT LEAST ONE ELEMENT - A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive. | 06-26-2014 |
20140175626 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURE - An integrated circuit package has a leadframe having an open space extending therethrough. An integrated circuit device is attached to a portion of the upper surface of the leadframe. A shunt is located within the open space such that it is not in contact with any portion of the leadframe. | 06-26-2014 |
20140183711 | Semiconductor Device and Method of Making a Semiconductor Device - In accordance with an embodiment of the present invention, a semiconductor device has a substrate having a first surface and a second surface opposite the first surface. Also, the substrate has a first hole. A plurality of leads is disposed over the first surface of the substrate and a die paddle is disposed in the first hole. Additionally, an encapsulant is disposed on the die paddle and the plurality of leads. | 07-03-2014 |
20140197523 | CHIP ARRANGEMENT AND A METHOD FOR FORMING A CHIP ARRANGEMENT - A chip arrangement is provided, the chip arrangement, including: a carrier; at least one chip including at least one contact pad disposed over the carrier; an encapsulation material at least partially surrounding the at least one chip and the carrier; and at least one low temperature co-fired ceramic sheet disposed over a side of the carrier. | 07-17-2014 |
20140197524 | DIE PACKAGE STRUCTURE - A die packaged structure includes a pad on the central region of the die. A packaged substrate with an opening disposed in the central region, and a connecting terminal is passed through the packaged substrate and disposed around the opening. An external connecting terminal is disposed on the four sides of the packaged substrate. A first metal wire is electrically connected the connecting terminal with the external connecting terminal, and the back of the packaged substrate is fixed on the die, such that the pad is exposed on the opening. A second metal wire is electrically connected the pad with the connecting terminal. A packaged body is encapsulated the packaged substrate, the die and the second metal wire, and the external connecting terminal is exposed. A conductive component is electrically connected with the external connecting terminal and is arranged on the four sides of the die packaged structure. | 07-17-2014 |
20140197525 | POWER MODULE - A power module configured to arrange a first electrode on a surface of which a first switching device is bonded, a second electrode on a surface of which a second switching device is bonded, and a third electrode by stacking the first electrode, the first switching device, the second electrode, the second switching device, and the third electrode in this order from the bottom in a stacking direction, characterized by first through third electrode pieces each connected to the first through third electrodes, first and second signal lines each connected to the first and second switching devices, wherein the first through third electrode pieces and the first and second signal lines are provided extending outward in the same plane as the second electrode. | 07-17-2014 |
20140203418 | LEAD FRAME AND A METHOD OF MANUFACTURING THEREOF - A method of manufacturing a lead frame, comprising the steps of: providing an electrically-conductive base material having first and second planar sides; forming a patterned conductive layer on the first planar side of the base material; etching the second planar side of the base material at portions with respect to exposed portions on the first planar side of the base material comprising the patterned conductive layer, to form partially-etched portions on the second planar side of the base material; providing a non-conductive filling material over the second planar side of the base material, wherein the filling material fills spaces inside the partially-etched portions on the second planar side of the base material to form adjacent portions of the filling material and a plurality of conductive portions on the second planar side of the base material; and etching the exposed portions of the first planar side of the base material comprising the patterned conductive layer to form partially-etched portions on the first planar side of the base material that combine with the partially-etched portions on the second planar side of the base material to thereby form a plurality of separate conductive regions on the first planar side of the base material, each conductive region being electrically conductive with at least a respective one of the plurality of conductive portions on the second planar side of the base material. | 07-24-2014 |
20140203419 | Half-Bridge Package with a Conductive Clip - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe. | 07-24-2014 |
20140210060 | SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device which includes a semiconductor chip, an insulating board mounted with the semiconductor chip and having a wiring pattern, and a leadframe connected to the wiring pattern, the semiconductor chip, the wiring pattern and the leadframe being partially sealed with a sealing resin, wherein: an epoxy resin composition formed by adding 0.3 to 0.7 mass % of epoxysilane as a silane coupling agent to an epoxy resin is used as the sealing resin; and a copper member made of copper or a copper alloy and having an oxide film formed in the surface with a film thickness in a color indicated by an L* value in the range of 48 to 51, an a* value in the range of 40 to 49 and a b* value in the range of 24 to 40 is used as the leadframe and the wiring pattern. | 07-31-2014 |
20140217565 | ELECTRICAL CONNECTIVITY OF DIE TO A HOST SUBSTRATE - According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc. | 08-07-2014 |
20140231975 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating circuit substrate mounted with at least one semiconductor element; a resin case having a bottom surface portion attached with the insulating circuit substrate and a side surface portion enclosing a periphery of the bottom surface portion; a lead molded integrally with the resin case and provided on a periphery of the insulating circuit substrate to be positioned on a surface of the bottom surface portion inside the resin case, the lead partially extending from inside the resin case to outside the resin case; and a sealing resin filled inside the resin case. A depressed portion is formed on two sides of the lead along a peripheral edge of the bottom surface portion inside the resin case. | 08-21-2014 |
20140239466 | Electronic Device - An electronic device includes a first transistor device with first contact elements, a second transistor device with second contact elements, and an electrical connection member with a first main face and a second main face opposite to the first main face. The first transistor device is disposed on the first main face of the electrical connection member and the second transistor device is disposed on the second main face of the electrical connection member. One of the first contact elements is electrically connected with one of the second contact elements by a part of the electrical connection member. | 08-28-2014 |
20140239467 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame, a semiconductor chip soldered to the lead frame, and a metal bar. The metal bar is arranged inside a solder layer so as to extend along one side of the semiconductor chip. When viewed in a stacking direction of the lead frame and the semiconductor chip, the metal bar is arranged so that a part of the metal bar overlaps the semiconductor chip, and the rest of the metal bar does not overlap the semiconductor chip. Then, in a section of the metal bar in a plane perpendicular to a longitudinal direction of the metal bar, an outline of the metal bar on a side of a center of the semiconductor chip is curved so as to project on the side of the center of the semiconductor chip. | 08-28-2014 |
20140239468 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property. A semiconductor device according to the present invention includes a plurality of semiconductor chips formed on a substrate, and a plate electrode connecting electrodes of the plurality of semiconductor chips. The plate electrode has half-cut portions formed by half-pressing and the raised sides of the half-cut portions are bonded with the electrodes of the semiconductor chips. | 08-28-2014 |
20140252571 | WAFER-LEVEL PACKAGE MITIGATED UNDERCUT - A wafer-level package device and techniques are described that include utilizing a dry-etch process for mitigating metal seed layer undercut. In an implementation, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, depositing a metal seed layer on the substrate, depositing and patterning a resist layer, depositing a redistribution layer structure, removing the photoresist layer, and dry-etching the metal seed layer. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a substrate, a metal seed layer disposed on the substrate, and a redistribution layer structure formed on the metal seed layer. The metal seed layer is dry-etched so that undercut is mitigated. | 09-11-2014 |
20140252572 | Structure and Method for 3D IC Package - Provided is a chip package structure and a method for forming the chip package. The method includes bonding a plurality of first dies on a carrier, encapsulating in a first molding compound the first dies on the carrier, coupling a plurality of second dies on the first dies using conductive elements, adding an underfill between the second dies and the first dies surrounding the conductive elements, and encapsulating in a second molding compound the second dies and the underfill. The chip package comprises a chip encapsulated in a molding compound, and a larger chip coupled to the first chip via conductive elements, wherein the conductive elements are encapsulated in an underfill between the chip and the larger chip without an interposer, and wherein the larger chip and the underfill are encapsulated in a second molding compound in contact with the molding compound. | 09-11-2014 |
20140252573 | Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB - A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to V | 09-11-2014 |
20140252574 | LEAD FRAME AND SEMICONDUCTOR DEVICE - A lead frame of high quality which can endure direct bonding to the electrodes of a semiconductor element and a metal member, and a semiconductor device of high reliability which utilizing the lead frame. The lead frame includes a pair of lead frame portions which are arranged spaced apart from and opposite to each other to be electrically connected to a pair of electrodes of a semiconductor element respectively, and a pair of support bars which are arranged spaced apart from the lead portions and extending from a side of either one of the lead portions to a side of the other lead portion. | 09-11-2014 |
20140264789 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die. | 09-18-2014 |
20140264790 | CHIP PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip. | 09-18-2014 |
20140264791 | DIRECT EXTERNAL INTERCONNECT FOR EMBEDDED INTERCONNECT BRIDGE PACKAGE - An external direct connection usable for an embedded interconnect bridge package is described. In one example, a package has a substrate, a first semiconductor die having a first bridge interconnect region, and a second semiconductor die having a second bridge interconnect region. The package has a bridge embedded in the substrate, the bridge having a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region, and an external connection rail extending between the interconnect bridge and the first and second semiconductor dies to supply external connection to the first and second bridge interconnect regions. | 09-18-2014 |
20140264792 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods for forming a semiconductor package are presented. The method includes providing a package substrate having first and second major surfaces. The package substrate includes at least one substrate layer having at least one cavity. Interconnect structure is formed. At least one conductive stud is formed within the cavity and a conductive trace and a connection pad are formed over the first major surface of the package substrate and are coupled to top surface of the conductive stud. A package pad is formed and is directly coupled to the conductive stud. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structure. A cap is formed over the package substrate to encapsulate the die. | 09-18-2014 |
20140284777 | Multi-Chip Semiconductor Power Device - A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip. | 09-25-2014 |
20140284778 | Methods And Systems For Selectively Forming Metal Layers On Lead Frames After Die Attachment - Methods and systems are disclosed for selectively forming metal layers on lead frames after die attachment to improve electrical connections for areas of interest on lead frames, such as for example, lead fingers and down-bond areas. By selectively forming metal layers on areas of interest after die attachment, the disclosed embodiments help to eliminate anomalies and associated defects for the lead frames that may be caused by the die attachment process. A variety of techniques can be utilized for selectively forming one or more metal layers, and a variety of metal materials can be used (e.g., nickel, palladium, gold, silver, etc.). Further, cleaning can also be performed with respect to the areas of interest prior to selectively forming the one or more metal layers on areas of interest for the leaf frame. | 09-25-2014 |
20140291822 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit (“IC”) package including an IC assembly mounted on a leadframe and an encapsulant block covering the IC assembly and portions of the leadframe. The encapsulant block has a molded chamfered outer surface portion and the leadframe has a saw cut outer periphery. | 10-02-2014 |
20140299977 | Semiconductor Device - A semiconductor device includes: a lead frame; an IC element mounted on a main face of the lead frame; an inductor mounted on a back face of the lead frame; and a resin body configured to seal the lead frame, the IC element and the inductor, wherein the inductor and the lead frame are closely contacted with each other, wherein the IC element is disposed at a position corresponding to an center axis of the inductor, wherein the inductor and the IC element are electrically connected to each other, and wherein wiring of main current flowing through the IC element is disposed between terminals of the inductor. | 10-09-2014 |
20140306327 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device includes a device carrier and a semiconductor chip attached to the device carrier. Further, the semiconductor device includes a lid having a recess. The lid includes a semiconductor material and is attached to the device carrier such that the semiconductor chip is accommodated in the recess. | 10-16-2014 |
20140306328 | SEMICONDUCTOR DEVICE - The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction. | 10-16-2014 |
20140312474 | SEMICONDUCTOR PACKAGE WITH WIRE BONDING - A semiconductor package having a die having a plurality of electrically continuous die wire bonding sites includes a first die wire bonding site and a second die wire bonding site. The package includes a substrate having a plurality of electrically continuous substrate wire bonding sites including a first substrate wire bonding site and a second substrate wire bonding site. A first bondwire is connected between the first die wire bonding site and the first substrate wire bonding site and a second bondwire is connected between the second die wire bonding site and the second substrate wire bonding site. The first and second bondwires lie in adjacent, substantially parallel bondwire planes. The second bondwire is substantially skewed with respect to said first bondwire. | 10-23-2014 |
20140312475 | DIE REUSE IN ELECTRICAL CIRCUITS - A die having multiple sets of contact pads, with each such set having two or more contact pads distributed over the die and electrically interconnected using a respective electrical intra-die path to enable die reuse in a manner that causes electrical inter-die buses to be relatively short in length. Each electrical intra-die path can optionally include one or more respective buffer circuits configured to reduce degradation of the various signals that are being shared by the reused dies. In some embodiments, multiple reused dies can be arranged in a linear or two-dimensional array on an interposer or on the package substrate and packaged together with one or more non-reused dies in a single integrated-circuit package. | 10-23-2014 |
20140312476 | NO-EXPOSED-PAD BALL GRID ARRAY (BGA) PACKAGING STRUCTURES AND METHOD FOR MANUFACTURING THE SAME - A no-exposed-pad ball grid array (BGA) packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of outer leads formed on the metal substrate and extending to the proximity of the die. A metal layer that contains a plurality of inner leads corresponding to the plurality of outer leads and extending to the proximity of the die is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Furthermore, the die and the plurality of inner leads are connected by metal wires, and a plurality of solder balls is attached to a back surface of the plurality of outer leads and a die pad. The die, the plurality of inner leads, and the metal wires are sealed with a molding compound. | 10-23-2014 |
20140312477 | Lead And Lead Frame For Power Package - A power device includes a semiconductor chip provided over a substrate, and a patterned lead. The patterned lead includes a raised portion located between a main portion and an end portion. At least part of the raised portion is positioned over the semiconductor chip at a larger height than both the main portion and the end portion. A bonding pad may also be included. The end portion may include a raised portion, bonded portion, and connecting portion. At least part of the bonded portion is bonded to the bonding pad and at least part of the raised portion is positioned over the bonding pad at a larger height than the bonded portion and connecting portion. The end portion may also include a plurality of similarly raised portions. | 10-23-2014 |
20140327121 | Semiconductor Device and Method for Manufacturing Same - The purpose of the present invention is to increase the reliability of a semiconductor device in which a semiconductor element and a substrate are connected by solder and which is molded by resin. | 11-06-2014 |
20140332938 | MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads. | 11-13-2014 |
20140339690 | Elimination of Die-Top Delamination - An integrated-circuit module includes an integrated-circuit device having a first surface and a plurality of bond pads disposed on the first surface. The module further includes metallic bond wires or metallic ribbons, which are attached between respective ones of a first subset of the bond pads and a package substrate or leadframe, such that a second subset of the bond pads are not attached to either a package substrate or leadframe. A metallic stud bump is affixed to each of one or more of the second subset of the bond pads. The integrated-circuit module further comprises a molding compound that contacts at least the first surface of the integrated-circuit device and substantially surrounds the bond wires or ribbon wires and the metallic stud bumps. | 11-20-2014 |
20140374889 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of semiconductor elements; first semiconductor chips including first semiconductor elements, the first semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements and having a current flowing greater than that of the other semiconductor elements; second semiconductor chips having second semiconductor elements, the second semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements for controlling the first semiconductor elements; an insulating substrate having a first wiring pattern bonded with the first semiconductor chips; and an insulating member having a second wiring pattern mounted with the second semiconductor chips. | 12-25-2014 |
20150014829 | Copper Leadframe Finish for Copper Wire Bonding - A semiconductor device ( | 01-15-2015 |
20150014830 | SEMICONDUCTOR DEVICE UTILZING REDISTRIBUTION LAYERS TO COUPLE STACKED DIE - A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer. | 01-15-2015 |
20150021749 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided which complies with restrictions on layout on a mounting substrate side. The semiconductor device includes a wiring substrate having a plurality of bonding leads at an upper surface having a rectangular shape, a semiconductor chip mounted over the upper surface of the wiring substrate, and having a plurality of electrode pads at a main surface having a rectangular shape similar to a square shape, and a plurality of metal wires for coupling the bonding leads of the wiring substrate to the electrode pads of the semiconductor chip. In a BGA, the metal wires are arranged at three sides of a main surface of the semiconductor chip, the bonding leads are provided in lines at the upper surface of the wiring substrate outside the respective opposed short sides of the main surface of the semiconductor chip, and the metal wires are coupled to the bonding leads. | 01-22-2015 |
20150028461 | Conductive Pads and Methods of Formation Thereof - In one embodiment, a device includes a first conductive pad disposed over a substrate, and a etch stop layer disposed over a top surface of the first conductive pad. The device further includes a solder barrier disposed over the etch stop layer. | 01-29-2015 |
20150035128 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a metal holder, a semiconductor chip on the holder, and a reinforcing portion. The reinforcing portion is formed by bending a portion of the holder, the reinforcing portion includes a groove depressed from a surface of the holder and a protrusion on a back of the groove. | 02-05-2015 |
20150054144 | SEMICONDUCTOR PACKAGE INCLUDING MULTIPLE CHIPS AND SEPARATE GROUPS OF LEADS - Provided sa a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package. | 02-26-2015 |
20150069589 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element in a frame body. The semiconductor element includes a first electrode electrically connected to an electrode block provided on a first side of the semiconductor element. A connection element, which in some embodiments may be a portion of the electrode block, connects the electrode block to the frame body. The semiconductor element is sealed within an enclosure formed at least in part by the frame body, the connection element, and the electrode block. The connection element includes a fragile portion which has a resistance to increases in pressure or temperature that is less than other portions of the connection element. That is, in general, the fragile portion will fail before other portions of the connection element when pressure or temperature increases, which may occur when, for example, the semiconductor element breaks down. | 03-12-2015 |
20150076672 | METHOD OF MANUFACTURING A CHIP PACKAGE, CHIP PACKAGE, METHOD OF MANUFACTURING A CHIP ASSEMBLY AND CHIP ASSEMBLY - A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip. | 03-19-2015 |
20150076673 | SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE HAVING AN OSCILLATOR - A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction: a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components. | 03-19-2015 |
20150091143 | SEMICONDUCTOR DEVICE AND ELECTRONIC UNIT PROVIDED WITH THE SAME - A semiconductor device includes first and semiconductor elements, an electroconductive support member including electroconductive elements, and a resin package. The first semiconductor element includes a first active surface and first electrodes formed on the first active surface. The second semiconductor element includes a second active surface and second electrodes formed on the second active surface. The electroconductive support member is electrically connected to the first and second semiconductor elements and support these elements. The resin package covers the first and second semiconductor elements. The second semiconductor element is located between the first semiconductor element and the electroconductive support member. The first electrodes of the first semiconductor element and the electroconductive elements are connected by wire. An electroconductive bonding material is also provided that bonds the second electrodes of the second semiconductor element and the electroconductive elements to which the wire is bonded. | 04-02-2015 |
20150091144 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device capable of being firmly bonded to a substrate. An outer lead ( | 04-02-2015 |
20150108623 | COATED LEAD FRAME BOND FINGER - A lead frame includes a lead formed of a conductive material and having first and second ends, opposing first and second main surfaces, and opposing first and second side surfaces each extending between the first and second main surfaces. A polymeric layer is formed at least on the first main surface and the first and second side surfaces of the lead at least proximate the second end of the lead. An opening in the polymeric layer on the first main surface of the lead proximate the second end is provided for connecting the lead to, for example, a semiconductor die via a bond wire. | 04-23-2015 |
20150115420 | SENSOR DIE GRID ARRAY PACKAGE - A semiconductor sensor die grid array package includes a semiconductor die having an active surface and an opposite backside surface. The active surface has external die connection pads. Conductive runners respectively connect the die connection pads to external connection mounts of the package. An encapsulant covers the semiconductor die. The encapsulant has a base surface proximal to the conductive runners and a stacking surface opposite the base surface. A sensor die is supported on the stacking surface. The sensor die has an active surface and an opposite backside surface that faces the stacking surface, and the sensor active surface has sensor connection pads. Conductive vias engage with the conductive runners and also are wire bonded to one of the sensor connection pads. | 04-30-2015 |
20150130035 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a stand-off layer over a plurality of microelectronic dies on a semiconductor workpiece, and removing selected portions of the stand-off layer to form a plurality of stand-offs with the individual stand-offs positioned on a backside of a corresponding die. The method further includes cutting the semiconductor workpiece to singulate the dies, and attaching the stand-off on a first singulated die to a second die. | 05-14-2015 |
20150145109 | Semiconductor Package and Method for Producing the Same - A semiconductor package includes a housing having a bottom surface and an upper surface and a solder pad arranged in the bottom surface of the housing. The solder pad includes a solderable through hole. The housing includes an opening extending from the through hole to the upper surface of the housing. | 05-28-2015 |
20150145110 | LEADLESS SURFACE MOUNT ASSEMBLY PACKAGE AND METHOD OF MANUFACTURING THE SAME - Embodiments of the present disclosure relate to a leadless surface mount assembly package, an electronic device, and a method for forming a surface mount assembly package, which package comprising: a first lead; a second lead; a chip fixed on an upper surface of the first lead; a clip coupled to the second lead, a lower surface of the clip being fixed to an upper surface of the chip. The surface mount assembly package further comprises a molding compound for molding the first lead, the second lead, the chip, and the clip, wherein ends of the first lead and the second lead are only exposed from the molding compound, without outward extending from the molding compound. By using the embodiments of the present disclosure, costs can be saved and processing flow can be simplified, and a new-model leadless surface mount assembly package is obtained. | 05-28-2015 |
20150294920 | SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor, lead frames, a metal spacer, one surface of which is bonded to the transistor by a first bonding material and the other surface of which is bonded to the lead frame by a second bonding material, and a plastic mold. The plastic mold packages the transistor and the metal spacer. One surface of each of the lead frames is attached to the plastic mold. Strength of the second bonding material is lower than strength of the first bonding material. According to the above configuration, when stress is repeatedly applied to the semiconductor device, a crack occurs earlier in the second bonding material than in the first bonding material. The stress is buffered at the first bonding material. | 10-15-2015 |
20150303121 | HERMETIC PLASTIC MOLDED MEMS DEVICE PACKAGE AND METHOD OF FABRICATION - A hermetically packaged microelectromechanical system (MEMS) device has a substrate with an assembly pad ( | 10-22-2015 |
20150336314 | Device Package Configuration and Method for Compensating for Unbalanced Resin Flow in Mold Cavities - A semiconductor package formation arrangement includes a mold housing with an interior cavity having top, bottom and first and second end sides. A gate for transferring liquefied molding material extends to the first end side. A lead frame having a top surface, a rear surface opposite the top surface and a mold flow modifier forms a first cavity section between the top surface and the top side and a second cavity section between the rear surface and the bottom side. A topology of the lead frame causes liquefied molding material to fill the first and second cavity sections at different rates. The mold flow modifier extends away from the lead frame so as to compensate for the difference between the first and second rates. | 11-26-2015 |
20150340305 | STACKED DIE PACKAGE WITH REDISTRIBUTION LAYER - A packaged semiconductor device has lead fingers that define a cavity, and a first die located within the cavity. A second die abuts an inactive side of the first die. The second die is electrically connected to one or more of the lead fingers. A redistribution layer abuts an active side of the first die. Metal structures are situated on an outer surface of the redistribution layer. The redistribution layer electrically connects (i) one or more of the metal structures to one or more of the lead fingers and (ii) one or more of the metal structures to one or more bond pads on the active side of the first die. | 11-26-2015 |
20150348912 | Metal Pad for Laser Marking - A package includes a device die, a molding material molding the device die therein, and a plurality of redistribution lines overlying the device die and the molding material. A laser mark pad is coplanar with one of the plurality of redistribution lines, wherein the laser mark pad and the one of the plurality of redistribution layers are formed of the same conductive material. A polymer layer is over the laser mark pad and the plurality of redistribution lines. A tape is attached over the polymer layer. A laser mark penetrates through the tape and the polymer layer. The laser mark extends to a top surface of the laser mark pad. | 12-03-2015 |
20150357266 | SEMICONDUCTOR DEVICE ASSEMBLED USING TWO LEAD FRAMES - A packaged semiconductor device is assembled using a first lead frame upon which a die is mounted and encapsulated and a second lead frame that provides bent leads for the device. By using two different lead frames, an array of the first lead frames can be configured with more lead frames for more devices than a comparably sized lead frame array of the prior art because the first lead frame array does not need to provide the leads for the packaged devices. Instead, the leads are provided by the second lead frame array, which can be attached to the first lead frame array after the dies have been mounted and encapsulated on the first lead frame array. | 12-10-2015 |
20150357303 | SEMICONDUCTOR CIRCUIT AND METHOD FOR PRODUCING THE SEMICONDUCTOR CIRCUIT - A power semiconductor circuit includes at least one semiconductor having at least one contact area, and at least one bonding conductor strip having at least one contact region fastened on at least one of the contact areas. The contact region of the bonding conductor strip includes cutouts. | 12-10-2015 |
20150364331 | EXTREMELY THIN PACKAGE - Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe or substrate via connections and EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate. | 12-17-2015 |
20150364373 | Quad Flat No Lead Package And Method Of Making - A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material. | 12-17-2015 |
20150364403 | PACKAGED SEMICONDUCTOR COMPONENTS HAVING SUBSTANTIALLY RIGID SUPPORT MEMBERS AND METHODS OF PACKAGING SEMICONDUCTOR COMPONENTS - Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die. | 12-17-2015 |
20150364431 | SILICON SHIELD FOR PACKAGE STRESS SENSITIVE DEVICES - A surface mount semiconductor package, semiconductor device, and method for fabrication of the surface mount semiconductor package and electrical device are described that include a leadframe assembly, an integrated circuit device disposed on the leadframe assembly, a silicon shield disposed on the integrated circuit device, where the silicon shield is configured to mitigate packaging stress to the integrated circuit device, and a molding layer that encapsulates the integrated circuit device, the silicon shield, and at least a portion of the leadframe assembly. | 12-17-2015 |
20150371932 | THIN FILM RDL FOR NANOCHIP PACKAGE - A high density film adapted for nanochip package comprises three redistribution layers. A bottom redistribution circuit has a plurality of first bottom pads adapted for a nanochip to mount; and has a plurality of first top pads. The density of the first bottom pads is higher than the density of the first top pads. A middle redistribution circuit has a plurality of second bottom pads electrically coupled to the first top pads; and has a plurality of second top pads. The density of the second bottom pads is higher than the density of the second top pads. A top redistribution circuit has a plurality of third bottom pads electrically coupled to the second top pads; and has a plurality of third top pads. The density of the third bottom pads is higher than the density of the third top pads. | 12-24-2015 |
20150380342 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor chip, a signal lead that is arranged in a periphery of the semiconductor chip and has a main surface and a rear surface opposed to the main surface, a wire that electrically connects the semiconductor chip and the main surface of the signal lead, and a sealing body made of sealing resin that seals the semiconductor chip, the signal lead and the wire. The signal lead has, in an extending direction of the signal lead, one end located inside the sealing body, the other end located outside the sealing body, and a wire connection region which is the main surface of the signal lead and to which the wire is connected, and an inner groove is provided in the main surface of the signal lead between the one end and the wire connection region. | 12-31-2015 |
20160005710 | METHODS OF ATTACHING ELECTRONIC COMPONENTS - A method of attaching an electronic component to a metal substrate, wherein the electronic component comprises solder provided on an exposed solder region. The method comprising: forming a metal-based compound layer on the substrate; placing the electronic component on the metal substrate such that the solder region is in contact with a contact region of the metal-based compound layer; and heating the solder region such that the contact region of the metal-based compound layer dissolves and the solder region forms an electrical connection between the electronic component and the metal substrate. The metal-based compound layer can have a minimum thickness of 10 nm. | 01-07-2016 |
20160035651 | LEADLESS SEMICONDUCTOR PACKAGE AND METHOD - A method of forming semiconductor devices on a leadframe structure. The leadframe structure comprising an array of leadframe sub-structures each having a semiconductor die arranged thereon. The method comprises; providing electrical connections between terminals of said lead frame sub-structures and said leadframe structure; encapsulating said leadframe structure, said electrical connections and said terminals in an encapsulation layer; performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose a side portion of said terminals; electro-plating said terminals to form metal side pads; and performing a second series of parallel cuts angled with respect to the first series of parallel cuts, the second series of cuts extending through the lead frame structure and the encapsulation layer to singulate a semiconductor device from the leadframe structure. | 02-04-2016 |
20160035666 | PACKAGES WITH MOLDING STRUCTURES AND METHODS OF FORMING THE SAME - A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via. | 02-04-2016 |
20160035700 | CHIP PACKAGE AND CHIP ASSEMBLY - A chip package is provided. The chip package may include an electrically conductive carrier; at least one first chip including a first side and a second side opposite of the first side, with its second side being electrically contacted to the electrically conductive carrier; an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip; at least one second chip arranged over the insulating layer and next to the first chip; encapsulating material over the first chip and the second chip; and electrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip. | 02-04-2016 |
20160043028 | PACKAGE-IN-SUBSTRATE, SEMICONDUCTOR DEVICE AND MODULE - A package-in-substrate includes an exposed pad having a surface that is capable of contacting the outside; a semiconductor chip arranged on a surface opposite to the surface of the exposed pad; a molding resin for molding the semiconductor chip; and a lead frame extending from a side surface of the molding resin and having a leading end portion with a machined shape. The leading end portion of the lead frame is cut to have a cutting angel that is an acute angle formed by an extended straight line of the lead frame with respect to a top surface of a package. | 02-11-2016 |
20160049358 | ELECTRONIC CIRCUIT, PRODUCTION METHOD THEREOF, AND ELECTRONIC COMPONENT - An electronic circuit according to this invention includes a printed circuit board and an electronic component that is soldered onto the printed circuit board. The electronic component is a flat package including a die pad exposed to outside and external electrode terminals. A gap is provided between the printed circuit board and the electronic component. The printed circuit board is provided with a hole between the die pad and the external electrode terminals in planar view. The gap is filled with insulating resin at least partially between the die pad and the external electrode terminals. The insulating resin is injected through the hole. | 02-18-2016 |
20160099199 | ELECTRONIC DEVICES WITH SOLDERABLE DIE STRUCTURES AND METHODS OF FORMATION OF SUCH DEVICES - An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer. | 04-07-2016 |
20160104665 | Power Converter Package with Integrated Output Inductor - In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier. | 04-14-2016 |
20160118320 | ELECTRONIC DEVICE PROVIDED WITH AN ENCAPSULATION STRUCTURE WITH IMPROVED ELECTRIC ACCESSIBILITY AND METHOD OF MANUFACTURING THE ELECTRONIC DEVICE - An electronic device comprising: a semiconductor die integrating an electronic component; a leadframe housing the semiconductor die; a protection body, which surrounds laterally and at the top the semiconductor die and, at least in part, the leadframe structure, defining a top surface, a bottom surface, and a thickness of the electronic device; and a conductive lead electrically coupled to the semiconductor die. The conductive lead is modelled in such a way as to extend throughout the thickness of the protection body for forming a front electrical contact accessible from the top surface of the electronic device, and a rear electrical contact accessible from the bottom surface of the electronic device. | 04-28-2016 |
20160118321 | LEAD FRAME AND MANUFACTURING METHOD OF LEAD FRAME - A lead frame includes a lead frame body processed in a predetermined shape, and including a notched part provided at an end of the lead frame body, the notched part being used as a starting point of tape-removing, a resin leakproof tape stuck on a back surface of the lead frame body, and a region of a periphery of the notched part in the back surface of the lead frame body, the region being reduced in a strength of bonding between the resin leakproof tape and the lead frame body is reduced relative to other region. | 04-28-2016 |
20160118328 | MOLDING COMPOUND SUPPORTED RDL FOR IC PACKAGE - A cylindrical molding compound supported RDL for IC package is disclosed wherein a central cavity is formed in the center of the molding compound. A plurality of metal pillar is embedded in the molding compound, a redistribution layer is configured on bottom of the plurality of metal pillar; at least one passive element such as a capacitor can be mounted in the central cavity. The bottom of the package is adaptive for at least one chip to mount so that the passive element is close to the chip and therefore simultaneous switching noise (SSN) can be reduced to a minimum at the initial first stage when a power is turned on. | 04-28-2016 |
20160126166 | FLIP-CHIP ON LEADFRAME SEMICONDUCTOR PACKAGING STRUCTURE AND FABRICATION METHOD THEREOF - Flip-chip on leadframe (FCOL) semiconductor packaging structure and fabrication method thereof are provided. A semiconductor chip with copper pillars formed there-over is provided. A barrier layer is formed on the copper pillars. A solder material is coated on the barrier layer. A layer of soldering flux is coated on the solder material. A leadframe with electric leads formed thereon is provided. An insulating layer is formed an the leadframe and having a plurality of openings to expose portion of the electric leads. The semiconductor chip is placed upside down onto the leadframe to have the soldering flux in contact with the portion of the electric leads exposed in the openings. The solder material flows back to form conductive interconnections between the copper pillars and the portion of the electric leads exposed in the openings. The semiconductor chip is packaged with the leadframe using a mold compound. | 05-05-2016 |
20160126169 | LEADLESS SEMICONDUCTOR DEVICE AND METHOD OF MAKING THEREOF - Consistent with an example embodiment, there is a leadless packaged semiconductor device having top and bottom opposing major surfaces and sidewalls extending there between. The leadless packaged semiconductor device comprises a lead frame sub-assembly having an array of two or more lead frame portions each having a semiconductor die arranged thereon. At least five I/O terminals each of said terminals comprise a respective metal side pad; and the respective metal side pad has a step profile. A feature of this embodiment is that these metal side pads, having a step profile, are electroplated to enhance their solderability. | 05-05-2016 |
20160126197 | SEMICONDUCTOR DEVICE HAVING A STRESS-COMPENSATED CHIP ELECTRODE - A semiconductor device includes a semiconductor chip having a first main surface and a second main surface. A chip electrode is disposed on the first main surface. The chip electrode includes a first metal layer and wherein the first metal layer is arranged between the semiconductor chip and the second metal layer. | 05-05-2016 |
20160133599 | QFN Package - A method of making a flat no lead package including attaching a first plurality of leads in spaced apart relationship in a predetermined pattern on a tape and attaching a first die to the tape at a predetermined position within the predetermined lead pattern. | 05-12-2016 |
20160148876 | FLAT NO-LEADS PACKAGE WITH IMPROVED CONTACT PINS - According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple. | 05-26-2016 |
20160148877 | QFN PACKAGE WITH IMPROVED CONTACT PINS - According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe, bonding the IC chip to at least some of the plurality of pins, encapsulating the leadframe and bonded IC chip, sawing a step cut into the encapsulated leadframe, plating the exposed portion of the plurality of pins, and cutting the IC package free from the bar. The leadframe may include a plurality of pins extending from the center support structure and a bar connecting the plurality of pins remote from the center support structure. The step cut may be sawn into the encapsulated leadframe along a set of cutting lines using a first saw width without separating the bonded IC package from the bar, thereby exposing at least a portion of the plurality of pins. The IC package may be cut free from the bar by sawing through the encapsulated lead frame at the set of cutting lines using a second saw width less than the first saw width. | 05-26-2016 |
20160155687 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 06-02-2016 |
20160172275 | PACKAGE FOR A SURFACE-MOUNT SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 06-16-2016 |
20160172316 | MOLD FOR RESIN SEALING, MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR DEVICE | 06-16-2016 |
20160181187 | SEMICONDUCTOR DEVICE AND LEAD FRAME | 06-23-2016 |