Entries |
Document | Title | Date |
20080246127 | Arrangement for high frequency application - A source mounted semiconductor device package is described which includes a semiconductor die having first and second opposing major surfaces, first and second major electrodes disposed on respective major surfaces and a control electrode disposed on the second major surface, and a thin metal clip electrically connected to the first major electrode of the die. The thin metal clip has a relatively large surface area, and package resistance which is caused by skin effect phenomenon is reduced thereby in high frequency applications. | 10-09-2008 |
20080251896 | Method of manufacturing a coaxial trace in a surrounding material, coaxial trace formed thereby, and semiconducting material containing same - A method of manufacturing a coaxial trace ( | 10-16-2008 |
20080290474 | Multi-Layer Circuit Substrate and Method Having Improved Transmission Line Integrity and Increased Routing Density - A multi-layer circuit substrate and method having improved transmission line integrity and increased routing density uses a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs. | 11-27-2008 |
20080290475 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit which is connected to a substrate by solder bumps wherein, when at least one solder bump is connected to a signal line of the semiconductor integrated circuit and the semiconductor integrated circuit is mounted on the substrate, the semiconductor integrated circuit is bonded to the substrate by the solder bump, and the interconnection to the substrate is made by dummy bumps forming wires at the substrate side. | 11-27-2008 |
20080303121 | Integrated Electronic Circuitry and Heat Sink - A multi-layer heatsink module for effecting temperature control in a three-dimensional integrated chip is provided. The module includes a high thermal conductivity substrate having first and second opposing sides, and a gallium nitride (GaN) layer disposed on the first side of the substrate. An integrated array of passive and active elements defining electronic circuitry is formed in the GaN layer. A metal ground plane having first and second opposing sides is disposed on the second side of the substrate, with the first side of the ground plane being adjacent to the second side of the substrate. A dielectric layer of low thermal dielectric material is deposited on the back side of the ground plane, and a metal heatsink is bonded to the dielectric layer. A via extends through the dielectric layer from the metal heatsink to the metal ground plane. | 12-11-2008 |
20090032914 | THREE-DIMENSIONAL PACKAGE MODULE, METHOD OF FABRICATING THE SAME, AND METHOD OF FABRICATING PASSIVE DEVICE APPLIED TO THE THREE-DIMENSIONAL PACKAGE MODULE - Provided is a three-dimensional aluminum package module including: an aluminum substrate; an aluminum oxide layer formed on the aluminum substrate and having at least one first opening of which sidewalls are perpendicular to an upper surface of the aluminum substrate; a semiconductor device mounted in the first opening using an adhesive; an organic layer covering the aluminum oxide layer and the semiconductor device; and a first interconnection line and a passive device circuit formed on the organic layer and the aluminum oxide layer. | 02-05-2009 |
20090039479 | MODULE FOR INTEGRATING PERIPHERAL CIRCUIT AND A MANUFACTURING METHOD THEREOF - A module for integrating peripheral circuit includes a silicon chip substrate, at least one peripheral circuit unit, and at least one main circuit unit. The peripheral circuit unit is integrated in the silicon chip substrate via a semiconductor manufacturing process. The main circuit unit is mounted on the surface of the silicon chip substrate and is electrically connected with the peripheral circuit unit for transmitting the signal. Thereby, the dimension of the module is reduced. | 02-12-2009 |
20090051015 | SEMICONDUCTOR DEVICE AND PRINTED CIRCUIT BOARD - For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines. | 02-26-2009 |
20090057849 | INTERCONNECT IN A MULTI-ELEMENT PACKAGE - A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side, and a connector block within the polymer layer. The connector block has at least one electrical path extending from a first surface of the connector block to a second surface of the connector block. The at least one electrical path electrically couples the interconnect layer to the first conductive element. A method of forming the packaged semiconductor device is also described. | 03-05-2009 |
20090072358 | Semiconductor Integrated Circuit Package, Printed Circuit Board, Semiconductor Apparatus, and Power Supply Wiring Structure - A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside. | 03-19-2009 |
20090079042 | Center Conductor to Integrated Circuit for High Frequency Applications - A microcircuit has a node thereon. A center conductor is electrically connected to the node and the center conductor has a length to minimum radius ratio of at least 50. A method of for providing electrical interconnections in a microcircuit, comprises the steps of depositing conductive bumps on the microcircuit; and aligning and bonding a center conductor to the conductive bumps, the center conductor having a first end and a second end, and the center conductor having a length to minimum radius ratio of at least 50. | 03-26-2009 |
20090108416 | DIRECT-CONNECT SIGNALING SYSTEM - A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board. | 04-30-2009 |
20090108417 | Method and System for Providing a Continuous Impedance Along a Signal Trace in an IC Package - A multi-layered integrated circuit chip package comprises a void layer that includes at least one void. The multi-layered integrated circuit chip package also includes an insulation layer that electrically insulates the void layer from a trace layer. At least one trace resides in the trace layer. The trace having a length in which a first section thereof is located an overlying relation to the at least one void, wherein the first section overlying the void has a width different from an adjacent section of the trace located on at least one opposing side of the void such that impedance mismatches and signal reflections along the trace are mitigated. | 04-30-2009 |
20090127675 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base substrate on which semiconductor elements are disposed; a covering member which is provided to the base substrate, which covers the semiconductor elements, and which includes an opening at an end thereof at the side of the base substrate; and a connector substrate which is provided on the base substrate in a manner that the connector substrate closes the opening, which includes a first high-frequency signal line in an area located inside the covering member for a first surface, and which includes a second high-frequency signal line on a second surface being a surface on the opposite side of the first surface, the second high-frequency signal line being electrically connected to the first high-frequency signal line; wherein the base substrate is formed in a manner that the base substrate is located away from the second high-frequency signal line. | 05-21-2009 |
20090140400 | Method of Mid-Frequency Decoupling - A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance. | 06-04-2009 |
20090152689 | Integrated Circuit Package for High-Speed Signals - An integrated circuit package having a multi-segment transmission line transformer for impedance matching a packaged integrated circuit, such as a driver or receiver, to a printed circuit board (PCB) transmission line to which the packaged chip is attached by, for example, solder balls. In one exemplary embodiment, a three-segment transmission line transformer provides improved broadband performance with the advantage of having a middle segment with a flexible length for easier routing. The length of each end segment of the three-segment transformer is adjusted to provide at least partial cancellation of reflections between the PCB and the transformer, and between the transformer and a circuit on the integrated circuit, respectively. Further, the inductive reactance of the solder balls and via wiring may be cancelled out by the transformed chip impedance to provide a non-inductive termination to the PCB transmission line at approximately one-half the highest data rate of the channel. | 06-18-2009 |
20090267201 | Vertical Transmission Structure - A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core. | 10-29-2009 |
20090315157 | PROTECTION FOR PROXIMITY ELECTRONICS AGAINST ELECTROSTATIC DISCHARGE - A system of protecting a proximity communication system against electrostatic discharge (ESD). The proximity communication system includes two chips, each having an array of electrical pads at its surface and covered by a thin dielectric layer such that capacitive coupling circuits are formed between the chips when they are joined together. In at least one of the chips, an additional protection pad is formed away from the array, and heavy protection circuitry is connected to it. Its surface is exposed through the dielectric surface over it such that, when an ESD aggressor approaches, the discharge occurs to the protection pad. | 12-24-2009 |
20090315158 | WIRING BOARD AND ELECTRICAL SIGNAL TRANSMISSION SYSTEM - A wiring board equipped with differential lines which compensate for differences in via lengths to minimize signal deterioration is disclosed. Two conductors are couple to different substrate levels through vias of different lengths. Compensation means are provided to correct for the phase difference caused by the different lengths. | 12-24-2009 |
20100006990 | INTERCONNECT STRUCTURE FOR HIGH FREQUENCY SIGNAL TRANSMISSIONS - A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects. | 01-14-2010 |
20100078781 | INPUT/OUTPUT PACKAGE ARCHITECTURES, AND METHODS OF USING SAME - A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s. | 04-01-2010 |
20100200968 | MICROWAVE CIRCUIT ASSEMBLY - A microwave circuit assembly including a flip-chip attachable integrated circuit die attached to a substrate by an interconnect device. The integrated circuit die and the substrate have microstrip transmission lines that are electrically coupled through the interconnect device. The interconnect device forms a transmission line configured to electrically couple the microstrip transmission line on the substrate to the microstrip transmission line on the integrated circuit die The interconnect device includes stubs to enhance the ground elements of the interconnect device transmission line and provide a microwave short for the integrated circuit die. | 08-12-2010 |
20110031595 | MICROWAVE MODULE - In a microwave module with at least one semiconductor chip, which provides on its upper side a connecting-line structure formed in particular as a coplanar line, which is connected to at least one adjacent incoming and/or outgoing line structure formed on the upper side of the substrate, the chip is glued with its underside and all lateral surfaces, on which no high-frequency connecting lines lead to the chip, within a recess of a metal part with good thermal conduction. | 02-10-2011 |
20110037151 | Multiple Substrate Electrical Circuit Device - In one embodiment of the disclosure, a method includes providing a carrier substrate, forming a first region over an upper surface of the substrate, creating an electrical component using a planar process, embedding the electrical component in the dielectric layer, and removing a substrate portion of the electrical component. The first region includes a dielectric layer and may be made of any material that electrically isolates the electrical component from the carrier substrate. The electrical component may be created using a planar process thereby having an epitaxial surface that is embedded in the dielectric layer. | 02-17-2011 |
20110089543 | SEMICONDUCTOR DEVICE WITH A BALUN - A semiconductor integrated circuit device with a balun which is formed above a conductive semiconductor substrate and which includes a dielectric film, an unbalanced line for transmitting an unbalanced signal, and balanced lines for transmitting a balanced signal. The unbalanced line is placed opposite to the balanced lines via a nano-composite film that is a region of the dielectric film. The nano-composite film, interposed between the unbalanced line and the balanced lines, has a relative permittivity higher than that of other regions of the dielectric film. This allows suppression of electromagnetic coupling of transmission lines or passive elements other than the balun, thereby providing a semiconductor device with a wide-band and small-size balun. | 04-21-2011 |
20110127655 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a wiring board including a conductor portion formed on a first surface thereof on which the semiconductor element is mounted, the conductor portion being electrically connected to the semiconductor element, and a concave cap provided to seal the first surface of the wiring board, the concave cap being mounted through an adhesive on the first surface of the wiring board | 06-02-2011 |
20110133317 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 06-09-2011 |
20110186974 | HIGH FREQUENCY FLIP CHIP PACKAGE STRUCTURE OF POLYMER SUBSTRATE - A high frequency flip chip package substrate of a polymer is a one-layer structure packaged by a high frequency flip chip package process to overcome the shortcomings of a conventional two-layer structure packaged by the high frequency flip chip package process. The conventional structure not only incurs additional insertion loss and return loss in its high frequency characteristic, but also brings out a reliability issue. Thus, the manufacturing process of a ceramic substrate in the conventional structure still has the disadvantages of a poor yield rate and a high cost. | 08-04-2011 |
20110210430 | DEVICE WITH GROUND PLANE FOR HIGH FREQUENCY SIGNAL TRANSMISSION AND METHOD THEREFOR - A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz. | 09-01-2011 |
20110210431 | MICROWAVE CIRCUIT PACKAGE - A microwave circuit package having a ball grid array, BGA, soldered on to a planar major surface of a metal housing of the package for the electrical connection of the ports of the microwave circuit through RF signal paths to an adjacent electrical device. Each of the RF signal paths comprises a pin electrically connected to a respective port of the microwave circuit package, projecting normally through an opening in the said major surface from which it is electrically insulated, and soldered to a ball of the BGA; the pin and the surrounding balls of the BGA, which are soldered to the metal housing, constituting a coaxial RF signal path. | 09-01-2011 |
20120068316 | TRANSITION FROM A CHIP TO A WAVEGUIDE PORT - The present invention relates to a transition from a chip to a waveguide port ( | 03-22-2012 |
20120104575 | Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes - A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips. | 05-03-2012 |
20120104576 | INTERCONNECT STRUCTURE FOR HIGH FREQUENCY SIGNAL TRANSMISSIONS - A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects. | 05-03-2012 |
20120146198 | INTEGRATED CIRCUITS AND FABRICATION PROCESS THEREOF - An integrated circuit includes a conductive pad and a substrate. The conductive pad is used to transfer a first signal. The substrate blocks a second signal from a first region of the substrate to the conductive pad. A second region of the substrate insulates a third region of the substrate from the first region. The first and third regions include a first type of semiconductor and the second region includes a second type of semiconductor. In addition, a first shadow obtained by perpendicularly projecting the third region onto a surface of the substrate overlaps with a second shadow obtained by perpendicularly projecting the conductive pad onto the surface. | 06-14-2012 |
20120175753 | THIN SEMICONDUCTOR DEVICE AND OPERATION METHOD OF THIN SEMICONDUCTOR DEVICE - The present invention provides a thin semiconductor device in which its security such as prevention of counterfeit or information leakage is to be enhanced. One feature of the present invention is a thin semiconductor device in which a plurality of thin film integrated circuits are mounted and in which at least one integrated circuit is different from the other integrated circuits in any one of a specification, layout, frequency for transmission or reception, a memory, a communication means, a communication rule and the like. According to the present invention, a thin semiconductor device tag having the plurality of thin film integrated circuits communicates with a reader/writer and at least one of the thin film integrated circuits receives a signal to write information in a memory, and the information written in the memory determines which of the thin film integrated circuits communicates. | 07-12-2012 |
20120193771 | TRANSMISSION LINE, IMPEDANCE TRANSFORMER, INTEGRATED CIRCUIT MOUNTED DEVICE, AND COMMUNICATION DEVICE MODULE - A transmission line includes two tapered lines having a tapered planar shape and arranged in parallel, opposite lines provided in opposition to the narrower width sides of the two tapered lines, and a bonding wire for connecting the narrower width sides of the two tapered lines and the opposite lines, wherein the width between two outer edges on the narrower width sides of the two tapered lines arranged in parallel is greater than the width between outer edges on the opposite side of the opposite lines in opposition to the narrower width sides of the two tapered lines. | 08-02-2012 |
20120217625 | INTEGRATED CIRCUIT MICRO-MODULE - One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna. | 08-30-2012 |
20120223422 | APPARATUS AND METHODS FOR REDUCING IMPACT OF HIGH RF LOSS PLATING - To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad. | 09-06-2012 |
20120241924 | SEMICONDUCTOR DEVICE HAVING ANTENNA AND METHOD FOR MANUFACTURING THEREOF - The present invention provides an antenna in that the adhesive intensity of a conductive body formed on a base film is increased, and a semiconductor device including the antenna. The invention further provides a semiconductor device with high reliability that is formed by attaching an element formation layer and an antenna, wherein the element formation layer is not damaged due to a structure of the antenna. The semiconductor device includes the element formation layer provided over a substrate and the antenna provided over the element formation layer. The element formation layer and the antenna are electrically connected. The antenna has a base film and a conductive body, wherein at least a part of the conductive body is embedded in the base film. As a method for embedding the conductive body in the base film, a depression is formed in the base film and the conductive body is formed therein. | 09-27-2012 |
20120248587 | Miniature Microwave Component for Surface-Mounting - A miniature component includes an MMIC microwave chip encapsulated in an individual package for surface-mounting capable of operating at a frequency F | 10-04-2012 |
20120267769 | INTEGRATED CIRCUIT PACKAGE WITH SEGREGATED TX AND RX DATA CHANNELS - A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively. | 10-25-2012 |
20130009289 | SEMICONDUCTOR DEVICE - An object of the present invention is providing a semiconductor device that is capable of improving the reliability of a semiconductor element and enhancing the mechanical strength without suppressing the scale of a circuit. The semiconductor device includes an integrated circuit sandwiched between first and second sealing films, an antenna electrically connected to the integrated circuit, the first sealing film sandwiched between a substrate and the integrated circuit, which includes a plurality of first insulating films and at least one second insulating film sandwiched therebetween, the second sealing film including a plurality of third insulating films and at least one fourth insulating film sandwiched therebetween. The second insulating film has lower stress than the first insulting film and the fourth insulating film has lower stress than the third insulating film. The first and third insulating films are inorganic insulating films. | 01-10-2013 |
20130037924 | ANTENNA SWITCH MODULES AND METHODS OF MAKING THE SAME - Antenna switch modules and methods of making the same are provided. In certain implementations, an antenna switch module includes a package substrate, an integrated filter, and a silicon on insulator (SOI) die attached to the package substrate. The SOI die includes a capacitor configured to operate in the integrated filter and a multi throw switch for selecting amongst the RF signal paths. In some implementations, a surface mount inductor is attached to the package substrate adjacent the SOI die and is configured to operate in the integrated filter with the capacitor. In certain implementations, the inductor is formed from a conductive layer of the package substrate disposed beneath a layer of the package substrate used to attach the SOI die. | 02-14-2013 |
20130175676 | HIGH FREQUENCY CIRCUIT COMPRISING GRAPHENE AND METHOD OF OPERATING THE SAME - A high frequency circuit includes a first electronic device, a second electronic device, and a graphene interconnection unit, where at least one of a trench and a via is defined under the graphene interconnection unit. | 07-11-2013 |
20130214397 | MULTILAYER WIRING BOARD AND ELECTRONIC DEVICE - A ground layer of a multilayer wiring board includes: a first clearance through which a first differential via is inserted without coming into contact with the ground layer; and a second clearance through which a second differential via is inserted without coming into contact with the ground layer. A distance between an outer edge of the first clearance on the side of the second differential via and the first differential via is set shorter than a distance between an outer edge of the first clearance on the side opposite from the second differential via and the first differential via. A distance between an outer edge of the second clearance on the side of the first differential via and the second differential via is set shorter than a distance between an outer edge of the second clearance on the side opposite from the first differential via and the second differential via. | 08-22-2013 |
20130221501 | DEVICES AND METHODS RELATED TO INTERCONNECT CONDUCTORS TO REDUCE DE-LAMINATION - Disclosed are systems, devices and methods for utilizing an interconnect conductor to inhibit or reduce the likelihood of de-lamination of a passivation layer of an integrated circuit die. In some implementations, a metal layer in ohmic contact with an intrinsic region of a semiconductor substrate can be partially covered by a passivation layer such as a dielectric layer. An interconnect conductor electrically connected to the metal layer can include an extension that covers an edge of the passivation layer to thereby inhibit the edge from lifting up. In some implementations, the metal layer in combination with a contact pad also in ohmic contact with the intrinsic region can yield a conduction path through the intrinsic region during an electrostatic discharge (ESD) event. In such a configuration, the interconnect conductor can route the ESD charge to a ground. | 08-29-2013 |
20130234305 | 3D TRANSMISSION LINES FOR SEMICONDUCTORS - A transmission line structure for semiconductor RF and wireless circuits, and method for forming the same. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground plane, and a second die including a second substrate, a second insulating layer, and a signal transmission line. The second die may be positioned above and spaced apart from the first die. An underfill is disposed between the ground plane of the first die and the signal transmission line of the second die. Collectively, the ground plane and transmission line of the first and second die and underfill forms a compact transmission line structure. In some embodiments, the transmission line structure may be used for microwave applications. | 09-12-2013 |
20130256849 | HIGH FREQUENCY TRANSITION MATCHING IN AN ELECTRONIC PACKAGE FOR MILLIMETER WAVE SEMICONDUCTOR DIES - A mmWave electronics package constructed from common Printed Circuit Board (PCB) technology and a metal cover. Assembly of the package uses standard pick and place technology and heat is dissipated directly to a pad on the package. Input/output of mmWave signal(s) is achieved through a rectangular waveguide. Mounting of the electronic package to an electrical printed circuit board (PCB) is performed using conventional reflow soldering processes and includes a waveguide I/O connected to an mmWave antenna. The electronic package provides for transmission of low frequency, dc and ground signals from the semiconductor chip inside the package to the PCB it is mounted on. An impedance matching scheme matches the chip to high frequency board transition by altering the ground plane within the chip. A ground plane on the high frequency board encircles the high frequency signal bump to confine the electromagnetic fields to the bump region reducing radiation loss. | 10-03-2013 |
20130256850 | ELECTRONIC PACKAGE FOR MILLIMETER WAVE SEMICONDUCTOR DIES - A mmWave electronics package constructed from common Printed Circuit Board (PCB) technology and a metal cover. Assembly of the package uses standard pick and place technology and heat is dissipated directly to a pad on the package. Input/output of mmWave signal(s) is achieved through a rectangular waveguide. Mounting of the electronic package to an electrical printed circuit board (PCB) is performed using conventional reflow soldering processes and includes a waveguide I/O connected to an mmWave antenna. The electronic package provides for transmission of low frequency, dc and ground signals from the semiconductor chip inside the package to the PCB it is mounted on. An impedance matching scheme matches the chip to high frequency board transition by altering the ground plane within the chip. A ground plane on the high frequency board encircles the high frequency signal bump to confine the electromagnetic fields to the bump region reducing radiation loss. | 10-03-2013 |
20130285218 | INTEGRATED ELECTRONIC COMPONENTS AND METHODS OF FORMATION THEREOF - Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals. | 10-31-2013 |
20130292809 | SEMICONDUCTOR PACKAGE - A semiconductor package including an antenna formed integrally therewith. The semiconductor package includes: a semiconductor chip; a sealing part sealing the semiconductor chip; a substrate part formed on at least one surface of the sealing part; and an antenna part formed on the sealing part and electrically connected to the semiconductor chip. | 11-07-2013 |
20140001610 | WIRELESS MODULE | 01-02-2014 |
20140008773 | Integrated Antenna Structure - Some embodiments relate to a semiconductor module comprising an integrated antenna structure configured to wirelessly transmit signals. The integrated antenna structure has a lower metal layer and an upper metal layer. The lower metal layer is disposed on a lower die and is connected to a ground terminal. The upper metal layer is disposed on an upper die and is connected to a signal generator configured to generate a signal to be wirelessly transmitted. The upper die is stacked on the lower die and is connected to the lower die by way of an adhesion layer having one or more micro-bumps. By connecting the lower and upper die together by way of the adhesion layer, the lower and upper metal layers are separated from each other by a large spacing that provides for a good performance of the integrated antenna structure. | 01-09-2014 |
20140077345 | SEMICONDUCTOR PACKAGE, METHOD AND MOLD FOR PRODUCING SAME, INPUT AND OUTPUT TERMINALS OF SEMICONDUCTOR PACKAGE - A semiconductor package according to the present invention includes: a semiconductor element where a high frequency signal is input or output; a planar lead terminal having an end electrically connected to an input terminal or an output terminal of the semiconductor element; an encapsulation resin for encapsulating the lead terminal and the semiconductor element, the lead terminal having another end exposed from the resin; and a ground enhancing metal body encapsulated in the encapsulation resin, having a first main surface facing the lead terminal and a second main surface exposed from the encapsulation resin, wherein the ground enhancing metal body has a shape with a cross section parallel to the second main surface and having a smaller area than an area of the first main surface. | 03-20-2014 |
20140097524 | COPLANAR WAVEGUIDE FOR STACKED MULTI-CHIP SYSTEMS - An approach for a coplanar waveguide structure in stacked multi-chip systems is provided. A method of manufacturing a semiconductor structure includes forming a first coplanar waveguide in a first chip. The method also includes forming a second coplanar waveguide in a second chip. The method further includes directly connecting the first coplanar waveguide to the second coplanar waveguide using a plurality of chip-to-chip connections. | 04-10-2014 |
20140117515 | INTEGRATED ANTENNAS IN WAFER LEVEL PACKAGE - A semiconductor module comprises a wafer package comprising an integrated circuit (IC) device embedded within the wafer package and a layer comprising at least one antenna structure and redistribution structures, wherein the antenna structure is coupled to the IC device and wherein the redistribution structures are coupled to the IC device. | 05-01-2014 |
20140124908 | HIGH FREQUENCY SWITCH - A compact high frequency switch needing no external control signal is obtained. The high frequency switch includes an anti-parallel diode (first anti-parallel diode) having one end and another end coupled with an antenna terminal (first high-frequency-signal input/output terminal) and a transmitting terminal (second high-frequency-signal input/output terminal), respectively, and becoming a conduction state in the input power not less than predetermined high frequency power. When the high frequency switch is an SPDT type, such a switch may include a ΒΌ-wavelength line in the use frequency of the high frequency switch having one end and another end coupled with the antenna terminal and a receiving terminal (third high-frequency-signal input/output terminal), respectively, and an anti-parallel diode (second anti-parallel diode) coupled between the receiving terminal and a ground and becoming a conduction state in the input power not less than predetermined high frequency power. | 05-08-2014 |
20140138804 | HIGH-FREQUENCY MODULE AND COMMUNICATION APPARATUS - A semiconductor component is face-up mounted on a package substrate. An antenna substrate is flip-chip mounted on a front side of the semiconductor component. A device-side high-frequency signal terminal is disposed on the front side of the semiconductor component, and an antenna-side high-frequency signal terminal is disposed on a back side of the antenna substrate. The device-side high-frequency signal terminal and the antenna-side high-frequency signal terminal are electrically connected to each other. Thus, the antenna substrate for high-frequency signals can be separated from the package substrate for baseband signals. | 05-22-2014 |
20140145316 | WIRELESS MODULE - A wireless module includes a first board ( | 05-29-2014 |
20140151860 | WIRELESS MODULE - A wireless module includes a first board which has a first component mounted thereon, a second board which faces the first board and has a second component mounted thereon, a connecting member which is provided between the first board and the second board and transmits a signal between the first board and the second board, and a filling material with which a space between the first board and the second board including the connecting member is sealed. A conductive member for connecting a ground between the first board and the second board is arranged in a periphery of the connecting member. | 06-05-2014 |
20140151861 | Managing Method of Building Material and Wireless Chip Applied to the Method - A lot of buildings have been built while it is concerned that a building material is used fraudulently. Therefore, the present invention provides a managing method of the material and a system thereof. The present invention provides a managing method including a step of attaching a sheet including a plurality of memories to each surface of a plurality of materials, a step of dividing the plurality of materials with the sheet in accordance with data in the memory, a step of constructing a building by using the divided material in accordance with the data in the memory, and a step of checking the data on the constructed building, which is stored in the plurality of memories. | 06-05-2014 |
20140183710 | LEADFRAME PACKAGE WITH INTEGRATED PARTIAL WAVEGUIDE INTERFACE - A MMIC package is disclosed comprising: a leadframe based overmolded package, a die positioned within the overmolded package; and a partial waveguide interface, wherein the partial waveguide interface is integral with the overmolded package facilitating low cost and reliable assembly. Also disclosed is an overmolded package where the die sits on a metal portion exposed on the bottom of the package and the package is configured for attachment to a chassis of a transceiver such that heat from the die is easily dissipated to the chassis with a direct thermal path. The disclosure facilitates parallel assembly of MMIC packages and use of pick and place/surface mounting technology for attaching the MMIC packages to the chassis of transceivers. This facilitates reliable and low cost transceivers. | 07-03-2014 |
20140191377 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package comprising a substrate and at least one semiconductor die is described. A connection unit may provide electrical connections between the substrate and the semiconductor die. The connection unit may comprise a stack of conduction layers and isolation layers stacked atop each other. The stack may include a microstrip line or a coplanar waveguide. The microstrip line or the coplanar waveguide may be part of a balun, a power divider, or a directional coupler. | 07-10-2014 |
20140203417 | MITIGATION OF FAR-END CROSSTALK INDUCED BY ROUTING AND OUT-OF-PLANE INTERCONNECTS - In accordance with one aspect of the present description, a transmission line such as a microstrip or stripline transmission line, has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk (FEXT) induced by inductive coupling between the transmission line and an adjacent transmission line, and also far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line. In another aspect of the present description, a microstrip transmission line may have multiple stubby line sections having different resistances and impedances to more gradually transition from to the typically low impedance characteristics of vertical interconnects such as the PTH vias and socket connectors. Other aspects are described. | 07-24-2014 |
20140217564 | SEMICONDUCTOR DEVICE WITH INTEGRATED ANTENNA AND MANUFACTURING METHOD THEREFOR - There is disclosed a package comprising at least an integrated circuit embedded in an electrically non-conductive moulded material. The moulded material includes at least one moulded pattern on at least one surface thereof, and at least one electrically conductive track in the pattern. There is further provided at least one capacitive, inductive or galvanic component electrically connecting between at least two parts of the at least one electrically conductive track. The conductive track can be configured as antenna, and the capacitive, inductive or galvanic component is used to adjust tuning and other characteristics of the antenna. | 08-07-2014 |
20140231974 | Module and Method of Manufacturing a Module - A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity. | 08-21-2014 |
20140246764 | ROLLED-UP TRANSMISSION LINE STRUCTURE FOR A RADIOFREQUENCY INTEGRATED CIRCUIT (RFIC) - A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure. | 09-04-2014 |
20140252570 | LEAD-FRAME CIRCUIT PACKAGE - A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. | 09-11-2014 |
20140264787 | DIFFERENTIAL EXCITATION OF PORTS TO CONTROL CHIP-MODE MEDIATED CROSSTALK - A differential port and a method of arranging the differential port are described. The method includes arranging a first electrode to receive a drive signal, and arranging a second electrode to receive a guard signal, the guard signal having a different phase than the drive signal and the first electrode and the second electrode having a gap therebetween. The method also includes disposing a signal line from the first electrode to drive a radio frequency (RF) device. | 09-18-2014 |
20140264788 | HIGH-FREQUENCY MODULE - A high-frequency module includes a lower base member having a recess part formed in an upper face thereof, and having a base metal part formed on a lower face thereof that is to be grounded, an upper substrate disposed inside the recess part of the lower base member, a semiconductor device mounted on an upper face of the upper substrate, a first ground line connected to the semiconductor device and formed on the upper substrate, and a ground metal part connected to the base metal part and disposed in the lower base member, wherein the ground metal part is connected to the first ground line on the upper substrate. | 09-18-2014 |
20140327120 | DIFFERENTIAL EXCITATION OF PORTS TO CONTROL CHIP-MODE MEDIATED CROSSTALK - A differential port and a method of arranging the differential port are described. The method includes arranging a first electrode to receive a drive signal, and arranging a second electrode to receive a guard signal, the guard signal having a different phase than the drive signal and the first electrode and the second electrode having a gap therebetween. The method also includes disposing a signal line from the first electrode to drive a radio frequency (RF) device. | 11-06-2014 |
20140339689 | HIGH FREQUENCY SWITCH MODULE - A high frequency switch module includes a multilayer substrate and a switch IC. The switch IC is mounted on a top plane of the multilayer substrate. A drive power signal input port and control signal input ports are connected to direct current external input ports through direct current voltage conductors, respectively. In-layer conductors of the direct current voltage conductors are arranged so that the in-layer conductors overlap each other at least partially in a state in which the multilayer substrate is viewed along a stacking direction. | 11-20-2014 |
20140374888 | SEMICONDUCTOR DEVICE - A high frequency signal can be transmitted and received in a semiconductor device. In a QFP, an antenna (frame body) is supported by three suspension leads. The antenna is arranged to be symmetrical with respect to a first virtual diagonal line of a plan view of a sealing body. One of the three suspension leads is arranged on the first virtual diagonal line. With this configuration, discontinuities of a wave of a signal in the antenna can be reduced, as a result of which the high frequency signal of 5 Gbps class can be transmitted and received in the QFP. | 12-25-2014 |
20150021748 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes: a substrate, a high-frequency integrated circuit being provided on the substrate, a cap, and a sealing wall provided between the substrate and the cap. The cap includes a first conductive layer, a second conductive layer, an insulating layer provided between the first conductive layer and the second conductive layer, and a conductive via provided in the insulating layer. The conductive via connects the first conductive layer and the second conductive layer. The first conductive layer or the second conductive layer is connected to a ground potential. The sealing wall surrounds the high-frequency integrated circuit. | 01-22-2015 |
20150028460 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A common mode filter monolithically integrated with a protection device. In accordance with an embodiment a semiconductor material having a resistivity of at least 5 Ohm-centimeters is provided. A protection device is formed from a portion of the semiconductor material and a dielectric material is formed over the semiconductor material. A coil is formed over the dielectric material. | 01-29-2015 |
20150061091 | Functionalised redistribution layer - An electronic device which comprises at least one interconnect, a semiconductor chip comprising at least one electric chip pad, an encapsulant structure packaging at least a part of the semiconductor chip, and an electrically conductive redistribution layer arranged between and electrically coupled with the at least one interconnect and the at least one chip pad, wherein the redistribution layer comprises at least one adjustment structure configured for adjusting radio frequency properties of a transition between the semiconductor chip and its periphery. | 03-05-2015 |
20150061092 | APPARATUS AND METHODS FOR REDUCING IMPACT OF HIGH RF LOSS PLATING - To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad. | 03-05-2015 |
20150108622 | INTERCONNECT BOARD AND SEMICONDUCTOR DEVICE - Impedance mismatching to be caused in signal transmission paths is reduced, without any restriction being put on the number of layers. | 04-23-2015 |
20150137335 | Managing Parasitic Capacitance and Voltage Handling of Stacked Radio Frequency Devices - Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. Some implementations include a radio frequency switch arrangement having a ground plane, a stack and a first solder bump. The stack is arranged in relation to the ground plane, and includes switching elements coupled in series with one another, and a first end of the stack includes a respective terminal of a first one of the plurality of switching elements. The first solder bump is coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement. | 05-21-2015 |
20150137336 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, IN-MILLIMETER-WAVE DIELECTRIC TRANSMISSION DEVICE, METHOD OF MANUFACTURING THE SAME, AND IN-MILLIMETER-WAVE DIELECTRIC TRANSMISSION SYSTEM - A millimeter-wave dielectric transmission device. The millimeter-wave dielectric transmission device includes a semiconductor chip provided on one interposer substrate and capable of millimeter-wave dielectric transmission, an antenna structure connected to the semiconductor chip, two semiconductor packages including a molded resin configured to cover the semiconductor chip and the antenna structure, and a dielectric transmission path provided between the two semiconductor packages to transmit a millimeter wave signal. The semiconductor packages are mounted such that the antenna structures thereof are arranged with the dielectric transmission path interposed therebetween. | 05-21-2015 |
20150145108 | MICROELECTRONIC PACKAGES HAVING RADIOFREQUENCY STAND-OFF LAYERS AND METHODS FOR THE PRODUCTION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within one or more redistribution layers built over the frontside of a semiconductor die. A molded radiofrequency (RF) separation or stand-off layer is formed over the redistribution layers through which the plurality of vertically-elongated contacts extend. An antenna structure is fabricated or otherwise provided over the molded RF stand-off layer and electrically coupled to the semiconductor die through at least one of the plurality of vertically-elongated contacts. | 05-28-2015 |
20150303173 | AN INTEGRATED ELECTRONIC DEVICE INCLUDING AN INTERPOSER STRUCTURE AND A METHOD FOR FABRICATING THE SAME - An integrated circuit device and a method of fabricating the same are presented. The integrated circuit device ( | 10-22-2015 |
20150311160 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a first dielectric layer surrounding a first transmission line and a magnetic layer surrounding the first dielectric layer. The magnetic layer increases the inductance of the transmission line. The semiconductor arrangement having the magnetic layer surrounding the first transmission line has increased impedance, which promotes current flow through the transmission line, without having increased resistance as compared to a semiconductor arrangement that does not have a magnetic layer. Increased resistance requires increased power, which results in a shorter semiconductor arrangement life span than the semiconductor arrangement without the increased resistance. | 10-29-2015 |
20150311576 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MOUNTING STRUCTURE - A semiconductor package mounting structure includes a substrate ( | 10-29-2015 |
20150325513 | Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes - A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips. | 11-12-2015 |
20150332997 | WIRELESS MODULE AND PRODUCTION METHOD FOR WIRELESS MODULE - Provided is a wireless module whose size can be made smaller. The wireless module includes: a first substrate on which an antenna is mounted; a second substrate which opposes the first substrate and on which an electronic component is mounted; and a plurality of electric conductors which connect the first substrate and the second substrate and which transmit a signal between the antenna and the electronic components, wherein the plurality of electric conductors are disposed between the first substrate and the second substrate in series in a substantially vertical direction with respect to mounting surfaces of the first substrate and the second substrate. | 11-19-2015 |
20150348920 | MICROELECTRONIC PACKAGES HAVING RADIOFREQUENCY STAND-OFF LAYERS AND METHODS FOR THE PRODUCTION THEREOF - Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within one or more redistribution layers built over the frontside of a semiconductor die. A molded radiofrequency (RF) separation or stand-off layer is formed over the redistribution layers through which the plurality of vertically-elongated contacts extend. An antenna structure is fabricated or otherwise provided over the molded RF stand-off layer and electrically coupled to the semiconductor die through at least one of the plurality of vertically-elongated contacts. | 12-03-2015 |
20150364445 | STACK MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Provided is a stack module package including: a first substrate where a first device is mounted, and a second substrate where a second device is mounted. The second substrate has a greater thickness than the first substrate, and the second device has a greater thickness than the first device. The first and second devices are vertically connected to each other. In the stack module package, vertical signal loss between the first and second substrates having different characteristics may be minimized | 12-17-2015 |
20160013130 | ELECTRONIC DEVICE | 01-14-2016 |
20160013157 | SEMICONDUCTOR APPARATUS INCLUDING A PLURALITY OF CHANNELS AND THROUGH-VIAS | 01-14-2016 |
20160093587 | FLEXIBLE CIRCUIT LEADS IN PACKAGING FOR RADIO FREQUENCY DEVICES AND METHODS THEREOF - A packaged RF device is provided that can provide improved performance and flexibility though the use of flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package. | 03-31-2016 |
20160099220 | HIGH ISOLATION WIDEBAND SWITCH - A high isolation wideband switch is disclosed. In one aspect, the switch includes an integrated circuit package having an integrated circuit die with a first plurality of leads that is positioned on a package substrate that has a second plurality of leads. The first leads of the integrated circuit die are connected to the second the leads of the package substrate via bond wires and a first electrical coupling occurs between the first leads and the integrated circuit die in response to an RF signal applied to the integrated circuit package. The bond wires have a second electrical coupling in response to the RF signal and the bond wires are arranged such that the second electrical coupling is matched to the first electrical coupling within a selected frequency band so as to reduce the overall electrical coupling of the integrated circuit package for RF signals within the selected frequency band. | 04-07-2016 |
20160163628 | PACKAGE SUBSTRATE COMPRISING CAPACITOR, REDISTRIBUTION LAYER AND DISCRETE COAXIAL CONNECTION - A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects. | 06-09-2016 |
20160172274 | SYSTEM, APPARATUS, AND METHOD FOR SEMICONDUCTOR PACKAGE GROUNDS | 06-16-2016 |
20160197048 | THREE-DIMENSIONAL INTEGRATED STRUCTURE COMPRISING AN ANTENNA CROSS REFERENCE TO RELATED APPLICATIONS | 07-07-2016 |
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20180025998 | SEMICONDUCTOR DEVICE | 01-25-2018 |
20190148316 | HIGH-FREQUENCY CERAMIC BOARD AND HIGH-FREQUENCY SEMICONDUCTOR ELEMENT PACKAGE | 05-16-2019 |