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WITH SHIELDING (E.G., ELECTRICAL OR MAGNETIC SHIELDING, OR FROM ELECTROMAGNETIC RADIATION OR CHARGED PARTICLES)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257660000 With means to shield device contained in housing or package from charged particles (e.g., alpha particles) or highly ionizing radiation (i.e., hard X-rays or shorter wavelength) 81
Entries
DocumentTitleDate
20080272469SEMICONDUCTOR DIE PACKAGE AND INTEGRATED CIRCUIT PACKAGE AND FABRICATING METHOD THEREOF - A semiconductor die package includes a substrate, a semiconductor die mounted on the substrates a molding covering the semiconductor die and which is formed on the substrate and a conductive layer laminated on the molding.11-06-2008
20130043570CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.02-21-2013
20130043569Integrated Circuit Devices and Methods and Apparatuses for Designing Integrated Circuit Devices - Methods and apparatuses for an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, an integrated Circuit (IC) device comprises a first plurality of signal wires disposed within a substrate a shielding mesh disposed on the substrate. In at least one embodiment, the shielding mesh comprises a first plurality of connected wires for a first reference voltage and a second plurality of connected wires for a second reference voltage. Wherein at least a first portion of each of the first plurality of the signal wires is shielded between one of the first plurality of connected wires and one of the second plurality of connected wires from adjacent signal wires and a second portion of the first plurality of signal wires are adjacent to each other in a region defined by the first and second pluralities of connected wires.02-21-2013
20130043568MEMORY DEVICE AND A FABRICATING METHOD THEREOF - A semiconductor device includes a substrate, a semiconductor chip, a first molding member and a metal layer. The substrate includes a first ground pad formed therein, the first ground pad having a first exposed surface exposed at a first surface of the substrate. The semiconductor chip is formed on the first surface of the substrate. The first molding member is formed on the first surface of the substrate and covers the semiconductor chip while not covering the first exposed surface. The metal layer covers the first molding member and extends to lateral surfaces of the substrate while contacting the first exposed surface.02-21-2013
20130026612METHOD OF SHIELDING THROUGH SILICON VIAS IN A PASSIVE INTERPOSER - A passive interposer apparatus with a shielded through silicon via (TSV) configuration is disclosed. The apparatus includes a p-doped substrate, wherein at least an upper portion of the p-doped substrate is heavily p-doped. An interlayer dielectric layer (ILD) is disposed over the upper portion of the p-doped substrate. A plurality of through silicon vias (TSVs) are formed through the ILD and the p-doped substrate. A plurality of shielding lines disposed between the TSVs electrically couple respective second metal contact pads to the upper portion of the p-doped substrate.01-31-2013
20100164076STACKED SEMICONDUCTOR PACKAGE - A semiconductor package includes a wire board, a plurality of semiconductor chips configured to be stacked over the wire board and to be electrically coupled with the wire board, and at least one shielding unit configured to be formed between the plurality of semiconductor chips and to be maintained at a predetermined voltage.07-01-2010
20130037923SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - There are provided a semiconductor package capable including an electromagnetic wave shielding structure having excellent electromagnetic interference (EMI) shielding characteristics while protecting individual elements therein from impacts, and a method of manufacturing the same. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an underfill resin filled in a space between the electronic component and the substrate; and a conductive shield part formed along an outer surface formed by the electronic component and the underfill resin and electrically connected to the ground electrodes.02-14-2013
20100072583Semiconductor Device and Manufacturing Method of the Same - With the use of a conductive shield formed on the top or bottom side of a semiconductor integrated circuit, an electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge is prevented, and sufficient communication capability is obtained. With the use of a pair of insulators which sandwiches the semiconductor integrated circuit, a highly reliable semiconductor device that is reduced in thickness and size and has resistance to an external stress can be provided. A semiconductor device can be manufactured with high yield while defects of shapes and characteristics due to an external stress or electrostatic discharge are prevented in the manufacturing process.03-25-2010
20100072582Semiconductor Device and Method of Electrically Connecting a Shielding Layer to Ground Through a Conductive Via Disposed in Peripheral Region Around Semiconductor Die - A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate.03-25-2010
20130032931LAYER STRUCTURE WITH EMI SHIELDING EFFECT - A layer structure with an electromagnetic interference (EMI) shielding effect is applicable for reducing an EMI effect caused by signal transmission between through silicon vias, so as to effectively provide the EMI shielding effect between electrical interconnections of a three-dimensional (3D) integrated circuit. By forming EMI-shielding through silicon vias at predetermined positions between the through silicon vias used for signal transmission, a good EMI shielding effect can be attended, and signal distortion possibly caused by the EMI effect can be reduced between different chips or substrates.02-07-2013
20130075878COAXIAL POWER MODULE - A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure.03-28-2013
20130075879SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MAKING SAME - A semiconductor chip package includes a substrate unit, a chip, metal members, a molding compound and a shielding layer. The chip is assembled on and electrically connected with the substrate unit. The substrate unit includes conductive seat portions surrounding the chip, and defines through holes respectively coated by conducting films to ground the corresponding seat portions. The metal members are assembled on the seat portions, surround the chip, and are grounded through the conducting films. The molding compound encapsulates the chip and the metal members, with part of each metal member exposed out of the molding compound. The shielding layer covers the molding compound and the parts of each metal member exposed out of the molding compound to shield the chip from electromagnetic radiation.03-28-2013
20100032814CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYERS CONFIGURED TO BLOCK ELECTROMAGNETIC EDGE INTERFERENCE - Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.02-11-2010
20100044840SHIELDED MULTI-LAYER PACKAGE STRUCTURES - Embodiments include shielded multi-layer packages for use with multi-chip modules and the like. A substrate (02-25-2010
20100102421INTEGRATED CIRCUIT CHIP WITH SEAL RING STRUCTURE - An integrated circuit chip includes an analog and/or RF circuit block and a seal ring structure surrounding the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring and an inner seal ring, wherein the inner seal ring comprises a gap that is situated in front of the analog and/or RF circuit block.04-29-2010
20130082367SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - There are provided a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate having a ground electrode formed on one surface thereof; at least one electronic component mounted on one surface of the substrate; an insulation layer including an exposed part exposing the ground electrode and a cover part covering the electronic component; and a shielding layer electrically connected to the ground electrode and covering the insulation layer.04-04-2013
20130082366SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor package including: a substrate having at least one element mounted thereon; a prepreg layer stacked on the substrate to cover the at least one element; a metal shielding layer stacked on the prepreg layer to electrically shield the at least one element; and a via electrode penetrating through the metal shielding layer and the prepreg layer and electrically connected to a ground electrode formed on the substrate.04-04-2013
20130082368EMI SHIELDED SEMICONDUCTOR PACKAGE AND EMI SHIELDED SUBSTRATE MODULE - An EMI shielded semiconductor package includes a semiconductor package and an EMI shield layer formed on at least a part of a surface of the EMI shielded semiconductor package. The EMI shield layer includes a matrix layer; a metal layer positioned on the matrix layer; and a first seed particle positioned in an interface between the matrix layer and the metal layer. Unlike a conventional shielding process that is performed for a device level, a shielding process may be performed for a mounting substrate level, and thus the semiconductor package and the substrate module may be manufactured with high-productivity at low costs in a short period of time.04-04-2013
20130082364EMI Package AND METHOD FOR MAKING SAME - An integrated circuit structure includes a substrate, a photosensitive molding on a first side of the substrate, a via formed in the molding, and a conformable metallic layer deposited over the first side of the substrate and in the via. A through via may be formed through the substrate aligned with the via in the molding with an electrically conductive liner deposited in the through via in electrical contact with the conformable metallic layer. The integrated circuit structure may further include a connector element such as a solder ball on an end of the through via on a second side of the substrate opposite the first side. The integrated circuit structure may further include a die on the first side of the substrate in electrical contact with another through via or with a redistribution layer.04-04-2013
20130082363Device Having Wirelessly Enabled Functional Blocks - Embodiments described herein provide enhanced integrated circuit (IC) devices. In an embodiment, an IC device includes a substrate, an IC die coupled to a surface of the substrate, a first wirelessly enabled functional block located, on the IC die, the first wirelessly enabled functional block being configured to wirelessly communicate with a second wirelessly enabled functional block located on the substrate, and a ground ring configured to provide electromagnetic shielding for the first and second wirelessly enabled functional blocks.04-04-2013
20130087896STACKING-TYPE SEMICONDUCTOR PACKAGE STRUCTURE - A stacking-type semiconductor package structure includes a first package body, multiple first connecting conductors, a second package body, multiple second connecting conductors, an electronic function module, and multiple third connecting conductors. The first connecting conductors are disposed on a lower surface of the first package body and connected electrically to the first package body. The second package body and the electronic function module are disposed on an upper surface of the first package body. The second connecting conductors are connected electrically between the first package body and the second package body, and the third connecting conductors are connected electrically between the first package body and the electronic function module. The second package body has an electronic function different from that of the electronic function module.04-11-2013
20130087895RADIATION-SHIELDED SEMICONDUCTOR DEVICE - A semiconductor device is disclosed including an electromagnetic radiation shield. The device may include a substrate having a shield ring defined in a conductance pattern on a surface of the substrate. One or more semiconductor die may be affixed and electrically coupled to the substrate. The one or more semiconductor die may then be encapsulated in molding compound. Thereafter, a metal may be plated around the molding compound and onto the shield ring to form an EMI/RFI shield for the device.04-11-2013
20130087897Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die - A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.04-11-2013
20090045488Magnetic shielding package structure of a magnetic memory device - This invention provides a magnetic shielding package structure of a magnetic memory device, in which at least a magnetic memory device is embedded between a magnetic shielding substrate and a magnetic shielding layer. A plurality of through vias is formed in the magnetic shielding substrate or the magnetic shielding layer, and a plurality of conductive contacts passes through the through vias such that electrical connection between the magnetic memory device and the external is established.02-19-2009
20100327417ELECTRONIC DEVICE HAVING A MOLDING COMPOUND INCLUDING A COMPOSITE MATERIAL - An electronic device includes a packaged integrated circuit having an integrated circuit die having an active surface, and a molding compound overlaying the active surface of the integrated circuit die. In a particular embodiment, the packaged integrated circuit includes at least approximately five weight percent (5 wt %) zinc relative to the molding compound. In another embodiment, the packaged integrated circuit includes approximately 0.3 μmol/cm12-30-2010
20100133664MODULE AND MOUNTED STRUCTURE USING THE SAME - A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (06-03-2010
20090302438IC HAVING VOLTAGE REGULATED INTEGRATED FARADAY SHIELD - An integrated circuit (IC) includes a substrate having a top semiconductor surface and a bottom surface, and integrated circuitry including an analog subcircuit and at least one digital subcircuit formed on the top semiconductor surface. A plurality of through substrate vias (TSVs) extend through the substrate. At least one integrated Faraday shield includes a top and a bottom electrically conducting member that are coupled by the TSVs which surround the analog subcircuit and/or the digital subcircuit. At least one voltage regulator supplies a regulated power supply voltage that is coupled to the integrated Faraday shield that surrounds the analog subcircuit.12-10-2009
20090302437Semiconductor Device and Method of Connecting a Shielding Layer to Ground Through Conductive Vias - A semiconductor device is made by providing a substrate having an interconnect structure, providing a plurality of semiconductor die each having a through silicon via (TSV), mounting the semiconductor die to the substrate to electrically connect the TSV to the interconnect structure, depositing an encapsulant between the semiconductor die, and forming a shielding layer over the encapsulant and semiconductor die. The shielding layer is electrically connected to the TSV which in turn electrically connects to the interconnect structure to isolate the semiconductor die from interference. The shielding layer is electrically connected to a ground potential through the TSV and interconnect structure. The semiconductor die includes solder bumps which are electrically connected to contact pads on the substrate. The substrate also includes solder bumps electrically connected to a conductive channel in the interconnect structure which is electrically connected to the TSV. The substrate is singulated to separate the semiconductor die.12-10-2009
20090302436Semiconductor Device and Method of Forming Shielding Layer Grounded Through Metal Pillars Formed in Peripheral Region of the Semiconductor - A shielded semiconductor device is made by mounting semiconductor die to a first substrate. An encapsulant is formed over the semiconductor die and first substrate. A dicing channel is formed through the encapsulant between the semiconductor die. A hole is drilled in the first substrate along the dicing channel on each side of the semiconductor die. A shielding layer is formed over the encapsulant and semiconductor die. The hole is lined with the shielding layer. The first substrate is singulated to separate the semiconductor die. The first substrate is mounted to a second substrate. A metal pillar is formed in the opening to electrically connect the shielding layer to a ground plane in the second substrate. The metal pillar includes a hook for a mechanically secure connection to the shielding layer. An interconnect structure is formed on the first substrate to electrically connect the semiconductor die to the second substrate.12-10-2009
20090302435Semiconductor Device and Method of Shielding Semiconductor Die from Inter-Device Interference - A plurality of stacked semiconductor wafers each contain a plurality of semiconductor die. The semiconductor die each have a conductive via formed through the die. A gap is created between the semiconductor die. A conductive material is deposited in a bottom portion of the gap. An insulating material is deposited in the gap and over the semiconductor die. A portion of the insulating material in the gap is removed to form a recess between each semiconductor die extending to the conductive material. A shielding layer is formed over the insulating material and in the recess to contact the conductive material. The shielding layer isolates the semiconductor die from inter-device interference. A substrate is formed as a build-up structure on the semiconductor die adjacent to the conductive material. The conductive material electrically connects to a ground point in the substrate. The gap is singulating to separate the semiconductor die.12-10-2009
20120217624CONNECTION USING CONDUCTIVE VIAS - In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.08-30-2012
20120112326Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die - A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.05-10-2012
20090236700SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a wiring board, a semiconductor element mounted on the wiring board, a sealing resin configured to cover the semiconductor element, a ground electrode having an end connected to a wiring layer of the wiring board and an exposing part exposed at a surface of the sealing resin, and a shielding member configured to cover the sealing resin and be connected to the ground electrode.09-24-2009
20080296744Integrated Circuit - According to one embodiment, an integrated circuit includes an internal circuit and a resin layer which covers the internal circuit. A radio wave absorbing material is mixed in the resin layer.12-04-2008
20110278704THREE-DIMENSIONAL PACKAGE STRUCTURE - A three-dimensional package structure includes an energy storage element, a semiconductor package body and a shielding layer. The semiconductor package body has a plurality of second conductive elements and at least one control device inside. The energy storage element is disposed on the semiconductor package body. The energy storage element including a magnetic body is electrically connected to the second conductive elements. The semiconductor package body or the energy storage element has a plurality of first conductive elements to be electrically connected to an outside device. The shielding layer is disposed between the control component and at least part of the magnetic body to inhibit or reduce EMI (Electro-Magnetic Interference) from the energy storage element and to get a tiny package structure. The three-dimensional package structure is applicable to a POL (Point of Load) converter.11-17-2011
20110278705Semiconductor Device and Method of Mounting Semiconductor Die to Heat Spreader on Temporary Carrier and Forming Polymer Layer and Conductive Layer Over the Die - A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer.11-17-2011
20110278703Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die - A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.11-17-2011
20130082365Interposer for ESD, EMI, and EMC - A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.04-04-2013
20100171200SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.07-08-2010
20120139089MODULE IC PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME - A module IC package structure includes a substrate unit, an electronic unit, a conductive unit, a package unit and a shielding unit. The substrate unit includes a circuit substrate having at least one grounding pad. The electronic unit includes a plurality of electronic elements electrically connected to the circuit substrate. The conductive unit includes at least one elastic conductive element disposed on the circuit substrate, and the elastic conductive element has a first end portion electrically connected to the grounding pad. The package unit includes a package resin body disposed on the circuit substrate to cover the electronic elements and one part of the elastic conductive element, and the elastic conductive element has a second end portion is exposed from the package resin body. The shielding unit includes a metal shielding layer formed on the outer surface of the package resin body to electrically contact the second end portion.06-07-2012
20110298108NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE GROUND SITES - A non-leaded integrated circuit package system includes: a die paddle of a lead frame; a dual row of terminals including an outer terminal and an inner terminal; and an inner terminal and an adjacent inner terminal to form a fused lead.12-08-2011
20110298107SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a shielded stacked integrated circuit packaging system includes: forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure.12-08-2011
20110298104Semiconductor Body with a Protective Structure and Method for Manufacturing the Same - A semiconductor body comprises a protective structure. The protective structure (12-08-2011
20110298102SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which is formed with a ground circuit and mounted with a semiconductor chip on one surface, a conductive ground layer, which is formed on the other surface of the substrate and connected with the ground circuit, a molding, which seals up the ground layer and the substrate having the semiconductor chip mounted thereon, and a conductive shield, which covers the molding and is connected with the ground layer. With a semiconductor package in accordance with an embodiment of the present invention, grounding for shielding is possible even in an entirely molded structure, and a double shielding structure to improve the shielding property.12-08-2011
20110298101Semiconductor Device and Method of Forming EMI Shielding Layer with Conductive Material Around Semiconductor Die - A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die.12-08-2011
20110298105Semiconductor Device and Method of Forming Shielding Layer After Encapsulation and Grounded Through Interconnect Structure - A method of manufacturing a semiconductor device includes providing a substrate having a conductive bump formed over the substrate and a semiconductor die with an active surface oriented to the substrate. An encapsulant is deposited over the semiconductor die and the conductive bump, and the encapsulant is planarized to expose a back surface of the semiconductor die opposite the active surface while leaving the encapsulant covering the conductive bump. A channel is formed into the encapsulant to expose the conductive bump. The channel extends vertically from a surface of the encapsulant down through the encapsulant and into a portion of the conductive bump. The channel extends through the encapsulant horizontally along a length of the semiconductor die. A shielding layer is formed over the encapsulant and the back surface of the semiconductor die. The shielding layer includes a docking pin extending into the channel and into the portion of the conductive bump to electrically connect to the conductive bump and provide isolation from inter-device interference.12-08-2011
20110298106INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MAGNETIC FILM AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system including: connecting a first integrated circuit device and a package substrate; attaching a support bump to the package substrate; providing a second integrated circuit device having an inner encapsulation; applying a magnetic film on the inner encapsulation of the second integrated circuit device; and mounting the second integrated circuit device over the first integrated circuit device with the magnetic film on the first integrated circuit device and the support bump.12-08-2011
20110298103SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which has a ground circuit formed thereon, a semiconductor chip, which is mounted on the substrate, a conductive first shield, which is formed on an upper surface of the semiconductor chip and connected with the ground circuit, and a conductive second shield, which covers the substrate and the semiconductor chip and is connected with the first shield. With a semiconductor package in accordance with an embodiment of the present invention, grounding is possible between semiconductor chips because a shield is also formed on an upper surface of the semiconductor chip, and the shielding property can be improved by a double shielding structure.12-08-2011
20110291248SHIELDING STRUCTURE FOR TRANSMISSION LINES - A shielding structure comprises first and second comb-like structures defined in a first metallization layer on an integrated circuit, each comb-like structure comprising a plurality of teeth, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comb-like structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias. The first and second comb-like structures, the first and second planar structures and the first, second, third, and fourth electrically conducting vias all being at substantially the same potential, preferably ground. In one embodiment, one or more signal lines are located in the second metallization layer between the first and second planar structures; and in another embodiment they are located in a third metallization layer between the first and second metallization layers.12-01-2011
20120098109CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.04-26-2012
20090294928Semiconductor Device and Method of Forming Holes In Substrate to Interconnect Top Shield and Ground Shield - A shielded semiconductor device is made by embedding a ground shield between layers of a substrate. Semiconductor die are mounted to the substrate over the ground shields. An encapsulant is formed over the semiconductor die and substrate. The encapsulant is diced to form dicing channels between the semiconductor die. A plurality of openings is drilled into the substrate along the dicing channels down through the ground shield on each side of the semiconductor die. A top shield is formed over the semiconductor die. The openings in the substrate are filled with a shielding material to electrically and mechanically connect the top shield to the ground shield. The substrate is singulated to separate the semiconductor die with top shield and ground shield into individual semiconductor devices. IPDs in the semiconductor die generate electromagnetic interference which is blocked by the respective top shield and ground shield.12-03-2009
20110193203SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In regard to a semiconductor device having a multilayered wiring board where a semiconductor chip is embedded inside, a technology which allows the multilayered wiring board to be made thinner is provided. A feature of the present invention is that, in a semiconductor device where bump electrodes are formed over a main surface (element forming surface) of a semiconductor chip embedded in a chip-embedded wiring board, an insulating film is formed over a back surface (a surface on the side opposite to the main surface) of the semiconductor chip. As a result, it becomes unnecessary to form a prepreg over the back surface of the semiconductor chip. Therefore, an effect of thinning the chip-embedded wiring board in which the semiconductor chip is embedded is obtained.08-11-2011
20090166819CHIPSET PACKAGE STRUCTURE - A chipset package structure includes a carrier, a plurality of pinouts, at least one semiconductor package preforms, at least one electromagnetic shielding layer and a protective layer. The pinouts are disposed on the carrier. The semiconductor package preforms is disposed on the second surface of the carrier and electrically connected to the pinouts. The electromagnetic shielding layer is disposed on the semiconductor package preforms and the electromagnetic shielding layer. At least one of the electromagnetic shielding layers comprises a carbon nanotube film structure. The protective layer covers the electromagnetic shielding layer.07-02-2009
20100078780Semiconductor device - A semiconductor device according to the present invention includes: a wiring; an interlayer insulating film formed over the wiring and having an opening reaching the wiring from a top surface thereof; an intra-opening metal film formed on the wiring inside the opening and made of a metal material that contains aluminum; a top surface metal film formed over the interlayer insulating film and made of the metal material; and a conduction securing film formed on a side surface of the opening to secure conduction between the intra-opening metal film and top surface metal film.04-01-2010
20090146269INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELD - An integrated circuit package system includes: forming a first lead and a second lead; connecting an integrated circuit die with the first lead; forming an encapsulation over the integrated circuit die, the first lead, and the second lead with a portion of a top side of the second lead exposed; and forming a shield over the encapsulation, the first lead, and the second lead with the shield not in contact with the first lead.06-11-2009
20090146268INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION - An integrated circuit package system comprising: providing a lead frame; forming an integrated circuit package including the lead frame; providing a selectively exposed area on the lead frame; and coating a conductive shielding layer on the integrated circuit package for coupling the selectively exposed area.06-11-2009
20090014847INTEGRATED CIRCUIT PACKAGE STRUCTURE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING STRUCTURE - An integrated circuit (IC) package structure with an electromagnetic interference (EMI) shielding structure utilizes double-layer successive cladding process. A dielectric coating layer and an EMI shielding layer material are sequentially coated on surface of a carrying substrate, an IC on the carrying substrate, and all the other devices. The EMI shielding layer is closely adhered to and bonded on a ground metal area exposed on an upper surface of the carrying substrate, the EMI shielding layer on the package is connected to a ground plane under the carrying substrate in series, so as to form a protection cover having a closed EMI shielding space to isolate the interference of electromagnetic waves from outside.01-15-2009
20100078776On-Chip RF Shields with Backside Redistribution Lines - Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.04-01-2010
20090309197INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE - An integrated circuit package system includes: fabricating an integrated circuit substrate; forming an internal stacking module coupled to the integrated circuit substrate including: forming a flexible substrate, coupling a stacking module integrated circuit to the flexible substrate, and bending a flexible extension over the stacking module integrated circuit; molding a package body on the integrated circuit substrate and the internal stacking module; and coupling an external integrated circuit to the internal stacking module exposed through the package body.12-17-2009
20100270660Semiconductor device and method for manufacturing metallic shielding plate - Provided is a semiconductor device capable of preventing a semiconductor chip from being damaged by any sharp burrs of a metallic shielding plate. The semiconductor device includes a semiconductor chip and a metallic shielding plate provided on a circuit surface of the semiconductor chip. The metallic shielding plate is disposed in such a manner that a second surface of a shielding plate body is directed towards the circuit surface of the semiconductor chip, and burrs are positioned contiguous to the second surface of the shielding plate body. At distal ends of the burrs, cutting burrs are formed in a direction orthogonal to the second surface. The sharp burrs extend in a direction opposite to the semiconductor chip, so that the sharp burrs are prevented from damaging the circuit surface of the semiconductor chip.10-28-2010
20100078779System on a Chip with On-Chip RF Shield - Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.04-01-2010
20100078778On-Chip RF Shields with Front Side Redistribution Lines - A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines.04-01-2010
20100078777On-Chip Radio Frequency Shield with Interconnect Metallization - Structure and method for fabricating a system on chip with an on-chip RF shield including interconnect metallization is described. In one embodiment, the system on chip includes an RF circuitry disposed on a first portion of a top surface of a substrate, and a semiconductor circuitry disposed on a second portion of the top surface of the substrate. An interconnect RF barrier is disposed between the RF circuitry and the semiconductor circuitry, the interconnect RF barrier coupled to a ground potential node.04-01-2010
20100006987INTEGRATED CIRCUIT PACKAGE WITH EMI SHIELD - An integrated circuit (IC) device (01-14-2010
20090206455INTEGRATED CIRCUIT STACKED PACKAGE PRECURSORS AND STACKED PACKAGED DEVICES AND SYSTEMS THEREFROM - A package-on-package (POP) package precursor and packaged devices and systems therefrom includes an electronic substrate including electrically conductive layers and a top surface. A first portion of the top surface has an IC die attached thereon. A second portion of the top surface has a plurality of first attach pads on opposing sides of the IC die for electrically coupling to a first electronic device on top of the IC die. At least a third portion of the top surface is positioned laterally with respect to the first and second portion. The third portion includes a plurality of second attach pads for electrically coupling to at least a second electronic device. At least one of the electrically conductive layers includes a coupling trace that couples at least one of the plurality of second attach pads to the IC die and/or one or more of the plurality of first attach pads.08-20-2009
20110198737QUAD FLAT NON-LEADED PACKAGE STRUCTURE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING FUNCTION AND METHOD FOR FABRICATING THE SAME - A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.08-18-2011
20090091005Shielding structure for semiconductors and manufacturing method therefor - A shielding structure for semiconductor includes a semiconductor substrate, at least one active region defined on the semiconductor substrate, a protecting layer, a shielding layer, and a covering layer. The protecting layer, produced by a semiconductor process, is disposed on the surface of the active region. The shielding layer produced by a semiconductor process is disposed on the surface of the protecting layer. The covering layer covers the shielding layers, and the protecting layer is harder than the covering layer. In the above-mentioned structure, the harder protecting layer is provided to prevent the active regions from heat damage.04-09-2009
20090283876ELECTROMAGNETIC INTERFERENCE SHIELD FOR SEMICONDUCTORS USING A CONTINUOUS OR NEAR-CONTINUOUS PERIPHERAL CONDUCTING SEAL AND A CONDUCTING LID - A semiconductor package structure including a conductive adhesive material which is used to form an electromagnetic interference shield-forming Faraday cage. The Faraday cage incorporates a module lid as the top surface thereof, the conductive material as the sides and a laminate ground plane(s) or substrate as its bottom. Also disclosed is a method for fabricating the foregoing semiconductor package structure.11-19-2009
20080211067SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.09-04-2008
20090278240Semiconductor apparatus - Disclosed is a semiconductor apparatus that prevents diffusion of materials of a magnetic film during the process for manufacturing the semiconductor apparatus. The semiconductor apparatus includes: a substrate; a semiconductor device formed on a principal surface of the substrate and including an interconnect layer; a magnetic shielding film of a magnetic material covering the semiconductor device; and a buffer film disposed between the semiconductor device and the magnetic shielding film. The buffer film prevents diffusion of the magnetic material of the magnetic shielding film.11-12-2009
20090283877SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.11-19-2009
20110169142SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are a semiconductor device and a method for manufacturing the same. Since an additional space for forming a shield line is unnecessary, the critical dimension of metal lines is reduced, thereby improving data transfer characteristics, signaling characteristics and noise characteristics of the metal lines. The semiconductor device includes: a plurality of metal lines disposed on the semiconductor device; a plurality of insulation layers disposed on the metal lines; and a plurality of shield lines disposed between the insulation layers.07-14-2011
20120139090STACKED PACKAGE STRUCTURE - A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package.06-07-2012
20090289335INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELD AND TIE BAR - An integrated circuit package system includes: providing a tie bar and a lead adjacent thereto; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield connected to the tie bar; and encapsulating the integrated circuit and the shield. An integrated circuit package system also includes: forming a lead and a support structure with substantially the same material as the lead and elevated above the lead; connecting an integrated circuit and the lead; mounting a shield over the integrated circuit with the shield on the support structure; and encapsulating the integrated circuit and the shield.11-26-2009
20090294929SEAL RING STRUCTURE FOR INTEGRATED CIRCUITS - A seal ring structure disposed along a periphery of an integrated circuit. The seal ring is divided into at least a first portion and a second portion. The second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A deep N well is disposed in a P substrate and is positioned under the second portion. The deep N well reduces the substrate noise coupling.12-03-2009
20110204495DEVICE HAVING WIRE BOND AND REDISTRIBUTION LAYER - A semiconductor device comprises a copper redistribution line, a copper inductor and aluminum wire bond pads and the integration of the resulting device with an integrated circuit on a single chip, resulting in the decreased size of the chip.08-25-2011
20110204493SHIELDING STRUCTURE FOR TRANSMISSION LINES - A shielding structure comprises first and second comb-like structures defined in a first metallization layer on an integrated circuit, each comb-like structure comprising a plurality of teeth, the teeth of each comb-like structure extending toward the other comb-like structure; a first plurality of electrically conducting vias extending upward from the first comb-like structure; a second plurality of electrically conducting vias extending upward from the second comb-like structure; first and second planar structures in a second metallization layer above the first metallization layer; a third plurality of electrically conducting vias extending downward from the first planar structure toward the first plurality of electrically conducting vias; and a fourth plurality of electrically conducting vias extending downward from the second planar structure toward the second plurality of electrically conducting vias. The first and second comb-like structures, the first and second planar structures and the first, second, third, and fourth electrically conducting vias all being at substantially the same potential, preferably ground. In one embodiment, one or more signal lines are located in the second metallization layer between the first and second planar structures; and in another embodiment they are located in a third metallization layer between the first and second metallization layers.08-25-2011
20100264523Panel, Semiconductor Device and Method for the Production Thereof - A panel has a baseplate with an upper first metallic layer and a multiplicity of a vertical semiconductor components. The vertical semiconductor components in each case have a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode. The second side of the semiconductor components is in each case mounted on the metallic layer of the baseplate. The semiconductor components are arranged in such a way that edge sides of adjacent semiconductor components are separated from one another. A second metallic layer is arranged in separating regions between the semiconductor components.10-21-2010
20080246126STACKED AND SHIELDED DIE PACKAGES WITH INTERCONNECTS - According to an example embodiment, a stacked die package 10-09-2008
20110204496CIRCUIT MODULE, ELECTRONIC DEVICE INCLUDING THE SAME, AND CIRCUIT MODULE MANUFACTURING METHOD - Provided is a circuit module reduced in size. The circuit module includes: a substrate to which electronic parts are mounted; a shield case; and a bonding material for bonding the substrate and the shield case. The shield case includes legs extending from given side walls of the shield case to overlap with portions of the side faces of the substrate, and the portions of the side faces of the substrate are bonded to the legs of the shield case by the bonding material. The shield case includes openings formed in the given side walls of the shield case to expose overlapping portions where the portions of the side faces of the substrate overlap with the legs of the shield case.08-25-2011
20110204494INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a device over the component side; forming a shield connector on the component side adjacent the device; forming a package interconnect on the component side outside a region having the shield connector and the device; applying an encapsulant around the package interconnect, the shield connector, and the device; and mounting a shield structure on the encapsulant, the shield connector, and the device, with the package interconnect partially exposed.08-25-2011
20120038033SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip 02-16-2012
20080277769Package Integrated Soft Magnetic Film for Improvement In On-Chip Inductor Performance - An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.11-13-2008
20080283976Electromagnetic Shielding Device for an Infrared Receiver - An electromagnetic shielding device in an infrared receiver comprises of a wiring frame (11-20-2008
20120292749Semiconductor Device and Method of Forming Discontinuous ESD Protection Layers Between Semiconductor Die - A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.11-22-2012
20120292750INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERNAL STACKING MODULE - An integrated circuit package system includes: providing an integrated circuit substrate; forming an internal stacking module coupled to the integrated circuit substrate including: forming a flexible substrate, coupling a stacking module integrated circuit to the flexible substrate, and bending a flexible extension over the stacking module integrated circuit; and molding a package body on the integrated circuit substrate and the internal stacking module.11-22-2012
20080272468GROUNDED SHIELD FOR BLOCKING ELECTROMAGNETIC INTERFERENCE IN AN INTEGRATED CIRCUIT PACKAGE - An integrated circuit package for blocking electromagnetic interference includes a top layer formed in a package substrate. A first plurality of via groups is formed in the top layer surrounding an area on the top layer for an integrated circuit die. At least one lower layer is formed in the package substrate. A lower via group is formed in the lower layer below each of the first plurality of via groups, respectively. An electrical connection is formed in the lower layer between each lower via group and the first plurality of via groups, respectively. A ground connection is formed in the integrated circuit package for each lower via group to connect each lower via group to an electrical ground to block electromagnetic interference.11-06-2008
20090146267SECURE CONNECTOR GRID ARRAY PACKAGE - Methods, systems, IC packages, and electrical devices for providing data security for ICs. A substrate-on-substrate connector grid array package with an electrical shield can protect sensitive information in a secure IC from being accessed by physical attacks. A current flow in the electrical shield can be monitored for disturbances which can indicate an attack on the IC package.06-11-2009
20130119523PACKAGING STRUCTURE AND METHOD AND ELECTRONIC DEVICE - A packaging structure includes: a substrate (05-16-2013
20100270661Semiconductor Device Having Electrical Devices Mounted to IPD Structure and Method of Shielding Electromagnetic Interference - A semiconductor device has an IPD structure formed over a substrate. First and second electrical devices are mounted to a first surface of the IPD structure. An encapsulant is deposited over the first and second electrical devices and IPD structure. A shielding layer is formed over the encapsulant and electrically connected to a conductive channel in the IPD structure. The conductive channel is connected to ground potential to isolate the first and second electrical devices from external interference. A recess can be formed in the encapsulant material between the first and second electrical devices. The shielding layer extends into the recess. An interconnect structure is formed on a second surface of the IPD structure. The interconnect structure is electrically connected to the first and second electrical devices and IPD structure. A shielding cage can be formed over the first electrical device prior to depositing encapsulant.10-28-2010
20100140757SEMICONDUCTOR PACKAGE HAVING AN ANTENNA WITH REDUCED AREA AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes an electromagnetic shielding member for shielding electromagnetic waves. An antenna is disposed on an upper face of the electromagnetic shielding member and includes an antenna part with a plurality of conductive particles electrically connected with each other and an insulation part disposed on the upper face of the electromagnetic shielding member and insulating the antenna part. Ball lands are disposed on the electromagnetic shielding member and are electrically connected with the antenna part. A Radio Frequency Identification (RFID) chip is electrically connected to the ball lands.06-10-2010
20100140758Integrated Circuit with Improved Transmission Line Structure and Electromagnetic Shielding Between Radio Frequency Circuit Paths - An integrated circuit is disclosed having through silicon vias spaced apart one from another and conductors, each coupled to one or more of the through silicon vias, the conductors in aggregate in use forming a segmented conductive plane maintained at a same potential and forming an electromagnetic shield.06-10-2010
20090127674MULTILAYER DIELECTRIC SUBSTRATE AND SEMICONDUCTOR PACKAGE - A multilayer dielectric substrate that mounts a semiconductor device in a cavity formed on a substrate. The multilayer dielectric substrate includes an opening formed in a surface-layer grounding conductor on the substrate in the cavity, and an impedance transformer, with a length of about ¼ of an in-substrate effective wavelength of a signal wave, electrically connected through the opening to the cavity. The multilayer dielectric substrate further includes a short-circuited end dielectric transmission line with a length of about ¼ of the in-substrate effective wavelength of the signal wave, a coupling opening formed on an inner-layer grounding conductor in a connecting section of the impedance transformer and the dielectric transmission line, and a resistor formed in the coupling opening.05-21-2009
20100200966SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING PACKAGE STACKED OVER DIE-UP FLIP CHIP BALL GRID ARRAY PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES - A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-up flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates.08-12-2010
20100200965PACKAGE STRUCTURE FOR WIRELESS COMMUNICATION MODULE - A package structure for a wireless communication module is disclosed and includes: a substrate having an upper surface defining a supporting region, an annular ground pad surrounding the supporting region, and at least one auxiliary ground pad formed in the supporting region; at least one chip mounted on the supporting region and electrically connected to the substrate; and a shielding lid having a receiving space for receiving the chip, a ground end surface electrically connected to the annular ground pad of the substrate, and at least one auxiliary ground portion electrically connected to the auxiliary ground pad for forming at least one auxiliary ground pathway to adjust the characteristic of the enhanced peak generated by the cavity-resonance effect of the shielding lid. Thus, the enhanced peak can be shifted out of a regulated frequency range of the EMI shielding test, so that the yield thereof can be increased.08-12-2010
20090184403METHOD OF FORMING A SEMICONDUCTOR PACKAGE AND STRUCTURE THEREOF - An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed by forming a conductive layer (07-23-2009
20090001528Lowering resistance in a coreless package - In one embodiment, the present invention includes a coreless substrate to provide a power net connection and a ground net connection to a semiconductor die, which is electrically coupled to the substrate, and a stiffener surrounding the semiconductor die and electrically coupled to the substrate to provide a lateral current path to the semiconductor die. Other embodiments are described and claimed.01-01-2009
20120068315METHOD OF IMPROVING MECHANICAL PROPERTIES OF SEMICONDUCTOR INTERCONNECTS WITH NANOPARTICLES - In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.03-22-2012
20090212401PACKAGE SYSTEM FOR SHIELDING SEMICONDUCTOR DIES FROM ELECTROMAGNETIC INTERFERENCE - The present invention provides a package system including: providing a semiconductor die with a contact pad and a ground pad, mounting the semiconductor die on a package substrate using and adhesive layer, forming a vertical conductive structure on top of the ground pad in the semiconductor die, encapsulating at least portions of the semiconductor die, the vertical conductive structure, and the package substrate using an encapsulant, covering at least portions of the encapsulant and the vertical conductive structure with a shielding layer to place the vertical conductive structure in electrical contact with the shielding layer, and connecting the shielding layer to the package substrate.08-27-2009
20090212402SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.08-27-2009
20090057848REDISTRIBUTION STRUCTURES FOR MICROFEATURE WORKPIECES - Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line.03-05-2009
20120104572SEMICONDUCTOR PACKAGE MODULE - There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate.05-03-2012
20120104571SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - There are provided a semiconductor package including an electromagnetic shielding structure having excellent electromagnetic interference (EMI) and electromagnetic susceptibility (EMS) characteristics, while protecting individual elements in an inner portion thereof from impacts, and a manufacturing method thereof. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an insulating molding part including an internal space in which the electronic component is accommodated, and fixed to the substrate such that at least a portion of the ground electrode is externally exposed; and a conductive shield part closely adhered to the molding part to cover an outer surface of the molding part and electrically connected to the externally exposed ground electrodes.05-03-2012
20120104570SEMICONDUCTOR PACKAGE MODULE - There is provided a semiconductor package module allowing a shield of a semiconductor package to be easily grounded and securing bonding reliability between the shield and a ground pattern. The semiconductor package module includes a semiconductor package having a shield formed on an upper surface thereof and side surfaces thereof; a main substrate having at least one ground electrode formed on a surface thereof and having the semiconductor package mounted thereon; and a bonding part bonding the ground electrode to the shield to electrically connect the ground electrode to the shield.05-03-2012
20120104569INTEGRATED CIRCUITS AND FABRICATION METHODS THEREOF - An integrated circuit includes a signal line routed in a first direction. A first shielding pattern is disposed substantially parallel with the signal line. The first shielding pattern has a first edge having a first dimension and a second edge having a second dimension. The first edge is substantially parallel with the signal line. The first dimension is larger than the second dimension. A second shielding pattern is disposed substantially parallel with the signal line. The second shielding pattern has a third edge having a third dimension and a fourth edge having a fourth dimension. The third edge is substantially parallel with the signal line. The third dimension is larger than the fourth dimension. The fourth edge faces the second edge. A first space is between the second and fourth edges.05-03-2012
20110140248SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.06-16-2011
20080265383Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips - A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.10-30-2008
20090200647SHIELDED INTEGRATED CIRCUIT PAD STRUCTURE - An integrated circuit pad structure includes a ground strip (08-13-2009
20090200648Embedded die system and method - A method and system is disclosed for facilitating miniaturization of an electronic device by efficiently utilizing available space. Specifically, in an exemplary embodiment, there is provided an electronic device comprising a substrate, a cavity formed in the substrate, and a bridge coupled to the substrate such that it spans the cavity. Further, the device may include a semiconductor device coupled to the bridge such that the semiconductor device is positioned within the cavity. In some embodiments, the bridge may include a tape automated bonding (TAB) tape having various layers, including a layer configured to provide electromagnetic shielding.08-13-2009
20090243052Electronic device with shielding structure and method of manufacturing the same - An electronic device includes a substrate, an active circuit, and a shielding structure. The active circuit is formed on the substrate. The shielding structure is disposed surrounding the active circuit, and includes a first heavy ion-doped region, first metal stack, second heavy ion-doped region, second metal stack and top metal. The first heavy ion-doped is formed in the substrate and located at a first side of the active circuit. The first metal stack is formed on the first heavy ion-doped region of the substrate, wherein the first metal stack is connected to a ground voltage. The second heavy ion-doped region is formed in the substrate and located at a second side of the active circuit. The second metal stack is formed on the second heavy ion-doped region of the substrate. The top metal is formed on the first metal stack and second metal stack and passing over the active circuit.10-01-2009
20080315375INTEGRATED CONDUCTIVE STRUCTURES AND FABRICATION METHODS THEREOF FACILITATING IMPLEMENTING A CELL PHONE OR OTHER ELECTRONIC SYSTEM - Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.12-25-2008
20080315372Wafer Level Integration Package - A semiconductor package includes a wafer having a first electrical contact pad integrated into a top surface of the wafer. A through-hole interconnection extends downward from a first surface of the first electrical contact pad. A die is electrically connected to a second surface of the first electrical contact pad. A second electrical contact pad is disposed over a surface of the through-hole interconnection. A dielectric layer is disposed along a side surface of the second electrical contact pad. The wafer is cut to form a channel portion and a connecting portion. An encapsulant is disposed over the die and the channel portion, and the wafer is backgrinded to remove the connecting portion and expose the surface of the through-hole interconnection.12-25-2008
20080315373METHOD OF ENABLING ALIGNMENT OF WAFER IN EXPOSURE STEP OF IC PROCESS AFTER UV-BLOCKING METAL LAYER IS FORMED OVER THE WHOLE WAFER - A method of enabling alignment of a wafer in at least one exposure step of an integrated circuit process after a UV-blocking metal layer is formed over the whole wafer covering a patterned upmost metal layer of the integrated circuit is described, wherein the wafer has an edge portion where a composite dielectric layer corresponding to the dielectric layers of the integrated circuit is formed. The method includes forming a cavity in the composite dielectric layer over the edge portion of the wafer in the patterning process of the upmost metal layer, such that an alignment mark is formed after the UV-blocking metal layer is formed.12-25-2008
20080315374INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH MAGNETIC FILM - An integrated circuit package-in-package system comprising: connecting a first integrated circuit device and a package substrate; applying a magnetic film over the first integrated circuit device; mounting a second integrated circuit device having an inner encapsulation over the magnetic film; and forming a package encapsulation over the first integrated circuit device, the magnetic film, and the second integrated circuit device.12-25-2008
20100264522SEMICONDUCTOR DEVICE HAVING AT LEAST ONE BUMP WITHOUT OVERLAPPING SPECIFIC PAD OR DIRECTLY CONTACTING SPECIFIC PAD - A semiconductor device includes a semiconductor chip, a plurality of bumps and at least one electrically conductive component. The semiconductor chip includes an active area having electronic circuits formed therein and a plurality of pads. The plurality of bumps is placed on the semiconductor chip, wherein a location where at least one of the bumps is located on the semiconductor chip does not overlap a location where a specific pad of the pads is located on the semiconductor chip. The electrically conductive component connects a top surface of at least the bump and the specific pad.10-21-2010
20080308912EMI SHIELDED SEMICONDUCTOR PACKAGE - An EMI shielded semiconductor package is provided. The package includes a substrate and a chip disposed on the substrate. The chip is electrically connected to the substrate by a plurality of bonding wires. At least one shielding conductive block is formed on the substrate and electrically connected to the ground trace of the substrate. A sealant is formed on the substrate and covers the chip, bonding wires and the shielding conductive block. The sealant has a side surface to expose a surface of the shielding conductive block. A layer of conductive film is formed on the outer surface of the sealant and covers the exposed surface of the shielding conductive block thereby shielding the chip from electromagnetic interference.12-18-2008
20110140247INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELDED PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate assembly having a connection path; mounting a base device over the substrate assembly with a mount layer; mounting a stack device over the base device and having a stack die and a stack-organic-material; forming a stack-through-via in the stack-organic-material of the stack device and connected to the stack die and the substrate assembly; and applying a shield layer directly on a planarized surface of the stack-through-via partially exposed from the stack-organic-material.06-16-2011
20130214396SEMICONDUCTOR PACKAGES - A semiconductor package includes a first package including a first wiring board and at least one first semiconductor chip mounted on the first wiring board, a second package stacked on the first package. The second package includes a second wiring board and at least one second semiconductor chip mounted on the second wiring board. The semiconductor package further includes at least one connection terminal connecting a plurality of signal lines of the first and second wiring boards, respectively, with each other. The semiconductor package further includes at least one ground terminal connecting a plurality of ground lines of the first and second wiring boards, respectively, with each other, and includes a side surface, and a shielding member covering a top surface and a side surface of a structure including the first and second packages and the shielding member is disposed on the at least one ground terminal.08-22-2013
20100276791SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on a principal surface of the semiconductor substrate and having a multiple-layered interconnect layer; and a heterostructure magnetic shield covering the semiconductor element. The heterostructure magnetic shield includes a first magnetic shield layered structure and a second magnetic shield layered structure that covers the first magnetic shield layered structure. Each of a first and a second magnetic shield layered structures includes a magnetic shielding film composed of a magnetic substance and covering the semiconductor element and a buffer film disposed between the semiconductor element and the magnetic shield films and preventing a diffusion of the magnetic substance.11-04-2010
20100213583ELECTRONIC PARTS, AND METHOD FOR ARRANGING SHIELDING CASE AND CHIP PARTS - An electronic part (08-26-2010
20080315371METHODS AND APPARATUS FOR EMI SHIELDING IN MULTI-CHIP MODULES - Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (12-25-2008
20120193770SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.08-02-2012
20100219513INTEGRATED CIRCUIT STRUCTURE AND A METHOD OF FORMING THE SAME - An integrated circuit structure is disclosed. The integrated circuit structure includes a first package substrate including a radiating element, the radiating element having a radiating element connection extending from the radiating element. The integrated circuit structure further includes a first chip positioned adjacent to the radiating element connection, the first chip having a first chip connection on a surface of the first chip, wherein the first chip connection forms a capacitive coupling with the radiating element connection. A method of forming an integrated circuit structure is also disclosed.09-02-2010
20100006989METHOD OF FORMING A SHIELDED SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer.01-14-2010
20100127360Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die - A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets. Each wafer section has at least two semiconductor die. The wafer sections are mounted over a temporary carrier in a grid pattern to reserve an interconnect area between the wafer sections. An encapsulant is deposited over the wafer sections and interconnect area. A conductive pillar can be formed in the encapsulant over the interconnect area. An interconnect structure is formed over the wafer sections and encapsulant in the interconnect area. The wafer sections and interconnect area are singulated to separate the semiconductor die each with a portion of the interconnect area. A heat sink or shielding layer can be formed over the wafer sections.05-27-2010
20100127359Die-To-Die Power Consumption Optimization - Power consumption of electronic components is reduced, particularly in a multi-chip package. Embodiments reduce parasitic capacitance of a semiconductor chip by reducing ESD protection circuitry that is not needed during operation of the package. ESD protection circuitry would be operational during production and/or testing of the chip, but some circuitry would be disabled or removed prior to normal operation of the multi-chip package.05-27-2010
20090243051INTEGRATED CONDUCTIVE SHIELD FOR MICROELECTRONIC DEVICE ASSEMBLIES AND ASSOCIATED METHODS - Microelectronic device assemblies having integrated conductive shields are disclosed herein. The microelectronic device assemblies include a semiconductor substrate having a bond site and a solder ball electrically connected to the bond site, a dielectric sidewall at least partially encapsulating the semiconductor substrate, and a conductive shield in direct contact with the sidewall and in electrical communication with the solder ball and the bond site.10-01-2009
20090184404Electromagnetic shilding structure and manufacture method for multi-chip package module - An electromagnetic shielding structure for a multi-chip package module includes a substrate having at least one conductive point, a plurality of chips, an encapsulating body and an electromagnetic shielding layer. Wherein the chips are arranged and encapsulated by the encapsulating body on the substrate. The electromagnetic shielding layer is arranged on the encapsulating body and the conductive point to shield highly frequency electromagnetic wave by printing. Meanwhile, the electromagnetic shielding layer can replace the conventional metal shell to reduce the whole size of the multi-chip package module.07-23-2009
20080303120Semiconductor chip package - A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the ceramic substrate facing the main board; and a conductive shielding layer provided with a predetermined thickness on the outside of the ceramic substrate. The ceramic substrate includes: at least one first ground line electrically connecting the conductive shielding layer with the main board; at least one second ground line electrically connecting the conductive shielding layer with the chip; and at least one signal line electrically connecting the chip with the main board. Thus, manufacturing costs are lowered because of the reduced number of components being used, miniaturization in device design can be achieved because of the small volume of the package, and the ground performance can be improved.12-11-2008
20090152688INTEGRATED CIRCUIT PACKAGE SYSTEM FOR SHIELDING ELECTROMAGNETIC INTERFERENCE - An integrated circuit package system comprising: providing a substrate; coupling an integrated circuit to the substrate; mounting a shielding element around the integrated circuit; applying a conductive shielding layer on the shielding element; and coupling a system interconnect to the shielding element.06-18-2009
20130134566STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING - A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.05-30-2013
20100301463REDUCED SOFT ERROR RATE THROUGH METAL FILL AND PLACEMENT - A method for reducing single event upsets in an integrated circuit includes the step of providing a plurality of levels within the integrated circuit, wherein the plurality of levels within the integrated circuit are in a stacked arrangement. The method also includes the step of providing a plurality of metal fill patterns within each of the plurality of levels within the integrated circuit. The method further includes the step of placing the plurality of metal fill patterns within at least one of the plurality of levels in a pattern such that a line of sight towards an active silicon layer does not exist within the stacked arrangement of the plurality of levels, thereby increasingly absorbing ionizing radiation particles, and thereby reducing single event upsets in the integrated circuit.12-02-2010
20110127652THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME - A three-dimensional semiconductor integrated circuit device is provided. A first semiconductor chip includes a solid-state circuit and is smaller than a base, and is stacked on the base. The first chip is buried by a first filling material having approximately the same contour as the base. Buried electrodes that penetrate through the first chip along its thickness direction are formed in the first chip. A second semiconductor chip includes a solid-state circuit and is smaller than the base, and is stacked on the first chip. The second chip is buried by a second filling material having approximately the same contour as the base. Buried electrodes that penetrate through the second chip along its thickness direction are formed in the second chip. The first and second filling materials have processibilities required for forming the buried electrodes and thermal expansion coefficients equivalent to those of the first and second chips, respectively.06-02-2011
20110018109Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation - According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.01-27-2011
20090065909Segmented magnetic shielding elements - A second shield layer, under the master shielding layer, is added to a segmented MRAM array. This additional shielding is patterned so as to provide one shield per bit slice. The placement of longitudinal biasing tabs at the ends of these segmented shields ensures that each segmented shield is a single magnetic domain, making it highly effective as a shield against very small stray fields.03-12-2009
20110031594CONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME - The present invention provides a conductor package structure that comprises a conductive base. An adhesive layer is formed on the conductive base. An electronic element is formed on the adhesive layer. Conductors form a signal connection between the surface of a filling material and the bottom of the filling material, wherein the filling material is filled in the space between the electronic element and the conductors.02-10-2011
20120175752DEVICES WITH FARADAY CAGES AND INTERNAL FLEXIBILITY SIPES - A computer or microchip comprising an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal sipe, and at least a portion of a surface of the outer chamber forming at least a portion of a surface of the internal sipe. The internal sipe has opposing surfaces that are separate from each other and therefore can move relative to each other, and at least a portion of the opposing surfaces are in contact with each other in a unloaded condition. The outer chamber including a Faraday Cage. A computer, comprising a semiconductor wafer having a multitude of microchips. The multitude of microchips forming a plurality of independently functioning computers, each computer having independent communication capabilities.07-12-2012
20110115059Semiconductor Device Packages with Electromagnetic Interference Shielding - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a circuit substrate, an electronic device, an encapsulant, and a conductive coating. The circuit substrate includes a carrying surface, a bottom surface, a lateral surface extending between the carrying surface and the bottom surface, a conductive layer, and a grounding ring. The grounding ring is in a substantially continuous pattern extending along a border of the circuit substrate, is exposed at a lateral surface of the circuit substrate, and is included in the conductive layer. The electronic device is disposed adjacent to the carrying surface and is electrically connected to the conductive layer of the circuit substrate. The encapsulant is disposed adjacent to the carrying surface and encapsulates the electronic device. The conductive coating is applied to the encapsulant and the grounding ring.05-19-2011
20100164077SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device.07-01-2010
20110241185SIGNAL SHIELDING THROUGH-SUBSTRATE VIAS FOR 3D INTEGRATION - A shielded through-substrate via (TSV) structure includes a first through-substrate via configured to transmit a signal at least from a top surface of a semiconductor device layer in a substrate to a bottommost surface of the substrate. The shielded TSV structure includes at least one second TSV located on the outside of the first TSV and configured to laterally shield the first TSV from external electrical signals. The at least one second TSV can be a unitary cylindrical structure including the first TSV therein, or a plurality of discrete structures configured to laterally shield the first TSV with gaps thereamongst. The at least one second TSV can include a conductive material that is different from the material of the substrate, or the at least one TSV can include a doped semiconductor material that is derived from the semiconductor material within the substrate.10-06-2011
20100219514SEMICONDUCTOR DEVICE - A semiconductor device includes: a first region, a second region and a third region surrounding the second region; an integrated circuit including an active element in the first region and provided in and above a first substrate; an antenna which is provided in the second region, connected to the integrated circuit and configured to receive or transmit a high-frequency signal; and a first shield layer which is grounded and includes a stack of a plurality of conductive layers in the third region.09-02-2010
20110210429Semiconductor Substrate, Package and Device and Manufacturing Methods Thereof - A semiconductor substrate including a carrier, a first conductive layer and a second conductive layer is disclosed. The carrier has a first surface, a second surface, and a concave portion used for receiving a semiconductor element. The first conductive layer is embedded in the first surface and forms a plurality of electric-isolated package traces. The second conductive layer is embedded in the second surface and electrically connected to the first conductive layer. The semiconductor substrate can be applied to a semiconductor package for carrying a semiconductor chip, and combined with a filling structure for fixing the chip' Furthermore, a plurality of the semiconductor substrates can be stacked and connected via adhesive layers, so as to form a semiconductor device with a complicated structure.09-01-2011
20110241186FORMING METAL FILLED DIE BACK-SIDE FILM FOR ELECTROMAGNETIC INTERFERENCE SHIELDING WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.10-06-2011
20090321896SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - There is provided a semiconductor device 12-31-2009
20090321897METHOD AND APPARATUS OF POWER RING POSITIONING TO MINIMIZE CROSSTALK - A method and/or an apparatus of power ring positioning to minimize crosstalk are disclosed. In one embodiment, a method includes generating an array of fingers between a power ring and a die, applying a signal wire between a bond pad of the die and a particular finger of the array of fingers, and applying a shielding wire between an adjacent bond pad and the power ring, such that the shielding wire is longer than the signal wire and does not couple to any of the array of fingers. The shielding wire may be placed between adjacent ones of the signal wire to minimize crosstalk between the adjacent ones of the signal wire.12-31-2009
20090032913Component and assemblies with ends offset downwardly - A stackable microelectronic component includes a dielectric layer having an attachment portion. The dielectric layer has a first side, a second side, and outer ends lying outwardly of the attachment portion. The outer ends are offset from the attachment portion. A semiconductor chip is assembled to the second side of the dielectric layer at the attachment portion. First terminal structures are carried by the outer ends of the dielectric layer for connecting the semiconductor chip with external circuitry located above the first side of the dielectric layer. Second terminal structures are carried by the outer ends of the dielectric layer for connecting the semiconductor chip with external circuitry located below the second side of the dielectric layer.02-05-2009
20120241921INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; attaching a first integrated circuit die to the bottom substrate; forming an interposer including: forming an intermediate substrate; forming a shield on the intermediate substrate; and applying a wire-in-film adhesive to the shield; and attaching the interposer to the first integrated circuit die with the wire-in-film adhesive.09-27-2012
20100059867INTEGRATED CIRCUIT CHIP WITH SEAL RING STRUCTURE - An integrated circuit chip includes an analog and/or RF circuit block, a digital circuit, and a seal ring structure surrounding and protecting the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring, and a discontinuous inner seal ring divided into at least a first portion and a second portion. The second portion is situated in front of the analog and/or RF circuit block for shielding a noise from interfering the analog and/or RF circuit block.03-11-2010
20110175209METHOD OF FORMING AN EM PROTECTED SEMICONDUCTOR DIE - In one embodiment, a semiconductor die is formed to have sloped sidewalls. A conductor is formed on the sloped sidewalls.07-21-2011
20110175210EMI SHIELDING PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.07-21-2011
20110248389SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An upper module board on which an integrated chip component with a low upper temperature limit is mounted and a lower module board on which a heat-generating semiconductor chip, a single chip component and an integrated chip component are mounted are electrically and mechanically connected via a plurality of conductive connecting members, and these are sealed together with mold resin. In such a circumstance, a shield layer made up of a stacked film of a Cu plating film and a Ni plating film is formed on side surfaces of the upper and lower module boards and surfaces (upper and side surfaces) of the mold resin, thereby realizing the electromagnetic wave shield structure.10-13-2011
20110068441Screened Electrical Device and a Process for Manufacturing the Same - A protected electrical device having at least one electrical sub-assembly (03-24-2011
20120119339Semiconductor Device and Manufacturing Method of the Same - With the use of a conductive shield formed on the top or bottom side of a semiconductor integrated circuit, an electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge is prevented, and sufficient communication capability is obtained. With the use of a pair of insulators which sandwiches the semiconductor integrated circuit, a highly reliable semiconductor device that is reduced in thickness and size and has resistance to an external stress can be provided. A semiconductor device can be manufactured with high yield while defects of shapes and characteristics due to an external stress or electrostatic discharge are prevented in the manufacturing process.05-17-2012
20120119338Semiconductor Device And Method Of Manufacturing Semiconductor Device - A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.05-17-2012
20120199958METHOD OF MANUFACTURING HIGH FREQUENCY MODULE AND HIGH FREQUENCY MODULE - In a high frequency module, electronic components are mounted on a mounting surface of a collective substrate including a plurality of unit substrates that include a via conductor electrically conducted to a ground potential in a peripheral portion thereof, and the mounting surface and the electronic components are encapsulated with an encapsulation layer. The collective substrate is cut on the encapsulation layer side, thereby forming a half-cut groove penetrating through the encapsulation layer and extending halfway along the collective substrate in a thickness direction such that the via conductor is exposed only at a bottom surface of the half-cut groove. A conductive shield layer is formed to cover the encapsulation layer and is electrically conducted to the exposed via conductor. The collective substrate is then cut into individual unit substrates each including the conductive shield layer electrically conducted to the ground potential through the via conductor.08-09-2012
20110163425SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.07-07-2011
20080251894Mounted Body and Method for Manufacturing the Same - A mounted body (10-16-2008
20100244208Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die - A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.09-30-2010
20080203545SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF - A ground line is exposed by removing a surface protecting film, which covers an uppermost metal wiring layer, and providing an opening portion at a portion of a top surface of a semiconductor chip, which portion is within a region contacted by a collet in a pick-up process and corresponds to an upper portion of, among plural metal wires provided at the uppermost metal wiring layer, the ground line which has ohmic connection to a semiconductor substrate. When the collet approaches the top surface of the semiconductor chip in the pick-up process, electrostatic discharge is occurred between the collet and the ground line via the opening portion, and neutralizing charges which have flowed into the ground line directly reach the semiconductor substrate. The semiconductor substrate thereby enters a state of electrostatic equilibrium with a mounting film.08-28-2008
20100320577Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-Up Interconnect Structure - A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.12-23-2010
20110133315SYSTEM SUPPORT FOR ELECTRONIC COMPONENTS AND METHOD FOR PRODUCTION THEREOF06-09-2011
20110169143METHOD FOR ESTABLISHING AND CLOSING A TRENCH OF A SEMICONDUCTOR COMPONENT - A method for establishing and closing at least one trench of a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one metal layer over the trench to be formed; forming a lattice having lattice openings in the at least one metal layer over the trench to be formed; forming the trench below the metal lattice, and closing the lattice openings over the trench.07-14-2011
20100059868ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING STRUCTURE FOR ELECTRONIC DEVICE - An electronic device including a shielded electronic element, and a method for manufacturing a shielding structure. An oxide film is formed on the surface of a silicon substrate having a [100] face. Part of the oxide film is removed to form a first window region. Silicon substrates are joined together to form an SOI substrate, which includes a buried mask having a second window region. Substrate thinning is then performed, and oxide films are formed on the two surfaces of the SOI substrate so that the first window region has a large area and includes the region above the buried second window region. Then, anisotropic etching is performed to form a cap that includes a step. Wire bonding for shielding is performed on the step.03-11-2010
20110260301SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING - Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.10-27-2011
20110215449Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package - A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.09-08-2011
20110215448INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit package system includes: providing a base package substrate including: forming component contacts on a component side of the base package substrate, forming system contacts on a system side of the base package substrate, and forming a reference voltage circuit between the component contacts and the system contacts; mounting a first integrated circuit die on the component contacts; mounting a lead frame on the first integrated circuit die and coupled to the component contacts; and isolating a conductive shield from the lead frame, the conductive shield coupled to the reference voltage circuit.09-08-2011
20100019359Semiconductor Device and Method of Forming Shielding Along a Profile Disposed in Peripheral Region Around the Device - A semiconductor device has a semiconductor die with a peripheral region around the die. A first insulating material is deposited in the peripheral region. A conductive via is formed through the first insulating material. A conductive layer is formed over the semiconductor die. The conductive layer is electrically connected between the conductive via and a contact pad of the semiconductor die. A second insulating layer is deposited over the first insulating layer, conductive layer, and semiconductor die. A profile is formed in the first and second insulating layers in the peripheral region. The profile is tapered, V-shaped, truncated V-shape, flat, or vertical. A shielding layer is formed over the first and second insulating layers to isolate the semiconductor die from inter-device interference. The shielding layer conforms to the profile in the peripheral region and electrically connects the shielding layer to the conductive via.01-28-2010
20090174041ULTRAVIOLET BLOCKING STRUCTURE AND METHOD FOR SEMICONDUCTOR DEVICE - Structures and methods for blocking ultraviolet rays during a film depositing process for semiconductor device are disclosed. In one embodiment, a semiconductor device includes an oxide-nitride-oxide (ONO) film formed on a semiconductor substrate, a gate electrode formed on the ONO film, a lower layer insulation film formed on the ONO film and the gate electrode, and a ultraviolet (UV) blocking layer based on a plurality of granular particles scattered in at least one insulation film formed on lower layer insulation film, where the UV blocking layer suppresses UV rays generated during an additional film deposition from reaching the ONO film.07-09-2009
20090072357Integrated shielding process for precision high density module packaging - An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (03-19-2009
20110133316INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a lead frame; forming an integrated circuit package including the lead frame; providing a selectively exposed area on the lead frame; and coating a conductive shielding layer on the integrated circuit package for coupling the selectively exposed area.06-09-2011
20120306063HIGH-FREQUENCY MODULE MANUFACTURING METHOD - In a method of manufacturing a high-frequency module, a resin substrate with a high frequency circuit including an electronic component mounted thereon is placed so that the electronic component faces a resin bath. A resin which is in a non-flowable state in the resin bath is softened until the resin becomes flowable, and air in space formed between the resin substrate and the resin is sucked. The resin substrate is brought into contact with a liquid surface of the resin. The resin is pressurized and allowed to flow into a gap between the resin substrate and the electronic component. The resin is cured so that a resin portion is formed on the resin substrate. A shield metal film is formed on a surface of the resin portion.12-06-2012
20120306061Apparatus and Method for Grounding an IC Package Lid for EMI Reduction - Methods and apparatus for improved electromagnetic interference (EMI) shielding and thermal performance in integrated circuit (IC) packages are described. A die-up or die-down package includes a protective lid, a plurality of ground posts, an IC die, and a substrate. The substrate includes a plurality of ground planes. The IC die is mounted to the substrate. Plurality of ground posts is coupled to plurality of ground planes that surround IC die. Protective lid is coupled to plurality of ground posts. The plurality of ground posts and the protective lid from an enclosure structure that substantially encloses the IC die, and shields EMI from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.12-06-2012
20120306062SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND ELECTRONIC DEVICE - A semiconductor device, a semiconductor package, and an electronic device are provided. The electronic device includes a first semiconductor package disposed on a circuit substrate. A second semiconductor package is provided on the circuit substrate and spaced apart from the first semiconductor package. An insulating electromagnetic shielding structure is provided on the top and the lateral surfaces of the first semiconductor package. A conductive electromagnetic shielding structure is provided on the circuit substrate to cover the first and second semiconductor packages and the insulating electromagnetic shielding structure.12-06-2012
20100006988Integrated Conformal Shielding Method and Process Using Redistributed Chip Packaging - An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (01-14-2010
20110316129MULTILAYER STRUCTURES FOR MAGNETIC SHIELDING - A magnetic shield is presented. The shield may be used to protect a microelectronic device from stray magnetic fields. The shield includes at least two layers. A first layer includes a magnetic material that may be used to block DC magnetic fields. A second layer includes a conductive material that may be used to block AC magnetic fields. Depending on the type of material that the first and second layers include, a third layer may be inserted in between the first and second layers. The third layer may include a non-conductive material that may be used to ensure that separate eddy current regions form in the first and second layers.12-29-2011
20110156225SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device achieving both electromagnetic wave shielding property and reliability in a heating process upon mounting electronic components. In the semiconductor device, mount devices 06-30-2011
20110156224Circuit-substrate laminated module and electronic apparatus - A device that comprises a plurality of circuit elements on a substrate; a shielding element between at least two of the plurality of circuit elements; and a bonding element that electrically connects the shielding element to a grounding circuit of a semiconductor chip that is on the substrate.06-30-2011
20120205788SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.08-16-2012
20120012990Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die - A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.01-19-2012
20110049684ANTICOUNTERFEITING SYSTEM AND METHOD FOR INTEGRATED CIRCUITS - An integrated circuit die comprises a device layer comprising a plurality of semiconductor devices; an interconnect layer comprising a plurality of interconnect paths connecting the semiconductor devices and embedded in a dielectric material; and a plurality of hard nanoparticles embedded in the dielectric material of the interconnect layer, the hard nanoparticles having a hardness greater than a hardness of the dielectric material and of a hardness of the interconnect paths.03-03-2011
20090146270Embedded Package Security Tamper Mesh - Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.06-11-2009
20120104573Semiconductor Device and Method of Shielding Semiconductor Die from Inter-Device Interference - A plurality of stacked semiconductor wafers each contain a plurality of semiconductor die. The semiconductor die each have a conductive via formed through the die. A gap is created between the semiconductor die. A conductive material is deposited in a bottom portion of the gap. An insulating material is deposited in the gap and over the semiconductor die. A portion of the insulating material in the gap is removed to form a recess between each semiconductor die extending to the conductive material. A shielding layer is formed over the insulating material and in the recess to contact the conductive material. The shielding layer isolates the semiconductor die from inter-device interference. A substrate is formed as a build-up structure on the semiconductor die adjacent to the conductive material. The conductive material electrically connects to a ground point in the substrate. The gap is singulating to separate the semiconductor die.05-03-2012
20120025356SEMICONDUCTOR DEVICE PACKAGES HAVING ELECTROMAGNETIC INTERFERENCE SHIELDING AND RELATED METHODS - The semiconductor device package includes a conformal shield layer applied to the exterior surface of the encapsulant. and an internal fence or separation structure embedded in the encapsulant. The fence separates the package into various compartments. with each compartment containing at least one die. The fence thus suppresses EMI between adjacent packages. The package further includes a ground path connected to the internal fence and conformal shield.02-02-2012
20090134500Structures for Preventing Cross-talk Between Through-Silicon Vias and Integrated Circuits - A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring.05-28-2009
20120119340SHIELDED SEMICONDUCTOR DEVICE STRUCTURE - In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer.05-17-2012
20120211875SEMICONDUCTOR DEVICE WITH STACKED SEMICONDUCTOR CHIPS - A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.08-23-2012
20100289126Semiconductor Device and Method of Forming a 3D Inductor from Prefabricated Pillar Frame - A semiconductor device is made by mounting a semiconductor die over a carrier. A ferromagnetic inductor core is formed over the carrier. A prefabricated pillar frame is formed over the carrier, semiconductor die, and inductor core. An encapsulant is deposited over the semiconductor die and inductor core. A portion of the pillar frame is removed. A remaining portion of the pillar frame provides an interconnect pillar and inductor pillars around the inductor core. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors. In another embodiment, a shielding layer is formed over the semiconductor die. A capacitor or resistor is formed within the first or second interconnect structures.11-18-2010
20120126381ADHESIVE FILM FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - An object of the present invention is to decrease the influence of an electromagnetic wave emitted from one semiconductor chip on other semiconductor chips in the same package, amounted substrate, adjacent devices, and the package. The present invention provides an adhesive film for a semiconductor device having an adhesive layer and an electromagnetic wave shielding layer, in which the attenuation of the electromagnetic wave that penetrates the adhesive film for a semiconductor device is 3 dB or more in at least a portion of the frequency range of 50 MHz to 20 GHz.05-24-2012
20120126379DIE BOND FILM, DICING DIE BOND FILM, METHOD OF MANUFACTURING DIE BOND FILM, AND SEMICONDUCTOR DEVICE HAVING DIE BOND FILM - A semiconductor device having an electromagnetic wave shielding layer can be manufactured without decreasing productivity. The present invention provides a die bond film including an adhesive layer and an electromagnetic wave shielding layer made of a metal foil or a die bond film including an adhesive layer and an electromagnetic wave shielding layer formed by vapor deposition.05-24-2012
20120126378SEMICONDUCTOR DEVICE PACKAGE WITH ELECTROMAGNETIC SHIELDING - A package for a semiconductor device includes shielding from RF interference. The package has a lead frame with a lead and a connecting bar. The lead has an inner end for connecting to the device and an outer end having an exposed surface at the package side face. The connecting bar also has an end with an exposed surface at the package side face. A molding compound overlying the leadframe forms a portion of the side face. Electrically conductive shielding forms a top surface of the package, and extends downward therefrom to form an upper portion of the package side face. The exposed surface at the connecting bar end has an upper edge higher than the upper edge of the exposed surface of lead end. Accordingly, the shielding makes electrical contact with the connecting bar adjacent to its exposed surface, while being electrically isolated from the lead.05-24-2012
20120126380FILM FOR THE BACKSIDE OF FLIP-CHIP TYPE SEMICONDUCTOR, DICING TAPE-INTEGRATED FILM FOR THE BACKSIDE OF SEMICONDUCTOR, METHOD OF MANUFACTURING FILM FOR THE BACKSIDE OF FLIP-CHIP TYPE SEMICONDUCTOR, AND SEMICONDUCTOR DEVICE - An electromagnetic wave shielding layer can be provided on the backside of a semiconductor element that is flip-chip connected to an adherend, and a semiconductor device having the electromagnetic wave shielding layer can be manufactured without deteriorating productivity. The present invention provides a film for the backside of a flip-chip type semiconductor to be formed on the backside of a semiconductor element that is flip-chip connected to an adherend, having an adhesive layer and an electromagnetic wave shielding layer.05-24-2012
20120161299INTERLEVEL CONDUCTIVE LIGHT SHIELD - A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.06-28-2012
20100207256SECURITY CHIP - A security chip is disclosed. The security chip includes: a substrate; an integrated circuit disposed on the substrate, the integrated circuit including circuit elements, circuit interconnect layers connecting the circuit elements together, and interlayer contacts supporting the circuit interconnect layers; a shield to at least partially shield the integrated circuit; and at least one lightwell in the shield and the integrated circuit, wherein each lightwell has a closed shape formed from parts of the circuit interconnect layers and interlayer contacts, wherein no exploitable voltage can be measured on the parts of the circuit interconnect layers and interlayer contacts, and wherein each lightwell forms a path for light to penetrate to the substrate preventing the light from reaching the circuit elements. Related apparatus and methods are also disclosed.08-19-2010
20100207255Shield for an intergrated circuit - A shield for an integrated circuit comprising an upper wall and a side wall assembly. The upper wall includes a top surface, a bottom surface and a perimeter. The side wall assembly depends from the perimeter of the upper wall. The side wall assembly has a proximal end, a distal end, an inner surface and an outer surface. The distal end defines a lower edge. At least a portion of the side wall assembly includes a plurality of surface variations along a length thereof, to, in turn, define a lower edge of the side wall assembly having a non-linear configuration. Such a non-linear configuration increases the rigidity of the shield.08-19-2010
20120133032PACKAGE HAVING ESD AND EMI PREVENTING FUNCTIONS AND FABRICATION METHOD THEREOF - A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits.05-31-2012
20120313226WIRING SUBSTRATE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a wiring substrate, and a semiconductor chip, wherein the wiring substrate includes a glass plate having an opening portion penetrating through a first surface of the glass plate to a second surface of the glass plate, a resin portion penetrating through the first surface to the second surface, and a through wiring penetrating through the resin portion from the first surface to the second surface to electrically connect a first wiring layer formed on a side of the first surface with a third wiring layer formed on a side of the second surface, wherein the semiconductor chip is accommodated inside the opening portion.12-13-2012
20120168916Semiconductor Device and Method of Forming Open Cavity in TSV Interposer to Contain Semiconductor Die in WLCSMP - A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer.07-05-2012
20120256305Integrated Circuit Package Security Fence - Embodiments of an integrated circuit package security fence are provided. The integrated circuit package includes a substrate, a die, and a security fence coupled to the substrate such that the die is located between the security fence and the substrate. The security fence includes a first signal net having a plurality of bonding wires and a second signal net having a second plurality of bonding wires. The bonding wires of the first signal net and second signal net are arranged in a pattern to overlap the top surface of die. The die may include tamper detection logic to detect attempt to access the die through the security fence.10-11-2012
20120074543PACKAGE APPARATUS OF POWER SEMICONDUCTOR DEVICE - A package apparatus is for packaging a power semiconductor device that includes a substrate formed, a mold part molded on the substrate, and electrode terminals extended from the mold part to a side opposite from the substrate by a predetermined length; includes: a holding unit that has insertion slots and is to holding the power semiconductor device, the insertion slots each being an opening into which the power semiconductor device is insertable in a direction perpendicular to extending direction of the electrode, edges of the opening being formed to make contact with the mold part and the substrate; and a container box that contains the holding unit. The insertion slots are provided to the holding unit so that an interval between the insertion slots in an extending direction of the electrode terminals of the power semiconductor device inserted is greater than the extending length of the electrode terminals.03-29-2012
20120074541SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique is provided which allows a chip mounted by wire bonding and a chip mounted by bump electrodes to share a manufacturing process. Both in a case where a chip is electrically coupled to an external circuit by bump electrodes and a case where the chip is electrically coupled to the external circuit by bonding wires, a bump coupling part and a bonding pad are both provided in a single uppermost wiring layer. When the bump electrodes are used, an opening is provided in an insulating film on the bump coupling part and a surface of the bonding pad is covered with the insulating film. On the other hand, when the bonding wires are used, an opening is provided in an insulating film on the bonding pad and a surface of the bump coupling part is covered with the insulating film.03-29-2012
20120074540SEMICONDUCTOR CHIP PACKAGE - A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.03-29-2012
20120074539DEVICE AND METHODS FOR ELECTROSTATIC DISCHARGE PROTECTION - An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.03-29-2012
20120074538PACKAGE STRUCTURE WITH ESD AND EMI PREVENTING FUNCTIONS - A package structure with ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a carrier having first and second ground structures electrically insulated from one another; a semiconductor component disposed on one surface of the carrier and electrically connected to the first ground structure; and a lid member disposed to cover the carrier and the semiconductor component and electrically connected to the second ground structure. The semiconductor component and the lid member are electrically connected with the first ground structure and the second ground structure, respectively, such that electrostatic charges and electromagnetic waves can be conducted away individually without damaging the semiconductor component, thereby improving yield and reducing the risk of short circuits.03-29-2012
20120181673Semiconductor Device and Method of Stacking Die on Leadframe Electrically Connected by Conductive Pillars - A semiconductor device has a first semiconductor die mounted to a first contact pad on a leadframe or substrate with bumps. A conductive pillar is formed over a second semiconductor die. The second die is mounted over the first die by electrically connecting the conductive pillar to a second contact pad on the substrate with bumps. The second die is larger than the first die. An encapsulant is deposited over the first and second die. Alternatively, the conductive pillars are formed over the substrate around the first die. A heat sink is formed over the second die, and a thermal interface material is formed between the first and second die. An underfill material is deposited under the first semiconductor die. A shielding layer is formed between the first and second die. An interconnect structure can be formed over the second contact pad of the substrate.07-19-2012
20120313227SEMICONDUCTOR DEVICE AND STRUCTURE FOR HEAT REMOVAL - A semiconductor device, including: a semiconductor substrate with first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors.12-13-2012
20120187551SEMICONDUCTOR MODULE - Provided is a semiconductor module (A), including: a substrate (07-26-2012
20120187550INTERCONNECTION STRUCTURE, APPARATUS THEREWITH, CIRCUIT STRUCTURE THEREWITH - An interconnection structure is disposed between a first conductive layer and a second conductive layer substantially parallel to each other. The conductive layer includes a signal trace. The interconnection structure includes a conductor pillar and a shielding wall pillar. The conductor pillar goes through between the two conductive layers and is electrically connected to the signal trace of the first conductive layer. The shielding wall pillar is also disposed between the two conductive layers and located at a portion of an external region surrounding the conductor pillar and electrically coupled to the conductor pillar. The conductor pillar and the shielding wall pillar are disposed in pair or in group. The shielding wall pillar with a shape different from that of the conductor pillar would make the conductor pillar serve as a connection with a designed impedance and the capability of controlling impedance based on the special shape design thereof.07-26-2012
20120187549IC In-process Solution to Reduce Thermal Neutrons Soft Error Rate - Integrated Circuits and methods for reducing thermal neutron soft error rate (SER) of a digital circuit are provided by doping a protection layer on top of the metal layer and in physical contact with the metal layer of the digital circuit, wherein the protection layer is doped with additional thermal neutron absorbing material. The thermal neutron absorbing material can be selected from the group consisting of Gd, Sm, Cd, B, and combinations thereof. The protection layer may comprise a plurality of sub-layers among which a plurality of them containing additional thermal neutron absorbing material.07-26-2012
20120228750SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a semiconductor chip having a front surface and a rear surface, a sealing resin layer stacked on the front surface of the semiconductor chip, a post passing through the sealing resin layer in the thickness direction and having a side surface flush with a side surface of the sealing resin layer and a forward end surface flush with a front surface of the sealing resin layer, and an external connecting terminal provided on the forward end surface of the post.09-13-2012
20120228749SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER SEMICONDUCTOR DIE MOUNTED TO TSV INTERPOSER - A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure.09-13-2012
20110121438EXTENDED UNDER-BUMP METAL LAYER FOR BLOCKING ALPHA PARTICLES IN A SEMICONDUCTOR DEVICE - An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion.05-26-2011
20120319253SEMICONDUCTOR MODULE MANUFACTURING METHOD, SEMICONDUCTOR MODULE, AND MANUFACTURING DEVICE - In the disclosed method for manufacturing a semiconductor module, a metal layer and a cooler, which have different coefficients of thermal expansion from each other, are joined into a single unit via an insulating resin sheet. A work, comprising a semiconductor element placed on the metal layer with solder interposed therebetween, is fed into a reflow furnace. The work, in that state, is heated in the reflow furnace, thereby mounting the semiconductor element to the metal layer. The heating is carried out such that the temperature of the cooler and the temperature of the metal layer differ by an amount that make the cooler and the metal layer undergo the same amount of thermal expansion as each other.12-20-2012
20120319254WIRING BOARD WITH BUILT-IN SEMICONDUCTOR ELEMENT - A wiring board including a built-in semiconductor element includes the semiconductor element, a peripheral insulating layer covering an outer peripheral side surface of the semiconductor element, an upper surface-side wiring provided on an upper surface side of the wiring board, and a lower surface-side wiring provided on a lower surface side of the wiring board. The semiconductor element includes a first wiring structure layer including a first wiring and a first insulating layer alternately provided on a semiconductor substrate, and a second wiring structure layer including a second wiring and a second insulating layer alternately provided on the first wiring structure layer. The upper surface-side wiring includes a wiring electrically connected to the first wiring via the second wiring. The second wiring is thicker than the first wiring and thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer.12-20-2012
20120080780SEM ICONDUCTOR DEVICE HAVING PADS AND WHICH MINIMIZES DEFECTS DUE TO BONDING AND PROBING PROCESSES - A semiconductor device includes: a semiconductor substrate; a first interlayer insulating film formed over the semiconductor substrate; a pad formed above the first interlayer insulating film; and a plurality of first interconnects spaced apart from each other in a portion of the first interlayer insulating film located below the pad. Below the pad, the first interconnects are formed in quadrangular plan shapes.04-05-2012
20110260302SHIELDING DEVICE - One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit.10-27-2011
20100230789SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A technology is provided which allows a reduction in the size of a semiconductor device without degrading an electromagnetic shielding effect and reliability against reflow heating. After a plurality of components are mounted over a component mounting surface of a module substrate, a resin is formed so as to cover the mounted components. Further, over surfaces (upper and side surfaces) of the resin, a shield layer including a laminated film of a Cu plating film and an Ni plating film is formed. In the shield layer, a plurality of microchannel cracks are formed randomly along grain boundaries and in a net-like configuration without being coupled to each other in a straight line, and form a plurality of paths extending from the resin to a surface of the shield layer by the microchannel cracks.09-16-2010
20120280374Semiconductor Device and Method of Mounting Cover to Semiconductor Die and Interposer with Adhesive Material - A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.11-08-2012
20130020685SUBSTRATES FOR SEMICONDUCTOR DEVICES INCLUDING INTERNAL SHIELDING STRUCTURES AND SEMICONDUCTOR DEVICES INCLUDING THE SUBSTRATES - A semiconductor device includes a substrate comprising a stack of alternating wiring layers and insulating layers. The wiring layers include conductive wiring patterns. Primary conductive vias extend through respective ones of the insulating layers and electrically connect first ones of the wiring patterns on different ones of the wiring layers to provide electrical connections between opposing first and second surfaces of the substrate. Dummy conductive vias extend through respective ones of the insulating layers and electrically connect second ones of the wiring patterns on different ones of the wiring layers. The dummy conductive vias are arranged in the substrate around a perimeter of a region including the first ones of the wiring patterns, and the dummy conductive vias and the second ones of the wiring patterns electrically connected thereto have a same electric potential to define an electromagnetic shielding structure within the substrate.01-24-2013
20120091567Semiconductor Die and Method of Forming Noise Absorbing Regions Between THVs in Peripheral Region of the Die - A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV.04-19-2012
20120286403SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.11-15-2012
20120286404Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure - A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.11-15-2012
20120139091SEMICONDUCTOR DEVICE HAVING SHIELD LAYER AND CHIP-SIDE POWER SUPPLY TERMINAL CAPACITIVELY COUPLED THEREIN - Provided is a semiconductor device including a wiring board having a first surface on which a board-side ground terminal and a board-side power supply terminal are provided; a semiconductor chip arranged so as to face the first surface of the wiring board, where the first surface faces an opposite surface of the semiconductor chip; a shield layer provided at the semiconductor chip so as to cover an outer surface of the semiconductor chip except for the opposite surface; a chip-side power supply terminal which is provided on the opposite surface and is electrically connected to the board-side power supply terminal; a chip-side ground terminal which is provided on the opposite surface and is electrically connected to the board-side ground terminal and the shield layer; and a first capacitively coupled part by which the shield layer and the chip-side power supply terminal are capacitively coupled with each other.06-07-2012
20130015563Semiconductor packageAANM Lee; Jung AunAACI SuwonAACO KRAAGP Lee; Jung Aun Suwon KRAANM Han; Myeong WooAACI HwaseongAACO KRAAGP Han; Myeong Woo Hwaseong KRAANM Yoo; Do JaeAACI SuwonAACO KRAAGP Yoo; Do Jae Suwon KRAANM Park; Chul GyunAACI YonginAACO KRAAGP Park; Chul Gyun Yongin KR - There is provided a semiconductor package, and more particularly, a semiconductor package including an antenna embedded in an inner portion thereof. The semiconductor package includes: a semiconductor chip; a main antenna disposed to be adjacent to the semiconductor chip and electrically connected thereto; a sealing part sealing both of the semiconductor chip and the main antenna; and an auxiliary antenna formed on an outer surface of the sealing part and coupled to the main antenna.01-17-2013
20130168837ESD PROTECTION DEVICE - An ESD protection device includes a semiconductor substrate including input/output electrodes and a rewiring layer located on the top surface of the semiconductor substrate. An ESD protection circuit is provided in the top layer of the semiconductor substrate, and the input/output electrodes are connected to the ESD protection circuit. The rewiring layer includes interlayer wiring lines, in-plane wiring lines, and post-shaped electrodes. First ends of the interlayer wiring lines provided in the thickness direction are connected to the input/output electrodes provided on the top surface of the semiconductor substrate and the second ends are connected to first ends of the in-plane wiring lines extending in the plane direction. The distance between the centers of the first and second post-shaped electrodes is larger than the distance between the centers of the first and second input/output electrodes.07-04-2013
20120241923IC WAFER HAVING ELECTROMAGNETIC SHIELDING EFFECTS AND METHOD FOR MAKING THE SAME - An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.09-27-2012
20120241922INTEGRATED CIRCUIT PACKAGING SYSTEM FOR ELECTROMAGNETIC INTERFERENCE SHIELDING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle pad and a peripheral lead pad with an inner lead pad between the die attach paddle pad and the peripheral lead pad; forming a component side of the lead frame for exposing an upper portion of a peripheral lead under the peripheral lead pad; forming an encapsulation on the lead frame and the upper portion of the peripheral lead; exposing the peripheral lead pad; depositing a conductive shielding layer on the encapsulation connected to the peripheral lead pad; and forming a mounting side of the lead frame for forming a lower portion of the peripheral lead over a peripheral lead contact pad.09-27-2012
20080251893MOUNTING CLIPS FOR USE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING AND METHODS OF USING THE SAME - According to various aspects, exemplary embodiments are provided of clips that may be compatible with surface mount technology. The clips may be surface mountable to a substrate for allowing repeated releasable attachment and detachment of a shielding structure thereto. In one exemplary embodiment, a clip generally includes a base member having generally opposed first and second side edge portions. Two or more arms extend generally upwardly in a first direction from the base member. The clip also includes a generally flat pick-up surface configured to enable the clip to be picked up by a head associated with pick-and-place equipment.10-16-2008
20130140683Semiconductor Device and Method of Forming Cavity in Build-Up Interconnect Structure for Short Signal Path Between Die - In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed to expose a first side of the encapsulant and active surface of the first semiconductor die. A masking layer is formed over the active surface of the first semiconductor die. A first interconnect structure is formed over the first side of the encapsulant. The masking layer blocks formation of the first interconnect structure over the active surface of the first semiconductor die. The masking layer is removed to form a cavity over the active surface of the first semiconductor die. A second semiconductor die is mounted in the cavity. The second semiconductor die is electrically connected to the active surface of the first semiconductor die with a short signal path.06-06-2013
20130140684Semiconductor Device Assembly Utilizing a DBC Substrate - A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.06-06-2013
20080224276Semiconductor device package - The present invention provides a package structure and a method for forming the same; wherein the structure comprises a substrate with certain open through holes filled with conducting metals for performing electrical connection or heat dissipation, a chip with bonding pads attached on the contacting pad by an adhesive with high thermal conductivity, wire bounded the contacting pad and the chip pad, a protection layer covered on the chip, wire and a portion of pad by molding or dispensing and a solder ball disposed on the pad. The advantages of the present invention are: the structure is reduced; the heat dissipation of the structure is enhanced; the structure can form package on package structure; the pads provides better ground shielding, heat dissipation of the structure.09-18-2008
20120248586SEMICONDUCTOR APPARATUS FOR PREVENTING CROSSTALK BETWEEN SIGNAL LINES - A semiconductor integrated circuit apparatus includes a semiconductor substrate, a plurality of signal lines, and at least one interface member. The signal lines are disposed on the semiconductor substrate. The interface member is disposed in the semiconductor substrate between the adjacent signal lines among the signal lines to pierce the semiconductor substrate.10-04-2012
20120248585ELECTROMAGNETIC INTERFERENCE SHIELDING STRUCTURE FOR INTEGRATED CIRCUIT SUBSTRATE AND METHOD FOR FABRICATING THE SAME - An electromagnetic interference (EMI) shielding structure for integrated circuit (IC) substrate includes a plurality of conductive contacts, a covering layer, and a sputtered layer. The conductive contacts are formed at the perimeter of a chip area on the IC substrate. The covering layer is formed on the conductive contacts and covers the chip area. A groove is formed on the covering layer for exposing the conductive contacts. The sputtered layer is formed on the covering layer and connected to the conductive contacts. The EMI shielding structure can restrain the interference in the chip area.10-04-2012
20130134565SYSTEM-IN-PACKAGE MODULE AND METHOD OF FABRICATING THE SAME - A method of fabricating a system-in-package (SiP) module is provided, which includes: providing a substrate having a plurality of scribe lines formed thereon, forming ground pads and ground vias along the scribe lines, disposing at least one electronic component on the substrate, forming on the substrate an encapsulant for encapsulating the electronic component, cutting the substrate along the scribe lines so as to expose the ground vias, and forming a shielding layer on the encapsulant and the ground vias to thereby obtain a plurality of SiP modules. Therefore, electromagnetic radiation interferences are avoided and the design complexity and fabrication cost are reduced.05-30-2013
20130093067WAFER LEVEL APPLIED RF SHIELDS - An embodiment of a method of forming an on-chip RE shield on an integrated circuit chip in accordance with the present disclosure includes providing a wafer level integrated circuit component wafer having a front side and a back side before singulation; applying a resin metal layer on a back side of the wafer; and then separating the wafer into discrete RF shielded components. It is this resin metal layer on the back side that acts effectively as the RF shield, after singulation, i.e. separation of the wafer, into discrete RF shielded components.04-18-2013
20130113088CHIP PACKAGING STRUCTURE, CHIP PACKAGING METHOD, AND ELECTRONIC DEVICE - The present invention relates to the field of chip packaging and discloses a chip packaging structure, a chip packaging method, and an electronic device, which are used to solve a problem that in the chip packaging structure, a shielding film formed by a conductive coating easily drops off. The chip packaging structure includes: a printed circuit board PCB; a shielding can, where the shielding can is fixedly set on a component side of the PCB; and a chip to be shielded, where the chip to be shielded is set on the component side of the PCB and is located inside the shielding can, and pins of the chip to be shielded are connected to a first pad on the PCB and the chip to be shielded does not touch the shielding can. The solution provided in the present invention can be applied to chip packaging.05-09-2013
20130127024INTEGRATED CIRCUIT CHIPS WITH FINE-LINE METAL AND OVER-PASSIVATION METAL - An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.05-23-2013
20110221046SEMICONDUCTOR ASSEMBLY PACKAGE HAVING SHIELDING LAYER AND METHOD THEREFOR - A semiconductor assembly package includes a package unit, a shielding layer and a protection layer. The package unit includes a semiconductor assembly, a daughter substrate and a mold compound. The semiconductor assembly is disposed on and electrically connected to the daughter substrate. The daughter substrate includes a metal portion grounded. The mold compound encapsulates the semiconductor assembly and the daughter substrate to expose the metal portion out of the package unit. The shielding layer is applied to the package unit and electrically connected to the metal portion, to provide electromagnetic shielding for the semiconductor assembly. The non-conductive protection layer is covered on the shielding layer.09-15-2011
20130147023INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE - The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.06-13-2013
20120273927Semiconductor Device and Method of Forming Wafer Level Multi-Row Etched Lead Package - A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.11-01-2012
20120273926Semiconductor Device and Method of Forming Shielding Layer Over Active Surface of Semiconductor Die - A semiconductor wafer contains a plurality of semiconductor die separated by a non-active area of the semiconductor wafer. A plurality of contact pads is formed on an active surface of the semiconductor die. A first insulating layer is formed over the semiconductor wafer. A portion of the first insulating layer is removed to expose the contact pads on the semiconductor die. An opening is formed partially through the semiconductor wafer in the active surface of the semiconductor die or in the non-active area of the semiconductor wafer. A second insulating layer is formed in the opening in the semiconductor wafer. A shielding layer is formed over the active surface. The shielding layer extends into the opening of the semiconductor wafer to form a conductive via. A portion of a back surface of the semiconductor wafer is removed to singulate the semiconductor die.11-01-2012
20110233737METHOD FOR MANUFACTURING 3-DIMENSIONAL STRUCTURES USING THIN FILM WITH COLUMNAR NANO PORES AND MANUFACTURE THEREOF - Disclosed is a method for manufacturing 3-dimensional structure using a thin film with a columnar nano pores and a manufacture thereof. A method for packaging an MEMS device or an NEMS device in accordance with an embodiment of the present invention includes: 09-29-2011
20110233736INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a rounded interconnect on the package carrier; mounting a conductive shield over the package carrier, the conductive shield having an elevated portion and a hole adjacent to the elevated portion with the elevated portion over the integrated circuit and the rounded interconnect exposed from the hole; and forming an encapsulation between the conductive shield and the package carrier with the rounded interconnect exposed.09-29-2011
20100314727Semiconductor device - A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.12-16-2010
20100314726FARADAY CAGE FOR CIRCUITRY USING SUBSTRATES - An apparatus and method uses a first Faraday cage portion and a second Faraday cage portion to provide a Faraday cage enclosure surrounding at least one circuit device.12-16-2010
20130154066SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package is presented which has a suitable structure for effectively shielding electromagnetic wave interference (EMI) in a cavity area to which a semiconductor chip is attached. The semiconductor package is assembled such that a lower substrate to which the semiconductor chip is attached is adhered to an EMI shielding & electric I/O body having various types of EMI shielding & electric I/O metal patterns by soldering. Further, the EMI shielding & electric I/O body is adhered to an upper substrate by soldering thereby simplifying assembling of the semiconductor package.06-20-2013
20110309482FINGER SENSOR INCLUDING ENCAPSULATING LAYER OVER SENSING AREA AND RELATED METHODS - A fingerprint sensor may include a substrate, and a finger sensing IC on the substrate and including a finger sensing area on an upper surface thereof for sensing an adjacent finger. The fingerprint sensor may include an encapsulating material on the finger sensing IC and covering the finger sensing area, and a bezel adjacent the finger sensing area and on an uppermost surface of the encapsulating layer.12-22-2011
20110309481INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIP CHIP MOUNTING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: fabricating a flip chip integrated circuit die having chip interconnects on an active side; providing a substrate for coupling the flip chip integrated circuit die by the chip interconnects; and applying a conductive underfill directly on the active side to completely fill a stand-off space surrounding the chip interconnects.12-22-2011
20120018858METHOD OF ASSEMBLING INTEGRATED CIRCUIT DEVICE - A method of assembling an integrated circuit (IC) device includes the steps of providing a lead frame or substrate panel, attaching a semiconductor die to the lead frame or substrate panel and electrically coupling the die to the lead frame or substrate panel. The method further includes encapsulating the die with a first encapsulant, and the encapsulating the first encapsulant with a second encapsulant where the second encapsulant includes a material that provides electromagnetic shielding.01-26-2012
20120018857SYSTEM AND METHOD OF CHIP PACKAGE BUILD-UP - A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.01-26-2012
20130193566Integrated Circuit Shielding Film and Manufacturing Method Thereof - An integrated circuit shielding film and a manufacturing method thereof. The manufacturing method provides a plate. A stripping glue is coated on the plate. An integrated circuit is disposed on the stripping glue and the stripping glue is deposited on the surface of the integrated circuit. A shielding film is then formed on the integrated circuit by coating operations.08-01-2013
20120299165Semiconductor Device and Method of Forming Shielding Layer Over Semiconductor Die Mounted to TSV Interposer - A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure.11-29-2012
20120074542SEMICONDUCTOR DEVICE - A semiconductor device, in which a control circuit board is mountable outside a sheath case and a power semiconductor element is placeable inside the sheath case, includes a metal step support, a shield plate and a metal ring. The support includes a base portion implanted in the sheath case, a connection portion which extends from an end of the base portion, and a step portion formed at a boundary between the base portion and the connection portion. The shield plate is disposed over the step portion such that the connection portion of the support pierces the shield plate. An end of the metal ring protrudes from an end of the connection portion over the shield plate. The semiconductor device is adapted such that the control circuit board is mounted over the protruded end of the metal ring and is fixed onto the connection portion by an engagement member.03-29-2012
20120086110IC PACKAGE - An IC package which can avoid electromagnetic waves leaked from a side surface of the IC package includes: an electric circuit board on which an IC chip is mounted; a first conductive board arranged at a position facing the electric circuit board while the IC chip on the electric circuit board is sandwiched therebetween; and a magnetic body which is arranged on a surface of the first conductive board on a side facing the IC chip and which is arranged at least partially on end portions of the first conductive board.04-12-2012
20120086109Semiconductor Device Including Shielding Layer And Fabrication Method Thereof - Example embodiments relate to a semiconductor device. The semiconductor device may include a first semiconductor chip including a semiconductor substrate, a first through via that penetrates the semiconductor substrate, a second semiconductor chip stacked on one plane of the first semiconductor chip, and a shielding layer covering at least one portion of the first and/or second semiconductor chip and electrically connected to the first through via.04-12-2012
20120086108CHIP LEVEL EMI SHIELDING STRUCTURE AND MANUFACTURE METHOD THEREOF - A chip level EMI shielding structure and manufacture method thereof are provided. The chip level EMI shielding structure includes a semiconductor substrate, at least one ground conductor line, a ground layer, and a connection structure. The ground conductor line is disposed on a first surface of the semiconductor substrate, and the ground layer is disposed on a second surface of the semiconductor substrate. The connection structure is formed on a lateral wall of the semiconductor substrate for connecting the ground conductor lines with the ground layer to form a shielding. With such arrangement, the chip level EMI shielding structure can reduce the chip size and the manufacturing cost.04-12-2012
20130207246Packaging an Integrated Circuit Die - An electronic device (08-15-2013
20130207247Semiconductor Device and Method of Forming a Shielding Layer Over a Semiconductor Die After Forming a Build-up Interconnect Structure - A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.08-15-2013

Patent applications in class WITH SHIELDING (E.G., ELECTRICAL OR MAGNETIC SHIELDING, OR FROM ELECTROMAGNETIC RADIATION OR CHARGED PARTICLES)

Patent applications in all subclasses WITH SHIELDING (E.G., ELECTRICAL OR MAGNETIC SHIELDING, OR FROM ELECTROMAGNETIC RADIATION OR CHARGED PARTICLES)