| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257653000 | WITH SPECIFIED SHAPE OF PN JUNCTION | 13 |
| 20090230516 | PIN Diode with Improved Power Limiting - A PIN diode comprising an N-type substrate comprising a cathode of the PIN diode and having an intrinsic layer disposed upon the N-type substrate and having a top surface a P-type material disposed upon the top surface of the intrinsic layer comprising an anode of the PIN diode and a N-type material disposed over the sidewall of the cathode and over the sidewall and a portion of the top surface of the intrinsic material that is not occupied by the anode, wherein a horizontal gap is defined between the anode and the cathode through the intrinsic material, the gap being variable in width and/or the horizontal gap is less than the thickness of the intrinsic layer. | 09-17-2009 |
| 20120032312 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF PRODUCING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate which allows desired electrical characteristics to be more easily acquired, a semiconductor device of the same, and a method of producing the semiconductor substrate. The method of producing this semiconductor substrate is provided with: a first epitaxial layer forming step (S | 02-09-2012 |
| 20100102419 | Epitaxy-Level Packaging (ELP) System - An epitaxy-level packaging grows an epitaxial film and transfers it to an assembly substrate. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications. | 04-29-2010 |
| 20090179309 | Power semiconductor component with trench- type second contact region - A power semiconductor component and method for producing it. The component has a semiconductor base body with a first doping and a pn junction formed by a contact region having a second doping with a doping profile in the base body. The second contact region is arranged at a second surface of the base body and extends into the base body. The base body has a trench-type cutout with an edge area and a base area, wherein the base area is formed as a second partial area of the second surface, and wherein the second contact region extends from the base area via the edge area as far as a first partial area. Furthermore, the pn junction has a curvature adjacent to the edge area. | 07-16-2009 |
| 20090218662 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor region of a first conductive type; a second semiconductor region of the first conductive type formed on an upper surface of the first semiconductor region and having a lower impurity concentration than that of the first semiconductor region; a third semiconductor region of the first conductive type formed on the upper surface of the first semiconductor region and having a higher impurity concentration than that of the second semiconductor region; and a fourth semiconductor region of a second conductive type different from the first conductive type formed on upper surfaces of the second semiconductor region and the third semiconductor region. A PN junction is formed between the second semiconductor region and third semiconductor region and the fourth semiconductor region. The second semiconductor region is formed to surround the third semiconductor region. | 09-03-2009 |
| 20110049683 | STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES - Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds. | 03-03-2011 |
| 20100155911 | ESD Protection Diode in RF pads - A diode is provided. The diode includes first and second diffusion layers formed in a substrate, a first metal coupled to the first diffusion layer, and a second metal coupled to the second diffusion layer that has width that is smaller than a width of the second diffusion layer. | 06-24-2010 |
| 20110068439 | DOUBLE TRENCH RECTIFIER - A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent. | 03-24-2011 |
| 20120248584 | NANO/MICRO-SIZED DIODE AND METHOD OF PREPARING THE SAME - A nano/micro-sized diode and a method of preparing the same, the diode including: a first electrode; a second electrode; and a diode layer that is disposed between the first electrode and the second electrode. The diode layer includes a first layer and a second layer. The first layer is disposed on the first electrode and has a first surface that is electrically connected to the first electrode, and an opposing second surface that has a protrusion. The second layer is disposed between the first layer and the second electrode and has a first surface having a recess that corresponds to the protrusion, and an opposing second surface that is electrically connected to the second electrode. | 10-04-2012 |
| 20120133031 | FABRICATION OF SELF-ASSEMBLED NANOWIRE-TYPE INTERCONNECTS ON A SEMICONDUCTOR DEVICE - Consistent with an example embodiment, there is a semiconductor device with nanowire-type interconnect elements. | 05-31-2012 |
| 20100052116 | FABRICATION OF SELF-ASSEMBLED NANOWIRE-TYPE INTERCONNECTS ON A SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor device with nanowire-type interconnect elements and a method for fabricating the same. The device comprises a metal structure with at least one self-assembled metal dendrite and forming an interconnect element ( | 03-04-2010 |
| 20120223421 | DOUBLE TRENCH RECTIFIER - A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent. | 09-06-2012 |
| 20120261804 | VERTICAL SUBSTRATE DIODE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE - A diode structure, formed under a buried dielectric layer of a silicon on insulator (SOI), method of manufacturing the same and design structure thereof are provided. In an embodiment the p-n junction of the diode structure can be advantageously arranged in a vertical orientation. The cathode comprises an N+ epitaxial layer formed upon a P-type substrate. The anode comprises an active region of the P-substrate. Contacts to the cathode and anode are formed through the buried dielectric layer. Contact to the anode is accomplished via a deep trench filled with a conductive plug. The deep trench also provides electrical isolation for the cathode (as well as p-n junction). Advantageously, embodiments of the present invention may be formed during formation of other structures which also include trenches (for example, deep trench capacitors) in order to reduce process steps required to form the diode structure under the buried dielectric layer of the SOI substrate. | 10-18-2012 |
