Class / Patent application number | Description | Number of patent applications / Date published |
257649000 | Insulating layer of silicon nitride or silicon oxynitride | 25 |
20080203544 | SEMICONDUCTOR WAFER STRUCTURE WITH BALANCED REFLECTANCE AND ABSORPTION CHARACTERISTICS FOR RAPID THERMAL ANNEAL UNIFORMITY - Disclosed are embodiments of semiconductor wafer structures and associated methods of forming the structures with balanced reflectance and absorption characteristics. The reflectance and absorption characteristics are balanced by manipulating thin film interferences. Specifically, thin film interferences are manipulated by selectively varying the thicknesses of the different films. Alternatively, reflectance and absorption characteristics can be balanced by incorporating an additional reflectance layer into the wafer structure above the substrate. | 08-28-2008 |
20090102027 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPLIANCE - An object of the present invention is to provide a semiconductor device including an insulating layer with a high dielectric strength voltage, a low dielectric constant, and low hygroscopicity. Another object of the present invention is to provide an electronic appliance with high performance and high reliability, which uses the semiconductor device. An insulator containing nitrogen, such as silicon oxynitride or silicon nitride oxide, and an insulator containing nitrogen and fluorine, such as silicon oxynitride added with fluorine or silicon nitride oxide added with fluorine, are alternately deposited so that an insulating layer is formed. By sandwiching an insulator containing nitrogen and fluorine between insulators containing nitrogen, the insulator containing nitrogen and fluorine can be prevented from absorbing moisture and thus a dielectric strength voltage can be increased. Further, an insulator contains fluorine so that a dielectric constant can be reduced. | 04-23-2009 |
20090108415 | INCREASING ETCH SELECTIVITY DURING THE PATTERNING OF A CONTACT STRUCTURE OF A SEMICONDUCTOR DEVICE - By forming an intermediate etch stop material or by appropriately positioning an additional etch stop material in a spacer structure of a polysilicon line, the probability of exposing a shallow doped region of an active semiconductor region during a critical contact etch step for forming rectangular contacts may be significantly reduced. Thus, leakage current, which may conventionally be created by etching into shallow doped regions during the contact etch step, may be reduced. | 04-30-2009 |
20090179308 | Method of Manufacturing a Semiconductor Device - According to one embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method includes: forming a semiconductor structure; forming a stress liner over the semiconductor structure; and changing the stress properties of at least a part of the stress liner. | 07-16-2009 |
20090283874 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps. | 11-19-2009 |
20090289334 | Metal gate structure and method of manufacturing same - A method of manufacturing a metal gate structure includes providing a substrate ( | 11-26-2009 |
20100013062 | NONVOLATILE MEMORY CELL - A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed. | 01-21-2010 |
20100013063 | THIN-FILM DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A method for manufacturing a thin-film device includes forming a separation layer on a substrate, forming a support layer of mainly clay containing silicate mineral having a layered crystal structure on the separation layer, forming a thin-film functional member on the support layer, applying an energy to the separation layer to reduce the adhesion between the substrate and the support layer, and removing the substrate from the support layer and the thin-film functional member. | 01-21-2010 |
20100109131 | REDUCED WAFER WARPAGE IN SEMICONDUCTORS BY STRESS ENGINEERING IN THE METALLIZATION SYSTEM - In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools. | 05-06-2010 |
20100155910 | METHOD FOR THE SELECTIVE ANTIREFLECTION COATING OF A SEMICONDUCTOR INTERFACE BY A PARTICULAR PROCESS IMPLEMENTATION - The invention refers to an efficient process for selectively rendering a semiconductor surface antireflective which is part of integrated circuits. The antireflective effect is based interference effects of a simple layer or a layer system. For example, an oxide layer and super-imposed silicon nitride layer form the system, wherein the silicon nitride layer is deposited in an earlier phase of the fabrication of the integrated circuit as a protective layer (“silicide block layer”) and also serves as an etch stop layer for the optical window. | 06-24-2010 |
20110062562 | DIELECTRIC LAYER STRUCTURE - A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile hydrophobic film. The ILD layer further includes a low-k dielectric layer, and the single tensile hydrophobic film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer. | 03-17-2011 |
20110095402 | Gate dielectric film with controlled structural and physical properties over a large surface area substrate | 04-28-2011 |
20110156223 | STRUCTURE AND METHOD TO CREATE STRESS TRENCH - An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed. | 06-30-2011 |
20110175208 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND ELECTRONIC APPLIANCE - An object of the present invention is to provide a semiconductor device including an insulating layer with a high dielectric strength voltage, a low dielectric constant, and low hygroscopicity. Another object of the present invention is to provide an electronic appliance with high performance and high reliability, which uses the semiconductor device. An insulator containing nitrogen, such as silicon oxynitride or silicon nitride oxide, and an insulator containing nitrogen and fluorine, such as silicon oxynitride added with fluorine or silicon nitride oxide added with fluorine, are alternately deposited so that an insulating layer is formed. By sandwiching an insulator containing nitrogen and fluorine between insulators containing nitrogen, the insulator containing nitrogen and fluorine can be prevented from absorbing moisture and thus a dielectric strength voltage can be increased. Further, an insulator contains fluorine so that a dielectric constant can be reduced. | 07-21-2011 |
20120104568 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and to provide a highly-reliable semiconductor device in the case of using a large-area substrate including an impurity element. A plurality of single crystal semiconductor substrates are concurrently processed to manufacture an SOI substrate, so that an area of a semiconductor device can be increased and a semiconductor device can be manufactured with improved efficiency. In specific, a series of processes is performed using a tray with which a plurality of semiconductor substrates can be concurrently processed. Here, the tray is provided with at least one depression for holding single crystal semiconductor substrates. Further, deterioration of characteristics of a manufactured semiconductor element is prevented by providing an insulating layer serving as a barrier layer against an impurity element which may affect characteristics of the semiconductor element. | 05-03-2012 |
20120153442 | SILICON NITRIDE FILM AND PROCESS FOR PRODUCTION THEREOF, COMPUTER-READABLE STORAGE MEDIUM, AND PLASMA CVD DEVICE - Provided is a process of forming a silicon nitride film having concentration of hydrogen atoms below or equal to 9.9×10 | 06-21-2012 |
20120280373 | ACTIVE ELECTRONICS ON STRENGTHENED GLASS WITH ALKALI BARRIER - Articles are described utilizing strengthened glass substrates, for example, ion-exchanged glass substrates, with oxide or nitride containing alkali barrier layers and with semiconductor devices which may be sensitive to alkali migration are described along with methods for making the articles. | 11-08-2012 |
20130009288 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer comprises metal interconnects therein; forming a top metal layer on the dielectric layer; and forming a passivation layer on the top metal layer through high-density plasma chemical vapor deposition (HDPCVD) process. | 01-10-2013 |
20130181331 | ATMOSPHERIC-PRESSURE PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION - Provided are silicon-containing films with a refractive index suitable for antireflection, articles having a surface comprising the films, and atmospheric-pressure plasma-enhanced chemical vapor deposition (AE-PECVD) processes for the formation of surface films and coatings. The processes generally include providing a substrate, providing a precursor comprising silicon, and reacting the precursor with a gas comprising nitrogen (N2) in a low-temperature plasma at atmospheric pressure, wherein the products of the reacting form a film on the substrate. An antireflection coating made by the process can have a refractive index of about 1.5 to about 2.2. Articles are provided having a surface that includes the antireflection coating. | 07-18-2013 |
20130341770 | RADIATION HARDENED SOI STRUCTURE AND METHOD OF MAKING SAME - An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact. | 12-26-2013 |
20140138802 | Method and Device for Manufacturing a Barrier Layer on a Flexible Substrate - The invention provides a method for manufacturing a barrier layer on a substrate, the method comprising: —providing a substrate with an inorganic oxide layer having a pore volume between 0.3 and 10 vol. %; —treating said substrate with an inorganic oxide layer in a glow discharge plasma, said plasma being generated by at least two electrodes in a treatment space formed between said two electrodes, said treatment space also being provided with a gas comprising Nitrogen compounds; and —the treating of the substrate in said treatment space is done at a temperature below 150° C., e.g. below 100° C. The invention further provides a device for manufacturing a barrier layer on a substrate. | 05-22-2014 |
20140145314 | SEMICONDUCTOR STRUCTURE WITH BERYLLIUM OXIDE - A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate ( | 05-29-2014 |
20140167229 | PROTECTING LAYER IN A SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a dielectric layer, a conduction piece, a first metal piece, a first protecting layer, and a second protecting layer. The conduction piece is surrounded by electrical materials of the dielectric layer. The first metal piece is over the dielectric layer and is in contact with the conduction piece. The first protecting layer covers dielectric materials of the dielectric layer that are not covered by the first metal piece. The second protecting layer is over the first protecting layer. | 06-19-2014 |
20140203415 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, DELAMINATION METHOD, AND TRANSFERRING METHOD - A substrate and a delamination film are separated by a physical means, or a mechanical means in a state where a metal film formed over a substrate, and a delamination layer comprising an oxide film including the metal and a film comprising silicon, which is formed over the metal film, are provided. Specifically, a TFT obtained by forming an oxide layer including the metal over a metal film; crystallizing the oxide layer by heat treatment; and performing delamination in a layer of the oxide layer or at both of the interface of the oxide layer is formed. | 07-24-2014 |
20140327117 | OPTICALLY TUNED HARDMASK FOR MULTI-PATTERNING APPLICATIONS - The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiO | 11-06-2014 |