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Multiple layers

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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257629000 - WITH MEANS TO CONTROL SURFACE EFFECTS

257632000 - Insulating coating

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257637000 Three or more insulating layers 30
257640000 At least one layer of silicon nitride 15
257642000 At least one layer of organic material 14
257639000 At least one layer of silicon oxynitride 4
20100006984SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate; a layered body formed on the substrate and including a multilayer interconnection structure, the layered body including multiple interlayer insulating films stacked in layers, the interlayer insulating films being lower in dielectric constant than a SiO01-14-2010
20110073998Adhesion Promotion Layer For A Semiconductor Device - Embodiments of semiconductor devices are provided. In one embodiment, the semiconductor device includes a substrate, an etch stop layer formed on the substrate, an adhesion promotion layer formed directly on the etch stop layer, and a dielectric layer formed directly on the adhesion promotion layer. The etch stop layer may include silicon, carbon, and nitrogen. The dielectric layer may include silicon, oxygen, and carbon. The adhesion promotion layer may include carbon, oxygen, and nitrogen. An example of an adhesion promotion layer includes polyimide.03-31-2011
20110254141PHYSICAL STRUCTURE FOR USE IN A PHYSICAL UNCLONABLE - The invention relates to a semiconductor device comprising a physical structure (10-20-2011
20100244207MULTIPLE THICKNESS AND/OR COMPOSITION HIGH-K GATE DIELECTRICS AND METHODS OF MAKING THEREOF - Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve forming a layer of high-K atoms over a conventional gate dielectric and heating the layer of high-K atoms to form a high-K gate dielectric layer. Methods of suppressing gate leakage current while mitigating mobility degradation are also described.09-30-2010
257636000 At least one layer of semi-insulating material 2
20090085174STRUCTURAL BODY AND MANUFACTURING METHOD THEREOF - The present invention includes a substrate structural body having a high electrostatic chuck force at a low voltage even when an insulated board is used, and a method for manufacturing the substrate structural body. As the substrate structural body, there is provided a substrate structural body for attaining its fixing by an electrostatic chuck mechanism, comprising at least a first polycrystalline silicon film formed on the back surface of a substrate comprised of an insulating material or its back and side surfaces, wherein a top layer of part of the back surface or the back and side surfaces is of a first silicon insulating film.04-02-2009
20090250793BPSG FILM DEPOSITION WITH UNDOPED CAPPING - Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 Å and about 350 Å. The cap layer may be formed using a low temperature CVD process that is controlled for density by adjusting the amount of silicon precursor in the gas-phase. In some embodiments, the cap layer is deposited on the BPSG layer followed immediately by the BPSG film deposition prior to any annealing of the BPSG layer. The cap layer may prevent dopant out-diffusion and/or out-gassing during storage and high-temperature annealing, and moisture penetration into the BPSG layer, as well as suppress defect nucleation on the as-deposited BPSG surface and defect formation during high temperature annealing, while still allowing flow ability of the BPSG layer. Other embodiments are also described.10-08-2009
257644000 At least one layer of glass 1
20120306059SELECTIVE WET ETCHING OF HAFNIUM ALUMINUM OXIDE FILMS - Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlO12-06-2012
257638000 With discontinuous or varying thickness layer (e.g., layer covers only selected portions of semiconductor) 1
20090140398HARD MASK PATTERNS OF A SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING THE SAME - In a method for forming hard mask patterns of a semiconductor device first hard mask patterns are formed on a semiconductor substrate. Second hard mask patterns are formed and include first patterns which are substantially perpendicular to the first hard mask patterns and second patterns which are positioned between the first hard mask patterns. Third hard mask patterns are formed between the first patterns.06-04-2009
Entries
DocumentTitleDate
20090294926DEEP TRENCH IN A SEMICONDUCTOR STRUCTURE - A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.12-03-2009
20100155908PASSIVATION STRUCTURE AND FABRICATING METHOD THEREOF - A passivation structure and fabricating method thereof includes providing a chip having a main die region and a scribe line region defined thereon and a plurality of metal pads respectively positioned in the main die region and the scribe line region, forming a first patterned passivation layer having a plurality of first openings and second openings respectively exposing the metal pads in the main die region and the scribe line region on the chip, and forming a second patterned passivation layer filling the first openings in the scribe line region and having a plurality of third openings corresponding to the first openings thus exposing the metal pads in the main die region.06-24-2010
20110186970METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises: etching a semiconductor substrate to form a plurality of pillars; depositing a first protective film on the sidewalls of the pillar; first etching the semiconductor substrate with the pillar deposited with the first protective film as a mask; forming a first insulating film on the sidewalls of the pillar and the first etched semiconductor substrate; second etching the semiconductor substrate with the pillar including the first insulating film as a mask; forming a second protective film and a second insulating film on the surface of the second etched semiconductor substrate; depositing a barrier film on the sidewalls of the pillar including the second insulating film; and removing the first insulating film, the second insulating film and the barrier film disposed at one sidewall of the pillar to form a contact hole defined by the first protective film and the second protective film.08-04-2011
20130037921RESIST UNDERLAYER COMPOSITION AND PROCESS OF PRODUCING INTEGRATED CIRCUIT DEVICES USING SAME - A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product of hydrolyzed products produced from a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, and a compound represented by Chemical Formula 3.02-14-2013
20130026610LITHOGRAPHY METHOD AND DEVICE - Lithography methods and devices are shown that include a semiconductor structure such as a mask. Methods and devices are shown that include a pattern of mask features and a composite feature. Selected mask features include doubled mask features. Methods and devices shown may provide varied feature sizes (including sub-resolution) with a small number of processing steps.01-31-2013
20090001525HIGH-K DUAL DIELECTRIC STACK - The present invention discloses a method including: providing a Group III-V component semiconductor material; forming a first layer over a surface of the Group III-V component semiconductor material, the first layer to unpin a Fermi level at the surface; forming a second layer over the first layer, the second layer for scaling an equivalent oxide thickness (EOT); and annealing the first layer before or after forming the second layer to remove bulk trap defects in the first layer.01-01-2009
20120217623INTER-LEVEL DIELECTRIC LAYER, SEMICONDUCTOR DEVICE HAVING SAID INTER-LEVEL DIELECTRIC LAYER AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses an inter-level dielectric layer for a semiconductor device, a method for manufacturing the same and a semiconductor device having said inter-level dielectric layer. The method lies in forming non-interconnected holes within a dielectric layer, and these holes may be filled with porous low-k dielectric material with a much lower dielectric constant, or forming holes within the dielectric layer by filling the upper parts of the holes. The inter-level dielectric layer in such a structure has a much lower dielectric constant, reduces RC delay between devices of integrated circuits and also is easy to integrate; besides, since the holes within the dielectric layer are non-interconnected, they shall not cause change to the dielectric constant of the dielectric material or a short circuit between wires, thus the device shall have better stability and reliability which thence improve performance of the circuit.08-30-2012
20130161798GRADED DENSITY LAYER FOR FORMATION OF INTERCONNECT STRUCTURES - Methods and structure are provided for utilizing a dielectric mask layer having a gradated density structure. The density of the dielectric mask layer is greatest at the interface of the dielectric mask layer and an underlying dielectric layer. The density of the dielectric mask layer is lowest at the interface of the dielectric mask layer and an overlaying hard mask. The lower density dielectric mask layer is more susceptible to removal than the higher density dielectric mask layer. The lower density dielectric mask layer is removed during at least one of an RIE etch or a post-RIE etch wet clean. Selective removal of the lower density dielectric mask layer creates a dielectric mask layer having a rounded profile. The dielectric mask layer comprises tetraethyl orthosilicate.06-27-2013
20100164074Dielectric separator layer - The present invention describes a method including: providing a substrate; stacking interlevel dielectric layers over said substrate, and separating said interlevel dielectric layers with a dielectric separator layer.07-01-2010
20090085173SIDEWALL PROTECTION LAYER - The present disclosure generally relates to forming a metallization layer in a semiconductor device. In particular, this disclosure concerns the damascene inlay technique in low-k dielectric layers. Etching trenches and vias in low-k dielectric materials leads to uneven and porous sidewalls of the trenches and vias due to the porous nature of the low-k dielectric materials. Thus, smooth and dense sidewalls cannot be achieved, which is a prerequisite for an effective barrier layer, which prevents copper from being diffused into the low-k dielectric material. As a consequence, process tolerances are high and the reliability of the semiconductor device is reduced. The present disclosure overcomes these drawbacks by a surface treatment of the sidewalls of trenches and vias in order to densify the surface such that the following barrier layer may more effectively prevent copper from diffusing into the low-k or ultra high-k dielectric material.04-02-2009
20110284996SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a substrate, and a plurality of interconnects provided in the same interconnect layer above the substrate. The device further includes a plurality of insulators provided so as to be buried between the plurality of interconnects. Moreover, the plurality of interconnects include an interconnect group in which 211-24-2011
20120098107SYSTEMS AND METHODS FOR THIN-FILM DEPOSITION OF METAL OXIDES USING EXCITED NITROGEN-OXYGEN SPECIES - The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).04-26-2012
20090267198SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR - The present invention provides a multilayer wiring technology by which high adhesiveness and high insulation reliability between wirings are obtained, while maintaining effective low capacitance between wirings. A semiconductor device is characterized in that a first insulating film is an insulating film formed of at least one layer which contains a siloxane structure containing silicon, oxygen and carbon; the siloxane structure in the inner part of the first insulating film contains a larger number of carbon atoms than the number of silicon atoms; and a modified layer which containing a smaller number of carbon atoms and a larger number of oxygen atoms per unit volume than the inner part of the first insulating film is formed on at least one of an interface between the first insulating film and the metal and an interface between the first insulating film and a second insulating film.10-29-2009
20100078773Semiconductor device and method of forming semiconductor device - A semiconductor device includes a substrate, a semiconductor device structure over the substrate, an insulating film that covers the semiconductor device structure, and a stress-compensation film over the insulating film. The stress-compensation film has a first stress that compensates a second stress working to bend the substrate.04-01-2010
20090206454SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type.08-20-2009
20090091003INSULATOR UNDERGOING ABRUPT METAL-INSULATOR TRANSITION, METHOD OF MANUFACTURING THE INSULATOR, AND DEVICE USING THE INSULATOR - Provided are an insulator that has an energy band gap of 2 eV or more and undergoes an abrupt MIT without undergoing a structural change, a method of manufacturing the insulator, and a device using the insulator. The insulator is abruptly transitioned from an insulator phase into a metal phase by an energy change between electrons without undergoing a structural change.04-09-2009
20090294924HAFNIUM LANTHANIDE OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film.12-03-2009
20090294923Structure and Method for Reducing Threshold Voltage Variation - A structure comprises at least one transistor on a substrate, an insulator layer over the transistor, and an ion stopping layer over the insulator layer. The ion stopping layer comprises a portion of the insulator layer that is damaged and has either argon ion damage or nitrogen ion damage.12-03-2009
20110204492Microelectronic structure including a low K dielectric and a method of controlling carbon distribution in the structure - Embodiments of the present invention pertain to the formation of microelectronic structures. Low k dielectric materials need to exhibit a dielectric constant of less than about 2.6 for the next technology node of 32 nm. The present invention enables the formation of semiconductor devices which make use of such low k dielectric materials while providing an improved flexural and shear strength integrity of the microelectronic structure as a whole.08-25-2011
20090166813METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer on the first semiconductor layer, etching the second semiconductor layer and the first semiconductor layer to form a first groove passing through the second semiconductor layer and the first semiconductor layer, forming a first support having tensile stress in the first groove, etching the second semiconductor layer to form a second groove that exposes the first semiconductor layer, forming a cavity between the second semiconductor layer and the semiconductor substrate by etching the first semiconductor layer through the second groove, forming an insulating film in the cavity, and forming a buried film having tensile stress in the second groove.07-02-2009
20080296740Method of manufacturing semiconductor device, and semiconductor device - A method for manufacturing a semiconductor device is provided that can reduce warping of manufactured products after the formation of a final protective film. The method includes, in a semiconductor device having a semiconductor substrate provided with wiring and a final protective film formed on the wiring, forming a first protective film on the wiring, forming a second protective film having tensile stress on the first protective film, and removing the first protective film and the second protective film from contact regions of the wiring.12-04-2008
20120292748METHODS AND STRUCTURES FOR FORMING INTEGRATED SEMICONDUCTOR STRUCTURES - The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.11-22-2012
20100140756APPARATUS FOR MANUFACTURING SILICON OXIDE THIN FILM AND METHOD FOR FORMING THE SILICON OXIDE THIN FILM - An object of the present invention is to provide a semiconductor thin film device which employs a silicon oxide thin film having an equivalent level of high insulating performance to those currently used in electronic devices, through a low-temperature printing process on a plastic substrate having plasticity or other types of substrates at a temperature equal to or lower than the heat resistant temperature of the substrate, and to provide a method for forming the device. The semiconductor thin film device is formed as follows: a coating film of a silicon compound including a silazane structure or a siloxane structure is formed on a plastic substrate having plasticity; the coating film is converted into a silicon oxide thin film; and the thin film is utilized as part of an insulating layer or a sealing layer.06-10-2010
20090127671METHOD FOR FORMING A GATE INSULATING LAYER OF A SEMICONDUCTOR DEVICE - Embodiments relate to a method for forming a gate insulating layer, which may include forming a device isolation layer being divided into a device active region and a device isolation region, growing a first oxide layer at an entire surface of the semiconductor substrate as a gate insulating layer, performing a first annealing process to form a diffusion barrier layer an interface between the first oxide layer and the device active region, etching and removing a first oxide layer and a diffusion barrier layer of the core power source wiring region by masking the input/output power source wiring region, growing a second oxide layer on the core power source wiring region, and performing a second annealing process to form an NO gate oxide layer on which an N-rich oxide layer at an interface of the core power source wiring region.05-21-2009
20090032910DIELECTRIC STACK CONTAINING LANTHANUM AND HAFNIUM - Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices.02-05-2009
20120104567IIIOxNy ON REO/Si - An insulative layer on a semiconductor substrate and a method of fabricating the structure includes the steps of depositing a single crystal layer of rare earth oxide on a semiconductor substrate to provide electrical insulation and thermal management. The rare earth oxide is crystal lattice matched to the substrate. A layer of single crystal IIIO05-03-2012
20090102026SEMICONDUCTOR-ON-INSULATOR SUBSTRATE WITH A DIFFUSION BARRIER - A diffusion barrier layer is incorporated between a top semiconductor layer and buried oxide layer. The diffusion barrier layer blocks diffusion of dopants into or out of buried oxide layer. The diffusion barrier layer may comprise a dielectric material such as silicon oxynitride or a high-k gate dielectric material. Alternately, the diffusion barrier layer may comprise a semiconductor material such as SiC. Such materials provide less charge trapping than a silicon nitride layer, which causes a high level of interface trap density and charge in the buried oxide layer. Thus, diffusion of dopants from and into semiconductor devices through the buried oxide layer is suppressed by the diffusion barrier layer without inducing a high interface trap density or charge in the buried oxide layer.04-23-2009
20090001526TECHNIQUE FOR FORMING AN INTERLAYER DIELECTRIC MATERIAL OF INCREASED RELIABILITY ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES - By removing excess material of an interlayer dielectric material deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material, such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition.01-01-2009
20090243049DOUBLE DEPOSITION OF A STRESS-INDUCING LAYER IN AN INTERLAYER DIELECTRIC WITH INTERMEDIATE STRESS RELAXATION IN A SEMICONDUCTOR DEVICE - Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process.10-01-2009
20090140396STRESSED INTERLAYER DIELECTRIC WITH REDUCED PROBABILITY FOR VOID GENERATION IN A SEMICONDUCTOR DEVICE BY USING AN INTERMEDIATE ETCH CONTROL LAYER OF INCREASED THICKNESS - By forming an etch control material with increased thickness on a first stressed dielectric layer in a dual stress liner approach, the surface topography may be smoothed prior to the deposition of the second stressed dielectric material, thereby allowing the deposition of an increased amount of stressed material while not contributing to yield loss caused by deposition-related defects.06-04-2009
20100181655ESTABLISHING A UNIFORMLY THIN DIELECTRIC LAYER ON GRAPHENE IN A SEMICONDUCTOR DEVICE WITHOUT AFFECTING THE PROPERTIES OF GRAPHENE - A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.07-22-2010
20090294925MECHANICALLY ROBUST METAL/LOW-k INTERCONNECTS - A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.12-03-2009
20100176496MATERIAL FOR FORMING EXPOSURE LIGHT-BLOCKING FILM, MULTILAYER INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE - To provide a material for forming an exposure light-blocking film which includes at least one of a silicon compound expressed by the following structural formula (1) and a silicon compound expressed by the following structural formula (2), wherein at least one of R07-15-2010
20100193919METHOD OF FORMING OPENINGS IN A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, forming a main mask over the dielectric layer, the main mask comprising a plurality of main mask openings arranged in a regular pattern extending over the dielectric layer, using a selector mask to select some of the plurality of main mask openings and removing portions of the dielectric layer through the selected some of the plurality of main mask openings to provide openings extending through the dielectric layer to the layer.08-05-2010
20080211065Semiconductor devices and methods of manufacture thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of fabricating a material layer of a semiconductor device includes providing a workpiece, and forming a ZrO09-04-2008
20100176495LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS - A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive layer formed on the lower insulating layer; an upper insulating layer formed on the electrically conductive layer, the upper insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; and a semiconductor layer formed on the upper insulating layer.07-15-2010
20080296739Method of forming a thin film structure and stack structure comprising the thin film - Provided is a method of forming a thin film structure and a stack structure comprising the thin film. The method may include forming a crystalline Al12-04-2008
20090051014Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby - A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.02-26-2009
20110121436METHOD FOR FORMING DUAL HIGH-K METAL GATE USING PHOTORESIST MASK AND STRUCTURES THEREOF - Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N05-26-2011
20090032909SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS - Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.02-05-2009
20120032311MULTI COMPONENT DIELECTRIC LAYER - An in-situ process is described incorporating plasma enhanced chemical vapor deposition comprising flowing at least one of a Si, Si+C, B, Si+B, Si+B+C, and B+C containing precursor, and a N containing precursors at first times and removing the N precursor at second times and starting the flow of an oxidant gas and a porogen gas into the chamber. A dielectric layer is described comprising a network having inorganic random three dimensional covalent bonding throughout the network which contains at least one SiCN, SiCNH, SiN, SiNH, BN, BNH, CBN, CBNH, BSiN, BSiNH, SiCBN and SiCBNH as a first component and a low k dielectric as a second component adjacent thereto.02-09-2012
20100244206METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS - A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.09-30-2010
20110133313HARDMASK MATERIALS - Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si06-09-2011
20100117204FILM FORMING METHOD FOR A SEMICONDUCTOR - The present invention may be a semiconductor device including of a fluorinated insulating film and a SiCN film deposited on the fluorinated insulating film directly, wherein a density of nitrogen in the SiCN film decreases from interface between the fluorinated insulating film and the SiCN film. In the present invention, the SiCN film that is highly fluorine-resistant near the interface with the CFx film and has a low dielectric constant as a whole can be formed as a hard mask.05-13-2010
20100019358SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device and method is provided that has an oxygen diffusion barrier layer between a high-k dielectric and BOX. The method includes depositing a diffusion barrier layer on a BOX layer and gate structure and etching a portion of the diffusion barrier layer from sidewalls of the gate structure. The method further includes depositing a high-k dielectric on the diffusion barrier layer and the gate structure.01-28-2010
20120306058METHOD FOR BLISTER-FREE PASSIVATION OF A SILICON SURFACE - A method of forming a surface passivation layer on a surface of a crystalline silicon substrate is disclosed. In one aspect, the method includes depositing an Al12-06-2012
20120146195OVERLAY VERNIER MASK PATTERN, FORMATION METHOD THEREOF, SEMICONDUCTOR DEVICE INCLUDING OVERLAY VERNIER PATTERN, AND FORMATION METHOD THEREOF - An overlay vernier mask pattern of a semiconductor device includes a first overlay vernier mask pattern having a first opening for exposing a first area of a layer to be etched on a substrate and a second opening for exposing a second area spaced apart from the first area, and a second overlay vernier mask pattern aligned on the first overlay vernier mask pattern and the layer to be etched, and having an opening for exposing the second opening while exposing a portion of the layer to be etched in the first area.06-14-2012
20100019357SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVB) semiconductor board and a first oxide layer. The first oxide layer is composed of MO01-28-2010
20110062560BPSG FILM DEPOSITION WITH UNDOPED CAPPING - Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 Å and about 350 Å. The cap layer may be formed using a low temperature CVD process that is controlled for density by adjusting the amount of silicon precursor in the gas-phase. In some embodiments, the cap layer is deposited on the BPSG layer followed immediately by the BPSG film deposition prior to any annealing of the BPSG layer. The cap layer may prevent dopant out-diffusion and/or out-gassing during storage and high-temperature annealing, and moisture penetration into the BPSG layer, as well as suppress defect nucleation on the as-deposited BPSG surface and defect formation during high temperature annealing, while still allowing flow ability of the BPSG layer. Other embodiments are also described.03-17-2011
20110042790MULTIPLE PATTERNING USING IMPROVED PATTERNABLE LOW-k DIELECTRIC MATERIALS - A method of double patterning a semiconductor structure with a single material which after patterning becomes a permanent part of the semiconductor structure. More specifically, a method to form a patterned semiconductor structure with small features is provided which are difficult to obtain using conventional exposure lithographic processes. The method of the present invention includes the use of patternable low-k materials which after patterning remain as a low-k dielectric material within the semiconductor structure. The method is useful in forming semiconductor interconnect structures in which the patternable low-k materials after patterning and curing become a permanent element, e.g., a patterned interlayer low-k material, of the interconnect structure.02-24-2011
20120061807PITCH MULTIPLIED MASK PATTERNS FOR ISOLATED FEATURES - Crisscrossing spacers formed by pitch multiplication are used to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with conductive material to form conductive contacts.03-15-2012
20090134499ATOMIC LAYER DEPOSITION OF Hf3N4/HfO2 FILMS AS GATE DIELECTRICS - The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf05-28-2009
20120161296MULTIPLE PATTERNING USING IMPROVED PATTERNABLE LOW-k DIELECTRIC MATERIALS - A double patterned semiconductor structure is provided. The structure includes a first patterned and cured low-k structure located on a first portion of an antireflective coating, and a second patterned and cured low-k structure located on a second portion of the antireflective coating, wherein the second patterned and cured low-k structure is spaced apart from the first patterned and cured low-k dielectric structure.06-28-2012
20120168915RELIABLE INTERCONNECT INTEGRATION SCHEME - Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values.07-05-2012
20110186971METHOD OF MAKING DENSE, CONFORMAL, ULTRA-THIN CAP LAYERS FOR NANOPOROUS LOW-K ILD BY PLASMA ASSISTED ATOMIC LAYER DEPOSITION - Barrier layers and methods for forming barrier layers on a porous layer are provided. The methods can include chemically adsorbing a plurality of first molecules on a surface of the porous layer in a chamber and forming a first layer of the first molecules on the surface of the porous layer. A plasma can then be used to react a plurality of second molecules with the first layer of first molecules to form a first layer of a barrier layer. The barrier layers can seal the pores of the porous material, function as a diffusion barrier, be conformal, and/or have a negligible impact on the overall ILD k value of the porous material.08-04-2011
20120074536Methods of Manufacturing Semiconductor Devices and Structures Thereof - Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material layer over the etch stop layer. The material layer includes a transition layer. The method includes patterning the material layer partially with a first pattern, and patterning the material layer partially with a second pattern. Patterning the material layer partially with the second pattern further comprises simultaneously completely patterning the material layer with the first pattern.03-29-2012
20120267766RESIST UNDERLAYER COMPOSITION AND PROCESS OF PRODUCING INTEGRATED CIRCUIT DEVICES USING THE SAME - A resist underlayer composition includes a solvent and an organosilane condensation polymerization product, the organosilane condensation polymerization product including about 40 to about 80 mol % of a structural unit represented by the following Chemical Formula 1,10-25-2012
20120080779ULTRA HIGH SELECTIVITY DOPED AMORPHOUS CARBON STRIPPABLE HARDMASK DEVELOPMENT AND INTEGRATION - Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron containing amorphous carbon layer on a semiconductor substrate. In one embodiment, a method of processing a substrate in a processing chamber is provided. The method comprises providing a substrate in a processing volume, flowing a hydrocarbon containing gas mixture into the processing volume, generating a plasma of the hydrocarbon containing gas mixture by applying power from an RF source, flowing a boron containing gas mixture into the processing volume, and depositing a boron containing amorphous carbon film on the substrate in the presence of the plasma, wherein the boron containing amorphous carbon film contains from about 30 to about 60 atomic percentage of boron.04-05-2012
20120280372Method for Reducing Thickness of Interfacial Layer, Method for Forming High Dielectric Constant Gate Insulating Film, High Dielectric Constant Gate Insulating Film, High Dielectric Constant Gate Oxide Film, and Transistor Having High Dielectric Constant Gate Oxide Film - To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconducdor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.11-08-2012
20110304030SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: an insulating layer formed on a substrate; a plurality of interlayer insulating films which are formed on the insulating layer and comprise an opening window; a multilayer wiring which is formed with a plurality of wiring layers and a plurality of vias formed in the plurality of interlayer insulating films; a metal pad connected with the multilayer wiring, an upper surface part of the metal pad being a bottom part of the opening window, the metal pad formed closer to the substrate than a wiring layer of a lowermost layer of the plurality of wiring layers and is; and a pad ring provided on the metal pad, the pad ring penetrating the plurality of interlayer insulating films and the pad ring surrounding the opening window.12-15-2011
20080217747INTRODUCTION OF METAL IMPURITY TO CHANGE WORKFUNCTION OF CONDUCTIVE ELECTRODES - Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.09-11-2008
20130134563Electrical Connection Structure - A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer.05-30-2013
20130127023METHOD FOR PRODUCING A GRAPHENE SHEET ON A PLATINUM SILICIDE, STRUCTURES OBTAINED USING SAID METHOD AND USES THEREOF - The invention relates to a method for producing a graphene sheet on a platinum silicide, wherein the platinum silicide is in the form of a layer or a plurality of pins.05-23-2013
20130147021MULTI-LAYER SUBSTRATE STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A method for manufacturing a multi-layer substrate structure such as a CSOI wafer structure (cavity-SOI, silicon-on-insulator) comprising obtaining a first and second wafer, such as two silicon wafers, wherein at least one of the wafers may be optionally provided with a material layer such as an oxide layer (06-13-2013
20100314725Stress Balance Layer on Semiconductor Wafer Backside - A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.12-16-2010

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