| Entries |
| Document | Title | Date |
|---|
| 20090236699 | DISCREET PLACEMENT OF RADIATION SOURCES ON INTEGRATED CIRCUIT DEVICES - An integrated circuit and methods of forming and using the integrated circuit. The circuit includes: a radiation-emitting layer over a selected region of a top surface of an integrated circuit chip, the radiation emitting layer comprising a first polymer or resin and a first radioactive material, the region smaller than a whole of the top surface of the integrated circuit chip, the region including a circuit that is liable to temporary failure when struck by radiation generated by the first radioactive material. | 09-24-2009 |
| 20090008750 | SEAL RING FOR SEMICONDUCTOR DEVICE - A semiconductor device having a seal ring structure with high stress resistance is provided. The semiconductor device is provided with a semiconductor layer including a plurality of semiconductor elements, an insulating film formed on the semiconductor layer, and a body that passes through the insulating film and surrounds the semiconductor elements as a whole. The body includes a plurality of walls that are spaced apart from each other in a circumferential direction and are arranged in parallel with one another, and a plurality of bridges, each of which intersects at least one of the plurality of walls. | 01-08-2009 |
| 20090152685 | EPITAXIAL WAFER AND METHOD OF PRODUCING THE SAME - An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices. | 06-18-2009 |
| 20080237810 | Controlling substrate surface properties via colloidal coatings - Methods and apparatus to control surface properties via colloidal coatings are described. In one embodiment, colloidal coating may be used on a surface to enhance flow control. Other embodiments are also described. | 10-02-2008 |
| 20090267197 | SEMICONDUCTOR DEVICE FOR PREVENTING THE LEANING OF STORAGE NODES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device for preventing the leaning of storage nodes and a method of manufacturing the same is described. The semiconductor device includes support patterns that are formed to support a plurality of cylinder type storage nodes. The support patterns are formed of a BN layer and have a hexagonal structure. The BN layer forming the support patterns has compressive stress as opposed to tensile stress and can therefore withstand cracking in the support patterns. | 10-29-2009 |
| 20100090320 | STRUCTURE AND METHOD FOR DEVICE-SPECIFIC FILL FOR IMPROVED ANNEAL UNIFORMITY - Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 04-15-2010 |
| 20110198736 | REACTIVE SITE DEACTIVATION AGAINST VAPOR DEPOSITION - Methods and structures relating to the formation of mixed SAMs for preventing undesirable growth or nucleation on exposed surfaces inside a reactor are described. A mixed SAM can be formed on surfaces for which nucleation is not desired by introducing a first SAM precursor having molecules of a first length and a second SAM precursor having molecules of a second length shorter than the first. Examples of exposed surfaces for which a mixed SAM can be provided over include reactor surfaces and select surfaces of integrated circuit structures, such as insulator and dielectric layers. | 08-18-2011 |
| 20090294918 | SEMICONDUCTOR WAFER - In a state where a semiconductor wafer is not acted upon by its own weight, a shear stress on a rear surface side portion of the semiconductor wafer is higher than that on a front surface side portion of the semiconductor wafer, in a compression direction. Thereby, sag of the semiconductor wafer is reduced when the semiconductor wafer is simple-supported in a horizontal state. | 12-03-2009 |
| 20110204489 | SILICON SUBSTRATE HAVING NANOSTRUCTURES AND METHOD FOR PRODUCING THE SAME AND APPLICATION THEREOF - A method for forming a silicon substrate having a multiple silicon nanostructures includes the steps of: providing a silicon substrate; forming an oxidization layer on the silicon substrate; immersing the silicon substrate in a fluoride solution including metal ions, thereby depositing a plurality of metal nanostructures on the silicon substrate; and immersing the silicon substrate in an etching solution to etch the silicon under the metal nanostructures, the unetched silicon forming the silicon nano structures. | 08-25-2011 |
| 20080290471 | Method For Making a Thin-Film Structure and Resulting Thin-Film Structure - A method for making a thin-film structure includes a thin film stabilized on a substrate. The structure of the thin film is defined by a material which includes at least one first chemical species. The method includes a step of inputting particles of the first chemical species into the thin film so as to compensate for the flow of vacancies from the surface of the film. | 11-27-2008 |
| 20110006405 | SEMICONDUCTOR DEVICE, MANUFACTURE METHOD OF SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS - A semiconductor device includes a substrate, an electronic component and a resin member. The substrate has a first electrode. The electronic component is provided on the substrate, and has a second electrode electrically connected to the first electrode. The resin member alleviates an external stress to the second electrode of the electronic component. The resin member is disposed on the substrate at a region separated from the electronic component. | 01-13-2011 |
| 20090051013 | SEMICONDUCTOR WAFER FOR SEMICONDUCTOR COMPONENTS AND PRODUCTION METHOD - A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter zone for gettering impurity atoms in the semiconductor wafer. The getter zone contains oxygen precipitates. In the near-surface active zone, atoms of doping material are located on lattice vacancies. The atoms of doping material have a higher diffusion coefficient that the oxygen atoms. | 02-26-2009 |
| 20090102024 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAME - A semiconductor device has an IC chip with a thickness of equal to or less than 100 μm and includes a semiconductor substrate. A device forming region is within the depth of approximately equal to or less than 5 μm from a surface of the semiconductor substrate, and a total thickness of the semiconductor substrate is from 5 μm to 100 μm. A BMD layer for carrying out gettering of metal impurities is provided immediately under the device forming region. Since a gettering site is provided immediately under the device forming region, in a device or the like of which extreme thinness is required, degradation of device characteristics and reliability due to contamination of metal impurities can be prevented, and stabilize and improve the device yield. The present invention inhibits degradation of device characteristics and reliability caused by contamination of metal impurities, in a device of which lamination of device chips is required or in a device of which extreme chip thinness for an IC card and the like is required, in an attempt to cope with an enlarged capacity of the device. | 04-23-2009 |
| 20100148321 | Micro-Electro-Mechanical-System Device with Particles Blocking Function and Method for Making Same - The present invention discloses a MEMS device with particles blocking function, and a method for making the MEMS device. The MEMS device comprises: a substrate on which is formed a MEMS device region; and a particles blocking layer deposited on the substrate. | 06-17-2010 |
| 20090085170 | INTERFACIAL ROUGHNESS REDUCING FILM, WIRING LAYER, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An interfacial roughness reducing film which is in contact, on one side thereof, with an insulating film and in contact, on a side opposite from the one side, with wiring comprises a Si—O bond, and is formed using a composition containing a silicon compound that comprises at least one bond of Si—N bonds and Si—Cl bonds wherein the number of Si—N bonds and Si—Cl bonds combined per molecule of the compound is at least two. An interfacial roughness between the interfacial roughness reducing film and the wiring is smaller than that between the interfacial roughness reducing film and the insulating film. | 04-02-2009 |
| 20100181653 | METHOD FOR RECYCLING A SUBSTRATE, LAMINATED WATER FABRICATING METHOD AND SUITABLE RECYCLED DONOR SUBSTRATE - The invention relates to a method for recycling a substrate with a step-like residue in a first region of its surface, in particular along the edge of the substrate, which protrudes with respect to the surface of a remaining second region of the substrate, and wherein the first region comprises a modified zone, in particular an ion implanted zone, essentially in a plane corresponding to the plane of the surface of the remaining second region of the substrate and/or chamfered towards the edge of the substrate. To prevent the negative impact of contaminants in subsequent laminated wafer fabricating processes, the recycling method comprises a material removal step which is carried out such that the surface of the substrate in the first region is lying lower than the level of the modified zone before the material removal. The invention also relates to a laminated wafer fabricating method using the recycled substrate and to a recycled substrate in which the surface of a first region lies lower than the surface of the second region. | 07-22-2010 |
| 20100181652 | SYSTEMS AND METHODS FOR STICTION REDUCTION IN MEMS DEVICES - Systems and methods for reducing stiction between elements of a microelectromechanical systems (MEMS) device during anodic bonding. The MEMS device includes a substrate cover with an optional conductor on its interior surface and the cover is anchored to a first portion of a sensing element. The MEMS device further includes a second portion of the sensing element separated from the substrate cover with a space and an antistiction element disposed between the second portion and cover. The antistiction element can be formed of a material type with high electrostatic resistance, to prevent stiction between MEMS device elements during anodic bonding. | 07-22-2010 |
| 20100276788 | METHOD AND DEVICE OF PREVENTING DELAMINATION OF SEMICONDUCTOR LAYERS - Embodiments of the present invention describe a method and device of preventing delamination of semiconductor layers in a semiconductor device. The semiconductor device comprises a substrate with an interlayer dielectric (ILD). A protection layer is deposited on the ILD. Next, a getter layer is formed on the protection layer to remove any native oxides on the protection layer. A capping layer is then deposited on the getter layer to prevent oxidation of the getter layer. Next, a semiconductor layer is formed on the capping layer. An oxide layer is then deposited on the semiconductor layer. Subsequently, a buffered oxide etch solution is used to remove the oxide layer. By removing the native oxides on the protection layer, the getter layer prevents the reaction between the buffered oxide etch solution and the native oxides which may cause delamination of the semiconductor layer and protection layer. | 11-04-2010 |
| 20120193765 | EMISSIVITY PROFILE CONTROL FOR THERMAL UNIFORMITY - A substrate for processing in a heating system is disclosed. The substrate includes a bottom portion for absorbing heat from a radiating heat source, the bottom portion having a first region having a first emissivity and a second region having a second emissivity less than the first emissivity. The first region and the second region promote thermal uniformity of the substrate by compensating for thermal non-uniformity of the radiating heat source. | 08-02-2012 |
| 20100252917 | CARBOSILANE POLYMER COMPOSITIONS FOR ANTI-REFLECTIVE COATINGS - A silicon polymer material, which has a silicon polymer backbone with chromophore groups attached directly to at least a part of the silicon atoms, the polymer further exhibiting carbosilane bonds. The film forming composition and resulting coating properties can be tailored to suit the specific exposure wavelength and device fabrication and design requirements. By using two different chromophores the refractive index and the absorption co-efficient can be efficiently tuned. By varying the proportion of carbosilane bonds, and a desired Si-content of the anti-reflective coating composition can be obtained. | 10-07-2010 |
| 20090108412 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE - A semiconductor substrate includes: a silicon support substrate with a first crystal orientation; a silicon functional substrate which is formed on the silicon support substrate and which has a first crystalline region with a crystal orientation different from the first crystal orientation of the silicon support substrate and a second crystalline region with a crystal orientation equal to the first crystal orientation of the silicon support substrate; and a defect creation-preventing region formed at an interface between the first crystalline region and the second crystalline region of the silicon functional substrate so as to be at least elongated to a main surface of the silicon support substrate. | 04-30-2009 |
| 20090065908 | METHODS OF FABRICATING A MICROMECHANICAL STRUCTURE - Methods of fabricating a microelectromechanical structure are provided. An exemplary embodiment of a method of fabricating a microelectromechanical structure comprises providing a substrate. A first patterned sacrificial layer is formed on portions of the substrate, the first patterned sacrificial layer comprises a bulk portion and a protrusion portion. A second patterned sacrificial layer is formed over the first sacrificial layer, covering the protrusion portion and portions of the bulk portion of the first patterned sacrificial layer, wherein the second patterned sacrificial layer does not cover sidewalls of the first patterned sacrificial layer. An element layer is formed over the substrate, covering portions of the substrate, the first patterned sacrificial layer and second patterned sacrificial layer. The first and second patterned sacrificial layers are removed, leaving a microstructure on the substrate. | 03-12-2009 |
| 20110084366 | Epitaxial Wafer and Production Method Thereof - The epitaxial layer defects generated from voids of a silicon substrate wafer containing added hydrogen are suppressed by a method for producing an epitaxial wafer by: | 04-14-2011 |
| 20110241182 | DIE SEAL RING - An improved die seal ring is described which includes at least one break. In the region of the break in the die seal ring, the doping is modified so that the impedance of the electrical path across the break through the substrate is increased. Offsets in the break may also be used and the offset may be within a break in a track and/or between breaks in different tracks, where the die seal ring includes more than one track. | 10-06-2011 |
| 20090218661 | SILICON SUBSTRATE AND MANUFACTURING METHOD THEREOF - A silicon substrate is manufactured from single-crystal silicon which is grown to have a carbon concentration equal to or higher than 1.0×10 | 09-03-2009 |
| 20100237475 | NEUTRALIZATION OF TRAPPED CHARGE IN A CHARGE ACCUMULATION LAYER OF A SEMICONDUCTOR STRUCTURE - A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P-N junction diode. The P-N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage. | 09-23-2010 |
| 20120199956 | METHOD FOR RECYCLING A SOURCE SUBSTRATE - The present invention relates to process for recycling a source substrate that has a surface region and regions in relief on the surface region, with the regions in relief corresponding to residual regions of a layer of the source substrate that were not being separated from the rest of the source substrate during a prior removal step. The process includes selective electromagnetic irradiation of the source substrate at a wavelength such that the damaged material of the surface region absorbs the electromagnetic irradiation. The present invention also relates to a recycled source substrate and to a process for transferring a layer from a source substrate recycled for this purpose. | 08-09-2012 |
| 20120199955 | PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF - A manufacturing method of a package carrier is provided. A first opening communicating an upper surface and a lower surface of a substrate is formed. A heat-conducting element having a top surface and a bottom surface is configured in the first opening and fixed into the first opening via an insulation material. A first insulation layer and a first metal layer are laminated onto the upper surface. A second insulation layer and a second metal layer are laminated onto the lower surface. A second opening and a third opening respectively exposing portions of the top and the bottom surfaces are formed. At least one through via passing through the first metal layer, the first insulation layer, the substrate, the second insulation layer and the second metal layer is formed. A third metal layer covering the first and second metal layers and an inner wall of the through via is formed. | 08-09-2012 |
| 20110049682 | SYSTEM AND METHOD FOR SUBSTRATE WAFER BACK SIDE AND EDGE CROSS SECTION SEALS - Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column. | 03-03-2011 |
| 20100244203 | SEMICONDUCTOR STRUCTURE HAVING A PROTECTIVE LAYER - A semiconductor structure includes a substrate having a first nitride-based semiconductor layer. A pseudomorphic protective layer is formed on the first nitride-based semiconductor layer and a second nitride-based semiconductor layer is formed on the pseudomorphic protective layer. The pseudomorphic protective layer has a thickness that is less than a critical thickness so that it drives the material quality of the second nitride-based semiconductor layer to correspond with that of the first nitride-based semiconductor layer. | 09-30-2010 |
| 20080272467 | Method for Forming Fine Pattern of Semiconductor Device - A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern. The method also includes removing the spin-on-carbon layer and the amorphous carbon pattern, and forming a first mask pattern with the second mask pattern as an etching mask. | 11-06-2008 |
| 20080203540 | STRUCTURE AND METHOD FOR DEVICE-SPECIFIC FILL FOR IMPROVED ANNEAL UNIFORMITY - Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 08-28-2008 |
| 20100320576 | Die-warpage compensation structures for thinned-die devices, and methods of assembling same - A back-side lamination (BSL) is applied after thinning a microelectronic die. The BSL is configured to be a thermal-expansion complementary structure to a metal wiring interconnect layout that is disposed on the active side of the microelectronic die. | 12-23-2010 |
| 20110254138 | LOW-TEMPERATURE ABSORBER FILM AND METHOD OF FABRICATION - An improved low-temperature absorber, amorphous carbonitride (ACN) with an extinction coefficient (k) of greater than 0.15, and an emissivity of greater than 0.8 is disclosed. The ACN film can also be characterized as having a minimum of hydrocarbon content as observed by FTIR. The ACN film can be used as an effective absorbing layer that absorbs a wide range of electromagnetic radiation from different sources including lasers or flash lamps. A method of forming such an ACN film at a deposition temperature of less than, or equal to, 450° C. is also provided. | 10-20-2011 |
| 20110215444 | PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES HAVING THE SAME, AND METHODS OF FABRICATING THE SEMICONDUCTOR PACKAGES - A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip. | 09-08-2011 |
| 20090166812 | SEMICONDUCTOR AND AN ARRANGEMENT AND A METHOD FOR PRODUCING A SEMICONDUCTOR - The present invention relates generally to semiconductors, material layers within semiconductors, a production method of semiconductors, and a manufacturing arrangement for producing semiconductors. A semiconductor according to the invention includes at least one layer with a surface, produced by laser ablation, wherein the uniform surface area to be produced includes at least an area 0.2 dm | 07-02-2009 |
| 20120119336 | METHOD FOR MANUFACTURING BONDED WAFER - A method for manufacturing a bonded wafer having a semiconductor film on a handle substrate involving the steps of: implanting ions into a semiconductor substrate to form an ion-implanted layer; subjecting the surface of at least one of the semiconductor substrate and the handle substrate to a surface activation treatment; bonding the surface of the semiconductor substrate to the surface of the handle substrate at a temperature from 50° C. to 350° C.; heating the bonded substrates at a maximum temperature from 200° C. to 350° C. to obtain a bonded body; and transferring a semiconductor film to the handle substrate by subjecting the bonded body to a temperature 30° C. to 100° C. higher than the bonding temperature, and irradiating the bonded body with visible light from a handle or semiconductor substrate side toward the ion-implanted layer of the semiconductor substrate to embrittle the interface of the ion-implanted layer. | 05-17-2012 |
| 20120205784 | GROWING COMPRESSIVELY STRAINED SILICON DIRECTLY ON SILICON AT LOW TEMPERATURES - Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient. | 08-16-2012 |
| 20120018855 | METHOD OF PRODUCING A HETEROSTRUCTURE WITH LOCAL ADAPTATION OF THE THERMAL EXPANSION COEFFICIENT - A method of producing a heterostructure by bonding at least one first substrate having a first thermal expansion coefficient onto a second substrate having a second thermal expansion coefficient, with the first thermal expansion coefficient being different from the second thermal expansion coefficient. Prior to bonding, trenches are formed in one of the two substrates from the bonding surface of the substrate. The trenches are filled with a material having a third thermal expansion coefficient lying between the first and second thermal expansion coefficients. | 01-26-2012 |
| 20120061806 | SYSTEMS AND METHODS FOR DRYING A ROTATING SUBSTRATE - A method of drying a surface of a substrate is provided. The method includes supporting a substrate; rotating the substrate about a rotational center point; applying a liquid to the substrate via a liquid dispenser; applying a drying fluid to the substrate via a drying fluid dispenser; moving the drying fluid dispenser and the liquid dispenser in a direction toward an edge region of the substrate, the drying fluid being applied closer to the rotational center point than the fluid; upon the liquid being applied to the edge region of the substrate, discontinuing application of the liquid while continuing the manipulation of the drying fluid dispenser; and upon the drying fluid being applied to the edge region of the substrate, continuing to apply the drying fluid for a predetermined period of time. | 03-15-2012 |
| 20100207254 | Strained semiconductor materials, devices and methods therefore - Various applications are directed to a material stack having a strained active material therein. In connection with an embodiment, an active material (e.g. a semiconductor material) is at least initially and partially released from and suspended over a substrate, strained, and held in place. The release and suspension facilitates the application of strain to the semiconductor material. | 08-19-2010 |
| 20090096066 | Structure and Method for Device-Specific Fill for Improved Anneal Uniformity - Disclosed is a design structure embodiment of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 04-16-2009 |
| 20120175750 | GEOMETRY OF CONTACT SITES AT BRITTLE INORGANIC LAYERS IN ELECTRONIC DEVICES - An electronic device ( | 07-12-2012 |
| 20120074532 | SEMICONDUCTOR PACKAGE WITH INTEGRATED METAL PILLARS AND MANUFACTURING METHODS THEREOF - A semiconductor package includes a substrate and a semiconductor device. The semiconductor device includes a body having a center, a layer disposed adjacent to the body, and a plurality of conductive pillars configured to electrically connect the semiconductor device to the substrate. The layer defines a plurality of openings. Each of the plurality of conductive pillars extends at least partially through a corresponding one of the plurality of openings. An offset between a first central axis of the each of the plurality of conductive pillars and a second central axis of the corresponding one of the plurality of openings varies with distance between the first central axis and the center of the body. The second central axis of the corresponding one of the plurality of openings is disposed between the first central axis of the each of the plurality of conductive pillars and the center of the body. | 03-29-2012 |
| 20100314723 | MANUFACTURING OF OPTICAL STRUCTURES BY ELECTROTHERMAL FOCUSSING - This invention relates to methods and devices for the production of optical microstructures or domains in dielectric substrates based on electrothermal focussing. More specifically, the invention relates to a method of introducing a change of dielectric and/or optical properties in a region of an electrically insulating or electrically semiconducting substrate, and to substrates produced by such method. | 12-16-2010 |
| 20120299160 | Method of Forming Contacts for Devices with Multiple Stress Liners - Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness. | 11-29-2012 |
| 20120280368 | LAMINATED STRUCTURE FOR SEMICONDUCTOR DEVICES - Articles are described utilizing laminated glass substrates, for example, ion-exchanged glass substrates, with flexible glass or polymers and with semiconductor devices which may be sensitive to alkali migration are described along with methods for making the articles. | 11-08-2012 |
| 20120280369 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a semiconductor device, comprising simultaneously or alternately exposing a substrate, which has two or more kinds of thin films having different elemental components laminated or exposed; and performing different modification treatments to the thin films respectively. | 11-08-2012 |
| 20120091566 | SEMICONDUCTOR APPARATUS AND METHOD OF FABRICATION FOR A SEMICONDUCTOR APPARATUS - The invention relates to a semiconductor apparatus and a method of fabrication for a semiconductor apparatus, whereby the semiconductor apparatus includes a semiconductor layer and a passivation layer arranged on a surface of the semiconductor layer and serving for passivating the semiconductor layer surface, whereby the passivation layer comprises a chemically passivating passivation sublayer and a field-effect-passivating passivation sublayer, which are arranged one above the other on the semiconductor layer surface. | 04-19-2012 |
| 20100213580 | ACID-SENSITIVE, DEVELOPER-SOLUBLE BOTTOM ANTI-REFLECTIVE COATINGS - Acid-sensitive, developer-soluble bottom anti-reflective coating compositions are provided, along with methods of using such compositions and microelectronic structures formed thereof. The compositions preferably comprise a crosslinkable polymer dissolved or dispersed in a solvent system. The polymer preferably comprises recurring monomeric units having adamantyl groups. The compositions also preferably comprise a crosslinker, such as a vinyl ether crosslinking agent, dispersed or dissolved in the solvent system with the polymer. In some embodiments, the composition can also comprise a photoacid generator (PAG) and/or a quencher. The bottom anti-reflective coating compositions are thermally crosslinkable, but can be decrosslinked in the presence of an acid to be rendered developer soluble. | 08-26-2010 |
| 20130134560 | SEMICONDUCTOR STRUCTURE COMPRISING MOISTURE BARRIER AND CONDUCTIVE REDISTRIBUTION LAYER - A semiconductor structure includes semiconductor devices on a substrate, a moisture barrier on the substrate surrounding the semiconductor devices, and a metal conductive redistribution layer formed over the moisture barrier. The metal conductive redistribution layer and the moisture barrier define a closed compartment containing the semiconductor devices. | 05-30-2013 |
| 20100276789 | SEMICONDUCTOR DEVICE HAVING MULTIPLE-LAYER HARD MASK WITH OPPOSITE STRESSES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a hard mask including a first layer and a second layer in contact with each other and having opposite stress types, wherein a difference between initial stresses of the first layer and the second layer is increased so that after a thermal process, the difference between the final stresses of the first and second layer becomes smaller, to reduce the likelihood of peeling of the first or second layer. The initial stress of the first layer includes a compressive stress and the initial stress of the second layer includes a tensile stress. | 11-04-2010 |
