Entries |
Document | Title | Date |
20080211064 | DEEP TRENCH BASED FAR SUBCOLLECTOR REACHTHROUGH - A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region. | 09-04-2008 |
20080217744 | Semiconductor device and method of manufacturing the same - A semiconductor device includes: a semiconductor chip including: a first main face having an edge portion, a second main face locating the opposite side to the first main face, a crystalline defect region present within a region including at least the edge portion being adjacent to the first main face, the crystalline defect region being configured to have lower stress than the stress in the other semiconductor region for the same strain; and a metallic substrate to be bonded via a bonding member to the first main face of the semiconductor chip. | 09-11-2008 |
20080224272 | Active Structure of a Semiconductor Device - An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n) | 09-18-2008 |
20080224273 | CHEMICAL OXIDE REMOVAL OF PLASMA DAMAGED SICOH LOW K DIELECTRICS - A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method. | 09-18-2008 |
20080237809 | METHOD OF FABRICATING HYBRID ORIENTATION SUBSTRATE AND STRUCTURE OF THE SAME - A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed. | 10-02-2008 |
20080246122 | POSITIVE-INTRINSIC-NEGATIVE (PIN)/NEGATIVE-INTRINSIC-POSITIVE (NIP) DIODE - A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity. | 10-09-2008 |
20080258268 | TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE - Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced. | 10-23-2008 |
20080277765 | INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES - A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT. | 11-13-2008 |
20080290470 | Integrated Circuit On Corrugated Substrate - By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance. | 11-27-2008 |
20080296736 | METHOD FOR REDUCING MICROLOADING IN ETCHING HIGH ASPECT RATIO STRUCTURES - A method for etching features of different aspect ratios in a conductive layer is provided. The method comprises: depositing over the conductive layer with an aspect ratio dependent deposition; etching features into the conductive layer with an aspect ratio dependent etching of the conductive layer; and repeating the depositing and the etching at least once. | 12-04-2008 |
20080315369 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area defined around the first area, and an insulation layer covering the first and second areas and having at least one void removing part which extends from the first area to the second area to prevent a void from being formed. | 12-25-2008 |
20090001522 | DIE SEAL RING AND WAFER HAVING THE SAME - A die seal ring disposed in a die and surrounding an integrated circuit region of the die is described. The die seal ring has at least two different local widths. | 01-01-2009 |
20090008748 | ULTRA-THIN DIE AND METHOD OF FABRICATING SAME - In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die. | 01-08-2009 |
20090072355 | DUAL SHALLOW TRENCH ISOLATION STRUCTURE - A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths. | 03-19-2009 |
20090085169 | METHOD OF ACHIEVING ATOMICALLY SMOOTH SIDEWALLS IN DEEP TRENCHES, AND HIGH ASPECT RATIO SILICON STRUCTURE CONTAINING ATOMICALLY SMOOTH SIDEWALLS - A high aspect ratio silicon structure comprises a silicon substrate ( | 04-02-2009 |
20090115027 | Method of Fabricating an Integrated Circuit - A method of fabricating an integrated circuit is disclosed. An etching process is performed in order to create a structure in a substrate. A material layer is generated during the etching process. The material layer is formed from at least one of the group of a Si/C/O composition and/or a Si/metal composition. | 05-07-2009 |
20090121324 | ETCH WITH STRIATION CONTROL - A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed. | 05-14-2009 |
20090160031 | Semiconductor Device and Method for Fabricating the Same - A semiconductor device capable of preventing damage to a thermal oxide layer in a trench, and a method for fabricating the same are disclosed. The device includes a trench in a field region of a semiconductor substrate; a pad oxide layer on the surface of the semiconductor substrate outside the trench; a thermal oxide layer on sidewalls of the trench; a nitride layer covering the thermal oxide layer; an insulating layer filling the trench; and a spacer covering the thermal oxide layer outside the trench. | 06-25-2009 |
20090160032 | Printed Electronic Device and Transistor Device and Manufacturing Method Thereof - An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap. | 06-25-2009 |
20090174039 | Semiconductor device and method of forming the same - A semiconductor device and a method of forming the same are provided. A semiconductor device may comprise a semiconductor substrate including a main surface configured to define a groove, a trench, and a cavity sequentially disposed downward from a given region of the main surface and open toward the main surface. | 07-09-2009 |
20090294917 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device is manufactured by forming a mask having a first opening and a second opening wider than the first opening on a principal surface of a first conductivity type semiconductor substrate, etching semiconductor portions of the first conductivity type semiconductor substrate exposed in the first and second openings to thereby form a first trench in the first opening and form a second trench deeper than the first trench in the second opening, and filling the first and second trenches with a second conductivity type semiconductor to concurrently form an alignment marker for device production and a junction structure of alternate arrangement of the first conductivity type semiconductor and the second conductivity type semiconductor. In this manner, it is possible to provide a semiconductor device in which a parallel pn structure and an alignment marker can be formed concurrently to improve the efficiency of a manufacturing process. | 12-03-2009 |
20090302431 | METHOD OF ACCESSING SEMICONDUCTOR CIRCUITS FROM THE BACKSIDE USING ION-BEAM AND GAS-ETCH - The invention generally relates to semiconductor device processing, and more particularly to methods of accessing semiconductor circuits from the backside using ion-beam and gas-etch to mill deep vias through full-thickness silicon. A method includes creating a pocket in a material to be etched, and performing an isotropic etch of the material by flowing a reactive gas into the pocket and directing a focused ion beam into the pocket. | 12-10-2009 |
20100001380 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device includes: forming a groove portion in a dicing region of an insulating layer and forming a via hole in an internal circuit formation region; providing a first resist film on the insulating layer; providing a second resist film to cover the first resist film; forming an interconnect opening in a region covering an internal circuit formation region of the second resist film and forming a position aligning opening in a region covering the dicing region of the second resist film; and detecting a positional relationship between the groove portion and the position aligning opening so as to detect whether the interconnect opening of the second resist film exists at a predetermined position with respect to the via hole of the insulating layer. In selective removing of the second resist film, the position aligning opening is formed such that a region of the position aligning opening covers the groove portion of the insulating layer. | 01-07-2010 |
20100001381 | SEMICONDUCTOR DEVICE - Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist. | 01-07-2010 |
20100013061 | SEMICONDUCTOR STRUCTURES INCLUDING SQUARE CUTS IN SINGLE CRYSTAL SILICON - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction. | 01-21-2010 |
20100044839 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device and a method of manufacturing the same. In semiconductor devices of the conventional technologies, the chip size is increased when a breakdown voltage is increased. In the semiconductor device of this invention, an end of a pn junction interface ( | 02-25-2010 |
20100117202 | MOLD AND SUBSTRATE FOR USE WITH MOLD | 05-13-2010 |
20100148317 | CRITICAL DIMENSION REDUCTION AND ROUGHNESS CONTROL - A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer. | 06-17-2010 |
20100224967 | SILICON PILLARS FOR VERTICAL TRANSISTORS - In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon. | 09-09-2010 |
20100237473 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area defined around the first area, and an insulation layer covering the first and second areas and having at least one void removing part which extends from the first area to the second area to prevent a void from being formed. | 09-23-2010 |
20100283131 | Discontinuous Thin Semiconductor Wafer Surface Features - A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers. | 11-11-2010 |
20100301460 | SEMICONDUCTOR DEVICE HAVING A FILLED TRENCH STRUCTURE AND METHODS FOR FABRICATING THE SAME - Methods are provided for packaging a semiconductor die having a first surface. In accordance with an exemplary embodiment, a method comprises the steps of forming a trench in the first surface of the die, electrically and physically coupling the die to a packaging substrate, forming a sealant layer on the first surface of the die, forming an engagement structure within the trench, and infusing underfill between the sealant layer and the engagement structure and the packaging substrate. | 12-02-2010 |
20100308444 | Method of Manufacturing an Electronic Device - In order to protect IMD layers, particularly low-k dielectrics, a protection film is formed on the sidewall of an opening in the IMD layers prior to etching a trench in the underlying silicon substrate. After etching the trench, such as through a TMAH wet etch, at least part of the protection film can be removed. The protection film can be removed in an anisotropic etch process such that a portion of the protection film remains as a sidewall spacer on the sidewall of the opening within the IMD layers. | 12-09-2010 |
20110062559 | PLANARIZATION STOP LAYER IN PHASE CHANGE MEMORY INTEGRATION - A key hole structure and method for forming a key hole structure to form a pore in a memory cell. The method includes forming a first dielectric layer on a semiconductor substrate having an electrode formed therein, forming an isolation layer on the first dielectric layer, forming a second dielectric layer on the isolation layer, and forming a planarization stop layer on the second dielectric layer. The method further includes forming a via to extend to the first dielectric layer and recessing the isolation layer and the stop layer with respect to the second dielectric layer, depositing a conformal film within via and over the stop layer, forming a key hole within the conformal film at a center region of the via such that a tip of the key hole is disposed at an upper surface of the second dielectric layer, and planarizing the conformal film to the stop layer. | 03-17-2011 |
20110108960 | SUB-LITHOGRAPHIC PRINTING METHOD - A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size. | 05-12-2011 |
20110127650 | Method of Manufacturing a Semiconductor Device and Semiconductor Devices Resulting Therefrom - A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed. | 06-02-2011 |
20110147899 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING - A method of manufacturing an integrated circuit packaging system includes: providing an inner lead and an outer lead, the inner lead having an inner peripheral side with a non-linear contour; forming a bump contact, having a groove in and a mesa from the inner lead or the outer lead, the groove adjacent to the mesa; mounting a first device adjacent to the inner lead; connecting a second device to the mesa; and forming an encapsulation material over the first device, the inner lead, and the outer lead and covering the second device. | 06-23-2011 |
20110180909 | SEMICONDUCTOR DEVICE - A semiconductor device includes an n-type semiconductor substrate, an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately, p-type channel regions on the alternating conductivity type layer, and trenches formed from the surfaces of the p-type channel regions down to respective n-type drift regions or both the n-type drift regions and the p-type partition regions. The bottom of each trench is near or over the pn-junction between the p-type partition region and the n-type drift region. The semiconductor device facilitates preventing the on-resistance from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof. | 07-28-2011 |
20110193200 | SEMICONDUCTOR WAFER CHIP SCALE PACKAGE TEST FLOW AND DICING PROCESS - A method for forming a semiconductor device can include electrically testing a plurality of semiconductor dies in wafer form subsequent to performing a first wafer dicing process, then performing a second wafer dicing process to dice the wafer and to singularize the plurality of semiconductor dies. Electrically testing the plurality of semiconductor dies in wafer form subsequent to the first dicing process can identify chips damaged during the first dicing process. The method can also include forming a plurality of grooves between adjacent dies which leaves a full wafer thickness at a perimeter of the wafer to result in a wafer which is more resistant to deflection and damage during handling. | 08-11-2011 |
20110198733 | SEMICONDUCTOR DEVICE AND METHOD OF PATTERNNING RESIN INSULATION LAYER ON SUBSTRATE OF THE SAME - In a method of manufacturing a semiconductor device, an electrode layer is formed on a surface of a semiconductor substrate, and a resin insulation layer is formed on the surface of the semiconductor substrate so that the electrode layer can be covered with the resin insulation layer. A tapered hole is formed in the insulation layer by using a tool bit having a rake angle of zero or a negative value. The tapered hole has an opening defined by the insulation layer, a bottom defined by the electrode layer, and a side wall connecting the opening to the bottom. | 08-18-2011 |
20110198734 | METHOD OF IMPROVING A SHALLOW TRENCH ISOLATION GAPFILL PROCESS - A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes removing a first portion of the dielectric layer from the trench bottom to expose the substrate region with a second portion of the dielectric layer remaining on the sidewalls of the trench. In addition, the method includes etching the substrate region to increase the depth of at least a portion of the trench to a second depth. Also, the method includes removing the second portion of the dielectric layer from the trench. | 08-18-2011 |
20110198735 | ASSEMBLY OF A MICROELECTRONIC CHIP HAVING A GROOVE WITH A WIRE ELEMENT IN THE FORM OF A STRAND, AND METHOD FOR ASSEMBLY - Assembly of at least one microelectronic chip with a wire element, the chip comprising a groove for embedment of the wire element. The wire element is a strand with a longitudinal axis substantially parallel to the axis of the groove, comprising at least two electrically conducting wires covered with insulator. The chip comprises at least one electrically conducting bump in the groove, this bump being in electric contact with a stripped area of a single one of the electrically conducting wires of the strand. | 08-18-2011 |
20110204488 | SEMICONDUCTOR WAFER AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes preparing a semiconductor wafer including a silicon substrate and a laminate having a compound semiconductor layer; etching and removing a part of the laminate in a thickness direction to form trench regions in a grid, each trench region including a plurality of stripe grooves extending in parallel to each other; filling the groove with a material having a lower hardness than the compound semiconductor layer to form a buried region; and dividing the semiconductor wafer into a plurality of chips by dicing using a blade at a dicing line which is defined within the trench region and includes a plurality of the buried regions. | 08-25-2011 |
20110210427 | STRAIN MEMORIZATION IN STRAINED SOI SUBSTRATES OF SEMICONDUCTOR DEVICES - In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors. | 09-01-2011 |
20110241181 | SEMICONDUCTOR DEVICE WITH A CONTROLLED CAVITY AND METHOD OF FORMATION - A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. The second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. A vacuum sealing layer is formed over the first cap wafer, wherein the sealing layer vacuum seals the first opening. | 10-06-2011 |
20110248388 | MULTI-LAYER CHIP OVERLAY TARGET AND MEASUREMENT - A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and a length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of a target rectangle disposable within the target region. | 10-13-2011 |
20110254137 | MULTI-DIRECTIONAL TRENCHING OF A DIE IN MANUFACTURING SUPERJUNCTION DEVICES - A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die. | 10-20-2011 |
20110260298 | SEMICONDUCTOR STRUCTURES INCLUDING SQUARE CUTS IN SINGLE CRYSTAL SILICON AND METHOD OF FORMING SAME - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction. | 10-27-2011 |
20110266659 | TECHNIQUE FOR STABLE PROCESSING OF THIN/FRAGILE SUBSTRATES - A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas. | 11-03-2011 |
20110284995 | MICROMECHANICAL MEMBRANES AND RELATED STRUCTURES AND METHODS - Micromechanical membranes suitable for formation of mechanical resonating structures are described, as well as methods for making such membranes. The membranes may be formed by forming cavities in a substrate, and in some instances may be oxidized to provide desired mechanical properties. Mechanical resonating structures may be formed from the membrane and oxide structures. | 11-24-2011 |
20110309480 | PROCESS FOR MANUFACTURING POWER INTEGRATED DEVICES HAVING SURFACE CORRUGATIONS, AND POWER INTEGRATED DEVICE HAVING SURFACE CORRUGATIONS - According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized. | 12-22-2011 |
20110316125 | INTERMEDIATE STRUCTURES FOR FORMING CIRCUITS - In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon. | 12-29-2011 |
20120001302 | METHOD FOR FABRICATING SEMICONDUCTOR THIN FILM USING SUBSTRATE IRRADIATED WITH FOCUSED LIGHT, APPARATUS FOR FABRICATING SEMICONDUCTOR THIN FILM USING SUBSTRATE IRRADIATED WITH FOCUSED LIGHT, METHOD FOR SELECTIVELY GROWING SEMICONDUCTOR THIN FILM USING SUBSTRATE IRRADIATED WITH FOCUSED LIGHT, AND SEMICONDUCTOR ELEMENT USING SUBSTRATE IRRADIATED WITH FOCUSED LIGHT - An apparatus ( | 01-05-2012 |
20120007220 | Method for Reducing Chip Warpage - A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material. | 01-12-2012 |
20120018852 | VIA STRUCTURE AND METHOD THEREOF - A vent hole precursor structure ( | 01-26-2012 |
20120018853 | PHOTOELECTROCHEMICAL ETCHING OF P-TYPE SEMICONDUCTOR HETEROSTRUCTURES - A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force from an internal bias generated internally in the heterostructure; generating electron-hole pairs in a separate area of the heterostructure than the surface to be etched; and using an etchant solution to etch the surface of the p-type layer. | 01-26-2012 |
20120018854 | SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device is provided with: a step of preparing a semiconductor wafer ( | 01-26-2012 |
20120038031 | DISPENSING LIQUID CONTAINING MATERIAL TO PATTERNED SURFACES USING A DISPENSING TUBE - Materials that contain liquid are deposited into grooves upon a surface of a work piece, such as a silicon wafer to form a solar cell. Liquid can be dispensed into work piece paths, such as grooves under pressure through a dispensing tube. The tube mechanically tracks in the groove. The tube may be small and rest at the groove bottom, with the sidewalls providing restraint. Or it may be larger and ride on the top edges of the groove. A tracking feature, such as a protrusion, Non-circular cross-sections, molded-on protrusions and lobes also enhance tracking. The tube may be forced against the groove by spring or magnetic loading. Alignment guides, such as lead-in features may guide the tube into the groove. Restoring features along the path may restore a wayward tube. Many tubes may be used. Many work pieces can be treated in a line or on a drum. | 02-16-2012 |
20120061805 | DICING DIE BOND FILM - The present invention provides a dicing die bond film in which peeling electrification hardly occurs and which has good tackiness and workability. The dicing die bond film of the present invention is a dicing die bond film including a dicing film and a thermosetting type die bond film provided thereon, wherein the thermosetting type die bond film contains conductive particles, the volume resistivity of the thermosetting type die bond film is 1×10 | 03-15-2012 |
20120074531 | EPITAXY SUBSTRATE - An epitaxy substrate for growing a plurality of semiconductor epitaxial layers thereon, includes a plurality of growth areas and a plurality of protected areas. The growth areas are provided for growing the semiconductor epitaxial layers thereon. The growth areas and the protected areas are alternating. A thickness of the growth areas is less than ⅓ of a thickness H of the protected areas. | 03-29-2012 |
20120080776 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: element formation regions each including a cell region where a semiconductor element is formed, a termination trench region; and a dicing line region including a groove separating the element formation regions. The termination trench region includes four trenches surrounding four sides of the cell region. Two of the trenches extend longitudinally in parallel to an X direction and the other two trenches extend longitudinally in parallel to a Y direction perpendicular to the X direction. The termination trench region is perpendicularly in contact with longitudinal sides of the dicing line region while the trenches extending longitudinally in parallel to the X direction intersect the trenches extending longitudinally in parallel to the Y direction at four corners of the element formation region, while vertical sections of the termination trench region in a cross direction are opened in four side surfaces of the element formation region. | 04-05-2012 |
20120104564 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent. | 05-03-2012 |
20120112325 | Integrated Circuit Device, System, and Method of Fabrication - A semiconductor device ( | 05-10-2012 |
20120126374 | Forming Three Dimensional Isolation Structures - A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then conformally depositing in said second set of trenches. In some embodiments, only one wet anneal, one etch back, and one high density plasma chemical vapor deposition step may be used to fill both sets of trenches. | 05-24-2012 |
20120175745 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES USING THE SAME - A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width. | 07-12-2012 |
20120175746 | Selective Deposition in the Fabrication of Electronic Substrates - A semiconductor substrate is coated with a single layer of different materials selected from adhesives, coatings, and encapsulants. | 07-12-2012 |
20120175747 | MEMS DEVICE ASSEMBLY AND METHOD OF PACKAGING SAME - An assembly ( | 07-12-2012 |
20120175748 | SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS AND METHODS OF FABRICATION - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 07-12-2012 |
20120187546 | BILAYER TRENCH FIRST HARDMASK STRUCTURE AND PROCESS FOR REDUCED DEFECTIVITY - A method and structure for transferring a lithographic pattern into a substrate includes forming a dielectric hardmask layer over a dielectric substrate. A metal hardmask layer is formed over the dielectric hardmask layer. A protective capping hardmask layer or capping film is formed over the metal hardmask layer, and a lithographic structure for pattern transfer is formed over the capping layer. A pattern is transferred into the dielectric substrate using the defined lithographic structure. The capping hardmask layer can be removed during subsequent processing. | 07-26-2012 |
20120187547 | SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE WAFER - A semiconductor wafer having a disc shape includes a chamfer provided around a circumferential edge of the wafer, and an anti-cracking and chipping groove provided in one or more areas around one circumference of an end face of the wafer along a circumferential direction of the end face. The anti-cracking and chipping groove is configured to prevent cracking or chipping of the end face in back grinding. | 07-26-2012 |
20120199954 | SEMICONDUCTOR DEVICE - A semiconductor device which provides a small and simple design with efficient cooling. A first electrically conducting cooling element is in contact with first electrodes of semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the first electrodes of the semiconductor elements to an external apparatus. A second electrically conducting cooling element is in contact with second electrodes of the semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the second electrodes of the semiconductor elements to an external apparatus. The semiconductor device includes an interface which is electrically connected to gates of the semiconductor elements for external control of respective states of the semiconductor elements. | 08-09-2012 |
20120217621 | STRUCTURE AND METHOD FOR HARD MASK REMOVAL ON AN SOI SUBSTRATE WITHOUT USING CMP PROCESS - A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask material after a deep trench reactive ion etch (RIE) process. The blocking material on top of the hard mask material is removed. A selective wet etching process is used to remove the hard mask material. Trench recess depth is effectively controlled. | 08-30-2012 |
20120241916 | WAFER EDGE CONDITIONING FOR THINNED WAFERS - The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process. | 09-27-2012 |
20120241917 | SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, AND SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate; and a through electrode that penetrates the semiconductor substrate. The semiconductor substrate has a groove structure that is positioned between a peripheral edge of the semiconductor substrate and the through electrode. | 09-27-2012 |
20120248581 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided, which includes an annular insulation separation portion penetrating a semiconductor substrate, and an electrode penetrating the semiconductor substrate in a region surrounded by the annular insulation separation portion, wherein the insulation separation portion includes at least a first film that gives compressive stress in a depth direction on the side of a substrate, a second film that gives tensile stress in the depth direction is formed on the first film, and film thicknesses of the first and second films are adjusted so that the compressive stress and the tensile stress are almost balanced. | 10-04-2012 |
20120256301 | SELF-ALIGNED NANO-STRUCTURES - A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques. | 10-11-2012 |
20120280367 | METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE - The invention relates to a method for manufacturing a semiconductor substrate by providing a seed support layer and a handle support layer, forming at least one semiconductor layer, in particular of a Group III/V-semiconductor material, over the seed support layer, wherein the at least one semiconductor layer is in a strained state, forming a bonding layer over the at least one semiconductor layer, forming a bonding layer over the handle support layer, and bonding the seed and handle substrates together to obtain a donor-handle compound, by direct bonding between the bonding layer of the seed substrate and the bonding layer of the handle substrate. At least one of the bonding layer of the seed substrate and the bonding layer of the handle substrate includes a silicon nitride. | 11-08-2012 |
20120313224 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 μm or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip. | 12-13-2012 |
20130001752 | METHOD OF SEMICONDUCTOR MANUFACTURING PROCESS - The present invention related to a method for manufacturing a semiconductor, comprising steps of: providing a growing substrate; forming on the growing substrate to have plural grooves; forming a semiconductor element layer on the growing substrate; and changing the temperature of the growing substrate and the semiconductor element layer so as to separate the semiconductor element layer from the growing substrate. | 01-03-2013 |
20130037918 | Semiconductor Structure and Manufacturing Method Thereof - A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer. | 02-14-2013 |
20130037919 | METHODS OF FORMING TRENCHES IN SILICON AND A SEMICONDUCTOR DEVICE INCLUDING SAME - A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed. | 02-14-2013 |
20130056858 | INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A method for fabricating integrated circuit is provided. First, a substrate having a micro electromechanical system (MEMS) region is provided. A first interconnect structure and a hard mask layer have been disposed on the MEMS region in sequence. Next, an anisotropic etching process is performed by using the hard mask layer as a photo mask to etch a portion of the first interconnect structure exposed by the hard mask layer. Accordingly, a MEMS structure is formed. A portion of the substrate in MEMS region is exposed by the MEMS structure. Then, an isotropic etching process is performed for removing the portion of the substrate in MEMS region to form a cavity with a center region and a ring-like indentation region. The center region is surrounded by the ring-like indentation region and the MEMS structure suspends above the cavity. An integrated circuit is also provided. | 03-07-2013 |
20130056859 | SEMICONDUCTOR DEVICE HAVING GROOVES ON A SIDE SURFACE AND METHOD OF MANUFACTURING THE SAME - In one embodiment of a method of manufacturing a semiconductor device, a plurality of substantially columnar trenches are formed along a region for forming a dicing line in a semiconductor substrate having first surface and second surfaces opposed to each other, from the first surface. The substrate is subjected to a heat treatment. At least one hollow portion is formed in the substrate by migration of a material which composes the substrate. Semiconductor devices are formed in semiconductor regions of the substrate which are surrounded by the region for forming the dicing line. The semiconductor regions are provided on a side of the first surface. A portion of the substrate is removed from a side of the second surface until the thickness is reduced to a predetermined value. The substrate is divided into chips along a dicing line from at least the one hollow portion as a starting point. | 03-07-2013 |
20130062737 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor device comprises a device substrate, and a supporting substrate. The supporting substrate is joined onto the device substrate. The device substrate has a first groove in an outer circumferential portion on a joint surface side to the supporting substrate. | 03-14-2013 |
20130075870 | METHOD FOR PROTECTION OF A LAYER OF A VERTICAL STACK AND CORRESPONDING DEVICE - A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed. | 03-28-2013 |
20130075871 | MULTI-LAYER CHIP OVERLAY TARGET AND MEASUREMENT - A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of target rectangle disposable within the target region. | 03-28-2013 |
20130087894 | FLANGE PACKAGE FOR A SEMICONDUCTOR DEVICE - In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed. | 04-11-2013 |
20130093062 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess. | 04-18-2013 |
20130093063 | BONDED SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A bonded substrate having a plurality of grooves and a method of manufacturing the same. The method includes the following steps of implanting ions into a first substrate, thereby forming an ion implantation layer, bonding the first substrate to a second substrate having a plurality of grooves in one surface thereof such that the first substrate is bonded to the one surface, and cleaving the first substrate along the ion implantation layer. | 04-18-2013 |
20130140682 | BURIED WORD LINE AND METHOD FOR FORMING BURIED WORD LINE IN SEMICONDUCTOR DEVICE - A buried word line includes a substrate having thereon a recessed trench, an insulating layer on a bottom surface and a sidewall of the recessed trench, and a lining layer in the recessed trench. The lining layer has a cleaned surface that is cleaned by a cleaning solution comprising HF or H3PO4. A tungsten layer is selectively deposited on the cleaned surface of the lining layer. | 06-06-2013 |
20130161797 | SINGLE CRYSTAL SUBSTRATE, MANUFACTURING METHOD FOR SINGLE CRYSTAL SUBSTRATE, MANUFACTURING METHOD FOR SINGLE CRYSTAL SUBSTRATE WITH MULTILAYER FILM, AND ELEMENT MANUFACTURING METHOD - In order to correct warpage resulting from the formation of a multilayer film, provided are a single crystal substrate which includes a heat-denatured layer provided in one of two regions including a first region and a second region obtained by bisecting the single crystal substrate in a thickness direction thereof, and which is warped convexly toward a side of a surface of the region provided with the heat-denatured layer, a manufacturing method for the single crystal substrate, a manufacturing method for a single crystal substrate with a multilayer film using the single crystal substrate, and an element manufacturing method using the manufacturing method for a single crystal substrate with a multilayer film. | 06-27-2013 |
20130193563 | TRENCH CAPACITOR WITH SPACER-LESS FABRICATION PROCESS - A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench. | 08-01-2013 |
20130214391 | Lateral-Dimension-Reducing Metallic Hard Mask Etch - A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is controlled to a level that limits conversion of a metallic nitride material in an underlying hard mask layer to a metal oxide, and causes organic polymers generated from the organic photoresist to cover peripheral regions of each opening formed in the organic photoresist. The hard mask layer is etched with a taper by the oxygen-limited fluorine-based etch chemistry provided by the combination of gases. The taper angle can be controlled such that a shrink ratio of the lateral dimension by the etch can exceed 2.0. | 08-22-2013 |
20130214392 | METHODS OF FORMING STEPPED ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES USING A SPACER TECHNIQUE - Disclosed herein are various methods of forming stepped isolation structures for semiconductor devices using a spacer technique. In one example, the method includes forming a first trench in a semiconducting substrate, wherein the first trench has a bottom surface, a width and a depth, the depth of the first trench being less than a target final depth for a stepped trench isolation structure, performing an etching process through the first trench on an exposed portion of the bottom surface of the first trench to form a second trench in the substrate, wherein the second trench has a width and a depth, and wherein the width of the second trench is less than the width of the first trench, and forming the stepped isolation structure in the first and second trenches. | 08-22-2013 |
20130221495 | OXIDE MICROCHANNEL WITH CONTROLLABLE DIAMETER - Described herein is a microchannel that is formed beneath and parallel to a surface of a silicon substrate. Silicon migration technology is utilized to form a microchannel that is buried beneath the surface of the silicon substrate. Etching opens at least one end of the microchannel. Oxidization is utilized through the open end of the microchannel to facilitate a controlled diameter of the microchannel. | 08-29-2013 |
20130228899 | MECHANISM OF PATTERNING A SEMICONDUCTOR DEVICE AND PRODUCT RESULTING THEREFROM - The description relates to a method of patterning a semiconductor device to create a through substrate via. The method produces a through substrate via having no photoresist material therein. An intermediate layer deposited over an interlayer dielectric prevents etching solutions from etching interlayer dielectric sidewalls to prevent peeling. The description relates to a semiconductor apparatus including a semiconductor substrate having a through substrate via therein. The semiconductor apparatus further includes an interlayer dielectric over the semiconductor substrate and an intermediate layer over semiconductor substrate and over sidewalls of the interlayer dielectric. | 09-05-2013 |
20130256843 | WAFER SAWING METHOD AND WAFER STRUCTURE BENEFICIAL FOR PERFORMING THE SAME - A wafer sawing method comprises steps as follows: A wafer having a first surface and a second surface is firstly provided. An integrated circuit fabricating process is performed on the first surface of the wafer to define a first integrated circuit region and a periphery region surrounding around the first integrated circuit region, wherein the integrated circuit fabricating process includes an etching process used to form a first deep trench having an aspect ratio larger than 10 as well as a depth substantially ranging from one-third to two-third thickness of the wafer on the periphery region. Subsequently, an adhesive tape is disposed on the first surface at least covering the first integrated circuit region and the periphery region. A tensile stress is then imposed on the adhesive tape in order to make the wafer broken off along the first deep trench. | 10-03-2013 |
20130256844 | Semiconductor Fabrication Utilizing Grating and Trim Masks - Disclosed are a method for fabricating a semiconductor device and the associated semiconductor structure. The method includes exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in the photoresist layer. The method further includes exposing the photoresist layer utilizing a trim mask having a blocking portion situated over a selected one of the unexposed lines. The photoresist layer may be developed after exposing the photoresist layer utilizing the trim mask. A line may then be etched into the semiconductor wafer where the selected one of the unexposed lines was blocked by the blocking portion of the trim mask. The width of the unexposed lines may be controlled by adjusting an exposure time or an exposure power for the photoresist layer while utilizing the grating mask. | 10-03-2013 |
20130264688 | METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT SYSTEM WITH INTERCONNECTED STACKED DEVICE WAFERS - An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer. | 10-10-2013 |
20130264689 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR CHIP HAVING THE SAME, AND STACKED SEMICONDUCTOR PACKAGE - A semiconductor substrate includes a substrate body divided into device regions and a peripheral region outside the device region, and having one surface, another surface substantially facing away from the one surface, trenches defined in the device regions under the one surface and inner surfaces which are formed due to defining of the trenches; active regions formed in the trenches; and a gettering layer formed between the inner surfaces of the substrate body and the active regions. | 10-10-2013 |
20130264690 | METHOD OF PRODUCING EPITAXIAL WAFER AND THE EPITAXIAL WAFER - The present invention provides a method of producing an epitaxial wafer having a highly flat rear surface without polishing top and rear surfaces of the epitaxial wafer after forming an epitaxial film. A method of producing an epitaxial wafer | 10-10-2013 |
20130277808 | DIPPING SOLUTION FOR USE IN PRODUCTION OF SILICEOUS FILM AND PROCESS FOR PRODUCING SILICEOUS FILM USING THE DIPPING SOLUTION - This invention relates to a dipping solution used in a process for producing a siliceous film. The present invention provides a dipping solution and a siliceous film-production process employing the solution. The dipping solution enables to form a homogeneous siliceous film even in concave portions of a substrate having concave portions and convex portions. The substrate is coated with a polysilazane composition, and then dipped in the solution before fire. The dipping solution comprises hydrogen peroxide, a foam-deposit inhibitor, and a solvent. | 10-24-2013 |
20130285214 | POLYMERIC MATERIALS IN SELF-ASSEMBLED ARRAYS AND SEMICONDUCTOR STRUCTURES COMPRISING POLYMERIC MATERIALS - Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. The lines of half-cylinders may be within trenches in the semiconductor structures. | 10-31-2013 |
20130292805 | METHODS OF FORMING SPACERS ON FINFETS AND OTHER SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure. | 11-07-2013 |
20130299950 | SEMICONDUCTOR STRUCTURE WITH BURIED THROUGH SUBSTRATE VIAS - Semiconductor structures and methods of fabrication are provided. One semiconductor structure includes a substrate, a semiconductor device layer supported by the substrate, and one or more buried through substrate vias (TSVs) disposed at least partially within the substrate. The buried through substrate via(s) is buried within the semiconductor substrate, and terminates below the semiconductor device layer of the semiconductor structure, and the semiconductor device layer extends over the buried through substrate via(s), thereby providing the buried through substrate via(s) without consuming space within the semiconductor device layer. A dielectric layer may be disposed between the substrate and the semiconductor device layer, with the TSV(s) terminating at a first end within the dielectric layer. Alternatively, the semiconductor device layer may be an epitaxially-grown layer extending over the TSV(s). Where a plurality of buried TSV(s) are employed, the vias may be disposed in a repeating pattern across the semiconductor structure. | 11-14-2013 |
20130313691 | THINNED WAFER AND FABRICATING METHOD THEREOF - A thinning method of a wafer is provided. The method includes the following steps. First, a wafer having a first surface, a second surface, and a side surface is provided, and the side surface is connected between the first surface and the second surface. At least one semiconductor device is formed on the first surface. Then, an anisotropy etching process is performed to the second surface with a mask to remove portions of the wafer while remaining the side surface thereby forming a number of grooves in the second surface and at least one reinforcing wall between the grooves. As a result, a thinned wafer is obtained. | 11-28-2013 |
20130320507 | SEMICONDUCTOR DEVICE HAVING PLURAL PATTERNS EXTENDING IN THE SAME DIRECTION - A photomask has a mask blank and a light shielding film formed on the mask blank. The light shielding film includes a plurality of opening traces extending in a first direction. An end of a first opening trace in the first direction and an end of a second opening trace in the first direction are in different positions in the first direction. The second opening trace adjoins the first opening trace. | 12-05-2013 |
20130328173 | HIGH ASPECT RATIO AND REDUCED UNDERCUT TRENCH ETCH PROCESS FOR A SEMICONDUCTOR SUBSTRATE - A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved. | 12-12-2013 |
20130341767 | SEMICONDUCTOR DEVICE MOUNTING STRUCTURE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A semiconductor device mounting structure includes: a substrate with an opening provided therein; a frame member with a frame body and a protruding portion that protrudes from the frame body, the frame body being formed and accommodated in a groove around the opening; a coreless substrate provided above the substrate and supported by the protruding portion of the frame member; and semiconductor elements provided on the coreless substrate. | 12-26-2013 |
20140015115 | SEMICONDUCTOR CHIPS HAVING IMPROVED SOLIDITY, SEMICONDUCTOR PACKAGES INCLUDING THE SAME AND METHODS OF FABRICATING THE SAME - Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided. | 01-16-2014 |
20140042595 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING GRINDING FROM A BACK SURFACE AND SEMICONDUCTOR DEVICE - A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device. | 02-13-2014 |
20140054752 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF - A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer. | 02-27-2014 |
20140061868 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device with an SON structure having a thick cavity inside a semiconductor substrate is disclosed. The method forms a plurality of trenches with a predetermined distance between adjacent trenches. Each trench has, at a middle portion between the trench top and bottom, an outwardly expanding sectional shape. High temperature annealing is conducted driving surface migration of silicon atoms in the surface region of the silicon substrate to close the top of the trench, resulting in formation of a plurality of small cavities composed of the trenches in the silicon substrate. Further high temperature annealing joins the plurality of small cavities to form a single cavity. Second opening width x | 03-06-2014 |
20140091439 | SILICON SHAPING - One embodiment for forming a shaped substrate for an electronic device can form a shaped perimeter to define the substrate shape on the surface of a substrate. The shaped perimeter can extend at least part way into the substrate. A subsequent thinning process can remove substrate material and expose the shaped perimeter effectively forming shaped dies from the substrate. | 04-03-2014 |
20140097520 | METHODS OF FORMING AN ARRAY OF OPENINGS IN A SUBSTRATE, RELATED METHODS OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE, AND A RELATED SEMICONDUCTOR DEVICE STRUCTURE - A method of forming an array of openings in a substrate. The method comprises forming a template structure comprising a plurality of parallel features and a plurality of additional parallel features perpendicularly intersecting the plurality of additional parallel features of the plurality over a substrate to define wells, each of the plurality of parallel features having substantially the same dimensions and relative spacing as each of the plurality of additional parallel features. A block copolymer material is formed in each of the wells. The block copolymer material is processed to form a patterned polymer material defining a pattern of openings. The pattern of openings is transferred to the substrate to form an array of openings in the substrate. A method of forming a semiconductor device structure, and a semiconductor device structure are also described. | 04-10-2014 |
20140097521 | Silicon on Nothing Devices and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate. | 04-10-2014 |
20140117507 | DOUBLE TRENCH WELL FORMATION IN SRAM CELLS - A method is provided for forming SRAM cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each deep trench; filling the deep trenches with oxide; forming a first or second shallow trench between each pair of adjacent deep trenches; forming a first p-well or first n-well, respectively, above each deep n-well or p-well; forming a second n-well at a bottom of each first shallow trench; forming a p+ region above each second n-well on each side of each first shallow trench; filling the first shallow trenches with oxide; forming a second p-well at a bottom of each second shallow trench; filling the second shallow trenches with oxide; forming a p+ region above each second n-well on each side of each first shallow trench; and forming an n+ region above each second p-well. | 05-01-2014 |
20140117508 | SEMICONDUCTOR UNIT - A semiconductor unit includes an insulating substrate having a first surface and a second surface opposite to the first surface, a first conductive layer bonded to the first surface of the insulating substrate, a second conductive layer bonded to the first surface of the insulating substrate at a position different from that for the first conductive layer, a stress relief layer bonded to the second surface of the insulating substrate, a radiator bonded to the stress relief layer on the side thereof opposite to the insulating substrate, and semiconductor devices electrically bonded to the respective first and second conductive layers. The insulating substrate has a low-rigidity portion provided between the first and second conductive layers and having a lower rigidity than the rest of the insulating substrate, and at least the low-rigidity portion is sealed and covered by a mold resin. | 05-01-2014 |
20140145311 | METHODS OF FORMING FEATURES IN SEMICONDUCTOR DEVICE STRUCTURES - Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively exposing the resist to an energy source to form exposed resist portions and non-exposed resist portions, and diffusing acid or base of the acidic or basic material from the pool into proximal portions of the resist. Another method comprises forming a plurality of recesses in a substrate structure. The plurality of recesses are filled with a pool material comprising acid or base. A resist is formed over the pool material and the substrate structure and acid or base is diffused into adjacent portions of the resist. The resist is patterned to form openings in the resist. The openings comprise wider portions distal to the substrate structure and narrower portions proximal to the substrate structure. Additional methods and semiconductor device structures including the features are disclosed. | 05-29-2014 |
20140159209 | MANUFACTURING METHOD FOR A MICROMECHANICAL COMPONENT AND A CORRESPONDING MICROMECHANICAL COMPONENT - A manufacturing method is described for a micromechanical component and a corresponding micromechanical component. The manufacturing method includes the steps: forming at least one crystallographically modified area in a substrate; forming an etching mask having a mask opening on a main surface of the substrate; and carrying out an etching step using the etching mask, the crystallographically modified area and a surrounding area of the substrate being removed and thus forming a cavern in the substrate. | 06-12-2014 |
20140159210 | VERTICAL OUTGASSING CHANNELS - InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H | 06-12-2014 |
20140191374 | FILM THICKNESS METROLOGY - Methods for determining a target thickness of a conformal film with reduced uncertainty, and an integrated circuit (IC) chip having a conformal film of the target thickness are provided. In an embodiment, a first critical dimension of a structure disposed on a wafer is measured. Said structure has at least one vertical surface. A first conformal film is deposited over the structure covering each of a horizontal and the vertical surface of the structure. A second critical dimension of the covered structure is then measured. The target thickness of the conformal film is determined based on difference between the first CD measured on the structure and the second CD measured on the covered structure. | 07-10-2014 |
20140217561 | DOUBLE TRENCH RECTIFIER - A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent. | 08-07-2014 |
20140217562 | Power Semiconductor Device with an Edge Termination Region - A power semiconductor device includes a semiconductor substrate, an active device region disposed in the semiconductor substrate, an edge termination region spaced laterally outward from the active device region in the semiconductor substrate, and first and second trenches. The first trench is disposed in the edge termination region and has an inner sidewall, an outer sidewall and a bottom, the inner sidewall being spaced closer to the active device region than the outer sidewall. The second trench is spaced laterally outward from the first trench in the edge termination region, and extends further into the semiconductor substrate than the first trench and has a sidewall which outwardly faces the outer sidewall of the first trench and is doped opposite as the inner sidewall and bottom of the first trench. | 08-07-2014 |
20140231967 | SYSTEMS AND METHODS FOR POST-BONDING WAFER EDGE SEAL - A method for fabricating a semiconductor device is disclosed. A first substrate is arranged over a second substrate. A wafer bonding process is performed on the semiconductor device. First regions of the device are enclosed by the bonding process. Second regions of the device remain exposed. One or more processes are performed on the exposed second regions, after performing the wafer bonding process. The one or more processes include a fill process that forms a fill material within the exposed second regions. An edge seal material is applied on the first and second substrates after performing the one or more processes. | 08-21-2014 |
20140239459 | METHOD FOR PRODUCING MECHANICALLY FLEXIBLE SILICON SUBSTRATE - A method for making a mechanically flexible silicon substrate is disclosed. In one embodiment, the method includes providing a silicon substrate. The method further includes forming a first etch stop layer in the silicon substrate and forming a second etch stop layer in the silicon substrate. The method also includes forming one or more trenches over the first etch stop layer and the second etch stop layer. The method further includes removing the silicon substrate between the first etch stop layer and the second etch stop layer. | 08-28-2014 |
20140252563 | Semiconductor Device with Trench Structure and Methods of Manufacturing - A vertical semiconductor device includes a semiconductor body having semiconductor portions of semiconductor elements of the vertical semiconductor device, a front side contact on a front surface of the semiconductor body and a back side contact on an opposite back surface of the semiconductor body, and a trench structure extending from the front surface into the semiconductor body. The trench structure includes an etch stop layer lining an inner surface of the trench structure and surrounding a void within the trench structure. | 09-11-2014 |
20140252564 | Process for Structuring Silicon - A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H | 09-11-2014 |
20140264774 | WAFER AND FILM COATING METHOD OF USING THE SAME - The present disclosure provides a wafer that can be used in coating films. The wafer includes a front surface, a back surface opposite to the front surface, and a plurality of trenches. The back surface further includes a central region and a surrounding region. The trenches are disposed on the back surface. The spacing between any two adjacent trenches in surrounding region is less than the spacing between any two adjacent trenches in the central region. | 09-18-2014 |
20140312469 | LASER-BASED MATERIAL PROCESSING METHODS AND SYSTEMS - Various embodiments may be used for laser-based modification of target material of a workpiece while advantageously achieving improvements in processing throughput and/or quality. Embodiments of a method of processing may include focusing and directing laser pulses to a region of the workpiece at a pulse repetition rate sufficiently high so that material is efficiently removed from the region and a quantity of unwanted material within the region, proximate to the region, or both is reduced relative to a quantity obtainable at a lower repetition rate. Embodiments of an ultrashort pulse laser system may include a fiber amplifier or fiber laser. Various embodiments are suitable for at least one of dicing, cutting, scribing, and forming features on or within a semiconductor substrate. Workpiece materials may include metals, inorganic or organic dielectrics, or any material to be micromachined with femtosecond, picosecond, and/or nanosecond pulses. | 10-23-2014 |
20140319657 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate ( | 10-30-2014 |
20140332931 | Compensation Devices - Methods, apparatuses and devices related to the manufacturing of compensation devices are provided. In some cases, an n/p-codoped layer is deposited for calibration purposes to minimize a net doping concentration. In other cases, alternatingly n- and p-doped layers are then deposited. In other embodiments, an n/p-codoped layer is deposited in a trench where n- and p-dopants have different diffusion behavior. To obtain different doping profiles, a heat treatment may be performed. | 11-13-2014 |
20140332932 | SHALLOW TRENCH AND FABRICATION METHOD - Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided. A mask layer can be provided on the semiconductor substrate. An etch-cleaning process can be performed. The etch-cleaning process can include etching the semiconductor substrate to form a shallow trench by one or more etching steps using the mask layer as an etch mask. The etch-cleaning process can further include performing a plasma cleaning process after each of the one or more etching steps. The plasma cleaning process can use a plasma that is electronegative. | 11-13-2014 |
20140346647 | MONITORING STRUCTURE AND MONITORING METHOD FOR SILICON WET ETCHING DEPTH - A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are W | 11-27-2014 |
20140353802 | METHODS FOR INTEGRATION OF PORE STUFFING MATERIAL - A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided. | 12-04-2014 |
20140353803 | SEMICONDUCTOR DEVICE STRUCTURES - Methods of forming features are disclosed. One method comprises forming a resist over a pool of acidic or basic material on a substrate structure, selectively exposing the resist to an energy source to form exposed resist portions and non-exposed resist portions, and diffusing acid or base of the acidic or basic material from the pool into proximal portions of the resist. Another method comprises forming a plurality of recesses in a substrate structure. The plurality of recesses are filled with a pool material comprising acid or base. A resist is formed over the pool material and the substrate structure and acid or base is diffused into adjacent portions of the resist. The resist is patterned to form openings in the resist. The openings comprise wider portions distal to the substrate structure and narrower portions proximal to the substrate structure. Additional methods and semiconductor device structures including the features are disclosed. | 12-04-2014 |
20140361412 | Cavity Structure Using Patterned Sacrificial Layer - A method includes forming a sacrificial layer over a bottom substrate. The sacrificial layer is patterned based on a desired etching distance. A top layer is formed over the sacrificial layer. At least one release hole is formed through the top layer. The sacrificial layer is etched through the at least one release hole. | 12-11-2014 |
20140361413 | PROCESS FOR FABRICATING A THREE-DIMENSIONAL INTEGRATED STRUCTURE WITH IMPROVED HEAT DISSIPATION, AND CORRESPONDING THREE-DIMENSIONAL INTEGRATED STRUCTURE - A three-dimensional integrated structure includes a first integrated circuit having a substrate assembled in an interlocking manner with a second integrated circuit having a substrate. The substrate of the first integrated circuit comprises first pores separated by first partitions, and the substrate of the second integrated circuit comprises second pores separated by second partitions. The first partitions interlock with the second pores and the second partitions interlock with the first pores so as to define at least one region bounded by the two substrates. A phase-change material is retained within the at least one region. | 12-11-2014 |
20140374885 | NARROW GAP DEVICE WITH PARALLEL RELEASING STRUCTURE - The present disclosure relates to a method of etching a narrow gap using one or more parallel releasing structures to improve etching performance, and an associated apparatus. In some embodiments, the method provides a semiconductor substrate with a narrow gap having a sacrificial material. One or more parallel releasing structures are formed within the semiconductor substrate at positions that abut the narrow gap. An etching process is then performed to simultaneously remove the sacrificial material from the narrow gap along a first direction from the one or more parallel releasing structures and along a second direction, perpendicular to the first direction. By simultaneously etching the sacrificial material from both the direction of the narrow gap and from the direction of the one or more parallel releasing structures, the sacrificial material is removed in less time, since the etch is not limited by a size of the narrow gap. | 12-25-2014 |
20150014820 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SUPPORT SUBSTRATE-ATTACHED WAFER - A recessed portion is formed around an outer edge of a device wafer at a peripheral edge portion of a first face of the device wafer. A recessed portion is formed around an outer edge of a support substrate, at a bonding face of the support substrate. The first face of the device wafer and the bonding face of the support substrate are bonded together by an adhesive. The device wafer is ground from a second face side, on the opposite side to the first face | 01-15-2015 |
20150014821 | FILM THICKNESS METROLOGY - Methods for determining a target thickness of a conformal film with reduced uncertainty, and an integrated circuit (IC) chip having a conformal film of the target thickness are provided. In an embodiment, a first critical dimension of a structure disposed on a wafer is measured. Said structure has at least one vertical surface. A first conformal film is deposited over the structure covering each of a horizontal and the vertical surface of the structure. A second critical dimension of the covered structure is then measured. The target thickness of the conformal film is determined based on difference between the first CD measured on the structure and the second CD measured on the covered structure. | 01-15-2015 |
20150021745 | REACTIVE ION ETCHING - A method of reactive ion etching a substrate | 01-22-2015 |
20150048486 | SPATIAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening. | 02-19-2015 |
20150069581 | NOBLE GAS BOMBARDMENT TO REDUCE SCALLOPS IN BOSCH ETCHING - A method of etching a trench in a substrate is provided. The method repeatedly alternates between using a fluorine-based plasma to etch a trench, which has trench sidewalls, into a selected region of the substrate; and using a fluorocarbon plasma to deposit a liner on the trench sidewalls. The liner, when formed and subsequently etched, has an exposed sidewall surface that includes scalloped recesses. The trench, which includes the scalloped recesses, is then bombarded with a molecular beam where the molecules are directed on an axis parallel to the trench sidewalls to reduce the scalloped recesses. | 03-12-2015 |
20150069582 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a plurality of pillars vertically extending from the semiconductor substrate, each pillar including a groove formed in an upper surface thereof, a salicide layer formed to cover the upper surface and a lateral circumference of an upper end of each pillar and a lower electrode formed to cover an upper surface and a lateral surface of the salicide layer. | 03-12-2015 |
20150076667 | SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING CHANNEL AND METHOD OF FORMING A SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING CHANNEL - A semiconductor substrate for use in an integrated circuit, the semiconductor substrate including a channel defined on a surface of the substrate. The channel includes a first wall, a second wall, and a third wall. The first wall is recessed from the surface. The second wall extends from the surface to the first wall. The third wall extends from the surface to the first wall and faces the second wall across the channel. At least one of the second wall and the third wall includes a plurality of structures projecting into the channel from the second wall or the third wall. | 03-19-2015 |
20150091140 | MULTIPLE SILICON TRENCHES FORMING METHOD FOR MEMS SEALING CAP WAFER AND ETCHING MASK STRUCTURE THEREOF - A multiple silicon trenches forming method and an etching mask structure, the method comprises: step S | 04-02-2015 |
20150115413 | Assembly of Wafer Stacks - A method of forming a wafer stack includes providing a sub-stack comprising a first wafer and a second wafer. The sub-stack includes a first thermally-curable adhesive at an interface between the upper surface of the first wafer and the lower surface of the second wafer. A third wafer is placed on the upper surface of the second wafer. A second thermally-curable adhesive is present at an interface between the upper surface of the second wafer and the lower surface of the third wafer. Ultra-violet (UV) radiation is provided in a direction of the upper surface of the third wafer to cure a UV-curable adhesive in openings in the second wafer and in contact with portions of the third wafer so as to bond the third wafer to the sub-stack at discrete locations. Subsequently, the third wafer and the sub-stack are heated so to cure the first and second thermally-curable adhesives. | 04-30-2015 |
20150130031 | Semiconductor Device With An Overlay Mark Including Segment Regions Surrounded By A Pool Region - Disclosed herein is a semiconductor device that includes a plurality of segment regions arranged with a first distance, each of segment regions including a plurality of first grooves arranged with a second distance that is smaller than the first distance, and a second groove enclosing the plurality of the segment regions with a third distance that is larger than the second distance. The third distance may be substantially equal to the first direction | 05-14-2015 |
20150137330 | METHOD FOR ESTIMATING THE DIFFUSION LENGTH OF METALLIC SPECIES WITHIN A THREE-DIMENSIONAL INTEGRATED STRUCTURE, AND CORRESPONDING THREE-DIMENSIONAL INTEGRATED STRUCTURE - A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations. | 05-21-2015 |
20150137331 | POLYMERIC MATERIALS IN SELF-ASSEMBLED ARRAYS AND SEMICONDUCTOR STRUCTURES AND METHODS COMPRISING SUCH POLYMERIC MATERIALS - Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. The lines of half-cylinders may be within trenches in the semiconductor structures. | 05-21-2015 |
20150303249 | METHODS FOR THE PRODUCTION OF INTEGRATED CIRCUITS COMPRISING EPITAXIALLY GROWN REPLACEMENT STRUCTURES - Integrated circuits and methods for producing such integrated circuits are provided. A method for producing the integrated circuit includes forming dummy structures in a substrate, and forming shallow trench isolation regions between the dummy structures where the shallow trench isolation regions includes a liner overlying a core. The dummy structures are etched to expose structure bases, and the structure bases are precleaned. Replacement structures are epitaxially grown over the structure bases. | 10-22-2015 |
20150311063 | Methods for Integrated Circuit Design and Fabrication - The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of: forming a plurality of first features over the target material layer using a first sub-layout, with each first feature having sidewalls; forming a plurality of spacer features, with each spacer feature conforming to the sidewalls of one of the first features and having a spacer width; and forming a plurality of second features over the target material layer using a second sub-layout. The method further includes steps of removing the plurality of spacer features from around each first feature and patterning the target material layer using the plurality of first features and the plurality of second features. Other methods and associated patterned semiconductor wafers are also provided herein. | 10-29-2015 |
20150311163 | Anchoring Structure and Intermeshing Structure - An anchoring structure for a metal structure of a semiconductor device includes an anchoring recess structure having at least one overhanging side wall, the metal structure being at least partly arranged within the anchoring recess structure. | 10-29-2015 |
20150325538 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The method for producing a semiconductor device includes: forming an opening in an area of at least one of the complementary metal-oxide semiconductor wafer that includes a first part and the other semiconductor wafer that includes a second part, the opening terminating within the area and not penetrating through the area, the area including corresponding one of the first part and the second part and an outer peripheral part of the corresponding one of the first part and the second part; forming a conduction hole within the first part, the conduction hole communicating with a metallic material in the complementary metal-oxide semiconductor wafer; arranging a first joining material inside the conduction hole and on the first part, and a second joining material on the second part; and joining the arranged first joining material and the arranged second joining material. | 11-12-2015 |
20150340330 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad. | 11-26-2015 |
20150348784 | SIMPLIFIED CHARGE BALANCE IN A SEMICONDUCTOR DEVICE - A method of forming a charge balance region in an active semiconductor device includes: forming an epitaxial region including material of a first conductivity type on an upper surface of a substrate of the semiconductor device; forming multiple recessed features at least partially through the epitaxial region; depositing a film comprising material of a second conductivity type on a bottom and/or sidewalls of the recessed features using atomic layer deposition; and performing thermal processing such that at least a portion of the film deposited on the bottom and/or sidewalls of each of the recessed features forms a region of the second conductivity type in the epitaxial layer which follows a contour of the recessed features, the region of the second conductivity type, in conjunction with the epitaxial layer proximate the region of the second conductivity type, forming the charge balance region. | 12-03-2015 |
20150357410 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, it includes an object film and an opening that is formed in the object film and in which a second taper adjoining a first taper is provided. A step is provided at the boundary between the first taper and the second taper. | 12-10-2015 |
20150364362 | WAFER STRESS CONTROL WITH BACKSIDE PATTERNING - Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication. | 12-17-2015 |
20150371981 | FILM THICKNESS METROLOGY - Methods for determining a target thickness of a conformal film with reduced uncertainty, and an integrated circuit (IC) chip having a conformal film of the target thickness are provided. In an embodiment, a first critical dimension of a structure disposed on a wafer is measured. Said structure has at least one vertical surface. A first conformal film is deposited over the structure covering each of a horizontal and the vertical surface of the structure. A second critical dimension of the covered structure is then measured. The target thickness of the conformal film is determined based on difference between the first CD measured on the structure and the second CD measured on the covered structure. | 12-24-2015 |
20150380266 | METHODS FOR PROVIDING LITHOGRAPHY FEATURES ON A SUBSTRATE BY SELF-ASSEMBLY OF BLOCK COPOLYMERS - Causing a self-assemblable block copolymer (BCP) having first and second blocks to migrate from a region surrounding a lithography recess of the substrate and a dummy recess on the substrate to within the lithography recess and the dummy recess, causing the BCP to self-assemble into an ordered layer within the lithography recess, the layer having a first block domain and a second block domain, and selectively removing the first domain to form a lithography feature having the second domain within the lithography recess, wherein a width of the dummy recess is smaller than the minimum width required by the BCP to self-assemble, the dummy recess is within the region of the substrate surrounding the lithography recess from which the BCP is caused to migrate, and the width between portions of a side-wall of the lithography recess is greater than the width between portions of a side-wall of the dummy recess. | 12-31-2015 |
20150380299 | METHODS FOR PROVIDING SPACED LITHOGRAPHY FEATURES ON A SUBSTRATE BY SELF-ASSEMBLY OF BLOCK COPOLYMERS - A method of forming a plurality of regularly spaced lithography features, e.g. contact holes, including: providing a trench on a substrate, the trench having opposing side-walls and a base, with the side-walls having a width therebetween, wherein the trench is formed by photolithography including exposing the substrate using off-axis illumination whereby a modulation is provided to the side-walls of the trench; providing a self-assemblable block copolymer having first and second blocks in the trench; causing the self-assemblable block copolymer to self-assemble into an ordered layer in the trench, the layer having first domains of the first block and second domains of the second block; and selectively removing the first domain to form at least one regularly spaced row of lithography features having the second domain along the trench. | 12-31-2015 |
20150380363 | Methods and Apparatus to Reduce Semiconductor Wafer Warpage in the Presence of Deep Cavities - Methods and apparatus for forming structures to reduce wafer warpage. A method includes providing a semiconductor wafer having a plurality of integrated circuits; providing a photomask defining a plurality of cavities to be formed by an etch on a backside surface of the semiconductor wafer; defining structural support areas for the backside surface, the structural support areas being contiguous areas; providing areas on the photomask that correspond to the structural support areas, the structural support areas being areas that are not to be etched; using the photomask, performing an etch on the backside surface of the semiconductor wafer to form the cavities by removing semiconductor material from the backside surface of the semiconductor wafer; and the structural supports on the backside of the semiconductor wafer formed as areas that are not subjected to the etch. Additional methods and apparatus are also disclosed. | 12-31-2015 |
20150380369 | WAFER PACKAGING STRUCTURE AND PACKAGING METHOD - The present invention provides a wafer packaging structure and a wafer packaging method. The wafer packaging structure includes: a substrate, wherein grooves are formed in one surface of the substrate, and chips are arranged in the grooves; a material sealing layer formed on the substrate, wherein connecting components of the chips are exposed from the surface of the material sealing layer; a wiring layer formed on the material sealing layer and electrically connected with the connecting components; a protective film layer formed on the wiring layer, wherein the protective film layer is provided with openings for exposing the wiring layer; lower ball metal layers formed in the openings and connected with the wiring layer; and metal balls formed on the lower ball metal layers. The wafer packaging structure provided by the present invention can be used for packaging a plurality of chips, thereby having a higher integration level and a higher integration degree. | 12-31-2015 |
20160005694 | SEMICONDUCTOR PACKAGE STRUCTURE, ALIGNMENT STRUCTURE, AND ALIGNMENT METHOD - A semiconductor package structure includes a first wafer and a second wafer. The first wafer has a concave portion. The concave portion has a bottom surface and at least one sidewall adjacent to the bottom surface. An obtuse angle is formed between the bottom surface and the sidewall. The second wafer is disposed on the first wafer and has a protruding portion. When the protruding portion enters an opening of the concave portion, the protruding portion slides along the sidewall to the bottom surface, such that the protruding portion is coupled to the concave portion. | 01-07-2016 |
20160013099 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD | 01-14-2016 |
20160013126 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE | 01-14-2016 |
20160060106 | METHOD AND STRUCTURE FOR CREATING CAVITIES WITH EXTREME ASPECT RATIOS - Embodiments relate to structures, systems and methods for more efficiently and effectively etching sacrificial and other layers in substrates and other structures. In embodiments, a substrate in which a sacrificial layer is to be removed to, e.g., form a cavity comprises an etch dispersion system comprising a trench, channel or other structure in which etch gas or another suitable gas, fluid or substance can flow to penetrate the substrate and remove the sacrificial layer. The trench, channel or other structure can be implemented along with openings or other apertures formed in the substrate, such as proximate one or more edges of the substrate, to even more quickly disperse etch gas or some other substance within the substrate. | 03-03-2016 |
20160064362 | Semiconductor Device Package and Methods of Packaging Thereof - An embodiment of the present invention describes a method for forming a doped region at a first major surface of a semiconductor substrate where the first doped region being part of a first semiconductor device. The method includes forming an opening from the first major surface into the semiconductor substrate and attaching a semiconductor die to the semiconductor substrate at the opening. The semiconductor die includes a second semiconductor device, which is a different type of semiconductor device than the first semiconductor device. The method further includes forming a chip isolation region on sidewalls of the opening and surrounding the second semiconductor device, and singulating the semiconductor substrate. | 03-03-2016 |
20160079061 | SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE - A substrate includes a base substrate including a processed portion processed by irradiation with an ultrashort-pulse laser light and an unprocessed portion which is not irradiated with the ultrashort-pulse laser light, the processed portion and the unprocessed portion are on a surface of the base substrate, and a semiconductor crystal layer crystal-grown at least on the unprocessed portion of the base substrate. | 03-17-2016 |
20160126109 | Method for Manufacturing a Transistor Device Comprising a Germanium Channel Material on a Silicon Based Substrate, and Associated Transistor Device - Method for manufacturing a transistor device comprising a germanium channel material on a silicon based substrate, the method comprising providing a shallow trench isolation (STI) substrate comprising a silicon protrusion embedded in STI dielectric structures, and partially recessing the silicon protrusion in order to provide a trench in between adjacent STI structures, and to provide a V-shaped groove at an upper surface of the recessed protrusion. The method also includes growing a Si | 05-05-2016 |
20160189977 | PATTERNING METHOD AND SEMICONDUCTOR STRUCTURE - A patterning method and a patterned material layer are provided. After providing a substrate including a material layer, a hard mask layer including trenches extending in a first direction is formed over the material layer. A filling material layer is formed on the hard mask layer to cover the hard mask layer and fills in the trenches. A mask layer in a grid pattern is formed on the filling material layer. The mask layer includes first grid lines extending in the first direction and second grid lines extending in a second direction, and each of the underlying trench is located between two most adjacent first grid lines. The material layer is etched with the mask layer as an etching mask to form a patterned material layer including a plurality of first holes and a plurality of second holes. | 06-30-2016 |
20170236765 | CHIP PART AND METHOD FOR MANUFACTURING A CHIP PART | 08-17-2017 |
20180026096 | SEMICONDUCTOR WAFERS WITH REDUCED BOW AND WARPAGE | 01-25-2018 |