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Groove

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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257618000 - PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.)

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DocumentTitleDate
20090085169METHOD OF ACHIEVING ATOMICALLY SMOOTH SIDEWALLS IN DEEP TRENCHES, AND HIGH ASPECT RATIO SILICON STRUCTURE CONTAINING ATOMICALLY SMOOTH SIDEWALLS - A high aspect ratio silicon structure comprises a silicon substrate (04-02-2009
20110193200SEMICONDUCTOR WAFER CHIP SCALE PACKAGE TEST FLOW AND DICING PROCESS - A method for forming a semiconductor device can include electrically testing a plurality of semiconductor dies in wafer form subsequent to performing a first wafer dicing process, then performing a second wafer dicing process to dice the wafer and to singularize the plurality of semiconductor dies. Electrically testing the plurality of semiconductor dies in wafer form subsequent to the first dicing process can identify chips damaged during the first dicing process. The method can also include forming a plurality of grooves between adjacent dies which leaves a full wafer thickness at a perimeter of the wafer to result in a wafer which is more resistant to deflection and damage during handling.08-11-2011
20100148317CRITICAL DIMENSION REDUCTION AND ROUGHNESS CONTROL - A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.06-17-2010
20130037919METHODS OF FORMING TRENCHES IN SILICON AND A SEMICONDUCTOR DEVICE INCLUDING SAME - A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.02-14-2013
20130037918Semiconductor Structure and Manufacturing Method Thereof - A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer.02-14-2013
20130075871MULTI-LAYER CHIP OVERLAY TARGET AND MEASUREMENT - A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of target rectangle disposable within the target region.03-28-2013
20130075870METHOD FOR PROTECTION OF A LAYER OF A VERTICAL STACK AND CORRESPONDING DEVICE - A device and corresponding fabrication method includes a vertical stack having an intermediate layer between a lower region and an upper region. The intermediate layer is extended by a protection layer. The vertical stack has a free lateral face on which the lower region, the upper region and the protection layer are exposed.03-28-2013
20090121324ETCH WITH STRIATION CONTROL - A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.05-14-2009
20100044839SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device and a method of manufacturing the same. In semiconductor devices of the conventional technologies, the chip size is increased when a breakdown voltage is increased. In the semiconductor device of this invention, an end of a pn junction interface (02-25-2010
20090160031Semiconductor Device and Method for Fabricating the Same - A semiconductor device capable of preventing damage to a thermal oxide layer in a trench, and a method for fabricating the same are disclosed. The device includes a trench in a field region of a semiconductor substrate; a pad oxide layer on the surface of the semiconductor substrate outside the trench; a thermal oxide layer on sidewalls of the trench; a nitride layer covering the thermal oxide layer; an insulating layer filling the trench; and a spacer covering the thermal oxide layer outside the trench.06-25-2009
20090160032Printed Electronic Device and Transistor Device and Manufacturing Method Thereof - An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap.06-25-2009
20090302431METHOD OF ACCESSING SEMICONDUCTOR CIRCUITS FROM THE BACKSIDE USING ION-BEAM AND GAS-ETCH - The invention generally relates to semiconductor device processing, and more particularly to methods of accessing semiconductor circuits from the backside using ion-beam and gas-etch to mill deep vias through full-thickness silicon. A method includes creating a pocket in a material to be etched, and performing an isotropic etch of the material by flowing a reactive gas into the pocket and directing a focused ion beam into the pocket.12-10-2009
20130087894FLANGE PACKAGE FOR A SEMICONDUCTOR DEVICE - In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed.04-11-2013
20100001381SEMICONDUCTOR DEVICE - Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist.01-07-2010
20120217621STRUCTURE AND METHOD FOR HARD MASK REMOVAL ON AN SOI SUBSTRATE WITHOUT USING CMP PROCESS - A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask material after a deep trench reactive ion etch (RIE) process. The blocking material on top of the hard mask material is removed. A selective wet etching process is used to remove the hard mask material. Trench recess depth is effectively controlled.08-30-2012
20130056858INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A method for fabricating integrated circuit is provided. First, a substrate having a micro electromechanical system (MEMS) region is provided. A first interconnect structure and a hard mask layer have been disposed on the MEMS region in sequence. Next, an anisotropic etching process is performed by using the hard mask layer as a photo mask to etch a portion of the first interconnect structure exposed by the hard mask layer. Accordingly, a MEMS structure is formed. A portion of the substrate in MEMS region is exposed by the MEMS structure. Then, an isotropic etching process is performed for removing the portion of the substrate in MEMS region to form a cavity with a center region and a ring-like indentation region. The center region is surrounded by the ring-like indentation region and the MEMS structure suspends above the cavity. An integrated circuit is also provided.03-07-2013
20130056859SEMICONDUCTOR DEVICE HAVING GROOVES ON A SIDE SURFACE AND METHOD OF MANUFACTURING THE SAME - In one embodiment of a method of manufacturing a semiconductor device, a plurality of substantially columnar trenches are formed along a region for forming a dicing line in a semiconductor substrate having first surface and second surfaces opposed to each other, from the first surface. The substrate is subjected to a heat treatment. At least one hollow portion is formed in the substrate by migration of a material which composes the substrate. Semiconductor devices are formed in semiconductor regions of the substrate which are surrounded by the region for forming the dicing line. The semiconductor regions are provided on a side of the first surface. A portion of the substrate is removed from a side of the second surface until the thickness is reduced to a predetermined value. The substrate is divided into chips along a dicing line from at least the one hollow portion as a starting point.03-07-2013
20120112325Integrated Circuit Device, System, and Method of Fabrication - A semiconductor device (05-10-2012
20130062737SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor device comprises a device substrate, and a supporting substrate. The supporting substrate is joined onto the device substrate. The device substrate has a first groove in an outer circumferential portion on a joint surface side to the supporting substrate.03-14-2013
20130161797SINGLE CRYSTAL SUBSTRATE, MANUFACTURING METHOD FOR SINGLE CRYSTAL SUBSTRATE, MANUFACTURING METHOD FOR SINGLE CRYSTAL SUBSTRATE WITH MULTILAYER FILM, AND ELEMENT MANUFACTURING METHOD - In order to correct warpage resulting from the formation of a multilayer film, provided are a single crystal substrate which includes a heat-denatured layer provided in one of two regions including a first region and a second region obtained by bisecting the single crystal substrate in a thickness direction thereof, and which is warped convexly toward a side of a surface of the region provided with the heat-denatured layer, a manufacturing method for the single crystal substrate, a manufacturing method for a single crystal substrate with a multilayer film using the single crystal substrate, and an element manufacturing method using the manufacturing method for a single crystal substrate with a multilayer film.06-27-2013
20080290470Integrated Circuit On Corrugated Substrate - By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.11-27-2008
20120001302METHOD FOR FABRICATING SEMICONDUCTOR THIN FILM USING SUBSTRATE IRRADIATED WITH FOCUSED LIGHT, APPARATUS FOR FABRICATING SEMICONDUCTOR THIN FILM USING SUBSTRATE IRRADIATED WITH FOCUSED LIGHT, METHOD FOR SELECTIVELY GROWING SEMICONDUCTOR THIN FILM USING SUBSTRATE IRRADIATED WITH FOCUSED LIGHT, AND SEMICONDUCTOR ELEMENT USING SUBSTRATE IRRADIATED WITH FOCUSED LIGHT - An apparatus (01-05-2012
20110284995MICROMECHANICAL MEMBRANES AND RELATED STRUCTURES AND METHODS - Micromechanical membranes suitable for formation of mechanical resonating structures are described, as well as methods for making such membranes. The membranes may be formed by forming cavities in a substrate, and in some instances may be oxidized to provide desired mechanical properties. Mechanical resonating structures may be formed from the membrane and oxide structures.11-24-2011
20110198734METHOD OF IMPROVING A SHALLOW TRENCH ISOLATION GAPFILL PROCESS - A method of forming a graded trench for a shallow trench isolation region is provided. The method includes providing a semiconductor substrate with a substrate region. The method further includes forming a pad oxide layer overlying the substrate region. Additionally, the method includes forming an etch stop layer overlying the pad oxide layer. The method further includes patterning the etch stop layer and the pad oxide layer to expose a portion of the substrate region. In addition, the method includes forming a trench within an exposed portion of the substrate region, the trench having sidewalls and a bottom and a first depth. The method additionally includes forming a dielectric layer overlying the trench sidewalls, the trench bottom, and mesa regions adjacent to the trench. The method further includes removing a first portion of the dielectric layer from the trench bottom to expose the substrate region with a second portion of the dielectric layer remaining on the sidewalls of the trench. In addition, the method includes etching the substrate region to increase the depth of at least a portion of the trench to a second depth. Also, the method includes removing the second portion of the dielectric layer from the trench.08-18-2011
20110198735ASSEMBLY OF A MICROELECTRONIC CHIP HAVING A GROOVE WITH A WIRE ELEMENT IN THE FORM OF A STRAND, AND METHOD FOR ASSEMBLY - Assembly of at least one microelectronic chip with a wire element, the chip comprising a groove for embedment of the wire element. The wire element is a strand with a longitudinal axis substantially parallel to the axis of the groove, comprising at least two electrically conducting wires covered with insulator. The chip comprises at least one electrically conducting bump in the groove, this bump being in electric contact with a stripped area of a single one of the electrically conducting wires of the strand.08-18-2011
20110198733SEMICONDUCTOR DEVICE AND METHOD OF PATTERNNING RESIN INSULATION LAYER ON SUBSTRATE OF THE SAME - In a method of manufacturing a semiconductor device, an electrode layer is formed on a surface of a semiconductor substrate, and a resin insulation layer is formed on the surface of the semiconductor substrate so that the electrode layer can be covered with the resin insulation layer. A tapered hole is formed in the insulation layer by using a tool bit having a rake angle of zero or a negative value. The tapered hole has an opening defined by the insulation layer, a bottom defined by the electrode layer, and a side wall connecting the opening to the bottom.08-18-2011
20090294917METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device is manufactured by forming a mask having a first opening and a second opening wider than the first opening on a principal surface of a first conductivity type semiconductor substrate, etching semiconductor portions of the first conductivity type semiconductor substrate exposed in the first and second openings to thereby form a first trench in the first opening and form a second trench deeper than the first trench in the second opening, and filling the first and second trenches with a second conductivity type semiconductor to concurrently form an alignment marker for device production and a junction structure of alternate arrangement of the first conductivity type semiconductor and the second conductivity type semiconductor. In this manner, it is possible to provide a semiconductor device in which a parallel pn structure and an alignment marker can be formed concurrently to improve the efficiency of a manufacturing process.12-03-2009
20110266659TECHNIQUE FOR STABLE PROCESSING OF THIN/FRAGILE SUBSTRATES - A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.11-03-2011
20080246122POSITIVE-INTRINSIC-NEGATIVE (PIN)/NEGATIVE-INTRINSIC-POSITIVE (NIP) DIODE - A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.10-09-2008
20110204488SEMICONDUCTOR WAFER AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes preparing a semiconductor wafer including a silicon substrate and a laminate having a compound semiconductor layer; etching and removing a part of the laminate in a thickness direction to form trench regions in a grid, each trench region including a plurality of stripe grooves extending in parallel to each other; filling the groove with a material having a lower hardness than the compound semiconductor layer to form a buried region; and dividing the semiconductor wafer into a plurality of chips by dicing using a blade at a dicing line which is defined within the trench region and includes a plurality of the buried regions.08-25-2011
20080258268TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE - Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced.10-23-2008
20120104564SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent.05-03-2012
20130214392METHODS OF FORMING STEPPED ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES USING A SPACER TECHNIQUE - Disclosed herein are various methods of forming stepped isolation structures for semiconductor devices using a spacer technique. In one example, the method includes forming a first trench in a semiconducting substrate, wherein the first trench has a bottom surface, a width and a depth, the depth of the first trench being less than a target final depth for a stepped trench isolation structure, performing an etching process through the first trench on an exposed portion of the bottom surface of the first trench to form a second trench in the substrate, wherein the second trench has a width and a depth, and wherein the width of the second trench is less than the width of the first trench, and forming the stepped isolation structure in the first and second trenches.08-22-2013
20080315369SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area defined around the first area, and an insulation layer covering the first and second areas and having at least one void removing part which extends from the first area to the second area to prevent a void from being formed.12-25-2008
20130214391Lateral-Dimension-Reducing Metallic Hard Mask Etch - A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is controlled to a level that limits conversion of a metallic nitride material in an underlying hard mask layer to a metal oxide, and causes organic polymers generated from the organic photoresist to cover peripheral regions of each opening formed in the organic photoresist. The hard mask layer is etched with a taper by the oxygen-limited fluorine-based etch chemistry provided by the combination of gases. The taper angle can be controlled such that a shrink ratio of the lateral dimension by the etch can exceed 2.0.08-22-2013
20100013061SEMICONDUCTOR STRUCTURES INCLUDING SQUARE CUTS IN SINGLE CRYSTAL SILICON - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.01-21-2010
20080211064DEEP TRENCH BASED FAR SUBCOLLECTOR REACHTHROUGH - A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.09-04-2008
20090008748ULTRA-THIN DIE AND METHOD OF FABRICATING SAME - In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.01-08-2009
20100001380Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device includes: forming a groove portion in a dicing region of an insulating layer and forming a via hole in an internal circuit formation region; providing a first resist film on the insulating layer; providing a second resist film to cover the first resist film; forming an interconnect opening in a region covering an internal circuit formation region of the second resist film and forming a position aligning opening in a region covering the dicing region of the second resist film; and detecting a positional relationship between the groove portion and the position aligning opening so as to detect whether the interconnect opening of the second resist film exists at a predetermined position with respect to the via hole of the insulating layer. In selective removing of the second resist film, the position aligning opening is formed such that a region of the position aligning opening covers the groove portion of the insulating layer.01-07-2010
20100224967SILICON PILLARS FOR VERTICAL TRANSISTORS - In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.09-09-2010
20100237473SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area defined around the first area, and an insulation layer covering the first and second areas and having at least one void removing part which extends from the first area to the second area to prevent a void from being formed.09-23-2010
20090115027Method of Fabricating an Integrated Circuit - A method of fabricating an integrated circuit is disclosed. An etching process is performed in order to create a structure in a substrate. A material layer is generated during the etching process. The material layer is formed from at least one of the group of a Si/C/O composition and/or a Si/metal composition.05-07-2009
20090072355DUAL SHALLOW TRENCH ISOLATION STRUCTURE - A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths.03-19-2009
20110127650Method of Manufacturing a Semiconductor Device and Semiconductor Devices Resulting Therefrom - A method is disclosed for manufacturing a semiconductor device, including providing a substrate comprising a main surface with a non flat topography, the surface comprising at least one substantial topography variation, forming a first capping layer over the main surface such that, during formation of the first capping layer, local defects in the first capping layer are introduced, the local defects being positioned at locations corresponding to the substantial topography variations and the local defects being suitable for allowing a predetermined fluid to pass through. Associated membrane layers, capping layers, and microelectronic devices are also disclosed.06-02-2011
20110108960SUB-LITHOGRAPHIC PRINTING METHOD - A trench structure and an integrated circuit comprising sub-lithographic trench structures in a substrate. In one embodiment the trench structure is created by forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.05-12-2011
20110241181SEMICONDUCTOR DEVICE WITH A CONTROLLED CAVITY AND METHOD OF FORMATION - A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. The second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. A vacuum sealing layer is formed over the first cap wafer, wherein the sealing layer vacuum seals the first opening.10-06-2011
20110210427STRAIN MEMORIZATION IN STRAINED SOI SUBSTRATES OF SEMICONDUCTOR DEVICES - In sophisticated semiconductor devices, the initial strain component of a globally strained semiconductor layer may be substantially preserved during the formation of shallow trench isolations by using a rigid mask material, which may efficiently avoid or reduce a deformation of the semiconductor islands upon patterning the isolation trenches. Consequently, selected regions with high internal stress levels may be provided, irrespective of the height-to-length aspect ratio, which may limit the application of globally strained semiconductor layers in conventional approaches. Furthermore, in some illustrative embodiments, active regions of substantially relaxed strain state or of inverse strain type may be provided in addition to the highly strained active regions, thereby enabling an efficient process strategy for forming complementary transistors.09-01-2011
20120241917SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, AND SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate; and a through electrode that penetrates the semiconductor substrate. The semiconductor substrate has a groove structure that is positioned between a peripheral edge of the semiconductor substrate and the through electrode.09-27-2012
20110062559PLANARIZATION STOP LAYER IN PHASE CHANGE MEMORY INTEGRATION - A key hole structure and method for forming a key hole structure to form a pore in a memory cell. The method includes forming a first dielectric layer on a semiconductor substrate having an electrode formed therein, forming an isolation layer on the first dielectric layer, forming a second dielectric layer on the isolation layer, and forming a planarization stop layer on the second dielectric layer. The method further includes forming a via to extend to the first dielectric layer and recessing the isolation layer and the stop layer with respect to the second dielectric layer, depositing a conformal film within via and over the stop layer, forming a key hole within the conformal film at a center region of the via such that a tip of the key hole is disposed at an upper surface of the second dielectric layer, and planarizing the conformal film to the stop layer.03-17-2011
20110248388MULTI-LAYER CHIP OVERLAY TARGET AND MEASUREMENT - A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and a length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of a target rectangle disposable within the target region.10-13-2011
20120199954SEMICONDUCTOR DEVICE - A semiconductor device which provides a small and simple design with efficient cooling. A first electrically conducting cooling element is in contact with first electrodes of semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the first electrodes of the semiconductor elements to an external apparatus. A second electrically conducting cooling element is in contact with second electrodes of the semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the second electrodes of the semiconductor elements to an external apparatus. The semiconductor device includes an interface which is electrically connected to gates of the semiconductor elements for external control of respective states of the semiconductor elements.08-09-2012
20110147899INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING DEVICE STACKING - A method of manufacturing an integrated circuit packaging system includes: providing an inner lead and an outer lead, the inner lead having an inner peripheral side with a non-linear contour; forming a bump contact, having a groove in and a mesa from the inner lead or the outer lead, the groove adjacent to the mesa; mounting a first device adjacent to the inner lead; connecting a second device to the mesa; and forming an encapsulation material over the first device, the inner lead, and the outer lead and covering the second device.06-23-2011
20080277765INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES - A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.11-13-2008
20100283131Discontinuous Thin Semiconductor Wafer Surface Features - A semiconductor wafer has a semiconductor substrate and films on the substrate. The substrate and/or the films have at least one etch line creating a discontinuous surface that reduces residual stress in the wafer. Reducing residual stress in the semiconductor wafer reduces warpage of the wafer when the wafer is thin. Additionally, isolation plugs may be used to fill a portion of the etch lines to prevent shorting of the layers.11-11-2010
20110254137MULTI-DIRECTIONAL TRENCHING OF A DIE IN MANUFACTURING SUPERJUNCTION DEVICES - A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.10-20-2011
20100117202MOLD AND SUBSTRATE FOR USE WITH MOLD05-13-2010
20110260298SEMICONDUCTOR STRUCTURES INCLUDING SQUARE CUTS IN SINGLE CRYSTAL SILICON AND METHOD OF FORMING SAME - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.10-27-2011
20080217744Semiconductor device and method of manufacturing the same - A semiconductor device includes: a semiconductor chip including: a first main face having an edge portion, a second main face locating the opposite side to the first main face, a crystalline defect region present within a region including at least the edge portion being adjacent to the first main face, the crystalline defect region being configured to have lower stress than the stress in the other semiconductor region for the same strain; and a metallic substrate to be bonded via a bonding member to the first main face of the semiconductor chip.09-11-2008
20090174039Semiconductor device and method of forming the same - A semiconductor device and a method of forming the same are provided. A semiconductor device may comprise a semiconductor substrate including a main surface configured to define a groove, a trench, and a cavity sequentially disposed downward from a given region of the main surface and open toward the main surface.07-09-2009
20120038031DISPENSING LIQUID CONTAINING MATERIAL TO PATTERNED SURFACES USING A DISPENSING TUBE - Materials that contain liquid are deposited into grooves upon a surface of a work piece, such as a silicon wafer to form a solar cell. Liquid can be dispensed into work piece paths, such as grooves under pressure through a dispensing tube. The tube mechanically tracks in the groove. The tube may be small and rest at the groove bottom, with the sidewalls providing restraint. Or it may be larger and ride on the top edges of the groove. A tracking feature, such as a protrusion, Non-circular cross-sections, molded-on protrusions and lobes also enhance tracking. The tube may be forced against the groove by spring or magnetic loading. Alignment guides, such as lead-in features may guide the tube into the groove. Restoring features along the path may restore a wayward tube. Many tubes may be used. Many work pieces can be treated in a line or on a drum.02-16-2012
20100301460SEMICONDUCTOR DEVICE HAVING A FILLED TRENCH STRUCTURE AND METHODS FOR FABRICATING THE SAME - Methods are provided for packaging a semiconductor die having a first surface. In accordance with an exemplary embodiment, a method comprises the steps of forming a trench in the first surface of the die, electrically and physically coupling the die to a packaging substrate, forming a sealant layer on the first surface of the die, forming an engagement structure within the trench, and infusing underfill between the sealant layer and the engagement structure and the packaging substrate.12-02-2010
20080296736METHOD FOR REDUCING MICROLOADING IN ETCHING HIGH ASPECT RATIO STRUCTURES - A method for etching features of different aspect ratios in a conductive layer is provided. The method comprises: depositing over the conductive layer with an aspect ratio dependent deposition; etching features into the conductive layer with an aspect ratio dependent etching of the conductive layer; and repeating the depositing and the etching at least once.12-04-2008
20110316125INTERMEDIATE STRUCTURES FOR FORMING CIRCUITS - In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.12-29-2011
20120061805DICING DIE BOND FILM - The present invention provides a dicing die bond film in which peeling electrification hardly occurs and which has good tackiness and workability. The dicing die bond film of the present invention is a dicing die bond film including a dicing film and a thermosetting type die bond film provided thereon, wherein the thermosetting type die bond film contains conductive particles, the volume resistivity of the thermosetting type die bond film is 1×1003-15-2012
20120007220Method for Reducing Chip Warpage - A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.01-12-2012
20090001522DIE SEAL RING AND WAFER HAVING THE SAME - A die seal ring disposed in a die and surrounding an integrated circuit region of the die is described. The die seal ring has at least two different local widths.01-01-2009
20120126374Forming Three Dimensional Isolation Structures - A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then conformally depositing in said second set of trenches. In some embodiments, only one wet anneal, one etch back, and one high density plasma chemical vapor deposition step may be used to fill both sets of trenches.05-24-2012
20110180909SEMICONDUCTOR DEVICE - A semiconductor device includes an n-type semiconductor substrate, an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately, p-type channel regions on the alternating conductivity type layer, and trenches formed from the surfaces of the p-type channel regions down to respective n-type drift regions or both the n-type drift regions and the p-type partition regions. The bottom of each trench is near or over the pn-junction between the p-type partition region and the n-type drift region. The semiconductor device facilitates preventing the on-resistance from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof.07-28-2011
20120313224SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 μm or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.12-13-2012
20120175748SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS AND METHODS OF FABRICATION - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.07-12-2012
20120175747MEMS DEVICE ASSEMBLY AND METHOD OF PACKAGING SAME - An assembly (07-12-2012
20120175746Selective Deposition in the Fabrication of Electronic Substrates - A semiconductor substrate is coated with a single layer of different materials selected from adhesives, coatings, and encapsulants.07-12-2012
20120175745METHODS FOR FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES USING THE SAME - A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width.07-12-2012
20120074531EPITAXY SUBSTRATE - An epitaxy substrate for growing a plurality of semiconductor epitaxial layers thereon, includes a plurality of growth areas and a plurality of protected areas. The growth areas are provided for growing the semiconductor epitaxial layers thereon. The growth areas and the protected areas are alternating. A thickness of the growth areas is less than ⅓ of a thickness H of the protected areas.03-29-2012
20120256301SELF-ALIGNED NANO-STRUCTURES - A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques.10-11-2012
20120187546BILAYER TRENCH FIRST HARDMASK STRUCTURE AND PROCESS FOR REDUCED DEFECTIVITY - A method and structure for transferring a lithographic pattern into a substrate includes forming a dielectric hardmask layer over a dielectric substrate. A metal hardmask layer is formed over the dielectric hardmask layer. A protective capping hardmask layer or capping film is formed over the metal hardmask layer, and a lithographic structure for pattern transfer is formed over the capping layer. A pattern is transferred into the dielectric substrate using the defined lithographic structure. The capping hardmask layer can be removed during subsequent processing.07-26-2012
20120187547SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE WAFER - A semiconductor wafer having a disc shape includes a chamfer provided around a circumferential edge of the wafer, and an anti-cracking and chipping groove provided in one or more areas around one circumference of an end face of the wafer along a circumferential direction of the end face. The anti-cracking and chipping groove is configured to prevent cracking or chipping of the end face in back grinding.07-26-2012
20120080776SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: element formation regions each including a cell region where a semiconductor element is formed, a termination trench region; and a dicing line region including a groove separating the element formation regions. The termination trench region includes four trenches surrounding four sides of the cell region. Two of the trenches extend longitudinally in parallel to an X direction and the other two trenches extend longitudinally in parallel to a Y direction perpendicular to the X direction. The termination trench region is perpendicularly in contact with longitudinal sides of the dicing line region while the trenches extending longitudinally in parallel to the X direction intersect the trenches extending longitudinally in parallel to the Y direction at four corners of the element formation region, while vertical sections of the termination trench region in a cross direction are opened in four side surfaces of the element formation region.04-05-2012
20120280367METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE - The invention relates to a method for manufacturing a semiconductor substrate by providing a seed support layer and a handle support layer, forming at least one semiconductor layer, in particular of a Group III/V-semiconductor material, over the seed support layer, wherein the at least one semiconductor layer is in a strained state, forming a bonding layer over the at least one semiconductor layer, forming a bonding layer over the handle support layer, and bonding the seed and handle substrates together to obtain a donor-handle compound, by direct bonding between the bonding layer of the seed substrate and the bonding layer of the handle substrate. At least one of the bonding layer of the seed substrate and the bonding layer of the handle substrate includes a silicon nitride.11-08-2012
20120241916WAFER EDGE CONDITIONING FOR THINNED WAFERS - The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.09-27-2012
20080237809METHOD OF FABRICATING HYBRID ORIENTATION SUBSTRATE AND STRUCTURE OF THE SAME - A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed.10-02-2008
20130140682BURIED WORD LINE AND METHOD FOR FORMING BURIED WORD LINE IN SEMICONDUCTOR DEVICE - A buried word line includes a substrate having thereon a recessed trench, an insulating layer on a bottom surface and a sidewall of the recessed trench, and a lining layer in the recessed trench. The lining layer has a cleaned surface that is cleaned by a cleaning solution comprising HF or H3PO4. A tungsten layer is selectively deposited on the cleaned surface of the lining layer.06-06-2013
20080224273CHEMICAL OXIDE REMOVAL OF PLASMA DAMAGED SICOH LOW K DIELECTRICS - A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method. 09-18-2008
20080224272Active Structure of a Semiconductor Device - An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)09-18-2008
20120248581SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided, which includes an annular insulation separation portion penetrating a semiconductor substrate, and an electrode penetrating the semiconductor substrate in a region surrounded by the annular insulation separation portion, wherein the insulation separation portion includes at least a first film that gives compressive stress in a depth direction on the side of a substrate, a second film that gives tensile stress in the depth direction is formed on the first film, and film thicknesses of the first and second films are adjusted so that the compressive stress and the tensile stress are almost balanced.10-04-2012
20130093062SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.04-18-2013
20130093063BONDED SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A bonded substrate having a plurality of grooves and a method of manufacturing the same. The method includes the following steps of implanting ions into a first substrate, thereby forming an ion implantation layer, bonding the first substrate to a second substrate having a plurality of grooves in one surface thereof such that the first substrate is bonded to the one surface, and cleaving the first substrate along the ion implantation layer.04-18-2013
20100308444Method of Manufacturing an Electronic Device - In order to protect IMD layers, particularly low-k dielectrics, a protection film is formed on the sidewall of an opening in the IMD layers prior to etching a trench in the underlying silicon substrate. After etching the trench, such as through a TMAH wet etch, at least part of the protection film can be removed. The protection film can be removed in an anisotropic etch process such that a portion of the protection film remains as a sidewall spacer on the sidewall of the opening within the IMD layers.12-09-2010
20110309480PROCESS FOR MANUFACTURING POWER INTEGRATED DEVICES HAVING SURFACE CORRUGATIONS, AND POWER INTEGRATED DEVICE HAVING SURFACE CORRUGATIONS - According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.12-22-2011
20120018854SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device is provided with: a step of preparing a semiconductor wafer (01-26-2012
20120018853PHOTOELECTROCHEMICAL ETCHING OF P-TYPE SEMICONDUCTOR HETEROSTRUCTURES - A method for photoelectrochemical (PEC) etching of a p-type semiconductor layer simply and efficiently, by providing a driving force for holes to move towards a surface of a p-type cap layer to be etched, wherein the p-type cap layer is on a heterostructure and the heterostructure provides the driving force from an internal bias generated internally in the heterostructure; generating electron-hole pairs in a separate area of the heterostructure than the surface to be etched; and using an etchant solution to etch the surface of the p-type layer.01-26-2012
20120018852VIA STRUCTURE AND METHOD THEREOF - A vent hole precursor structure (01-26-2012
20130193563TRENCH CAPACITOR WITH SPACER-LESS FABRICATION PROCESS - A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.08-01-2013

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