Class / Patent application number | Description | Number of patent applications / Date published |
257619000 | With thin active central semiconductor portion surrounded by thicker inactive shoulder (e.g., for mechanical support) | 17 |
20090020854 | Process of forming ultra thin wafers having an edge support ring - A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes. | 01-22-2009 |
20090057841 | WAFER - A wafer having a device region, where a plurality of devices is formed, and an outer peripheral surplus region, which surrounds the device region, on the face of a circular wafer substrate is disclosed. A chamfered portion whose cross-sectional shape defines an arc-shaped surface in a range from the face to the back of the wafer substrate is formed in an outer peripheral end portion of the outer peripheral surplus region of the wafer substrate. A flat surface orthogonal to the face and the back is formed in the chamfered portion as a mark showing the crystal orientation of the wafer substrate. An identification code for specifying the wafer substrate is printed on the flat surface. | 03-05-2009 |
20100059863 | Stretchable Form of Single Crystal Silicon for High Performance Electronics on Rubber Substrates - The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices. | 03-11-2010 |
20100117200 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE HAVING A REINFORCING MEMBER THAT PREVENTS DISTORTIONS AND METHOD FOR FABRICATING THE SAME - A substrate for a semiconductor package having a reinforcing member that prevents or minimizes distortions is presented. The substrate for the semiconductor package includes a substrate body, an insulation layer, and a reinforcing member. The substrate body has a first region having a plurality of chip mount regions, a second region disposed along a periphery of the first region, a circuit pattern disposed in each chip mount region and a dummy pattern disposed along the second region. The insulation layer covers the first and second regions and has an opening exposing some portion of each circuit pattern. The reinforcing member is disposed in the second region and prevents deflection of the substrate body. | 05-13-2010 |
20100148312 | REINFORCED SMART CARDS & METHODS OF MAKING SAME - Reinforced smart cards with and methods of making an integrated circuit chip for smart are disclosed. In some embodiments, a method includes generally providing an integrated circuit wafer including a plurality of integrated circuits, providing a stiffener, attaching the stiffener top surface to the wafer bottom surface, and physically separating integrated circuits. The wafer can be substantially disc-shaped with a wafer perimeter. Integrated circuits can be disposed on the wafer's top surface, and the wafer's bottom surface can span a wafer bottom area. The stiffener can have a top surface spanning an area corresponding to a circuitry portion of the wafer's top surface (where integrated circuits can be disposed). The stiffener's can be applied to the wafer's bottom surface to form a wafer/stiffener assembly. Integrated circuits of the wafer/stiffener assembly can be separated by removing wafer material between integrated circuits and stiffener material between regions of the stiffener underlying the integrated circuits. Other aspects, features, and embodiments are claimed and disclosed. | 06-17-2010 |
20100187659 | Semiconductor device and method for manufacturing semiconductor device - An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface. | 07-29-2010 |
20100200958 | PEDESTAL GUARD RING HAVING CONTINUOUS M1 METAL BARRIER CONNECTED TO CRACK STOP - A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip. | 08-12-2010 |
20100207249 | WAFER INCLUDING A REINFORCING FLANGE FORMED UPRIGHT AT A PERIPHERY AND METHOD FOR MANUFACTURING THE SAME - A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed upright along the circumference and a notch portion formed upright near the orientation notch, and a width of the circumferential portion as viewed parallel to a major surface of the wafer is smaller than a depth of the orientation notch as viewed parallel to the major surface. | 08-19-2010 |
20100252915 | MICROELECTRONIC DEVICE WAFERS AND METHODS OF MANUFACTURING - Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched. | 10-07-2010 |
20110193198 | Corner Stress Release Structure Design for Increasing Circuit Routing Areas - An integrated circuit structure includes a semiconductor chip, which further includes a corner and a seal ring dispatched adjacent edges of the semiconductor chip; and a corner stress release (CSR) structure adjacent the corner and physically adjoining the seal ring. The CSR structure includes a portion in a top metallization layer. A circuit component selected from the group consisting essentially of an interconnect structure and an active circuit is directly underlying the CSR structure. | 08-11-2011 |
20110260296 | SEMICONDUCTOR WAFER AND METHOD FOR PRODUCING SAME - A semiconductor wafer ( | 10-27-2011 |
20120068311 | SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor substrate having a semiconductor device formable area, wherein a reinforcing part, which is thicker than the semiconductor device formable area and has a top part of which surface is flat, is formed on an outer circumference part of the semiconductor substrate, and an inner side surface connecting the top part of the reinforcing part and the semiconductor device formable area has a cross-sectional shape of which inner diameter becomes smaller as being closer to the semiconductor device formable area. | 03-22-2012 |
20140048909 | COMPLIANT BIPOLAR MICRO DEVICE TRANSFER HEAD - A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes. | 02-20-2014 |
20140084423 | PROTECTIVE MEMBER AND WAFER PROCESSING METHOD - A wafer processing method including a fixing step of providing a wafer on a protective member so that a device area of the wafer faces an unevenness absorbing member provided in a recess of the protective member and providing an adhesive outside the device area to thereby fix the protective member and the wafer, a grinding step of holding the protective member on a holding table in the condition where the back side of the wafer is exposed and next grinding the back side of the wafer by using a grinding unit to thereby reduce the thickness of the wafer to a predetermined thickness, and a removing step of removing the protective member from the wafer. The adhesive is locally provided outside of the device area, so that the protective member can be easily removed from the wafer without leaving the adhesive on the front side of each device. | 03-27-2014 |
20140084424 | Semiconductor Device with Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die. | 03-27-2014 |
20140239454 | WAFER EDGE PROTECTION - A semiconductor device and a method for forming a device are presented. A wafer substrate having first and second regions is provided. The second region includes an inner region of the substrate while the first region includes an outer peripheral region from an edge of the substrate towards the inner region. A protection unit is provided above the substrate. The protection unit includes a region having a total width W | 08-28-2014 |
20160133496 | SEMICONDUCTOR BONDING WITH COMPLIANT RESIN AND UTILIZING HYDROGEN IMPLANTATION FOR TRANSFER-WAFER REMOVAL - A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light. | 05-12-2016 |