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PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257621000 With electrical contact in hole in semiconductor (e.g., lead extends through semiconductor body) 218
257620000 With peripheral feature due to separation of smaller semiconductor chip from larger wafer (e.g., scribe region, or means to prevent edge effects such as leakage current at peripheral chip separation area) 210
257622000 Groove 93
257627000 With specified crystal plane or axis 46
257623000 Mesa structure (e.g., including undercut or stepped mesa configuration or having constant slope taper) 44
257619000 With thin active central semiconductor portion surrounded by thicker inactive shoulder (e.g., for mechanical support) 12
Entries
DocumentTitleDate
20110175204SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a manufacturing method of a semiconductor device is disclosed. This method can include dicing along a predetermined line a laminated substrate which has a first substrate and a second substrate, one of which is made of a semiconductor substrate, mutually adhered with an adhesive layer interposed between them. The dicing process includes irradiating a laser beam to the adhesive layer along the dicing line to form scribe lines corresponding to the dicing line on the first and second substrates. And, the dicing process includes applying an impact to the laminated substrate to divide along the scribe lines.07-21-2011
20130043565INTEGRATED CIRCUIT SYSTEM WITH SUB-GEOMETRY REMOVAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.02-21-2013
20110198730HYPERBRANCHED POLYMER SYNTHESIZING METHOD, HYPERBRANCHED POLYMER, RESIST COMPOSITION, SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION METHOD - A method of synthesizing a hyperbranched polymer by living radical polymerization of a monomer in the presence of a metal catalyst includes at least adding a compound or setting the amount of the monomer in the living radical polymerization. The compound added is at least a compound represented by R08-18-2011
20090206451Semiconductor device - A semiconductor device is provided, in which a well contact diffusion layer pattern (08-20-2009
20110180907Organic Electronic Devices and Methods of Making the Same Using Solution Processing Techniques - A method of manufacturing an organic electronic device, the method comprising: providing a substrate; forming a well-defining structure over the substrate; and depositing a solution of organic semiconductive material and/or organic conductive material in wells defined by the well-defining structure, wherein the well-defining structure is formed by depositing a solution comprising a mixture of a first insulating material and a second insulating material, the second insulating material having a lower wettability than the first insulating material, and allowing the first and second insulating materials to at least partially phase separate wherein the second insulating material phase separates in a direction away from the substrate.07-28-2011
20110180906METHOD OF APPLYING A PATTERN OF METAL, METAL OXIDE AND/OR SEMICONDUCTOR MATERIAL ON A SUBSTRATE - A method of applying a pattern of metal, metal oxide, and/or semiconductor material on a substrate, a pattern created by that method, and uses of that pattern.07-28-2011
20110204484Sub-Wavelength Segmentation in Measurement Targets on Substrates - Measurement targets for use on substrates, and overlay targets are presented. The targets include an array of first regions alternating with second regions, wherein the first regions include structures oriented in a first direction and the second regions include structures oriented in a direction different from the first direction. The effective refractive index of the two sets of regions are thereby different when experienced by a polarized beam, which will act as a TM-polarized beam when reflected from the first set of regions, but as a TE-polarized beam when reflected from the second set of regions.08-25-2011
20090194849METHODS AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR WAFERS - Methods and apparatus for fabricating a semiconductor sheet are provided. In one aspect, a method for fabricating a semiconductor wafer includes applying a layer of semiconductor material across a portion of a setter material, introducing the setter material and the semiconductor material to a predetermined thermal gradient to form a melt, wherein the thermal gradient includes a predetermined nucleation and growth region, and forming at least one local cold spot in the nucleation and growth region to facilitate inducing crystal nucleation at the at least one desired location.08-06-2009
20100052105Free-standing thickness of single crystal material and method having carrier lifetimes - A method of fabricating a thickness of silicon material includes providing a silicon ingot material having a surface region and introducing a plurality of particles having an energy of about 1-5 MeV through the surface region to a depth to define a cleave region and a thickness of detachable material between the cleave region and the surface region. Additionally, the method includes processing the silicon ingot material to free the thickness of detachable material at a vicinity of the cleave region and causing formation of a free-standing thickness of material characterized by a carrier lifetime about 10 microseconds and a thickness ranging from about 20 microns to about 150 microns with a thickness variation of less than about five percent. Furthermore, the method includes treating the free-standing thickness of material using a thermal treatment process to recover the carrier lifetime to about 200 microseconds and greater.03-04-2010
20110193197STRUCTURE AND METHOD FOR MAKING CRACK STOP FOR 3D INTEGRATED CIRCUITS - A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.08-11-2011
20100148311SEMICONDUCTOR DEVICE - Patterns provided on a surface of a substrate include an adhesion area pattern and one or more non-adhesion area patterns. A chip electrode on a backside of a semiconductor chip is attached to the adhesion area pattern by a conductive adhesive. Consequently, an area of patterns subjected to gold plating that is stable in a steady state is smaller in a substrate of the present invention than in a conventional substrate, resulting in reduction in costs. Further, the chip electrode is attached to the adhesion area pattern by a conductive adhesive in a liquid form. Consequently, a semiconductor device of the present invention allows reducing use of an expensive conductive adhesive compared with a conventional semiconductor device, resulting in reduction in costs.06-17-2010
20130037915Method and Apparatus for Providing a Layout Defining a Structure to be Patterned onto a Substrate - A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate.02-14-2013
20120175742EPITAXIAL STRUCTURE AND METHOD FOR MAKING THE SAME - An epitaxial structure and a method for making the same are provided. The epitaxial structure includes a substrate, an epitaxial layer and a carbon nanotube layer. The epitaxial layer is located on the substrate. The carbon nanotube layer is located in the epitaxial layer. The method includes following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is suspended above the epitaxial growth surface. An epitaxial layer is epitaxially grown from the epitaxial growth surface to enclose the carbon nanotube layer therein.07-12-2012
20090057839POLYMER-EMBEDDED SEMICONDUCTOR ROD ARRAYS - A structure consisting of well-ordered semiconductor structures embedded in a binder material which maintains the ordering and orientation of the semiconductor structures. Methods for forming such a structure include forming the semiconductor structures on a substrate, casting a binder material onto the substrate to embed the semiconductor structures in the binder material, and separating the binder material from the substrate at the substrate. These methods provide for the retention of the orientation and order of highly ordered semiconductor structures in the separated binder material.03-05-2009
20130043564ATTACHING A MEMS TO A BONDING WAFER - A MEMS is attached to a bonding wafer in part by forming a support layer over the MEMS. A first eutectic layer is formed over the support layer. The eutectic layer is patterned into segments to relieve stress. A second eutectic layer is formed over the bonding wafer. A eutectic bond is formed with the segments and the second eutectic layer to attach the bonding wafer to the MEMS.02-21-2013
20100044837REPLICATION AND TRANSFER OF MICROSTRUCTURES AND NANOSTRUCTURES - A method for the duplication of microscopic patterns from a master to a substrate is disclosed, in which a replica of a topographic structure on a master is formed and transferred when needed onto a receiving substrate using one of a variety of printing or imprint techniques, and then dissolved. Additional processing steps can also be carried out using the replica before transfer, including the formation of nanostructures, microdevices, or portions thereof. These structures are then also transferred onto the substrate when the replica is transferred, and remain on the substrate when the replica is dissolved. This is a technique that can be applied as a complementary process or a replacement for various lithographic processing steps in the fabrication of integrated circuits and other microdevices.02-25-2010
20090160028METHOD FOR FORMING GAPS IN MICROMECHANICAL DEVICE AND MICROMECHANICAL DEVICE - An exemplary method for forming gaps in a micromechanical device includes providing a substrate. A first material layer is deposited over the substrate. A sacrificial layer is deposited over the first material layer. A second material layer is deposited over the sacrificial layer such that at least a portion of the sacrificial layer is exposed. The exposed portion of the sacrificial layer is etched by dry etching. The remaining portion of the sacrificial layer is etched by wet etching to form gaps between the first material layer and the second material layer. One or more bulges are formed at one side of the second material layer facing the first material layer, and are a portion of the sacrificial layer remaining after the wet etching.06-25-2009
20100109127Semiconductor Constructions - Some embodiments include methods of reflecting ions off of vertical regions of photoresist mask sidewalls such that the ions impact foot regions along the bottom of the photoresist mask sidewalls and remove at least the majority of the foot regions. In some embodiments, trenches may be formed adjacent the photoresist mask sidewalls in a material that is beneath the photoresist mask. Another material may be formed to have projections extending into the trenches. Such projections may assist in anchoring said other material to the material that is beneath the photoresist mask. In some embodiments, the photoresist mask is utilized for patterning flash memory structures. Some embodiments include semiconductor constructions having materials anchored to underlying materials through fang-like projections.05-06-2010
20130082358SINGLE CRYSTAL SUBSTRATE WITH MULTILAYER FILM, MANUFACTURING METHOD FOR SINGLE CRYSTAL SUBSTRATE WITH MULTILAYER FILM, AND ELEMENT MANUFACTURING METHOD - In order to correct warpage that occurs in formation of a multilayer film, provided are a single crystal substrate with a multilayer film, a manufacturing method therefor, and an element manufacturing method using the manufacturing method. The single crystal substrate with a multilayer film includes: a single crystal substrate (04-04-2013
20100006982METHOD OF PRODUCING SEMICONDUCTOR WAFER - There is provided a method of producing a semiconductor wafer which is high in the beveling accuracy and the yield for large-size wafers having a diameter of not less than 450 mm, comprising a slicing step for cutting out a disc-shaped wafer having a diameter of not less than 450 mm from a single crystal ingot, a step for lapping a surface of the wafer to conduct planarization, a step for beveling an edge portion of the wafer, a step for grinding the surface of the wafer and a step for mirror-polishing the surface of the wafer, wherein the planarizing step performs the lapping with free abrasive grains of #1000 to #1500.01-14-2010
20130087890METHOD FOR FABRICATING OPTICAL SEMICONDUCTOR TUBES AND DEVICES THEREOF - Semiconductor micro- and nanotubes allow the incorporation of ordered structures such as quantum wells and quantum dots into them providing the potential for ultralow threshold micro- and nanoscale lasers for use in applications such as future ultrahigh-speed photonic systems as well as quantum information processing. According to the invention a means of manufacturing these with high reproducibility, low processing complexity, and at high densities is provided. Also provided is a means of releasing these micro- and nanotubes with low stress and a method of “pick-and-place” allowing micro- and nanotubes to be exploited in devices integrated on substrates that are either incompatible with the manufacturing technique or where the area of substrate required to manufacture them is detrimental to the cost or performance of the circuit.04-11-2013
20120181667SOLAR CELL AND METHOD FOR MANUFACTURING SUCH A SOLAR CELL - A method for manufacturing a solar cell from a semiconductor substrate (07-19-2012
20120181666SILICON DEVICE AND SILICON DEVICE MANUFACTURING METHOD - A silicon device has a flat panel shape which is a polygon in a plan view, and at least one corner of the polygon includes two sides adjacent to each other out of plural sides of the polygon and a corner curve portion connected to the two sides so as to connect the two sides.07-19-2012
20100327416Laser beam machining method, laser beam machining apparatus, and laser beam machining product - It is an object to provide a laser beam machining method which can easily cut a machining target. The laser beam machining method irradiates laser light while positioning a focus point at the inside of a machining target to thereby form a treated area based on multiphoton absorption along a planned cutting line of the machining target inside the machining target and also form a minute cavity at a predetermined position corresponding to the treated area in the machining target.12-30-2010
20100133659SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP - A semiconductor device including a plurality of circuit regions formed in a semiconductor substrate and a scribe region formed around the circuit regions for separating the respective circuit regions, the scribe region having a plurality of laminated interlayer films including a plurality of metal films and an optically-transparent insulation film formed between and on the plurality of metal films, wherein a first metal film included in a first upper interlayer film of the plurality of interlayer films is positionally offset in a vertical direction to a second metal film included in a second lower interlayer film under the first interlayer film.06-03-2010
20120217619SEMICONDUCTOR DEVICE WITH TRIANGLE PRISM PILLAR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a triangle prism pillar having a first, a second, and a third sidewall surface, a bit line contacted with the first sidewall surface of the pillar, and a word line adjacent to the second sidewall surface of the pillar over the bit line.08-30-2012
20130069204Method and Apparatus to Control Surface Texture Modification of Silicon Wafers for Photovoltaic Cell Devices - A method and apparatus to modify the surface structure of a silicon substrate or deposited silicon layer in a controllable manner using gas only in an atmospheric environment, suitable for making photovoltaic (PV) wafer based devices. The method and apparatus comprising the steps of disposing the substrate or deposited layer on a moveable carrier; pre-heating the substrate or deposited layer; and moving the substrate or deposited layer for etching through an atmospheric reactor; under an etchant delivering module inside the reactor and applying at least one etchant in gas form at a controlled flow rate and angle to the substrate or deposited layer in the reactor, wherein the at least one etchant gas is selected from the group comprising fluoride-containing gases and chlorine-based compounds. The technical problem that has been solved is the provision of a high throughput dry etching method at atmospheric pressure. This apparatus does not require plasma to aid the etching process using fluoride-containing gases and chlorine-based compounds and is performed at open atmospheric pressure. The use of elemental fluorine, which has a significantly lower bonding energy than any of the other etchants used to date, allows for the use of much lower power energy source to crack the elemental fluorine in to its etching radicals. The apparatus enables the delivery of a predetermined texture finish by controlling the flow rate of the gasses which are bombarded on the surface of the substrate.03-21-2013
20130056857DEVICE CHIP AND MANUFACTURING METHOD THEREFOR - A manufacturing method for a device chip having a substrate, a device formed on the front side of the substrate, and chip identification information marked inside the substrate includes preparing a device wafer having a base wafer and a plurality of devices formed on the front side of the base wafer so as to be partitioned by division lines, next applying a laser beam having a transmission wavelength to the device wafer from the back side thereof in the condition where the focal point of the laser beam is set inside the base wafer at the positions respectively corresponding to the devices, thereby forming a plurality of modified layer marks as the chip identification information inside the base wafer at the positions respectively corresponding to the devices, and finally dividing the device wafer along the division lines to obtain a plurality of device chips.03-07-2013
20120112323APPARATUS AND METHOD FOR CONTROLLED PARTICLE BEAM MANUFACTURING - A chamber for exposing a workpiece to charged particles includes a charged particle source for generating a stream of charged particles, a collimator configured to collimate and direct the stream of charged particles from the charged particle source along an axis, a beam digitizer downstream of the collimator configured to create a digital beam including groups of at least one charged particle by adjusting longitudinal spacing between the charged particles along the axis, a deflector downstream of the beam digitizer including a series of deflection stages disposed longitudinally along the axis to deflect the digital beams, and a workpiece stage downstream of the deflector configured to hold the workpiece.05-10-2012
20120112322Seal Ring in an Integrated Circuit Die - The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.05-10-2012
20120112321ALKALINE ETCHING LIQUID FOR TEXTURING A SILICON WAFER SURFACE - An etching liquid for texturing a silicon wafer surface is provided. The etching liquid may include an aqueous solution of at least one alkaline etching agent and at least one polysaccharide or derivative thereof. Also provided is a process for texture etching a silicon wafer using the etching liquid of the invention.05-10-2012
20130113082METHOD OF FORMING PATTERN AND DEVELOPER FOR USE IN THE METHOD - Provided is a method of forming a pattern, including (a) forming a chemically amplified resist composition into a film, (b) exposing the film to light, (c) developing the exposed film with a developer containing an organic solvent, and (d) rinsing the developed film with a rinse liquid containing an organic solvent, which rinse liquid has a specific gravity larger than that of the developer.05-09-2013
20100084745Nitride semiconductor substrate - A nitride semiconductor substrate has a first surface forming a principal surface of the substrate. A first edge is formed by beveling at least a portion of an edge of the first surface of the substrate. A scattering region is formed in at least a portion of the first edge. The scattering region scatters more external incident light than the first surface.04-08-2010
20100084744Thermal processing of substrates with pre- and post-spike temperature control - Provided are apparatuses and method for the thermal processing of a substrate surface, e.g., controlled laser thermal annealing (LTA) of substrates. The invention typically involves irradiating the substrate surface with first and second images to process regions of the substrate surface at a substantially uniform peak processing temperature along a scan path. A first image may serve to effect spike annealing of the substrates while another may be used to provide auxiliary heat treatment to the substrates before and/or after the spike annealing. Control over the temperature profile of the prespike and/or postspike may also reduce stresses and strains generated in the wafers. Also provided are microelectronic devices formed using the inventive apparatuses and methods.04-08-2010
20130062735METHOD FOR FORMING STAIR-STEP STRUCTURES - A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.03-14-2013
20110012236EVALUATION OF AN UNDERCUT OF DEEP TRENCH STRUCTURES IN SOI WAFERS - A technique is provided which enables quantitative evaluation of an undercutting of deep trench structures in semiconductor wafers and, in particular, SOI wafers, by means of electrical or optical measuring. A specific control structure (01-20-2011
20120193762REVERSAL LITHOGRAPHY APPROACH BY SELECTIVE DEPOSITION OF NANOPARTICLES - A novel reversal lithography process without etch back is described. The reversal material comprises nanoparticles that are selectively deposited into the gaps between features without overcoating the tops of the features. As a result, a patterned imaging layer can be removed using solvent, blanket exposure followed by developer washing, or dry etching directly, without an etch-back process, and the original bright field lithography pattern can be reversed into dark field features, and transferred into subsequent layers using the nanoparticle reversal material as an etch mask.08-02-2012
20090236697SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.09-24-2009
20090014842FEMTOSECOND LASER-INDUCED FORMATION OF SUBMICROMETER SPIKES ON A SEMICONDUCTOR SUBSTRATE - The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes placing at least a portion of a surface of the substrate in contact with a fluid, and exposing that surface portion to one or more femtosecond pulses so as to modify the topography of that portion. The modification can include, e.g., generating a plurality of submicron-sized spikes in an upper layer of the surface.01-15-2009
20090267192CMP METHODS AVOIDING EDGE EROSION AND RELATED WAFER - Methods of avoiding chemical mechanical polish (CMP) edge erosion and a related wafer are disclosed. In one embodiment, the method includes providing a wafer; forming a first material across the wafer; forming a second material at an outer edge region of the wafer, leaving a central region of the wafer devoid of the second material; and performing chemical mechanical polishing (CMP) on the wafer. The second material diminishes CMP edge erosion.10-29-2009
20090026584METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device which includes fine patterns having various critical dimensions (CDs) by adjusting a thickness of spacer used as an etching mask in Spacer Patterning Technology (SPT). The method for manufacturing a semiconductor device includes forming spacers at a different level over an etching target layer and etching the etching target layer exposed among the spacers.01-29-2009
20120235283SILICON ON INSULATOR STRUCTURES HAVING HIGH RESISTIVITY REGIONS IN THE HANDLE WAFER - Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps.09-20-2012
20120235282SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device manufacturing method is disclosed. The method comprises (a) forming cut grooves in a front surface of a semiconductor wafer on which semiconductor elements are formed to partition the front surface into a plurality of regions, (b) disposing partly a resin in the cut grooves, (c) adhering a protection tape on the front surface of the semiconductor wafer, (d) thinning the semiconductor wafer by grinding a rear surface of the semiconductor wafer to reach the cut grooves, (e) forming an adhesive agent layer on the rear surface of the semiconductor wafer, and (f) dividing the semiconductor wafer into a plurality of semiconductor chips by cutting the adhesive agent layer together with the disposed resin along the cut grooves.09-20-2012
20100013058Semiconductor Wafer and Semiconductor Wafer Inspection Method - Affords semiconductor wafers that achieve uniformization of semiconductor films. In a semiconductor wafer (01-21-2010
20120098103METHOD FOR FORMING RESIST PATTERN, SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - A method for producing a semiconductor device includes forming a resist pattern by coating a resist pattern thickening material to cover the surface of the resist pattern, baking the resist pattern thickening material, and developing and separating the resist pattern thickening material, wherein at least one of the coating, the baking and the developing is carried out plural times.04-26-2012
20100032806EPITAXIAL SILICON WAFER AND PRODUCTION METHOD THEREOF - Provided are an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one, and a production method thereof.02-11-2010
20090206452METHOD AND SYSTEM FOR CREATING SELF-ALIGNED TWIN WELLS WITH CO-PLANAR SURFACES IN A SEMICONDUCTOR DEVICE - A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.08-20-2009
20100171195THIN FILM SILICON WAFER AND METHOD FOR MANUFACTURING THE SAME - Provided are a thin film silicon wafer having high gettering capability, a manufacturing method therefor, a multi-layered silicon wafer formed by laminating the thin film silicon wafers, and a manufacturing method therefor. The thin film silicon wafer is manufactured by: forming one or more gettering layers immediately below a device layer which is formed in a vicinity of a front surface of a semiconductor silicon wafer; fabricating a device in the device layer of the semiconductor silicon wafer; and after the device has been fabricated, removing part of the semiconductor silicon wafer from a rear surface thereof to immediately below the gettering layers so as to leave at least one of the gettering layers in place. As a result, the thin film silicon wafer is allowed to have gettering capability even after having been reduced in thickness to be in a thin film form.07-08-2010
20120139085Structure and Method for Topography Free SOI Integration - A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.06-07-2012
20120181668INK JET PRINTABLE ETCHING INKS AND ASSOCIATED PROCESS - The present invention refers to a method for contactless deposition of new etching compositions onto surfaces of semiconductor devices as well as to the subsequent etching of functional layers being located on top of these semiconductor devices. Said functional layers may serve as surface passivation layers and/or anti-reflective coatings (ARCs).07-19-2012
20110284994Electrically Broken, but Mechanically Continuous Die Seal for Integrated Circuits - A semiconductor die has multiple discontinuous conductive segments arranged around a periphery of the semiconductor die, and an electrically insulating barrier within discontinuities between the conductive segments. The conductive segments and the barriers form a mechanically continuous seal ring around the semiconductor die.11-24-2011
20110298094EPITAXIAL WAFER AND METHOD OF PRODUCING THE SAME - An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices.12-08-2011
20110298093Thermal Processing of Substrates with Pre- and Post-Spike Temperature Control - Provided are apparatuses and method for the thermal processing of a substrate surface, e.g., controlled laser thermal annealing (LTA) of substrates. The invention typically involves irradiating the substrate surface with first and second images to process regions of the substrate surface at a substantially uniform peak processing temperature along a scan path. A first image may serve to effect spike annealing of the substrates while another may be used to provide auxiliary heat treatment to the substrates before and/or after the spike annealing. Control over the temperature profile of the prespike and/or postspike may also reduce stresses and strains generated in the wafers. Also provided are microelectronic devices formed using the inventive apparatuses and methods.12-08-2011
20100090315FILM FORMING METHOD, FILM FORMING APPARATUS, STORAGE MEDIUM AND SEMICONDUCTOR DEVICE - Provided is a film forming method comprising: placing a substrate on a loading portion inside a processing chamber; supplying a gas for generating plasma, which is excited by microwaves, into the processing chamber; evacuating an inside of the processing chamber; supplying a C04-15-2010
20110291244SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a wiring substrate having an insulating film formed on a surface thereof, a first semiconductor chip mounted on the wiring substrate, and a second semiconductor chip stacked and mounted on the first semiconductor chip so as to form an overhang portion. The insulating film is removed from an area of the wiring substrate that faces the overhang portion.12-01-2011
20110291243PLANARIZING ETCH HARDMASK TO INCREASE PATTERN DENSITY AND ASPECT RATIO - Methods for manufacturing a semiconductor device in a processing chamber are provided. In one embodiment, a method includes depositing over a substrate a first base material having a first set of interconnect features, filling an upper portion of the first set of interconnect features with an ashable material to an extent capable of protecting the first set of interconnect features from subsequent processes while being easily removable when desired, planarizing an upper surface of the first base material such that an upper surface of the ashable material filled in the first set of interconnect features is at the same level with the upper surface of the first base material, providing a substantial planar outer surface of the first base material, depositing a first film stack comprising a second base material on the substantial planar outer surface of the first base material, forming a second set of interconnect features in the second base material, wherein the second set of interconnect features are aligned with the first set of interconnect features, and removing the ashable material from the first base material, thereby extending a feature depth of the semiconductor device by connecting the second set of interconnect features to the first set of interconnect features. In another embodiment, a method includes providing a base material having a first film stack deposited thereon, wherein the base material is formed over the substrate and having a first set of interconnect features filled with an amorphous carbon material, the first film stack comprising a first amorphous carbon layer deposited on a surface of the base material, a first anti-reflective coating layer deposited on the first amorphous carbon layer, and a first photoresist layer deposited on the first anti-reflective coating layer, and patterning a portion of the first photoresist layer by shifting laterally a projection of a mask on the first photoresist layer relative to the substrate a desired distance, thereby introducing into the first photoresist layer a first feature pattern to be transferred to the underlying base material, wherein the first feature pattern is not aligned with the first set of interconnect features.12-01-2011
20090321886EPITAXIAL LIFT OFF STACK HAVING A UNIDIRECTIONALLY SHRUNK HANDLE AND METHODS THEREOF - Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming an ELO thin film is provided which includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a unidirectionally induced-shrinkage support handle onto the epitaxial material, and shrinking the support handle tangential to reinforcement fibers therein to form tension in the support handle and compression in the epitaxial material during the shrinking process. The unidirectionally induced-shrinkage support handle contains a shrinkable material and reinforcement fibers extending unidirectional throughout the shrinkable material. The method further includes removing the sacrificial layer during an etching process, peeling the epitaxial material from the substrate while forming an etch crevice therebetween, and bending the support handle to have substantial curvature.12-31-2009
20100264520SEMICONDUCTOR MODULE - Provided is a semiconductor module wherein a stress relaxing layer is arranged between a ceramic substrate, upon which semiconductor elements are mounted, and a cooling device on the rear side of the ceramic substrate; and the ceramic substrate, the cooling device and the stress relaxing layer are integrally formed. Furthermore, the stress relaxing layer is separated into a plurality of separated sections by two slits. Furthermore, the slits are positioned between the semiconductor elements when viewed from the thickness direction of the stress relaxing layer and not in a projection region of the semiconductor element.10-21-2010
20120032308GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS - Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.02-09-2012
20090189255WAFER HAVING HEAT DISSIPATION STRUCTURE AND METHOD OF FABRICATING THE SAME - A wafer having a heat dissipation structure is provided. The wafer having the heat dissipation structure includes a wafer and a number of metallic heat dissipation parts. The wafer has a first surface and a second surface opposite thereto. Besides, a number of blind holes are formed on the second surface of the wafer. The metallic heat dissipation parts are partially embedded in the blind holes respectively and protrude from the second surface of the wafer.07-30-2009
20090146259Sub-Resolution Assist Feature To Improve Symmetry for Contact Hole Lithography - A method of making a mask design having optical proximity correction features is provided. The method can include obtaining a target pattern comprising a plurality of target pattern features corresponding to a plurality of features to be imaged on a substrate. The method can also comprise generating a mask design comprising mask features corresponding to the plurality of features to be imaged on the substrate and controlling the aspect ratio of at least one of the features of the plurality of features to be imaged on the substrate by positioning a sub-resolution assist feature proximate to the corresponding mask feature.06-11-2009
20120228743Methods of Manufacturing Semiconductor Devices and Optical Proximity Correction - Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.09-13-2012
20090189254CIRCUIT CONNECTION STRUCTURE, METHOD FOR PRODUCING THE SAME AND SEMICONDUCTOR SUBSTRATE FOR CIRCUIT CONNECTION STRUCTURE - A circuit connection structure that exhibits excellent adhesiveness between a heat resistant resin film and a circuit adhesive member, even under high temperature and high humidity, is provided by introducing a chemically stable functional group into the heat resistant resin film by additional surface treatment to improve adhesiveness. In a circuit connection structure, a semiconductor substrate and a circuit member are adhered by a circuit adhesive member sandwiched therewith. First circuit electrode on the semiconductor substrate and second circuit electrode on the circuit member are connected electrically by conductive particles in the circuit adhesive member. A surface modification is given to the semiconductor substrate by plasma treatment using gas containing nitrogen, ammonia and the like. Therefore, the heat resistant resin film on the semiconductor substrate and the circuit adhesive member are firmly adhered for a long period of time even under high temperature and high humidity.07-30-2009
20090309192INTEGRATED CIRCUIT SYSTEM WITH SUB-GEOMETRY REMOVAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.12-17-2009
20090309191SEMICONDUCTOR DEVICE - A semiconductor device includes a wafer having a first surface opposite a second surface, and at least one laser irradiated region between the first and second surfaces. The laser irradiated region includes a laser-induced stress that is configured to minimize curvature of at least one of the first and second surfaces.12-17-2009
20100117199METHOD AND APPARATUS FOR THE PRODUCTION OF THIN DISKS OR FILMS FROM SEMICONDUCTOR BODIES - The invention relates to a method and an apparatus for the production of thin disks or films (05-13-2010
20110147896CLUSTER JET PROCESSING METHOD, SEMICONDUCTOR ELEMENT, MICROELECTROMECHANICAL ELEMENT, AND OPTICAL COMPONENT - A method for processing a sample using an electrically neutral reactive cluster is provided. The surface of a sample is processed by jetting out a mixed gas that is composed of a reactive gas and a gas with a boiling point lower than that of the reactive gas from a gas jetting part of a vacuum process room in which the sample is placed by a pressure in a range in which the mixed gas is not liquefied, in a predetermined direction, while adiabatically-expanding the mixed gas, thereby generating a reactive cluster and jetting the reactive cluster against the sample in the vacuum process room.06-23-2011
20100084746PROCESS FOR PRODUCING LAMINATED SUBSTRATE AND LAMINATED SUBSTRATE - A method of manufacturing a laminated substrate is provided. The method includes: forming an oxide film on at least a surface of a first substrate having a hardness of equal to or more than 150 GPa in Young's modulus, and then smoothing the oxide film; implanting hydrogen ions or rare gas ions, or mixed gas ions thereof from a surface of a second substrate to form an ion-implanted layer inside the substrate, laminating the first substrate and the second substrate through at least the oxide film, and then detaching the second substrate in the ion-implanted layer to form a laminated substrate, heat-treating the laminated substrate and diffusing outwardly the oxide film.04-08-2010
20090289331Semiconductor chip and semiconductor device, and method of manufacturing the same - At least a part of an outer edge of a surface where a circuit forming region, for example, of a semiconductor substrate that forms a semiconductor chip is arranged (a region surrounded by a scribe line around the circuit forming region) is cut or polished, so as to form a smooth slope is chamfered non-parallel and non-vertical to the circuit forming region. Then, a code indicating management information is assigned to the slope. Further, a plurality of semiconductor chips are stacked to manufacture a semiconductor device.11-26-2009
20090278235MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Provided is a manufacturing method of a semiconductor device, which is capable of realizing fine-pitch patterns and thus improving stabilization of patterning precision. The manufacturing method of the semiconductor device comprises forming a first photoresist pattern in a predetermined region on a substrate, depositing a thin film on the surface of the first photoresist pattern, and forming a second photoresist pattern in a region where the first photoresist pattern is not formed.11-12-2009
20090283868Structure Replication Through Ultra Thin Layer Transfer - Methods and apparatus for forming a product from ultra thin layers of a base material are disclosed. Some embodiments provide a process that allows one to structure a silicon base material, like the ingot, and to transfer this structure into a respective silicon process step. Some embodiments provide a process that allows one to structure any complex structured layer stacks, where the layers can be applied on top of each other using, e.g., bonding technology.11-19-2009
20090289332METHODS FOR MAKING SUBSTRATES AND SUBSTRATES FORMED THEREFROM - A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.11-26-2009
20090261456EPITAXIALLY COATED SILICON WAFER AND METHOD FOR PRODUCING EPITAXIALLY COATED SILICON WAFERS - A multiplicity of silicon wafers polished at least on their front sides are provided and successively coated individually in an epitaxy reactor by a procedure whereby one of the wafers is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow rate, and with addition of an etching medium to the hydrogen atmosphere at a reduced hydrogen flow rate in a second step, is subsequently coated epitaxially on its polished front side, and removed from the reactor. An etching treatment of the susceptor follows a specific number of epitaxial coatings. Silicon wafers produced thereby have a global flatness value GBIR of 0.07-0.3 μm relative to an edge exclusion of 2 mm.10-22-2009
20090261455METHOD FOR THE PRODUCTION OF A COMPONENT STRUCTURE - A method for the production of a component structure. On embodiment provides a semiconductor body having a first side. A first trench and a second trench are produced, which extend into the semiconductor body proceeding from the first side and are arranged at a distance from one another in a lateral direction of the semiconductor body. A first material layer in the first trench is produced. A third trench proceeding from the second trench is produced, extending as far as the first material layer in the first lateral direction.10-22-2009
20090008746METHOD OF FABRICATING SEMICONDUCTOR HIGH-VOLTAGE DEVICE - A semiconductor high-voltage device including a semiconductor substrate having a deep trench formed therein, a gate oxide film formed on sidewalls of the deep trench, a polysilicon layer formed in the deep trench and on the gate oxide film, and spacers formed on sidewalls of the trench at a portion of the deep trench above the gate oxide film. Loss of a gate oxide film can be prevented during processing, thereby also preventing a change of a current path, a phenomenon such as current leakage between a top surface of polysilicon and source/drain regions.01-08-2009
20100127354SILICON SINGLE CRYSTAL AND METHOD FOR GROWING THEREOF, AND SILICON WAFER AND METHOD FOR MANUFACTURING THEREOF - A method for growing a silicon single crystal having a hydrogen defect density of equal to or less than 0.003 pieces/cm05-27-2010
20080246121METHOD OF FABRICATING A DEVICE WITH A CONCENTRATION GRADIENT AND THE CORRESPONDING DEVICE - A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.10-09-2008
20090166809SEMICONDUCTOR DEVICE AND ITS MANUFACTURE - A reliable semiconductor device is provided which comprises lower and upper IGBTs 07-02-2009
20080277764Method of Manufacturing a Semiconductor Device Having a Buried Doped Region - A method of providing a region of doped semiconductor (11-13-2008
20080296733SEMICONDUCTOR WAFER ASSEMBLY AND METHOD OF PROCESSING SEMICONDUCTOR WAFER - A semiconductor wafer assembly includes a disk-shaped semiconductor wafer including on a face side thereof a flat area having a plurality of semiconductor devices formed thereon and a beveled surface disposed around the flat surface, and a circular adhesive film bonded to a reverse side of the semiconductor wafer. The adhesive film is bonded only to an area of the reverse side which is coextensive with the flat area.12-04-2008
20120292743SURFACE TREATMENT METHOD FOR ATOMICALLY FLATTENING A SILICON WAFER AND HEAT TREATMENT APPARATUS - In a silicon wafer which has a surface with a plurality of terraces formed stepwise by single-atomic-layer steps, respectively, no slip line is formed.11-22-2012
20090014841SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A first region having a first pattern which includes a first minimum dimension, a second region having a second pattern which includes a second minimum dimension larger the first minimum dimension, the second region being arranged adjacent to the first region, wherein a boundary between the first region and the second region is sectioned by a width which is twice of more of a minimum dimension which exists in an adjacent region.01-15-2009
20120139087SEMICONDUCTOR DEVICE - The semiconductor device includes: a semiconductor substrate; a pair of injection elements; an active barrier structure; and a p-type ground region. The semiconductor substrate has a main surface and a p-type region formed therein. The active barrier structure is arranged in a region sandwiched between the pair of injection elements over the main surface. The p-type ground region is a ground potential-applicable region which is formed closer to an end side of the main surface than the pair of injection elements and the active barrier structure, bypassing a region sandwiched between the pair of injection elements over the main surface, and which is electrically coupled to the p-type region. The p-type ground region is divided by a region adjacent to the region sandwiched between the pair of injection elements.06-07-2012
20080265376Ic Chip and Its Manufacturing Method - It is an object of the present invention to decrease a unit cost of an IC chip and to achieve the mass-production of IC chips. According to the present invention, a substrate having no limitation in size, such as a glass substrate, is used instead of a silicon substrate. This achieves the mass-production and the decrease of the unit cost of the IC chip. Further, a thin IC chip is provided by grinding and polishing the substrate such as the glass substrate.10-30-2008
20130119517Plasma Dicing and Semiconductor Devices Formed Thereof - In one embodiment, a method of forming a semiconductor device includes forming islands by forming deep trenches within scribe lines of a substrate. The islands have a first notch disposed on sidewalls of the islands. A first electrode stack is formed over a top surface of the islands. The back surface of the substrate is thinned to separate the islands. A second electrode stack is formed over a back surface of the islands.05-16-2013
20100270654SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, DRY-ETCHING PROCESS, METHOD FOR MAKING ELECTRICAL CONNECTIONS, AND ETCHING APPARATUS - A method for manufacturing a semiconductor device comprises dry-etching a thin film using a resist mask carrying patterns in which at least one of the width of each pattern and the space between neighboring two patterns ranges from 32 to 130 nm using a halogenated carbon-containing compound gas with the halogen being at least two members selected from the group consisting of F, I and Br. The ratio of at least one of I and Br is not more than 26% of the total amount of the halogen atoms as expressed in terms of the atomic compositional ratio to transfer the patterns onto the thin film. Such etching of a thin film avoids causing damage to the resist mask used. The resulting thin film carrying the transferred patterns is used as a mask for subjecting the underlying material to dry-etching.10-28-2010
20110006402METHODS TO REDUCE THE CRITICAL DIMENSION OF SEMICONDUCTOR DEVICES AND RELATED SEMICONDUCTOR DEVICES - A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to foil the features on the target layer. A partially fabricated integrated circuit device is also disclosed.01-13-2011
20080258265METHODS FOR FORMING AN ASSEMBLY FOR TRANSFER OF A USEFUL LAYER - Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral recess on the first support below the interface so that the periphery of the interface is exposed to facilitate removal and transfer of the useful layer. An epitaxial layer can be formed on the useful layer after forming the recess, with the width and depth of the recess being sufficient to accommodate the volume of residual material resulting from formation of the epitaxial layer without covering the periphery of the interface. Alternatively, an epitaxial layer can be formed on the useful layer after forming the recess, wherein the peripheral recess is configured for receiving sufficient residual material from the epitaxial layer to prevent bonding between the residual material and the useful layer.10-23-2008
20100270652DOUBLE EXPOSURE TECHNOLOGY USING HIGH ETCHING SELECTIVITY - Ultrafine patterns with dimensions smaller than the chemical and optical limits of lithography are formed by superimposing two photoresist patterns using a double exposure technique. Embodiments include forming a first resist pattern over a target layer to be patterned, forming a protective cover layer over the first resist pattern, forming a second resist pattern on the cover layer superimposed over the first resist pattern while the cover layer protects the first resist pattern, selectively etching the cover layer with high selectivity with respect to the first and second resist patterns leaving an ultrafine target pattern defined by the first and second resist patterns, and etching the underlying target layer using the superimposed first and second resist patterns as a mask.10-28-2010
20100270651Sapphire substrate with periodical structure - A sapphire substrate with periodical structure is disclosed, which comprises: a sapphire substrate, and at least one periodical structure formed on at least one surface of the sapphire substrate and having plural micro-cavities; wherein, the micro-cavities are arranged in an array, the micro-cavities are each in an inverted awl-shape, the length of the base line of the micro-cavities is 100˜2400 nm, and the depth of the micro-cavities is 25˜1000 nm.10-28-2010
20110266655SEMICONDUCTOR WAFER HAVING MULTILAYER FILM, METHOD FOR PRODUCING THE SAME, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor wafer having a multilayer film, in production of a semiconductor device by the steps of forming a porous layer on a surface of a semiconductor wafer by changing a surface portion into the porous layer, forming a semiconductor film on a surface of the porous layer to produce a semiconductor wafer having a multilayer film, fabricating a device on the semiconductor film, and producing the semiconductor device by delaminating the semiconductor film along the porous layer, the semiconductor film having the device formed thereon, including flattening the semiconductor wafer after delaminating and reusing the flattened semiconductor wafer, the method further including a thickness adjusting step of adjusting a whole thickness of the semiconductor wafer having a multilayer film to be produced by reusing the semiconductor wafer so as to satisfy a predetermined standard.11-03-2011
20100200957Scribe-Line Through Silicon Vias - A semiconductor wafer includes dies to be scored from the semiconductor wafer. The semiconductor wafer also includes scribe-lines between the dies. Each scribe-line includes multiple through silicon vias.08-12-2010
20100193917METHODS OF ISOLATING ARRAY FEATURES DURING PITCH DOUBLING PROCESSES AND SEMICONDUCTOR DEVICE STRUCTURES HAVING ISOLATED ARRAY FEATURES - Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.08-05-2010
20090174036PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES - A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing.07-09-2009
20120139088SILICON WAFER AND METHOD FOR HEAT-TREATING SILICON WAFER - A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 06-07-2012
20090184399SYSTEM FOR AND METHOD OF MICROWAVE ANNEALING SEMICONDUCTOR MATERIAL - A system for and method of processing, i.e., annealing semiconductor materials. By controlling the time, frequency, variance of frequency, microwave power density, wafer boundary conditions, ambient conditions, and temperatures (including ramp rates), it is possible to repair localized damage lattices of the crystalline structure of a semiconductor material that may occur during the ion implantation of impurities into the material, electrically activate the implanted dopant, and substantially minimize further diffusion of the dopant into the silicon. The wafer boundary conditions may be controlled by utilizing susceptor plates (07-23-2009
20090212398Semiconductor device - A thin-film semiconductor element is formed on a plastic substrate in a semiconductor device. A thermal expansion buffer layer is interposed between the thin-film semiconductor element and the plastic substrate. Although the thin-film semiconductor element is made from a material with a thermal expansion coefficient differing from the thermal expansion coefficient of the plastic substrate, the thermal expansion buffer layer interposed between the thin-film semiconductor element and the plastic substrate protects the thin-film semiconductor element from damage caused by mechanical stress in the device fabrication process due to the different thermal expansion coefficients, enabling the semiconductor device to function reliably.08-27-2009
20090212397Ultrathin integrated circuit and method of manufacturing an ultrathin integrated circuit - A method of manufacturing an ultra thin integrated circuit comprises providing a substrate having a front side, a back side, and an edge extending from the front side to the back side; creating a defect layer in the substrate; forming semiconductor devices proximate the front side after creating the defect layer; and cleaving proximate the defect layer after forming the semiconductor devices. Other methods and apparatus are also provided.08-27-2009
20090212396Laser Beam Machining Method And Semiconductor Chip - A laser processing method is provided, which, when cutting a substrate formed with a multilayer part including a plurality of functional devices, makes it possible to cut the multilayer part with a high precision in particular.08-27-2009
20100264518WAFER AND METHOD FOR CONSTRUCTION, STRENGTHENING AND HOMOGENIZATION THEREOF - The present invention provides a water and a method for strengthening, homogenization and construction thereof. The concave and convex portions are processed by laser or etching, and then formed at intervals on the grinding surface of the wafer. The concave and convex portions are round or polygonal shapes. With the alternated arrangement of the concave and convex portions, a mesh structure of consistent construction is formed on the grinding surface of the wafer, making it possible to cut down greatly the interference and influence generated by the texture of grinding surface, and improve substantially the structural strength of the grinding surface for a consistent quality of wafer with better applicability and industrial benefits.10-21-2010
20090057837WAFER WITH EDGE NOTCHES ENCODING WAFER IDENTIFICATION DESCRIPTOR - An apparatus includes a semiconductor wafer having a surface terminating in an edge. A plurality of notches is defined along the edge. The plurality of notches encodes a wafer identification descriptor for the wafer. A system for identifying wafers includes a wafer sorter. The wafer sorter is adapted to scan at least a portion of a wafer including the plurality of notches and decode the scan of the plurality of notches to generate a wafer identification descriptor for the wafer.03-05-2009
20120104559Semiconductor Device Having Island Type Support Patterns - A semiconductor device includes a plurality of cylindrical structures arranged in a first direction and a second direction, and a plurality of unit regions formed in the first direction and the second direction, each of the plurality of unit regions including an island type support pattern supporting the plurality of cylindrical structures contacting side surfaces of the plurality of cylindrical structures and an open region exposing the side surfaces of the plurality of cylindrical structures.05-03-2012
20110140244METHOD FOR ROUTING A CHAMFERED SUBSTRATE - The invention relates to a method for routing a chamfered substrate, having applications in the field of electronics, optics, or optoelectronics, which involves depositing a layer of a protective material on a peripheral annular zone of the substrate preferably with the aid of a plasma, partially etching the protective material with the aid of a plasma, so as to preserve a protective ring of the deposited material on the front face of the substrate, this ring located at a distance from the edge of the substrate, so as to delimit an accessible peripheral annular zone, etching a thickness of the material constituting the substrate to be routed, preferably with the aid of a plasma that is level with the accessible peripheral annular zone of the substrate, and removing the ring of protective material preferably with the aid of a plasma.06-16-2011
20090102020WAFER AND METHOD FOR MANUFACTURING SAME - A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed upright along the circumference and a notch portion formed upright near the orientation notch, and a width of the circumferential portion as viewed parallel to a major surface of the wafer is smaller than a depth of the orientation notch as viewed parallel to the major surface.04-23-2009
20110227200ALIGNMENT STRUCTURES FOR INTEGRATED-CIRCUIT PACKAGING - A multi-chip module (MCM) that includes alignment features is described. This MCM includes at least two substrates having facing surfaces with positive features disposed on them. Note that a given positive feature on either of the surfaces protrudes above the surface. Furthermore, the two substrates are mechanically coupled by these positive features. In particular, a given one of the positive features on one of the surfaces mates with a given subset of the positive features on the other of the surfaces. Additionally, the given subset of the positive features includes two or more of the positive features.09-22-2011
20090160027Methods of Manufacturing Semiconductor Devices and Optical Proximity Correction - Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.06-25-2009
20090224370NON-PLANAR CVD DIAMOND-COATED CMP PAD CONDITIONER AND METHOD FOR MANUFACTURING - The present invention relates to a composite material having non-planar geometries and edge-shaving surfaces comprising a CVD diamond coating applied to a composite substrate made from a ceramic material and a preferably unreacted carbide-forming material of various configurations and for a variety of applications.09-10-2009
20090256242METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE STORAGE ELEMENT IN A TRENCH OF A WORKPIECE - A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.10-15-2009
20110227202SILICON WAFER AND FABRICATION METHOD THEREOF - A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 μm to approximately 80 μm from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.09-22-2011
20100264519GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPRAOCH TO TARGET CD FOR SELECTED TRANSISTORS - Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.10-21-2010
20090250791Crystalline Semiconductor Stripes - Crystalline semiconductor stripes and an associated fabrication process are provided. The method provides an insulator substrate, and deposits a semiconductor layer overlying the insulator substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, oriented crystalline semiconductor stripes are formed on the insulator substrate. The crystalline semiconductor stripes are aligned approximately with a straight line stripe axis overlying a top surface of the insulating substrate. Each crystalline semiconductor stripe includes a plurality of consecutive ring segments aligned with the stripe axis. The rings segments have a width about equal to the laser annealing process step distance. The crystalline semiconductor stripes typically have a top surface shape of a truncated cylinder or a parabolic cross section.10-08-2009
20120193764NANOSTRUCTURING PROCESS FOR INGOT SURFACE, WAFER MANUFACTURING METHOD, AND WAFER USING THE SAME - The instant disclosure relates to a nanostructuring process for an ingot surface prior to the slicing operation. A surface treatment step is performed for at least one surface of the ingot in forming a nanostructure layer thereon. The nanostructure layer is capable of enhancing the mechanical strength of the ingot surface to reduce the chipping ratio of the wafer during slicing.08-02-2012
20120193763METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND RESIST COATER - To provide a method of manufacturing a semiconductor device with reduced generation of humps, a semiconductor device with reduced generation of humps, and a resist coater. An inactive liquid such as pure water is discharged at a predetermined pressure from a nozzle for discharging fluid for processing hump while spinning the semiconductor substrate to spray a region where a hump is generated. The hump is crushed by spraying the inactive liquid at a high pressure onto the hump, and the film thickness of the bottom-layer resist becomes almost uniform across the entire semiconductor substrate.08-02-2012
20100013056SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention prevents a fracture parallel to a cleavage plane of a supporting substrate along a groove formed in the supporting substrate before dicing. A supporting substrate is attached to a front surface of a semiconductor substrate formed with an electronic device with an adhesive layer being interposed therebetween. In this supporting substrate, dicing lines are not parallel with cleavage planes which are perpendicular to the front surface of supporting substrate, i.e., a fifth cleavage plane and a sixth cleavage plane crossing perpendicularly thereto. A groove is then formed in the supporting substrate from the front surface to the middle thereof in the direction perpendicular to the front surface, along the dicing lines inside an opening provided in the semiconductor substrate. This groove is not parallel with the fifth cleavage plane and the sixth cleavage plane. After given processes, dicing is performed to the layered body of layers from the semiconductor substrate to the supporting substrate along the dicing lines.01-21-2010
20100155904SEMICONDUCTOR DEVICE HAVING CMP DUMMY PATTERN AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a CMP dummy pattern and a method for manufacturing the same are provided. The warpage of a wafer can be prevented by forming the CMP dummy pattern in the same direction and/or at the same angle as a pattern of a cell region. Accordingly, overlay error caused by etching residues is reduced, thereby improving the yield of the semiconductor device.06-24-2010
20110127643METHOD AND APPARATUS FOR CONFORMABLE POLISHING - A multi-station polish system and process for polishing thin, flat (planar) and rigid workpieces. Workpieces are conveyed through multiple polishing stations that include a bulk material removal belt polishing station and finishing rotary polishing station. The bulk of the material is relatively quickly removed at the bulk removal station using a conformable abrasive belt and the workpiece surface is then polished to the desired finish at the finishing station using a conformable annular rotary polishing pad.06-02-2011
20100155905SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A device portion forming step includes an assisting layer forming step of forming a planarization assisting layer, which covers a plurality of conductive films, over a first planarizing layer before forming a second planarizing layer. In the assisting layer forming step, the planarization assisting layer is formed so that a height of the planarization assisting layer from a surface of the first planarizing layer located on a side opposite to the substrate layer becomes equal between at least a part of a region where the conductive films are formed, and at least a part of a region where no conductive film is formed.06-24-2010
20100187658MULTI-MATERIAL HARD MASK OR PREPATTERNED LAYER FOR USE WITH MULTI-PATTERNING PHOTOLITHOGRAPHY - A method of fabricating integrated circuits is described. A multi-material hard mask is formed on an underlying layer to be patterned. In a first patterning process, portions of the first material of the hard mask are etched, the first patterning process being selective to etch the first material over the second material. In a second patterning process, portions of the second material of the hard mask are etched, the second patterning process being selective to etch the second material over the first material. The first and second patterning processes forming a desired pattern in the hard mask which is then transferred to the underlying layer.07-29-2010
20100176491Epitaxially Coated Silicon Wafer and Method For Producing Epitaxially Coated Silicon Wafers - Silicon wafers polished on their front sides are individually placed on a susceptor in an epitaxy reactor and firstly pretreated under a hydrogen atmosphere, and secondly with addition of an etching medium with a flow rate of 1.5-5 slm to the hydrogen atmosphere, the hydrogen flow rate being 1-100 slm in both steps, and subsequently epitaxially coated on the polished front side, and then removed from the reactor. In a second method, gas flows introduced into the reactor by injectors are distributed into outer and inner zones of the chamber, such that the inner zone gas flow acts on a wafer central region and the outer zone gas flow acts on a wafer edge region, the inner/outer distribution of the etching medium I/O=0-0.75. Silicon wafers having an epitaxial layer having global flatness value GBIR of 0.02-0.06 μm, relative to an edge exclusion of 2 mm are produced.07-15-2010
20100193913METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes forming an aluminum layer on a core substrate, anodizing the aluminum layer into an alumina layer having a plurality of nanoholes, forming an n-type GaN layer by growing crystals of a compound semiconductor such as an n-type GaN on the alumina layer and inside the nanoholes, and dissolving the alumina layer with an acid. As a result, gaps are formed and a structure in which the core substrate is joined to the n-type GaN layer through portions, other than the gaps, having a very small area is generated. Then a laser beam is applied to the n-type GaN layer through the core substrate to separate the n-type GaN layer from the core substrate by a laser lift-off technique.08-05-2010
20090079037Micromechanical component and method for producing a micromechanical component - A micromechanical component, in particular a micromechanical sensor, having a first wafer and a second wafer is provided, the first wafer having at least one structural element, and the second wafer having at least one mating structural element, and, in addition, the structural element and the mating structural element are designed in such a way that a relative displacement of the first wafer relative to the second wafer parallel to a main extension plane of the first wafer essentially leads to compressive loading or tensile loading between the structural element and the mating structural element.03-26-2009
20100193914Semiconductor device, method of manufacturing the same, and electronic apparatus - Disclosed is a method of manufacturing a semiconductor device including forming a transistor on a first surface of a device substrate, forming a hole in a second surface opposite to the first surface of the device substrate, and supplying hydrogen to a gate insulating film of the transistor from the second surface of the device substrate through the hole.08-05-2010
20100258915SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. An epitaxial layer is formed on a semiconductor substrate. A semiconductor element is formed in the epitaxial layer. The semiconductor substrate is removed from the epitaxial layer.10-14-2010
20120032307SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a CSP type semiconductor device, the invention prevents a second wiring from forming a narrowed portion on a lower surface of a step portion at the time of forming the second wiring that is connected to the back surface of a first wiring formed near a side surface portion of a semiconductor die on the front surface and extends onto the back surface of the semiconductor die over the step portion of a window that is formed from the back surface side of the semiconductor die so as to expose the back surface of the first wiring. A glass substrate is bonded on a semiconductor substrate on which a first wiring is formed on the front surface near a dicing line with an adhesive resin being interposed therebetween. The semiconductor substrate is then etched from the back surface to form a window having step portions with inclined sidewalls around the dicing line as a center. A second wiring is then formed so as to be connected to the first wiring exposed in the window and extend onto the back surface of the semiconductor substrate over the step portions of the window except part of the step portions on the dicing line and near the dicing line, which extend perpendicular to the dicing line.02-09-2012
20100258914SURFACE MOUNTABLE SEMICONDUCTOR BRIDGE DIE - A semiconductor bridge die may have an “H-design” or “trapezoidal” configuration in which a center bridge segment is flanked by one or more angled walls on each side of the bridge segment. Each wall is plated with a conductive material, thereby providing a continuous conductive path across the top surface of the die. A bottom surface of the die may be connected to a top surface of a header by epoxy in various configurations. The plated angled walls facilitate the solderable connection of the walls to a plated top surface of each of several pins on a top surface of the header, thereby providing a continuous electrical connection between the pins and the die. Also, a method is provided for manufacturing a semiconductor bridge die in accordance with the various embodiments of the die.10-14-2010
20100258913PATTERNING METHOD AND INTEGRATED CIRCUIT STRUCTURE - A patterning method is provided. First, a mask layer and a plurality of first transfer patterns are sequentially formed on a target layer. Thereafter, a plurality of second patterns is formed in the gaps between the first transfer patterns. Afterwards, a plurality of third transfer patterns is formed, wherein each of the third transfer patterns is in a gap between a first transfer pattern and a second transfer pattern adjacent to the first transfer pattern. A portion of the mask layer is then removed, using the first transfer patterns, the second transfer patterns and third transfer patterns as a mask, so as to form a patterned mask layer. Further, a portion of the target layer is removed using the patterned mask layer as a mask.10-14-2010
20120228742METHODS FOR FORMING ARRAYS OF SMALL, CLOSELY SPACED FEATURES - Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.09-13-2012
20100176492Method for Forming a Pattern on a Semiconductor Using an Organic Hard Mask - A composition for the organic hard mask includes a polyamic acid compound, and a method for forming a pattern is used in a manufacturing process of semiconductor devices by coating the composition for organic hard mask film on an underlying layer, and depositing a second hard mask film with a silicon nitride SiON film thereon to form a double hard mask film having an excellent etching selectivity, thereby obtaining a uniform pattern.07-15-2010
20100193916METHODS FOR INCREASED ARRAY FEATURE DENSITY - The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.08-05-2010
20100224964Epitaxially coated silicon wafer and method for producing an epitaxially coated silicon wafer - Epitaxially coated silicon wafers have a rounded and polished edge region and a region adjacent to the edge having a width of 3 mm on the front and rear sides, a surface roughness in edge region of 0.1-1.5 nm RMS relative to a spatial wavelength range of 10-80 μm, and a variation of surface roughness of 1-10%. The wafer edges, after polishing, are examined for defects and roughness at the edge and surrounding region. Silicon wafers having a surface roughness of less than 1 nm RMS are pretreated in single wafer epitaxy reactors, first in a hydrogen atmosphere at a flow rate of 1-100 slm and in a second step, an etching medium with a flow rate of 0.5-5 slm is conducted onto the edge region of the wafer by a gas distribution device. The wafer is then epitaxially coated.09-09-2010
20110001220LASER BEAM MACHINING METHOD AND SEMICONDUCTOR CHIP - A laser processing method is provided, which, when cutting a substrate formed with a multilayer part including a plurality of functional devices, makes it possible to cut the multilayer part with a high precision in particular.01-06-2011
20090294910SILICON WAFER - A reinforcement member made with silicon carbide different from silicon is installed on the back face of a silicon wafer, thereby the silicon wafer is increased in Young's modulus and the wafer is less likely to deflect.12-03-2009
20100219510METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST - A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern.09-02-2010
20100237470EPITAXIAL WAFER - An epitaxial wafer is provided capable of eliminating particles in a device process, particles being generated from scratches in a boundary area between a rear surface and a chamfered surface of a wafer. The number of scratches in the boundary area between the rear surface and the chamfered surface is small, and thus the number of particles generated from the scratches is reduced at a time of immersion in an etching solution in the device process. Thereby, a device yield is increased.09-23-2010
20120139086METHOD FOR REDUCING INTERMIXING BETWEEN FILMS OF A PATTERNING PROCESS, PATTERNING PROCESS, AND DEVICE MANUFACTURED BY THE PATTERNING PROCESS - An example embodiment relates to a patterning process including forming a photoresist pattern on a structure. The photoresist pattern includes a cross-linked surface that is insoluble in an organic solvent. The process also includes spin-on coating a dielectric layer on the photoresist pattern, partially removing the dielectric layer to form a plurality of dielectric spacers surrounding the photoresist pattern, and removing the photoresist pattern.06-07-2012
20100237469PHOTOMASK, SEMICONDUCTOR DEVICE, AND CHARGED BEAM WRITING APPARATUS - A photomask has a pattern formed by writing of a charged beam on basis of a charged beam control data. The charged beam control data is produced by: setting a plurality of correction points in a writing area on pattern data; performing a simulation of writing with a charged beam on basis of the pattern data to divide the writing area, at time of writing each of the correction points, into a written area of writing been already completed and an unwritten area of writing yet to be performed; deriving, for each of the correction points, a first charging amount distribution due to a fogging effect around each of the correction points using a subset of the pattern data belonging to the written area; deriving, for each of the correction points, a second charging amount distribution modified from the first charging amount distribution on basis of an effect by which the charging amount due to the fogging effect is reduced at a position irradiated with the charged beam; deriving amount of pattern displacement at each of the correction points on basis of the second charging amount distribution; and deriving correction parameters of pattern position on basis of the amount of pattern displacement.09-23-2010
20110006401METHOD AND SYSTEM FOR COMBINING PHOTOMASKS TO FORM SEMICONDUCTOR DEVICES - A photomask set includes at least two masks that combine to form a device pattern in a semiconductor device. Orthogonal corners may be produced in a semiconductor device pattern to include one edge defined by a first mask and an orthogonal edge defined by a second mask. The mask set may include a first mask with compensation features and a second mask with void areas overlaying the compensation features when the first and second masks are aligned with one another, such that the compensation features are removed when patterns are successfully formed from the first and second masks. The compensation features alleviate proximity effects during the formation of device features.01-13-2011
20110175205SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.07-21-2011
20090121321Wafer and a Method of Dicing a Wafer - A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.05-14-2009
20110057296DELAMINATION RESISTANT PACKAGED DIE HAVING SUPPORT AND SHAPED DIE HAVING PROTRUDING LIP ON SUPPORT - A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ≧5% less than a cross sectional area of the top surface to provide a protruding lip having a bottom lip surface. A package substrate includes a top substrate surface including substrate bonding sites, a bottom substrate surface, and a die support structure on the top substrate surface having a gap region. The bottom lip surface of the IC die is secured to the die support structure and the bottom surface of the IC die extends below the die support structure into the gap region. Coupling connectors couple the bonding features on the IC die to the substrate bonding sites.03-10-2011
20090321887METHOD OF FABRICATING AN ELECTROMECHANICAL STRUCTURE INCLUDING AT LEAST ONE MECHANICAL REINFORCING PILLAR - The invention relates to a method of fabricating an electromechanical structure presenting a first substrate (12-31-2009
20090321885EPITAXIAL LIFT OFF STACK HAVING A UNIVERSALLY SHRUNK HANDLE AND METHODS THEREOF - Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming an ELO thin film is provided which includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a universally shrinkable support handle onto the epitaxial material, wherein the universally shrinkable support handle contains a shrinkable material, and shrinking the support handle to form tension in the support handle and compression in the epitaxial material during a shrinking process. The method further includes removing the sacrificial layer during an etching process, peeling the epitaxial material from the substrate while forming an etch crevice therebetween, and bending the support handle to have substantial curvature.12-31-2009
20110233733METHOD OF FABRICATING A RELEASE SUBSTRATE - The invention relates to a release substrate produced from semiconductor materials, and which includes a first substrate release layer having a surface in contact with a connecting layer, and a second substrate release layer having a surface in contact with the connecting layer opposite the first substrate release layer so that the connecting layer is located between the first substrate release layer and second substrate release layer; and a concentrated zone of solid nanoparticles located within the connecting layer to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment while also facilitating breaking of the connecting layer by mechanical action.09-29-2011
20100219507PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - According to the invention, a process for producing a semiconductor device using an adhesive sheet for a spacer, comprising preparing an adhesive sheet having a spacer layer provided with an adhesive layer on at least one surface thereof as the adhesive sheet for a spacer, a step of sticking the adhesive sheet for a spacer onto a dicing sheet with the adhesive layer as a sticking surface, a step of dicing the adhesive sheet for a spacer to form a chip-shaped spacer provided with the adhesive layer, a step of peeling the spacer from the dicing sheet together with the adhesive layer, and a step of fixing the spacer onto an adherend with the adhesive layer interposed therebetween.09-02-2010
20090166808LASER PROCESSING METHOD AND SEMICONDUCTOR CHIP - A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision.07-02-2009
20090152682LINE ELEMENT AND METHOD OF MANUFACTURING LINE ELEMENT - An element capable of manufacturing various devices of any shape having plasticity or flexibility without being limited by shape and a method for manufacturing thereof are provided. An element characterized by that a circuit element is formed continuously or intermittently in the longitudinal direction. An element characterized by that a cross section having a plurality of areas forming a circuit is formed continuously or intermittently in the longitudinal direction.06-18-2009
20100219508SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate on which an internal circuit is formed in a central position an insulating layer formed over the semiconductor substrate, and a moisture-resistant ring formed by a metal plug embedded in the insulating layer, the moisture-resistant ring surrounding the internal circuit, the moisture-resistant ring extending over the semiconductor substrate in a shape, the moisture-resistant ring including a first extending portion linearly extending in a first direction in parallel to the surface of the semiconductor substrate, a vertical portion connected to the first extending portion extending in a second direction orthogonal to the first extending portion, and a second extending portion orthogonal to the vertical portion and parallel to the surface of the semiconductor substrate, the second extending portion spaced apart from the first extending portion, the second extending portion crossing the vertical portion.09-02-2010
20100219509TILED SUBSTRATES FOR DEPOSITION AND EPITAXIAL LIFT OFF PROCESSES - Embodiments of the invention generally relate to epitaxial lift off (ELO) films and methods for producing such films. Embodiments provide a method to simultaneously and separately grow a plurality of ELO films or stacks on a common support substrate which is tiled with numerous epitaxial growth substrates or surfaces. Thereafter, the ELO films are removed from the epitaxial growth substrates by an etching step during an ELO process. The tiled growth substrate contains the epitaxial growth substrates disposed on the support substrate may be reused to grow further ELO films. In one embodiment, a tiled growth substrate is provided which includes two or more gallium arsenide growth substrates separately disposed on a support substrate having a coefficient of thermal expansion within a range from about 5×1009-02-2010
20100295158Semiconductor Constructions - In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically etched spacers. The spacers are utilized to pattern lines in material underlying the spacers. Some embodiments include constructions having one or more openings which contain steep sidewalls joining to one another at shallow sidewall regions. The constructions may also contain lines along and directly against the steep sidewalls, and spaced from one another by gaps along the shallow sidewall regions.11-25-2010
20110127642PACKAGE INCLUDING AT LEAST ONE TOPOLOGICAL FEATURE ON AN ENCAPSULANT MATERIAL TO RESIST OUT-OF-PLANE DEFORMATION - Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, including a die and an encapsulant material formed over the die, and at least one topological feature formed on an external surface of the encapsulant material, and configured to resist out-of-plane deformation of the package. Other embodiments may be described and claimed.06-02-2011
20100308439DUAL WAVELENGTH EXPOSURE METHOD AND SYSTEM FOR SEMICONDUCTOR DEVICE MANUFACTURING - A dual wavelength exposure system provides for patterning a resist layer formed on a wafer for forming semiconductor devices, using two exposure operations, one including a first radiation having a first wavelength and the other including a second radiation including a second wavelength. Different or the same lithography tool may be used to generate the first and second radiation. For each die formed on the semiconductor device, a critical portion of the pattern is exposed using a first exposure operation that uses a first radiation with a first wavelength and a non-critical portion of the pattern is exposed using a second exposure operation utilizing the second radiation at a second wavelength. The resist material is chosen to be sensitive to both the first radiation having a first wavelength and the second radiation having the second wavelength.12-09-2010
20100301456METHOD FOR APPLYING A STRUCTURE TO A SEMICONDUCTOR ELEMENT - A method for applying a predetermined structure of a structural material to a semiconductor element. The method includes the following steps: A) partially covering a surface of the semiconductor element with a masking layer, B) applying a film of a structural material to the masking layer and to the surface of the semiconductor element in the zones that are devoid of the masking layer and C) removing the masking layer together with the structural material present on the masking layer. The method according to the invention provides that between process steps B and C, the film of structural material is partially removed in a process step B2.12-02-2010
20100301457Lithography Masks, Systems, and Manufacturing Methods - Lithography masks, lithography systems, methods of manufacturing lithography masks, methods of altering material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a lithography mask includes a first pattern for at least one material layer of at least one die, the first pattern being oriented in a first position. The lithography mask includes a second pattern for at least one material layer of the at least one die, the second pattern being oriented in a second position. The second position is different than the first position.12-02-2010
20100314721Semiconductor Package and Method for Producing the Same - A semiconductor package includes a rewiring substrate and a semiconductor chip. The semiconductor chip includes: a first face with an active surface including integrated circuit devices and chip contact pads, a second face lying in a plane essentially parallel to the first face and side faces. Each side face of the semiconductor chip lies in a plane essentially perpendicular to the first and second faces. At least one edge between two mutually essentially perpendicular faces of the semiconductor chip includes a surface.12-16-2010
20110121430METHOD FOR FORMING A SILICON DIOXIDE/METAL OXIDE-NANOLAMINATE WITH A DESIRED WET ETCH RATE - An atomic layer deposition-deposited silicon dioxide/metal oxide-nanolaminate, comprising at least one layer of silicon dioxide and at least one layer of a metal oxide, and having a wet etch rate in an etchant, said wet etch rate being either greater or smaller than both a wet etch rate of a film of silicon dioxide and a wet etch rate of a film of said metal oxide in said etchant. Also provided is a method for manufacturing the same.05-26-2011
20110121431Substrate Comprising a Nanometer-scale Projection Array - A method for forming a substrate comprising nanometer-scale pillars or cones that project from the surface of the substrate is disclosed. The method enables control over physical characteristics of the projections including diameter, sidewall angle, and tip shape. The method further enables control over the arrangement of the projections including characteristics such as center-to-center spacing and separation distance.05-26-2011
20110241172Charge Balance Techniques for Power Devices - A silicon wafer includes a silicon region of first conductivity type and a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from a location along a perimeter of the silicon wafer to an opposing location along the perimeter of the silicon wafer. The plurality of strips of second conductivity type pillars extend to a predetermined depth within the silicon region.10-06-2011
20110012237SPACER DOUBLE PATTERNING FOR LITHOGRAPHY OPERATIONS - Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the tilled pattern to remove portions of the final material beyond dimensions of the layout elements.01-20-2011
20110108956ETCHING PROCESS FOR SEMICONDUCTORS - A process for etching semiconductors, such as II-VI or III-V semiconductors is provided. The method includes sputter etching the semiconductor through an etching mask using a nonreactive gas, removing the semiconductor and cleaning the chamber with a reactive gas. The etching mask includes a photoresist. Using this method, light-emitting diodes with light extracting elements or nano/micro-structures etched into the semiconductor material can be fabricated.05-12-2011
20110024880NANO-PATTERNED SUBSTRATE AND EPITAXIAL STRUCTURE - A nano-patterned substrate includes a plurality of nano-particles or nanopillars on an upper surface thereof. A ratio of height to diameter of each of the nano-particles or each of the nanopillars is either greater than or equal to 1. Particularly, a ratio of height to diameter of the nanopillars is greater than or equal to 5. Each of the nano-particles or each of the nanopillars has an arc-shaped top surface. When an epitaxial growth process is applied onto the nano-patterned substrate to form an epitaxial layer, the epitaxial layer has very low defect density. Thus, a production yield of fabricating the subsequent device can be improved.02-03-2011
20110024881SEMICONDUCTOR DEVICE HAVING UNDER-FILLED DIE IN A DIE STACK - A semiconductor device including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack. The material used in the vapor deposition under-fill process may for example be a member of the parylene family of polymers, and in embodiments, may be parylene-N.02-03-2011
20090065901Semiconductor Element and Manufacturing Method Thereof - A semiconductor element and a manufacturing method of the semiconductor element are provided. A ridge waveguide type semiconductor integrated element includes: an electrode of an EA portion and an electrode of an LD portion which are arranged so as to be away from each other; a contact layer of the EA portion and a contact layer of the LD portion which are arranged so as to be away from each other and in each of which the electrode is formed on an upper surface and an edge of at least a part of the upper surface is set to the same electric potential as that of the electrode; a passivation film as an insulative concave/convex structure extending from an edge of one of the two contact layers to an edge of the other contact layer; and a polyimide resin for embedding the passivation film.03-12-2009
20110024879METHOD TO REDUCE PRE-ALIGNMENT ERROR USING MULTI-NOTCH PATTERN OR IN COMBINATION WITH FLAT SIDE - A semiconductor wafer has a pre-alignment pattern including two or more notches on the wafer edge and the notches are used for wafer pre-alignment in fabrication processes. In one embodiment, at least two distances along the wafer edge between any adjacent notches are different. In another embodiment, distances along the wafer edge between any adjacent notches are each different. In another aspect, the pre-alignment pattern includes one or more notches on the wafer edge and one flat side on the wafer edge, wherein the notches and the flat side are used for wafer pre-alignment in fabrication processes. In one embodiment, at least two distances along the wafer edge between any adjacent notches or between the flat side and an adjacent notch are different. In another embodiment, distances along the wafer edge between any adjacent notches and between the flat side and an adjacent notch are each different.02-03-2011
20110241173RESIST PATTERN FORMATING METHOD - The present invention provides a pattern formation method capable of preventing formation of surface defects. In the method, a resist surface after subjected to exposure is coated with an acidic film and then subjected to heating treatment. This method is suitably adopted in a process employing liquid immersion lithography and/or light of short wavelength, such as ArF excimer laser beams, for producing a very fine pattern.10-06-2011
20110127641SELF-ORGANIZED PIN-TYPE NANOSTRUCTURES, AND PRODUCTION THEREOF ON SILICON - By means of an RIE etch process for silicon (06-02-2011
20090072354SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device includes an upper electrode line structure and a lower electrode line structure provided over a semiconductor substrate. The semiconductor device also includes a guard contact having a first portion and a second portion. The guard contact is disposed between the upper electrode line structure and the lower electrode line structure. The first and second portions of the guard contact have different line widths.03-19-2009
20110241176Substrate Bonding with Bonding Material Having Rare Earth Metal - A microchip has a bonding material that bonds a first substrate to a second substrate. The bonding material has, among other things, a rare earth metal and other material.10-06-2011
20110241174SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed.10-06-2011
20100193915PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD, AND SEMICONDUCTOR DEVICE - In a chamber of a plasma processing apparatus, a cathode electrode and an anode electrode are disposed at a distance from each other. The cathode electrode is supplied with electric power from an electric power supply portion. The anode electrode is electrically grounded and a substrate is placed thereon. The anode electrode contains a heater. In an upper wall portion of the chamber, an exhaust port is provided and connected to a vacuum pump through an exhaust pipe. In a lower wall portion of a wall surface of the chamber, a gas introduction port is provided. A gas supply portion is provided outside the chamber.08-05-2010
20090315153NANO STRUCTURE AND MANUFACTURING METHOD OF NANO STRUCTURE - To provide a method of manufacturing a nano structure having a pattern of 2 μm or more in depth formed on the surface of a substrate containing Si and a nano structure having a pattern of a high aspect and nano order. A nano structure having a pattern of 2 μm or more in depth formed on the surface of a substrate containing Si, wherein the nano structure is configured to contain Ga or In on the surface of the pattern, and has the maximum value of the concentration of the Ga or the In positioned within 50 nm of the surface of the pattern in the depth direction of the substrate. Further, its manufacturing method is configured such that the surface of the substrate containing Si is irradiated with a focused Ga ion or In ion beam, and the Ga ions or the In ions are injected, while sputtering away the surface of the substrate, and a layer containing Ga or In is formed on the surface of the substrate, and with this layer taken as an etching mask, a dry etching is performed.12-24-2009
20090321888ALIGNMENT FOR BACKSIDE ILLUMINATION SENSOR - Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.12-31-2009
20100072577Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.03-25-2010
20100065946Bonded Wafer Substrate for Use in MEMS Structures - A method of manufacturing a semiconductor device includes providing first and second semiconductor substrates, each having first and second main surfaces opposite to one another. A roughened surface is formed on at least one of the first main surface of the first semiconductor substrate and the second main surface of the second semiconductor substrate. A dielectric layer is formed on the first main surface of the semiconductor substrate and the second semiconductor substrate is disposed on the dielectric layer opposite to the first semiconductor substrate. The second main surface of the second semiconductor substrate contacts the dielectric layer.03-18-2010
20110248386METHOD OF FORMATION OF COHERENT WAVY NANOSTRUCTURES (VARIANTS) - The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.10-13-2011
20110248384Partial Die Process for Uniform Etch Loading of Imprint Wafers - Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.10-13-2011
20110031591SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a semiconductor chip possessing a shape with corners and has a circuit section. The semiconductor chip has one or more chamfered portions which are formed in a first corner group that includes one or more of the corners. Data bonding pads are disposed on the semiconductor chip and are electrically connected to the circuit section. A chip selection pad is disposed adjacent to a second corner group that includes at least one of the corners which is not formed with a chamfered portion. The chip selection pad is electrically connected to the circuit section. A plurality of the semiconductor packages may be stacked so that the chip selection pad of one of the semiconductor packages is left exposed when another semiconductor package is stacked thereover due to the chamfered portion of the other semiconductor package.02-10-2011
20100301458Alignment Target Contrast in a Lithographic Double Patterning Process - A system and method of manufacturing a semiconductor device lithographically and an article of manufacture involving a lithographic double patterning process having a dye added to either the first or second lithographic pattern are provided. The dye is used to detect the location of the first lithographic pattern and to directly align the second lithographic pattern to it. The day may be fluorescent, luminescent, absorbent, or reflective at a specified wavelength or a given wavelength band. The wavelength may correspond to the wavelength of an alignment beam. The dye allows for detection of the first lithographic pattern even when it is over coated with a radiation sensitive-layer (e.g., resist).12-02-2010
20080315365Method for designing dummy pattern, exposure mask, semiconductor device, method for manufacturing semiconductor device, and storage medium - A method for designing a dummy pattern that is formed in a vacant section of a chip region before a semiconductor substrate including the chip region that has a device graphics data section in which a circuit element pattern is formed and the vacant section in which the circuit element pattern is not formed is planarized by a chemical mechanical polishing process, the method includes: setting an overall dummy section on the entire chip region; setting a mesh section on the entire overall dummy section; dividing the overall dummy section by the mesh section so that a plurality of rectangular dummy patterns is formed on the entire chip region after the mesh section is set; and removing or transforming a part of the rectangular dummy patterns, thereby uniformizing a density of the dummy pattern in the chip region.12-25-2008
20110037147SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An improved manufacturing method of a semiconductor device is provided. The method includes preparing a semiconductor substrate having an integrated circuit together with connection pads. The method also includes forming a dielectric film on the semiconductor substrate. The method also includes forming connection wires having a predetermined pattern on the dielectric film such that the connection wires are electrically connected to the connection pads. The method also includes forming a surface resin layer to partially cover the connection wire. The method also includes forming a metal film over the exposed connection wires. The method also includes forming a display unit having through holes to present identification information in a region corresponding to the center area of the semiconductor substrate on the surface resin layer. The forming of the metal film and the forming of display unit are carried out simultaneously.02-17-2011
20120199953SEMICONDUCTOR STRUCTURE WITH SMOOTHED SURFACE AND PROCESS FOR OBTAINING SUCH A STRUCTURE - The present invention relates to a process for smoothing the surface of a semiconductor wafer by fusion. The process includes defining a reference length which dimensions wafer surface roughness that is to be reduced or removed, and scanning the surface with a fusion beam while adjusting parameters of the fusion beam so as to fuse, during the scanning of the surface, a local surface zone of the wafer whose length is greater than or equal to the reference length, with the scanning continued to smooth the entire surface of the wafer by eliminating surface roughnesses of period lower than the reference length. The present invention also relates to a semiconductor wafer having a surface layer made of a semiconducting material that is smoothed by the process and that does not exhibit any roughness of period lower than the reference length.08-09-2012
20100244199SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.09-30-2010
20080265377AIR GAP WITH SELECTIVE PINCHOFF USING AN ANTI-NUCLEATION LAYER - A method of forming cavities within a semiconductor device is disclosed. The method comprises depositing an anti-nucleating layer on the interior surface of cavities within an ILD layer of the semiconductor device. This anti-nucleating layer prevents subsequently deposited dielectric layers from forming within the cavities. By preventing the formation of these layers, the capacitance is reduced, thereby resulting in improved semiconductor performance.10-30-2008
20110163421Method for Fabricating Optical Semiconductor Tubes and Devices Thereof - Semiconductor micro- and nanotubes allow the incorporation of ordered structures such as quantum wells and quantum dots into them providing the potential for ultralow threshold micro- and nanoscale lasers for use in applications such as future ultrahigh-speed photonic systems as well as quantum information processing. According to the invention a means of manufacturing these with high reproducibility, low processing complexity, and at high densities is provided. Also provided is a means of releasing these micro- and nanotubes with low stress and a method of “pick-and-place” allowing micro- and nanotubes to be exploited in devices integrated on substrates that are either incompatible with the manufacturing technique or where the area of substrate required to manufacture them is detrimental to the cost or performance of the circuit.07-07-2011
20110163420ASPECT RATIO ADJUSTMENT OF MASK PATTERN USING TRIMMING TO ALTER GEOMETRY OF PHOTORESIST FEATURES - A method for adjusting the geometry of photomask patterns is provided. Such adjusted pattern can be employed to achieve pattern doubling in subsequent layers. A patterned photoresist mask is provided over an underlayer. A polymer layer is placed over the mask. The mask is selectively trimmed to generate individual mask features having an increased aspect ratio. Subsequent pattern layers can be formed on the trimmed mask pattern to generate a hard mask having increased pattern density. The hard mask is selectively etched and the material of the trimmed mask pattern is removed. The underlayer is then etched to achieve pattern transfer from the hard mask to the underlayer to achieve a final double density pattern.07-07-2011
20100320573ORGANOSILANE POLYMERS, HARDMASK COMPOSITIONS INCLUDING THE SAME AND METHODS OF PRODUCING SEMICONDUCTOR DEVICES USING ORGANOSILANE HARDMASK COMPOSITIONS - Provided herein, according to some embodiments of the invention, are organosilane polymers prepared by reacting organosilane compounds including12-23-2010
20100320574SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of forming a semiconductor device includes forming a first chip region, a second chip region, and a scribe lane region between the first and second chip regions in a wafer, the wafer having a first surface and a second surface facing the first surface, and forming a penetrating extension hole and a scribe connector in the scribe lane region, the penetrating extension hole penetrating the wafer from the first surface to the second surface and extending along the scribe lane region, wherein the scribe connector connects the first and second chip regions spaced apart from each other by the penetrating extension hole.12-23-2010
20120146194 METHOD OF TEXTURING THE SURFACE OF A SILICON SUBSTRATE, AND TEXTURED SILICON SUBSTRATE FOR A SOLAR CELL - The invention relates to a method for texturing the surface of a gaseous phase silicon substrate, and to a textured silicon substrate for a solar cell. The method includes at least a step a) of exposing the surface to an SF06-14-2012
20100059862THINNED SEMICONDUCTOR WAFER AND METHOD OF THINNING A SEMICONDUCTOR WAFER - A thinned semiconductor wafer and a method for thinning the semiconductor wafer. A semiconductor wafer is thinned from its backside to form a cavity in a central region of the backside of the semiconductor wafer. Forming the cavity also forms a ring support structure in a peripheral region of the semiconductor wafer. The ring support structure has an inner edge and an outer edge. The inner edge may be beveled or have a stepped shape.03-11-2010
20100219506Systems and Methods of Laser Texturing and Crystallization of Material Surfaces - The surface of a material is textured and crystallized in a single step by exposing the surface to pulses from an ultrafast laser. The laser treatment causes pillars to form on the treated surface. These pillars provide for greater light absorption. The crystallization of the material provides for higher electric conductivity and changes in optical properties of the material. The method may be performed in a gaseous environment, so that laser assisted chemical etching will aid in the texturing of the surface. This method may be used on various material surfaces, such as semiconductors, metals, ceramics, polymers, and glasses.09-02-2010
20110147895Apparatus and Method for Controlling Semiconductor Die Warpage - A semiconductor die has through silicon vias arranged to reduce warpage. The through silicon vias adjust the coefficient of thermal expansion of the semiconductor die, permit substrate deformation, and also relieve residual stress. The through silicon vias may be located in the edges and/or corners of the semiconductor die. The through silicon vias are stress relief vias that can be supplemented with round corner vias to reducing warpage of the semiconductor die.06-23-2011
20110215441SILICON NANOSTRUCTURES AND METHOD FOR PRODUCING THE SAME AND APPLICATION THEREOF - The present invention provides silicon nanostructures and their producing method. By employing a metal-assisted chemical etching method, the bottom of the produced silicon nanostructures, connected to the silicon substrate, is porous and side etched, such that the silicon nanostructures can be easily transferred to a hetero-substrate by a physical manner.09-08-2011
20090014840Method for the production of crystalline silicon foils - The invention is a method for the production of a silicon foil with a targeted charge carrier transport to the p-n transition by means of an integral electric field (‘drift field’). By varying the crystal growth speed and introducing a doping substance into the fluid silicon beforehand, a crystallization process can be carried out in such a way that a gradient over the foil thickness is produced in the doping profile in the silicon. This gradient of the doping profile gives rise to an electric field. With the aid of various foil casting techniques foils that are suitable for the production of solar cells can thus be produced in a relatively simple manner.01-15-2009
20090174038PRODUCTION OF SINGLE-CRYSTAL SEMICONDUCTOR MATERIAL USING A NANOSTRUCTURE TEMPLATE - A method of producing single-crystal semiconductor material comprises: providing a template material; creating a mask on top of the template material; using the mask to form a plurality of nanostructures in the template material; and growing the single-crystal semiconductor material onto the nanostructures.07-09-2009
20090174037SEMICONDUCTOR SUBSTRATE, METHOD OF FABRICATING THE SAME, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING IMAGE SENSOR - In an example embodiment, an image sensor includes a semiconductor layer and isolation regions disposed in the semiconductor layer. The isolation regions define active regions of the semiconductor layer. The image sensor further includes photoelectric converters disposed in the semiconductor layer and at least one wiring layer disposed over a top surface of the semiconductor layer. The image sensor also includes color filters disposed below a bottom surface of the semiconductor layer and lenses disposed below the color filters. Each lens is arranged to concentrate incoming light into an area spanned by a corresponding photoelectric converter.07-09-2009
20120146192INTEGRATED CIRCUIT MOUNTING SYSTEM WITH PADDLE INTERLOCK AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.06-14-2012
20120146193Thermal Conduction Paths for Semiconductor Structures - A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the semiconductor wafer. The semiconductor wafer has an active device layer formed therein. The thermal path is in contact with the active device layer within the semiconductor wafer. In some embodiments, the thermal path extends from the active device layer to a substrate layer of the handle wafer. In some embodiments, the thermal path extends from the active device layer to a back side external thermal contact below the active device layer.06-14-2012
20120038027METHOD FOR MOLECULAR ADHESION BONDING AT LOW PRESSURE - The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P02-16-2012
20090026583Method of Producing 3-D Mold, Method of Producing Finely Processed Product, Method of Producing Fine-Pattern Molded Product, 3-D Mold, Finely Processed Product, Fine-Pattern Molded Product and Optical Component - To provide production methods for a 3-D mold, a finely processed product, and a fine pattern molded product in which the depth and the line width can be formed with high precision, a 3-D mold, a finely processed product, a fine-pattern molded product, and an optical element formed with high precision.01-29-2009
20110316122WAFER LASER-MARKING METHOD AND DIE FABRICATED USING THE SAME - A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is thinned. Then, the thinned wafer is fixed on a non-UV tape such that the second surface of the wafer is attached to the tape. Finally, the laser marking step is performed, such that a laser light penetrates the non-UV tape and marks a pattern on the second surface of the wafer. According to the laser-marking method of the embodiment, the pattern is formed by the non-UV residuals left on the second surface of the wafer, and the components of the glue residuals at least include elements of silicon and carbon.12-29-2011
20120043647LOW-TEMPERATURE BONDING PROCESS - The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as the bonding layer, on each substrate, at least one of these bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C.02-23-2012
20110101503HYPERBRANCHED POLYMER SYNTHESIZING METHOD, HYPERBRANCHED POLYMER, RESIST COMPOSITION, SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION METHOD - A hyperbranched polymer synthesizing method employs living radical polymerization of a monomer in the presence of a metal catalyst. The method includes forming a shell portion by introducing an acid-decomposable group to a core portion formed of a hyperbranched polymer synthesized by living radical polymerization; forming an acid group by partially decomposing the acid-decomposable group by an acid catalyst; precipitating a core-shell hyperbranched polymer contained in a first solution and having the acid group, by mixing the first solution with ultrapure water; and extracting, from a mixed solution into an organic solvent by liquid-liquid extraction, the core-shell hyperbranched polymer having the acid group, wherein the mixed solution contains a second solution containing the core-shell hyperbranched polymer precipitated at the precipitating and dissolved into the organic solvent, and the ultrapure water of an amount yielding a prescribed ratio of the ultrapure water relative to the organic solvent in the second solution.05-05-2011
20110101504Methods of Grinding Semiconductor Wafers Having Improved Nanotopology - Methods for holding a workpiece with a hydrostatic pad are disclosed herein. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.05-05-2011
20120043649Method for making microchannels on a substrate, and substrate including such microchannels - The present invention relates to a process for fabricating microchannels on a substrate and to a substrate comprising these microchannels, the invention being especially applicable to the fabrication of microstructured substrates for microelectronic, microfluidic and/or micromechanical systems.02-23-2012
20120043648Electronic component and method of manufacturing electronic component - In order to solve the above problem, provided is an electronic component having an authentication pattern formed on an exposed surface, in which the authentication pattern includes a base section including a resin and colored particles having a hue that can be identified in the base section, and the colored particles are dispersed so as to form dotted pattern in the base section.02-23-2012
20120043646SPACER DOUBLE PATTERNING THAT PRINTS MULTIPLE CD IN FRONT-END-OF-LINE - A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions. Embodiments further include using a third mask to form a semiconductor device having further features with a different critical dimension, but the same pitch, as the sub-resolution features.02-23-2012
20090206450METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE OBTAINED HEREWITH, AND SLURRY SUITABLE FOR USE IN SUCH A METHOD - The invention relates to a method of manufacturing a semiconductor device (08-20-2009
20120056306MULTI-STACK SEMICONDUCTOR DEVICE - A multi-stack semiconductor device comprises: a substrate; a first conductive layer, a first group of the semiconductor material layers and a second group of the semiconductor material layers. The first conductive layer is formed on the substrate scribed by laser on the bottom of the first conductive layer to form a plurality of the first scribe lines. The first group of the semiconductor material layers is formed on the first conductive layer, and the second group of the semiconductor material layers is formed on the first group of the semiconductor material layers. The first group of the semiconductor material layers and the second group of the semiconductor material layers are simultaneously scribed by laser on bottom of the first group of the semiconductor material layers to form a plurality of the second scribe lines. Each second scribe line is comprised of a plurality of the second pores. The second conductive layer is formed on the second group of the semiconductor material layers and is scribe by laser on the bottom of the first group of the semiconductor material layers to form a plurality of the third scribe lines. The second pores are shortened for shortening the horizontal distance of the first scribe lines and the second scribe lines and/or the horizontal distance of the second scribe lines and the third scribe lines.03-08-2012
20120056307EPITAXIAL SILICON WAFER AND PRODUCTION METHOD THEREOF - Provided is an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.03-08-2012
20120056308METHOD OF FORMING AN ELECTROMECHANICAL TRANSDUCER DEVICE - A method of forming an electromechanical transducer device comprises forming on a fixed structure a movable structure and an actuating structure of the electromechanical transducer device, wherein the movable structure is arranged in operation of the electromechanical transducer device to be movable in relation to the fixed structure in response to actuation of the actuating structure. The method further comprises providing a stress trimming layer on at least part of the movable structure, after providing the stress trimming layer, releasing the movable structure from the fixed structure to provide a released electromechanical transducer device, and after releasing the movable structure changing stress in the stress trimming layer of the released electromechanical transducer device such that the movable structure is deflected a predetermined amount relative to the fixed structure when the electromechanical transducer device is in an off state.03-08-2012
20120007217ENCAPSULANT CAVITY INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD OF FABRICATION THEREOF - A method for fabricating an encapsulant cavity integrated circuit package system includes: providing an interposer; forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and the interposer; and attaching a component on the interposer in the encapsulant cavity.01-12-2012
20120205783SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a first non-flat non-polar nitride semiconductor layer, a first structure layer on at least a portion of the surface of the first non-flat non-polar nitride semiconductor layer and a first non-polar nitride semiconductor layer on the first non-flat non-polar nitride semiconductor layer and the first structure layer. The first non-flat non-polar nitride semiconductor layer includes a plurality of solid particles.08-16-2012
20120205782Imprint Apparatus, Imprint Method, and Process Condition Selection Method - An imprint apparatus of one embodiment includes: a resist dropping unit adapted to drop resist onto a substrate; a patterning unit adapted to pattern the resist into transfer patterns corresponding to the template patterns; and a control unit configured to change a dropping condition for a resist dropping process shot by shot. The control unit is adapted to control, as the dropping condition, the distance to the position of a droplet of the resist to be dropped onto the substrate from a position on the substrate to be pressed with an assessment pattern, the assessment pattern being one of the template patterns that is to be assessed.08-16-2012
20120012986METHOD FOR MANUFACTURING SOI SUBSTRATE AND SOI SUBSTRATE - A method is demonstrated to form an SOI substrate having a silicon layer with reduced surface roughness in a high yield. The method includes the step of bonding a base substrate such as a glass substrate and a bond substrate such as a single crystal semiconductor substrate to each other, where a region in which bonding of the base substrate with the bond substrate cannot be performed is provided at the interface therebetween. Specifically, the method is exemplified by the combination of: irradiating the bond substrate with accelerated ions; forming an insulating layer over the bond substrate; forming a region in which bonding cannot be performed in part of the surface of the bond substrate; bonding the bond substrate and the base substrate to each other with the insulating layer therebetween; and separating the bond substrate from the base substrate, leaving a semiconductor layer over the base substrate.01-19-2012
20120012985Substrate Stand-Offs for Semiconductor Devices - Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.01-19-2012
20120012987METHODS OF FORMING SEMICONDUCTOR CHIP UNDERFILL ANCHORS - Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.01-19-2012
20110049680DUAL EXPOSURE TRACK ONLY PITCH SPLIT PROCESS - An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.03-03-2011
20120153441OVERLAY MARK ENHANCEMENT FEATURE - An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.06-21-2012
20100193912METHODS AND APPARATUS FOR THE MANUFACTURE OF MICROSTRUCTURES - A method of manufacturing microstructures is disclosed, the method comprising a applying a mask to substrate; forming a pattern in the mask; processing the substrate according to the pattern; and mechanically removing the mask from the substrate. A polymer mask is disclosed for manufacturing micro scale structure, the polymer mask comprising a thin, preferably ultra thin flexible film. A method of manufacturing an integrated circuit is disclosed, the method comprising forming a plurality of isolated semiconductor devices on a common substrate; and connecting some of the devices. Apparatus for manufacturing microstructures is disclosed comprising: a mechanism for coating a mass substrate to create a structure; a mechanism for removing a mask from the substrate; and processing apparatus. A thin film transistor is disclosed comprising drain source and gate electrodes, the drain and source electrode being separated by a semiconductor, and the gate electrode being separated from the semiconductor by an insulator, comprising a bandgap alignment layer disposed between a semiconductor and the insulator.08-05-2010
20120025353Semiconductor And Solar Wafers - A silicon-on-insulator or bonded wafer includes an upper portion having a trapezoid shape in cross-section and a lower portion having an outer peripheral edge having a curved shape.02-02-2012
20100096728Nitride semiconductor sustrate and method of fabricating the same. - A nitride semiconductor substrate includes a front surface, a rear surface on an opposite side to the front surface, and a first edge portion including a chamfered edge on the front surface. A ratio of an average surface roughness of the front surface to an average surface roughness of the first edge portion is not more than 0.01. The substrate may include a second edge portion including a chamfered edge on the rear surface. A ratio of an average surface roughness of the rear surface to an average surface roughness of the second edge portion is not more than 0.01. The first edge portion has a visible light transmissivity not more than 0.2 times that of the front surface. The second edge portion has a visible light transmissivity not more than 0.2 times that of the rear surface.04-22-2010
20110031590Liquid film assisted laser die marking and structures formed thereby - Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a liquid on a region of a die, and then forming an identification mark through the liquid on the die.02-10-2011
20100013057SEMICONDUCTOR SUBSTRATE SUITABLE FOR THE REALISATION OF ELECTRONIC AND/OR OPTOELECTRONIC DEVICES AND RELATIVE MANUFACTURING PROCESS - A semiconductive substrate (01-21-2010
20110006400HANDLE WAFER HAVING VIEWING WINDOWS - The invention relates to a method for making a handle wafer (01-13-2011
20120211871METHOD OF PRODUCING NANOPATTERNED ARTICLES, AND ARTICLES PRODUCED THEREBY - A nanopatterned surface is prepared by forming a block copolymer film on a miscut crystalline substrate, annealing the block copolymer film, then reconstructing the surface of the annealed block copolymer film The method creates a well-ordered array of voids in the block copolymer film that is maintained over a large area. The nanopatterned block copolymer films can be used in a variety of different applications, including the fabrication of high density data storage media.08-23-2012
20100289124Printable Semiconductor Structures and Related Methods of Making and Assembling - The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.11-18-2010
20100289123METHOD FOR MAKING A SEMI-CONDUCTING SUBSTRATE LOCATED ON AN INSULATION LAYER - A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.11-18-2010
20120126372RESIST PATTERN THICKENING MATERIAL AND PROCESS FOR FORMING RESIST PATTERN, AND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A resist pattern thickening material is disclosed that can utilize ArF excimer laser light; which, when applied over a resist pattern such as an ArF resist having a line pattern or the like, can thicken the resist pattern regardless of the size of the resist pattern; which has excellent etching resistance; and which is suited for forming a fine space pattern or the like, exceeding the exposure limits. Also disclosed is a process for forming a resist pattern and a method for manufacturing a semiconductor device, wherein the resist pattern thickening material of the present invention is suitably utilized.05-24-2012
20120161293METHOD FOR PRODUCING AN INTEGRATED CIRCUIT AND RESULTING FILM CHIP - A semiconductor substrate having a first lateral dimension is combined with a flexible film piece having a second lateral dimension by arranging the semiconductor substrate in a recess of the film piece. The semiconductor substrate has circuit structures produced using lithography process steps. After the semiconductor substrate has been arranged in the recess of the film piece, a patterned layer of an electrically conductive material is produced above the semiconductor substrate and the film piece using lithography process steps. The patterned layer extends from the semiconductor substrate up to the flexible film piece and forms a number of electrically conductive contact tracks between the semiconductor substrate and the film piece.06-28-2012
20120161292PROCESS FOR ASSEMBLING TWO WAFERS AND CORRESPONDING DEVICE - A process for assembling a first wafer and a second wafer each bevelled on their peripheries includes excavating the bevelled peripheral part of at least one first side of the first wafer to create a deposit bordering the region excavated in the material of the first wafer. The first side and a second side of the second wafer are then bonded together.06-28-2012
20120161291PROCESS FOR CLEAVING A SUBSTRATE - A process for cleaving a substrate for the purpose of detaching a film therefrom. The method includes the formation of a stress-generating structure locally bonded to the substrate surface and designed to expand or contract in a plane parallel to the substrate surface under the effect of a heat treatment; and the application of a heat treatment to the structure, designed to cause the structure to expand or contract so as to generate a plurality of local stresses in the substrate which generates a stress greater than the mechanical strength of the substrate in a cleavage plane parallel to the surface of the substrate defining the film to be detached, the stress leading to the cleavage of the substrate over the cleavage plane. Also, an assembly of a substrate and the stress-generating structure as well as use of the assembly in a semiconductor device for photovoltaic, optoelectronic or electronic applications.06-28-2012
20100207248Patterns of Semiconductor Device and Method of Forming the Same - A method of forming patterns of a semiconductor device comprises providing a semiconductor substrate comprising a first region wherein first patterns are to be formed and a second region wherein second patterns are to be formed, each of the second patterns having a wider width than the first patterns, forming an etch target layer over the semiconductor substrate, forming first etch patterns over the etch target layer of the first and second regions, forming second etch patterns on both sidewalls of each of the first etch patterns, wherein the second etch pattern formed in the second region has a wider width than the second etch pattern formed in the first region, removing the first etch patterns, forming third etch patterns over the etch target layer of the second region, the third etch pattern overlapping part of the second pattern, and etching the etch target layer using the third etch patterns and the second etch patterns as an etch mask, to form the first and second patterns.08-19-2010
20120133029METHOD OF NANOSTRUCTURING A FILM OR A WAFER OF MATERIAL OF THE METAL OXIDE OR SEMI-CONDUCTOR TYPE - A method for nanostructuring a film (05-31-2012
20120133028METHOD OF PRODUCING A THIN LAYER OF SEMICONDUCTOR MATERIAL - A semiconductor structure includes a thin semiconductor layer fixed on an applicator or flexible support, the thin layer having an exposed surface characterized by fractured solid bridges spaced apart by cavities. A method of producing the thin layer of semiconductor material includes implanting ions into the semiconductor wafer to define a reference plane, where the ion dose is above a minimum dose, but below a critical dose so as to avoid degrading the wafer surface. The method further includes applying a thermal treatment to define a layer of microcavities and applying stress to free the thin layer from the wafer.05-31-2012
20120133027Semiconductor substrate suitable for the realisation of electronic and/or optoelectronic devices and relative manufacturing process - A semiconductive substrate that is suitable for realising electronic and/or optoelectronic devices that include at least one substrate, in particular of single crystal silicon, and an overlying layer of single crystal silicon. Advantageously, the semiconductive substrate comprises at least one functional coupling layer suitable for reducing the defects linked to the differences in the materials used. The functional coupling layer can comprise a corrugated portion made in the layer of single crystal silicon and suitable for reducing the defects linked to the differences in lattice constant of such materials used. Alternatively, the functional coupling layer can comprise a porous layer arranged between the substrate of single crystal silicon and the layer of single crystal silicon, and suitable for reducing the stress caused by the differences between the thermal expansion coefficients of the materials used. A manufacturing process of such a semiconductive substrate is also described.05-31-2012
20120313221SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a semiconductor device includes a substrate, a first insulating film on the substrate, wiring lines including a metal in trenches in the first insulating film, and a second insulating film. The second insulating film covers the first insulating film and the wiring line. The trenches are arranged parallel to one another at predetermined intervals. The dielectric constant of the material of the second insulating film is higher than that of the first insulating film. The lower surface of the second insulating film in a region between the wiring lines locates above a surface that connects the peripheral edges of the upper surfaces of the wiring lines.12-13-2012
20090057838Manufacturing Method for Semiconductor Chips, and Semiconductor Chip - In a manufacturing method for performing plasma etching on a second surface of a semiconductor wafer that has a first surface where an insulating film is placed in dividing regions and the second surface which is opposite from the first surface and on which a mask for defining the dividing regions is placed thereby exposing the insulating film from etching bottom portions by removing portions that correspond to the dividing regions and subsequently continuously performing the plasma etching in the state in which the exposed surfaces of the insulating film are charged with electric charge due to ions in the plasma thereby removing corner portions put in contact with the insulating film in the device-formation-regions, isotropic etching is performed on the semiconductor wafer at any timing.03-05-2009
20090057840WAFER MANUFACTURING METHOD, POLISHING APPARATUS, AND WAFER - The present invention provides a wafer manufacturing method and a wafer polishing apparatus which enable control of sags in a periphery of a wafer and improvement of nanotopology values thereof that is strongly required recently, and a wafer. In a polishing process for making a mirror surface of the wafer, a back surface of the wafer is polished to produce a reference plane thereof.03-05-2009
20120168913FINFET - A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.07-05-2012
20120168914EPITAXIAL STRUCTURE AND METHOD FOR MAKING THE SAME - A method for making an epitaxial structure includes: (a) providing a sacrificial layer on a temporary substrate, the sacrificial layer being made of gallium oxide; and (b) growing epitaxially an epitaxial layer unit over the sacrificial layer.07-05-2012
20090108409SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an element formed on a substrate, at least one insulating film formed on the substrate, and a seal ring formed in the insulating film so as to surround a region where the element is formed and to extend through the insulating film. The semiconductor device further includes a void region including a void and formed in the insulating film in a region located outside the seal ring when viewed from the element.04-30-2009
20120175743EPITAXIAL STRUCTURE - An epitaxial structure is provided. The epitaxial structure includes a substrate, an first epitaxial layer, a second epitaxial layer, a first carbon nanotube layer and a second carbon nanotube layer. The first epitaxial layer is located on the substrate. The first carbon nanotube layer is located between the substrate and the first epitaxial layer. The second epitaxial layer is located on the first epitaxial layer. The second carbon nanotube layer is located between the first epitaxial layer and the second epitaxial layer.07-12-2012
20100270653CRYSTALLINE THIN-FILM PHOTOVOLTAIC STRUCTURES AND METHODS FOR FORMING THE SAME - Methods for forming semiconductor devices include providing a textured template, forming a buffer layer over the textured template, forming a substrate layer over the buffer layer, removing the textured template, thereby exposing a surface of the buffer layer, removing oxide from the exposed surface of the buffer layer, and forming a semiconductor layer over the exposed surface of the buffer layer.10-28-2010
20100270650Silicon substrate with periodical structure - A silicon substrate with periodical structure is disclosed, which comprises: a silicon substrate, and at least one periodical structure formed on at least one surface of the silicon substrate and having plural micro-cavities; wherein, the micro-cavities are arranged in an array, the micro-cavities are each in an inverted awl-shape or an inverted truncated cone-shape, the length of the base line of the micro-cavities in the inverted awl-shape is 100˜2400 nm, the diameter of the micro-cavities in the inverted truncated cone-shape is 100˜2400 nm, and the depth of the micro-cavities is 100˜2400 nm.10-28-2010
20120074528TECHNIQUE TO MODIFY THE MICROSTRUCTURE OF SEMICONDUCTING MATERIALS - A method of treating a sheet of semiconducting material comprises forming a sinterable first layer over each major surface of a sheet of semiconducting material, forming a second layer over each of the first layers to form a particle-coated semiconductor sheet, placing the particle-coated sheet between end members, heating the particle-coated sheet to a temperature effective to at least partially sinter the first layer and at least partially melt the semiconducting material, and cooling the particle-coated sheet to solidify the semiconducting material and form a treated sheet of semiconducting material.03-29-2012
20100006983PROCESS FOR PRODUCING SUBLITHOGRAPHIC STRUCTURES - A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures. The first and second auxiliary layer structures are removed to uncover the sublithographic structures01-14-2010
20120181665STRUCTURE AND METHOD FOR HARD MASK REMOVAL ON AN SOI SUBSTRATE WITHOUT USING CMP PROCESS - A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask material after a deep trench reactive ion etch (RIE) process. The blocking material on top of the hard mask material is removed. A selective wet etching process is used to remove the hard mask material. Trench recess depth is effectively controlled.07-19-2012
20120187543SUBSTRATE STRIP PLATE STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a strip plate structure and a method for manufacturing the same. The strip plate structure comprises a strip plate array, which comprises a plurality of strip plates arranged with spacing in a predetermined direction on a same plane, wherein each of the strip plates has a first surface and a second surface opposite to the first surface and the strip plate array is arranged on a plane parallel to the first surface of the strip plates; a plurality of strip sheets which connect neighboring ones of the strip plates; flexible material layers, which are located on at least a portion of the surfaces of the strip sheets and/or on at least a portion of the surfaces of the strip plates.07-26-2012
20120187542SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF THE SAME - According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: (a) forming cutting grooves in an element formation surface of a semiconductor wafer on which semiconductor elements are formed; (b) applying a protection tape on the element formation surface of the semiconductor wafer; (c) grinding a rear surface of the semiconductor wafer to thin the semiconductor wafer and to divide the semiconductor wafer into a plurality of semiconductor chips on which the semiconductor elements are formed; (d) forming an adhesive layer on the rear surface of the semiconductor wafer; (e) separating and cutting the adhesive layer for each of the semiconductor chips; and (f) removing the protection tape. The (e) is performed by spraying a high-pressure air to the adhesive layer formed on the rear surface of the semiconductor wafer while melting or softening the adhesive layer by heating.07-26-2012
20120256298MONITORING PATTERN, AND PATTERN STITCH MONITORING METHOD AND WAFER THEREWITH - A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern.10-11-2012
20120256299ARC RESIDUE-FREE ETCHING - Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.10-11-2012
20090020853STRUCTURES OF AND METHODS FOR FORMING VERTICALLY ALIGNED Si WIRE ARRAYS - A structure consisting of vertically aligned wire arrays on a Si substrate and a method for producing such wire arrays. The wire arrays are fabricated and positioned on a substrate with an orientation and density particularly adapted for conversion of received light to energy. A patterned oxide layer is used to provide for wire arrays that exhibit narrow diameter and length distribution and provide for controlled wire position.01-22-2009
20080296734MICROCHIP AND METHOD OF MANUFACTURING MICROCHIP - A microchip formed by joining a first substrate having at least one recess on its surface and a second substrate, wherein small projections of 0.5 to 30 μm in height are formed on at least a part of the surface having the recess of the first substrate, and a coating formed of a surface processing agent is provided on at least a part of the surface having the small projections formed thereon, as well as a method of manufacturing the microchip, are provided. A microchip allowing easy inspection of the state of application or state of adhesion of liquid material such as a surface processing agent, and allowing accurate optical measurement without causing disturbance such as fluorescence, can be provided.12-04-2008
20090243044Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device - Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or may be exposed to a side surface of a semiconductor chip obtained by dicing the semiconductor wafer along the scribe line region, among the conductive patterns, so that the island-shaped passivation film is opposed to the conductive pattern.10-01-2009
20100327415SILICON EPITAXIAL WAFER AND MANUFACTURING METHOD THEREOF - Provided is a method for manufacturing a silicon epitaxial wafer by growing an epitaxial layer by placing a silicon substrate on a susceptor. The method includes at least a step of forming a silicon oxide film entirely on the rear surface of the silicon substrate; a step of removing the silicon oxide film formed at least on an edge section of the silicon substrate; and a step of placing the silicon substrate on the susceptor with the silicon oxide film in between. An epitaxial layer is grown on the silicon substrate, while holding the silicon substrate by the susceptor with the silicon oxide film in between. Thus, the silicon epitaxial wafer by which generation of particles can be reduced in a device manufacturing process and a method for manufacturing such silicon epitaxial wafer are provided.12-30-2010
20100327414Method For Producing A Semiconductor Wafer - Semiconductor wafers are produced by a process of: 12-30-2010
20100327413HARDMASK OPEN AND ETCH PROFILE CONTROL WITH HARDMASK OPEN - A method for opening a carbon-based hardmask layer formed on an etch layer over a substrate is provided. The hardmask layer is disposed below a patterned mask. The substrate is placed in a plasma processing chamber. The hardmask layer is opened by flowing a hardmask opening gas including a COS component into the plasma chamber, forming a plasma from the hardmask opening gas, and stopping the flow of the hardmask opening gas. The hardmask layer may be made of amorphous carbon, or made of spun-on carbon, and the hardmask opening gas may further include O12-30-2010
20100327412METHOD OF SEMICONDUCTOR MANUFACTURING FOR SMALL FEATURES - Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a first opening having an upper first opening with sides converging to a lower second opening and a second opening with substantially parallel sides and an opening substantially corresponding to the lower second opening of the first opening, etching through the second opening to form a corresponding opening in the first HM layer, and etching the substrate through the corresponding opening in the first HM layer.12-30-2010
20080296732METHODS OF ISOLATING ARRAY FEATURES DURING PITCH DOUBLING PROCESSES AND SEMICONDUCTOR DEVICE STRUCTURES HAVING ISOLATED ARRAY FEATURES - Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.12-04-2008
20120261800WAFER WITH RECESSED PLUG - In one embodiment, a method of forming a plug includes providing a base layer, providing an intermediate oxide layer above an upper surface of the base layer, providing an upper layer above an upper surface of the intermediate oxide layer, etching a trench including a first trench portion extending through the upper layer, a second trench portion extending through the oxide layer, and a third trench portion extending into the base layer, depositing a first material portion within the third trench portion, depositing a second material portion within the second trench portion, and depositing a third material portion within the first trench portion.10-18-2012
20120299157SEMICONDUCTOR PROCESS AND FABRICATED STRUCTURE THEREOF - A semiconductor process includes the following steps. A substrate is provided, which includes an isolation structure and an oxide layer. The isolation structure divides the substrate into a first region and a second region. The oxide layer is located on the surface of the first region and the second region. A dry cleaning process is performed to remove the oxide layer. A dielectric layer is formed on the first region and the second region. A wet etching process is performed to remove at least one of the dielectric layers located on the first region and the second region. A semiconductor structure is fabricated by the above semiconductor process.11-29-2012
20120319246IP PROTECTION - Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.12-20-2012
20120319245VENTED SUBSTRATE FOR SEMICONDUCTOR DEVICE - A substrate with a vent for a semiconductor device where the vent is integrated within the substrate itself. The integrated air vent forms a passageway or relief path for gas or air within a mold cavity to escape during a transfer molding packaging process. The vents integrated in the substrate reduce trapped gas and mold voids and limit vent flash to improve yield.12-20-2012
20120319247SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A MASK MATERIAL - A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a planar or substantially planar upper surface is formed on the surface of the substrate. The planarity or substantial planarity of the non-conformal material eliminates or substantially eliminates distortion in a “mask” formed thereover and, thus, eliminates or substantially eliminates distortion in any mask that is subsequently formed using the pattern of the mask. In some embodiments, mask material of the non-conformal mask does not extend into recesses in the upper surface of the substrate; instead it “bridges” the recesses. Semiconductor device structures that include non-conformal masks and semiconductor device structures that have been fabricated with non-conformal masks are also disclosed.12-20-2012
20110227201SEMICONDUCTOR CHIP WITH A ROUNDED CORNER - Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor wafer that has plural semiconductor chips. Each of the plural semiconductor chips includes a first principal side and a second and opposite principal side. Material is removed from the semiconductor wafer to define at least one rounded corner of the first principal side of at least one of the plural semiconductor chips.09-22-2011
20120280365DEVICE HAVING AND METHOD FOR FORMING FINS WITH MULTIPLE WIDTHS - A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.11-08-2012
20120280364SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING PATTERN PEELING - A semiconductor device includes a first pattern and a plurality of second patterns arranged at equal intervals. When the distance of the space between the first pattern and the second pattern closet to the first pattern is larger than a first distance, a plurality of dummy patterns are arranged in the space with shapes and intervals similar to those of the second patterns. When the distance of the space is equal to or less than the first distance and larger than a second distance, the dummy pattern is spaced from the second pattern closest to the first pattern, and extends toward the first pattern to be brought into contact with the first pattern. When the distance of the space is equal to or less than the second distance, the dummy pattern is spaced from the second pattern closest to the first pattern, and is connected to the first pattern.11-08-2012
20120091564SEMICONDUCTOR COMPONENT WITH MARGINAL REGION - A semiconductor wafer is disclosed. One embodiment provides at least two semiconductor components each having an active region, and wherein at least one zone composed of porous material is arranged between the active regions of the semiconductor components.04-19-2012
20120091563METHOD FOR INSULATING A SEMICONDUCTOR MATERIAL IN A TRENCH FROM A SUBSTRATE - A semiconductor structure is disclosed. In one embodiment, the trench is formed in a substrate, including an upper portion and a lower portion, the upper portion including a lateral dimension larger than a lateral dimension of the lower portion. The lower portion is lined with a first insulating layer and is at least partially filled with a semiconductor material. The first insulating layer extends into the upper portion. A second insulating layer covers, at least partially, the substrate, a portion of the first insulating layer extending into the upper portion and the semiconducting material in the lower portion.04-19-2012
20120091562SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, and possessing a recess which is defined on the upper surface; and a semiconductor chip mounted to the upper surface of the substrate, having one surface which faces the upper surface and the other surface which faces away from the one surface, and warped in a smile shape such that a warped edge portion of the semiconductor chip is inserted into the recess.04-19-2012
20120326279METHOD FOR FORMING SEMICONDUCTOR DEVICES WITH ACTIVE SILICON HEIGHT VARIATION - A semiconductor product has different active thicknesses of silicon on a single semiconductor substrate. The thickness of the silicon layer is changed either by selectively adding silicon or subtracting silicon from an original layer of silicon. The different active thicknesses are suitable for use in different types of devices, such as diodes and transistors.12-27-2012
20120326278METHOD TO SOLVE POTENTIAL YIELD LOSS DUE TO METAL MIGRATION TO WIRE ROUTING NETS FROM FIDUCIARY MARKS ON PRODUCT DURING CHEMICAL-MECHANICAL-POLISHING (CMP) PLANARIZATION PROCESSING STEPS - A mask for a semiconductor process step includes an indicia section. The indicia section on the mask is used to produce a field of separated polygon elements with a defined negative space in the field providing an indicia.12-27-2012
20100213578METHODS OF FORMING INTEGRATED CIRCUITS AND RESULTING STRUCTURES - Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.08-26-2010
20130009283METHODS TO REDUCE THE CRITICAL DIMENSION OF SEMICONDUCTOR DEVICES AND RELATED SEMICONDUCTOR DEVICES - A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. Integrated circuit devices are also disclosed.01-10-2013
20130009282MICROELECTRONIC STRUCTURE INCLUDING AIR GAP - A microelectronic structure and a method for fabricating the microelectronic structure provide a plurality of voids interposed between a plurality of conductor layers. The plurality of voids is also located between a liner layer and an inter-level dielectric layer. The voids provide for enhanced electrical performance of the microelectronic structure.01-10-2013
20130015561MECHANISMS FOR MARKING THE ORIENTATION OF A SAWED DIEAANM Chen; Hsien-WeiAACI Sinying CityAACO TWAAGP Chen; Hsien-Wei Sinying City TW - Mechanisms for identifying orientation of a sawed die are provided. By making metal pattern in the corner stress relief region in one corner of the die different from the other corners, users can easily identify the orientation of the die.01-17-2013
20120241913MICROELECTRONIC SUBSTRATE HAVING REMOVABLE EDGE EXTENSION ELEMENT - An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.09-27-2012
20080237805Semiconductor Device and Method for Manufacturing Semiconductor Device - An object is to provide a semiconductor device which is not easily broken even if stressed externally and a method for manufacturing such a semiconductor device. A semiconductor device includes an element layer including a transistor in which a channel is formed in a semiconductor layer and insulating layers which are formed as an upper layer and a lower layer of the transistor respectively, and a plurality of projecting members provided at intervals of from 2 to 200 μm on a surface of the element layer. The longitudinal elastic modulus of the material for forming the plurality of projecting members is lower than that of the materials of the insulating layers. (111 words)10-02-2008
20080237804QUALITY OF A THIN LAYER THROUGH HIGH-TEMPERATURE THERMAL ANNEALING - A method for forming a structure is provided and includes implanting an atomic species into a donor substrate having an upper surface at a given depth relative to the upper surface to form an embrittlement zone in the donor substrate, the embrittlement zone defining a removable layer within the donor substrate. The method further includes assembling the upper surface of the donor substrate to a receiver substrate. Additionally, the method includes detaching the removable layer from the donor substrate at the embrittlement zone, thereby forming a detachment surface on the removable layer, by high temperature annealing. The high temperature annealing includes a temperature upgrade phase to a predetermined maximum temperature, maintaining the maximum temperature for a predetermined exposure duration, and a temperature downgrade phase. The maximum temperature and the exposure duration are selected so as to prevent the appearance of significant defects at the detachment surface.10-02-2008
20080237803SEMICONDUCTOR DEVICE HAVING STRUCTURE WITH FRACTIONAL DIMENSION OF THE MINIMUM DIMENSION OF A LITHOGRAPHY SYSTEM - A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.10-02-2008
20130168826LASER SYSTEM WITH POLARIZED OBLIQUE INCIDENCE ANGLE AND ASSOCIATED METHODS - Novel laser processed semiconductor materials, systems, and methods associated with the manufacture and use of such materials are provided. In one aspect, for example, a method of processing a semiconductor material can include providing a semiconductor material and irradiating a target region of the semiconductor material with a beam of laser radiation to form a laser treated region. The laser radiation is irradiated at an angle of incidence relative to the semiconductor material surface normal of from about 5° to about 89°, and the laser radiation can be at least substantially p-polarized.07-04-2013
20130168827DESIGN METHOD OF WIRING LAYOUT, SEMICONDUCTOR DEVICE, PROGRAM FOR SUPPORTING DESIGN OF WIRING LAYOUT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.07-04-2013
20130168829PHENOLIC RESIN COMPOSITION, AND METHODS FOR MANUFACTURING CURED RELIEF PATTERN AND SEMICONDUCTOR - Provided is a photopolymer composition for a semiconductor element surface protective film or an interlayer insulating film, in which a solution of the photopolymer composition comprises 100 parts by mass of (A) a phenolic resin having a biphenyldiyl structure in a main chain of the resin; 1 to 30 parts by mass of (B) a photo acid-generating agent; and 1 to 60 parts by mass of (C) a compound that can be reacted with ingredient (A) by means of an acid generated from the photo acid-generating agent or heat.07-04-2013
20080224270SILICON SINGLE CRYSTAL SUBSTRATE AND MANUFACTURE THEREOF - A semiconductor wafer for an epitaxial growth is disclosed comprising: a main face on which a vapor phase epitaxial layer grows; a back face provided on an opposite side of the wafer; a main chamfered part along a circumferential edge where the main face and a side face of the wafer meet; and a back chamfered part along a circumferential edge where the back face and the side face meet is provided. After a CVD layer formation process is conducted to form a layer at least on the back face and the back chamfered part, a machining process is conducted on the main face to remove a CVD layer at least partially formed thereon so as to polish the main face to a mirror finished surface with a maximum height of profile (Rz) not exceeding 0.3 μm.09-18-2008
20130200498METHODS AND APPARATUS FOR LITHOGRAPHY USING A RESIST ARRAY - Methods, apparatus, and systems are provided for forming a resist array on a material to be patterned. The resist array may include an arrangement of two different materials that are adapted to react to activation energy differently relative to each other to enable selective removal of only one of the materials (e.g., one is reactive and the other is not reactive; one is slightly reactive and the other is very reactive; one is reactive in one domain and the other in an opposite domain). The first material may be disposed as isolated nodes between the second material. A subset of nodes may be selected from among the nodes in the array and the selected nodes may be exposed to activation energy to activate the nodes and create a mask from the resist array. Numerous additional aspects are disclosed.08-08-2013
20130200499SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device which includes the following components. A substrate with a first conductivity type has a cell region and a peripheral region thereon, wherein the peripheral region surrounds the cell region. An epitaxial layer having the first conductivity type is disposed on the substrate. A first spiral-shaped region having a second conductivity type is embedded in the epitaxial layer within the peripheral region and encircles the cell region.08-08-2013
20130181328SEMICONDUCTOR DEVICE - A semiconductor device is disclosed that has enhanced its electric charge resistance. A first parallel p-n layer is disposed in an element activating part, and a second parallel p-n layer is disposed in an element peripheral edge part. An n07-18-2013
20120248578SEMICONDUCTOR WAFER AND METHOD OF PRODUCING THE SAME - A wafer surface of a semiconductor wafer to be used as a device active region is mirror-polished, and an outer peripheral portion of the mirror-polished wafer surface is further polished, thereby forming an edge roll-off region between the device active region of the wafer surface and a beveled portion formed at the wafer edge. The edge roll-off region has a specific roll-off shape corresponding to an edge roll-off of the oxide film to be formed in a device fabrication process. Thus, a semiconductor wafer can be provided in which reduction in the thickness of an oxide film on the outer peripheral portion of the wafer in a CMP process can be prevented while maintaining high flatness of the wafer surface.10-04-2012
20130168828THROUGH-HOLE FORMING METHOD AND INKJET HEAD - A through-hole forming method includes steps of forming a first impurity region (07-04-2013
20130093060METHOD FOR PRODUCING SILICON WAFER AND SILICON WAFER - A silicon wafer and method for producing a silicon wafer, including at least: a first heat treatment process in which rapid heat treatment is performed on the wafer by using a rapid heating/cooling apparatus in an atmosphere containing at least one of nitride film formation atmospheric gas, rare gas, and oxidizing gas at a temperature higher than 1300° C. and lower than or equal to a silicon melting point for 1 to 60 seconds; and a second heat treatment process in which temperature and atmosphere are controlled to suppress generation of a defect caused by a vacancy in the wafer and rapid heat treatment is performed on the wafer. Therefore, RIE defects such as oxide precipitates, COPs, and OSFs are not present at a depth of at least 1 μm from the surface, which becomes a device fabrication region, and the lifetime is 500 μsec or longer.04-18-2013
20110272789Nanochannel Device and Method for Manufacturing Thereof - The present disclosure relates to a device comprising a mono-crystalline substrate, the mono-crystalline substrate having at least one recessed region which exposes predetermined crystallographic planes of the mono-crystalline substrate, the at least one recessed region further having a recess width and comprising a filling material and an embedded nanochannel, wherein the width, the shape, and the depth of the embedded nanochannel is determined by the recess width of the at least one recessed region and by the growth rate of the growth front of the filling material in a direction perpendicular to the exposed predetermined crystallographic planes. The present disclosure is also related to a method for manufacturing a nanochannel device.11-10-2011
20110272788Computer system wafer integrating different dies in stacked master-slave structures - A stacked 3D integrated circuit structure is manufactured with a common image design for dies which allows diced master dies to cut from the common wafer and diced slave dies cut to be cut from a wafer which has the common image design. In an embodiment is stacked to form a wafer-to-wafer 3D stack before dicing. Master and slave elements which are used for only one kind of separated individual integrated circuit dies which are located along die edges and at die centers before dicing separation of individual integrated circuit chips. A master wafer is shifted ½ way across a die to make cutting along a kerf line effective to provide both master and slave dies. Multiple slaves can be stacked and coupled to a master die which acts as a bus master when attached to a bus to which only the master die is directly connected. The use of a common wafer design minimizes cost of manufacture of chips destined to be stacked as 3D integrated circuits.11-10-2011
20130119519COMPOSITE SUBSTRATE, ELECTRONIC COMPONENT, AND METHOD FOR MANUFACTURING COMPOSITE SUBSTRATE, AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT - Provided are a composite substrate which includes a silicon substrate having improved crystallinity, a method for manufacturing a composite substrate, and a method for manufacturing an electronic component. A composite substrate is formed by bonding a semiconductor substrate onto a support substrate having electric insulating properties. The semiconductor substrate is formed of silicon. The semiconductor substrate includes a plurality of first regions on each of which an element portion which functions as a semiconductor device is formed, and a second region which is positioned between the plurality of first regions. In the semiconductor substrate, an oxidized portion which is composed of silicon oxide is formed on a bottom surface of the second region.05-16-2013
20110221040Composite Semiconductor Substrates for Thin-Film Device Layer Transfer - Described herein are composite semiconductor substrates for use in semiconductor device fabrication and related devices and methods. In one embodiment, a composite substrate includes: (1) a bulk silicon layer; (2) a porous silicon layer adjacent to the bulk silicon layer, wherein the porous silicon layer has a Young's modulus value that is no greater than 110.5 GPa; (3) an epitaxial template layer, wherein the epitaxial template layer has a root-mean-square surface roughness value in the range of 0.2 nm to 1 nm; and (4) a set of silicon nitride layers disposed between the porous silicon layer and the epitaxial template layer.09-15-2011
20110241175HARDMASK COMPOSITION FOR FORMING RESIST UNDERLAYER FILM, PROCESS FOR PRODUCING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A hardmask composition for forming a resist underlayer film, a process for producing a semiconductor integrated circuit device, and a semiconductor integrated circuit device, the hardmask composition including an organosilane polymer, and a stabilizer, the stabilizer including one of acetic anhydride, methyl acetoacetate, propionic anhydride, ethyl-2-ethylacetoacetate, butyric anhydride, ethyl-2-ethylacetoacetate, valeric anhydride, 2-methylbutyric anhydride, nonanol, decanol, undecanol, dodecanol, propylene glycol propyl ether, propylene glycol ethyl ether, propylene glycol methyl ether, propylene glycol, phenyltrimethoxysilane, diphenylhexamethoxydisiloxane, diphenylhexaethoxydisiloxane, dioctyltetramethyldisiloxane, hexamethyltrisiloxane, tetramethyldisiloxane, decamethyltetrasiloxane, dodecamethylpentasiloxane, hexamethyldisiloxane, and mixtures thereof.10-06-2011
20110248385METHOD FOR SELECTIVELY FORMING SYMMETRICAL OR ASYMMETRICAL FEATURES USING A SYMMETRICAL PHOTOMASK DURING FABRICATION OF A SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEMS INCLUDING THE SEMICONDUCTOR DEVICE - A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting features which are fabricated use spacers formed around a patterned material. If one particular etch is used to remove a base material, symmetrical features result. If two particular etches are used to remove the base material, asymmetrical features remain.10-13-2011
20100308441MARKING CO2 LASER-TRANSPARENT MATERIALS BY USING ABSORPTION-MATERIAL-ASSISTED LASER PROCESSING - The present invention relates to a CO12-09-2010
20100308440SEMICONDUCTOR STRUCTURES AND METHODS FOR STABILIZING SILICON-COMPRISING STRUCTURES ON A SILICON OXIDE LAYER OF A SEMICONDUCTOR SUBSTRATE - Methods are provided for substantially preventing and filling overetched regions in a silicon oxide layer of a semiconductor substrate. The overetched regions may be formed as a result of overetching of the silicon oxide layer during etching of an overlying silicon-comprising material layer to form a silicon-comprising structure. An etch resistant spacer may be formed after the initial or subsequent overetches. The etch resistant spacer may be formed by depositing an etch resistant material into the overetched region and etching the deposited etch resistant material to leave residual etch resistant material forming the etch resistant spacer. The etch resistant spacer may also be formed by exposing the silicon oxide layer in the overetched region to a nitrogen-supplying material to form a silicon oxynitride etch resistant spacer.12-09-2010
20100308438NON-CONFORMAL MASKS, SEMICONDUCTOR DEVICE STRUCTURES INCLUDING THE SAME, AND METHODS - A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a planar or substantially planar upper surface is formed on the surface of the substrate. The planarity or substantial planarity of the non-conformal material eliminates or substantially eliminates distortion in a “mask” formed thereover and, thus, eliminates or substantially eliminates distortion in any mask that is subsequently formed using the pattern of the mask. In some embodiments, mask material of the non-conformal mask does not extend into recesses in the upper surface of the substrate; instead it “bridges” the recesses. Semiconductor device structures that include non-conformal masks and semiconductor device structures that have been fabricated with non-conformal masks are also disclosed.12-09-2010
20110233732SUBSTRATE FOR AN ELECTRONIC OR ELECTROMECHANICAL COMPONENT AND NANO-ELEMENTS - A substrate configured to support at least one electronic or electromechanical component and one or more nano-elements, formed with a base support, with a catalytic system, with a barrier layer, and with a layer configured to receive the electronic or electromechanical component, in single-crystal Si or in Ge or in a mixture of these materials. The catalytic system lies on the base support without any contact with the layer configured to receive electronic or electromechanical component and the barrier layer is sandwiched between the catalytic system and the layer configured to receive the electronic or electromechanical component. This barrier layer is without any contact with the base support.09-29-2011
20110233734Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-On-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.09-29-2011
20100314720ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and connecting to the wire. A seal ring extending through the plurality of interlayer insulating films and continuously surrounding the chip region is formed in the peripheral portion of the chip region. A stress absorbing wall extending through the plurality of interlayer insulating films and discretely surrounding the seal ring is formed outside the seal ring.12-16-2010
20100314719Processes and structures for IC fabrication - The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.12-16-2010
20100314718Processes and structures for IC fabrication - The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides a beveled slope of the components to facilitate interconnection bonding.12-16-2010
20130154060WAFER AND METHOD OF PROCESSING WAFER - A wafer including a substrate, a dielectric layer over the substrate, and a conductive layer over the dielectric layer is disclosed. The substrate has a main portion. A periphery of the dielectric layer and the periphery of the main portion of the substrate are separated by a first distance. A periphery of the conductive layer and the periphery of the main portion of the substrate are separated by a second distance. The second distance ranges from about a value that is 0.5% of a diameter of the substrate less than the first distance to about a value that is 0.5% of the diameter greater than the first distance.06-20-2013
20130154061ANODIZING APPARATUS, AN ANODIZING SYSTEM HAVING THE SAME, AND A SEMICONDUCTOR WAFER - An anodizing apparatus for causing an anodizing reaction to substrates immersed in an electrolyte solution. The apparatus includes a storage tank for storing the electrolyte solution, a holder for holding a plurality of substrates in liquid-tight contact with circumferential surfaces of the substrates, a moving mechanism for moving the holder between a transfer position outside the storage tank and a treating position inside the storage tank, and a closing device disposed in the storage tank for cooperating with the holder to complete a liquid-tight closure of the circumferential surfaces of the substrates held by the holder. Chemical reaction treatment is carried out with the circumferential surfaces of the substrates placed in a liquid-tight state. After the chemical reaction treatment is completed, the closing device is made inoperative and the holder is moved away from the treating position to unload the substrates from the storage tank.06-20-2013
20130119518SEMICONDUCTOR FORMATION BY LATERAL DIFFUSION LIQUID PHASE EPITAXY - A method for growing semiconductor wafers by lateral diffusion liquid phase epitaxy is described. Also provided are a refractory device for practicing the disclosed method and semiconductor wafers prepared by the disclosed method and device. The disclosed method and device allow for significant cost and material waste savings over current semiconductor production technologies.05-16-2013
20110304023 METHOD OF GENERATING A HOLE OR RECESS OR WELL IN A SUBSTRATE - The present invention relates to a method of generating a hole or recess or well in an electrically insulating or semiconducting substrate, and to a hole or recess or well in a substrate generated by this method. The invention also relates to an array of holes or recesses or wells in a substrate generated by the method. The invention also relates to a device for performing the method according to the present invention.12-15-2011
20110304022SURFACE PASSIVATION BY QUANTUM EXCLUSION USING MULTIPLE LAYERS - A semiconductor device has a multilayer doping to provide improved passivation by quantum exclusion. The multilayer doping includes a plurality M of doped layers, where M is an integer greater than 1. The dopant sheet densities in the M doped layers need not be the same, but in principle can be selected to be the same sheet densities or to be different sheet densities. M-1 interleaved layers provided between the M doped layers are not deliberately doped (also referred to as “undoped layers”). Structures with M=2, M=3 and M=4 have been demonstrated and exhibit improved passivation.12-15-2011
20110309479Plasma Dicing and Semiconductor Devices Formed Thereof - In one embodiment, a method of forming a semiconductor device includes forming islands by forming deep trenches within scribe lines of a substrate. The islands have a first notch disposed on sidewalls of the islands. A first electrode stack is formed over a top surface of the islands. The back surface of the substrate is thinned to separate the islands. A second electrode stack is formed over a back surface of the islands.12-22-2011
20110316121METHOD FOR MANUFACTURING TRENCH TYPE SUPERJUNCTION DEVICE AND TRENCH TYPE SUPERJUNCTION DEVICE - A method for manufacturing trench type super junction device is disclosed. The method includes the step of forming one or more P type implantation regions in the N type epitaxial layer below the bottom of each trench. By using this method, a super junction device having alternating P type and N type regions is produced, wherein the P type region is formed by P type silicon filled in the trench and P type implantation regions below the trench. The present invention can greatly improve the breakdown voltage of a super junction MOSFET.12-29-2011
20120018850LASER PROCESSING METHOD AND SEMICONDUCTOR DEVICE OBTAINED BY USING THE PROCESSING METHOD - A conventional laser processing method has a problem that the number of scanning lines is large, and it is difficult to shorten the time needed for the marking. In a laser processing method of the present invention, a first laser processing is performed in accordance with the outer border of, for example, an English letter “A,” and thereafter, second and subsequent laser processings are performed on an inner region inside the outer border. In this event, for the second and subsequent laser processings, the respective processing lines (scanning lines) are set up in a longitudinal direction of a processing region. Thus, the number of processing lines is greatly reduced. As a result, the time needed for the marking is greatly shortened, and the laser marking workability is improved.01-26-2012
20120018849SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a CSP type semiconductor device, the invention prevents a second wiring from forming a protruding portion toward a dicing line at the time of forming the second wiring that is connected to the back surface of a first wiring formed near a side surface portion of a semiconductor die on the front surface and extends onto the back surface of the semiconductor die over a step portion in a window that is formed from the back surface side of the semiconductor die so as to expose the back surface of the first wiring. A glass substrate is bonded on a semiconductor substrate on which a first wiring is formed on the front surface near a dicing line with a resin as an adhesive being interposed therebetween. The semiconductor substrate is then etched from the back surface to form a window having inclined sidewalls with the dicing line as a center. A second wiring is then formed so as to be connected to the back surface of the first wiring exposed in the window and extend over one of the sidewalls of the window, that extends perpendicular to the dicing line, onto the back surface of the semiconductor substrate.01-26-2012
20130193560SEMICONDUCTOR SUBSTRATE HAVING DOT MARKS AND METHOD OF MANUFACTURING THE SAME - A semiconductor substrate having dot marks is provided. Particularly, a semiconductor substrate having dot marks having an improved reading rate is provided. In a semiconductor substrate having a plurality of dot marks formed of recess portions having an inverted frustum shape, the plurality of dot marks constitutes a two-dimensional code disposed in a rectangular region of 0.25 mm08-01-2013
20130193561Processes and structures for IC fabrication - The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.08-01-2013
20130193562STRUCTURE AND METHOD FOR TOPOGRAPHY FREE SOI INTEGRATION - A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.08-01-2013
20130200496MULTI-LAYER METAL SUPPORT - The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some embodiments the method comprises implanting the top surface of a donor body with an ion dosage to form a cleave plane followed by exfoliating a lamina from the donor body. After exfoliating the lamina, a flexible metal support that has a coefficient of thermal expansion with a value that is within 10% of the value of the coefficient of thermal expansion of the lamina is constructed on the lamina. In some embodiments the coefficients of thermal expansion of the metal support and the lamina are within 10% or within 5% of each other between the temperatures of 100 and 600 ° C.08-08-2013
20130200497MULTI-LAYER METAL SUPPORT - The invention provides a method of forming an electronic device from a lamina that has a coefficient of thermal expansion that is matched or nearly matched to a constructed metal support. In some embodiments the method comprises implanting the top surface of a donor body with an ion dosage to form a cleave plane followed by exfoliating a lamina from the donor body. After exfoliating the lamina, a flexible metal support that has a coefficient of thermal expansion with a value that is within 10% of the value of the coefficient of thermal expansion of the lamina is constructed on the lamina. In some embodiments the coefficients of thermal expansion of the metal support and the lamina are within 10% or within 5% of each other between the temperatures of 500 and 1050° C.08-08-2013
20130200500RESIST PATTERN THICKENING MATERIAL, METHOD FOR FORMING RESIST PATTERN, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a resist pattern thickening material, which can utilize ArF excimer laser light; which, when applied over a resist pattern to be thickened, e.g., in form of lines and spaces pattern, can thicken the resist pattern to be thickened regardless of the size of the resist pattern to be thickened; and which is suited for forming a fine space pattern or the like, exceeding exposure limits. The present invention also provides a process for forming a resist pattern and a process for manufacturing a semiconductor device, wherein the resist pattern thickening material of the present invention is suitably utilized.08-08-2013
20130099358ELECTRONIC, OPTICAL AND/OR MECHANICAL APPARATUS AND SYSTEMS AND METHODS FOR FABRICATING SAME - Flexible electronic structure and methods for fabricating flexible electronic structures are provided. An example method includes applying a first layer to a substrate, creating a plurality of vias through the first layer to the substrate, and applying a second polymer layer to the first layer such that the second polymer forms anchors contacting at least a portion of the substrate. At least one electronic device layer is disposed on a portion of the second polymer layer. At least one trench is formed through the second polymer layer to expose at least a portion of the first layer. At least a portion of the first layer is removed by exposing the structure to a selective etchant to providing a flexible electronic structure that is in contact with the substrate. The electronic structure can be released from the substrate.04-25-2013
20120299158CMP POLISHING LIQUID, METHOD FOR POLISHING SUBSTRATE, AND ELECTRONIC COMPONENT - The CMP polishing liquid of the invention is used by mixing a first solution and a second solution, the first solution comprises cerium-based abrasive grains, a dispersant and water, the second solution comprises a polyacrylic acid compound, a surfactant, a pH regulator, a phosphoric acid compound and water, the pH of the second solution is 6.5 or higher, and the first solution and second solution are mixed so that the phosphoric acid compound content is within a prescribed range. The CMP polishing liquid of the invention comprises cerium-based abrasive grains, a dispersant, a polyacrylic acid compound, a surfactant, a pH regulator, a phosphoric acid compound and water, with the phosphoric acid compound content being within a prescribed range.11-29-2012
20120074527INTEGRATED CIRCUIT COMPRISING A DEVICE WITH A VERTICAL MOBILE ELEMENT INTEGRATED IN A SUPPORT SUBSTRATE AND METHOD FOR PRODUCING THE DEVICE WITH A MOBILE ELEMENT - The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element.03-29-2012
20130207238BLOCK CO-POLYMER PHOTORESIST - An integrated circuit is made by depositing a pinning layer on a substrate. A block copolymer photoresist is formed on the pinning layer. The block copolymer has two blocks A and B that do not self-assemble under at least some annealing conditions. The exposed block copolymer photoresist is processed to cleave at least some block copolymer bonds in the exposed selected regions. The exposed pinning layer is processed to create a chemical epitaxial pattern to direct the local self assembly of the block copolymer.08-15-2013

Patent applications in class PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.)

Patent applications in all subclasses PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.)