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INCLUDING SEMICONDUCTOR MATERIAL OTHER THAN SILICON OR GALLIUM ARSENIDE (GAAS) (E.G., PB X SN 1-X TE)

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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

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Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257615000 Group III-V compound (e.g., InP) 201
257616000 Containing germanium, Ge 32
257614000 Group II-VI compound (e.g., CdTe, Hg x Cd 1-x Te) 6
Entries
DocumentTitleDate
20120168910MULTI-NARY GROUP IB AND VIA BASED SEMICONDUCTOR - Methods and devices are provided for forming multi-nary semiconductor. In one embodiment, a method is provided comprising of depositing a precursor material onto a substrate, wherein the precursor material may include or may be used with an additive to minimize concentration of group IIIA material such as Ga in the back portion of the final semiconductor layer. The additive may be a non-copper Group IB additive in elemental or alloy form. Some embodiments may use both selenium and sulfur, forming a senary or higher semiconductor alloy.07-05-2012
20090057834Method for Chemical Mechanical Planarization of Chalcogenide Materials - A method and associated composition for chemical mechanical planarization of a chalcogenide-containing substrate (e.g., germanium/antimony/tellurium (GST)-containing substrate) are described. The composition and method afford low defect levels as well as low dishing and local erosion levels on the chalcogenide-containing substrate during CMP processing.03-05-2009
20130082355NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor substrate is provided in which leak current reduction and improvement in current collapse are effectively attained when using Si single crystal as a base substrate. The nitride semiconductor substrate is such that an active layer of a nitride semiconductor is formed on one principal plane of a Si single crystal substrate through a plurality of buffer layers made of a nitride, in the buffer layers, a carbon concentration of a layer which is in contact with at least the active layer is from 1×1004-04-2013
20110018103SYSTEM AND METHOD FOR TRANSFERRING SUBSTRATES IN LARGE SCALE PROCESSING OF CIGS AND/OR CIS DEVICES - According to an embodiment, the present invention provide method for fabricating a copper indium diselenide semiconductor film. The method includes providing a plurality of substrates, each of the substrates having a copper and indium composite structure, each of the substrate including a peripheral region, the peripheral region including a plurality of openings, the plurality of openings including at least a first opening and a second opening. The also includes transferring the plurality of substrates into a furnace, each of the plurality of substrates provided in a vertical orientation with respect to a direction of gravity, the plurality of substrates being defined by a number N, where N is greater than 5, the furnace including a holding apparatus, the holding apparatus including a first elongated member being configured to hang each of the substrates using at least the first opening. The method further includes introducing a gaseous species including a hydrogen species and a selenide species and a carrier gas into the furnace and transferring thermal energy into the furnace to increase a temperature from a first temperature to a second temperature, the second temperature ranging from about 350° C. to about 450° C. to at least initiate formation of a copper indium diselenide film from the copper and indium composite structure on each of the substrates.01-27-2011
20120098101PHOTO-PATTERNED CARBON ELECTRONICS - A system is provided for the manufacture of carbon based electrical components including, an ultraviolet light source; a substrate receiving unit whereby a substrate bearing a first layer of carbon based semiconductor is received and disposed beneath the ultraviolet light source; a mask disposed between the ultraviolet light source and the carbon based semiconductor layer; a doping agent precursor source; and environmental chemical controls, configured such that light from the ultraviolet light source irradiates a doping agent precursor and the first carbon layer.04-26-2012
20090315148ELECTROPLATING METHOD FOR DEPOSITING CONTINUOUS THIN LAYERS OF INDIUM OR GALLIUM RICH MATERIALS - An electrochemical deposition method to form uniform and continuous Group IIIA material rich thin films with repeatability is provided. Such thin films are used in fabrication of semiconductor and electronic devices such as thin film solar cells. In one embodiment, the Group IIIA material rich thin film is deposited on an interlayer that includes 20-90 molar percent of at least one of In and Ga and at least 12-24-2009
20090121320Method of manufacturing p-type nitride semiconductor and semiconductor device fabricated by the method - The present invention includes a first step of forming a nitride semiconductor layer by metal organic chemical vapor deposition by using a first carrier gas containing a nitrogen carrier gas and a hydrogen carrier gas of a flow quantity larger than that of the nitrogen carrier gas to thereby supply a raw material containing Mg and a Group V raw material containing N, and a second step of lowering a temperature by using a second carrier gas to which a material containing N is added, and hence solves the problems.05-14-2009
20090267188GALLIUM NITRIDE MATERIAL PROCESSING AND RELATED DEVICE STRUCTURES - Gallium nitride material devices and related processes are described. In some embodiments, an N-face of the gallium nitride material region is exposed by removing an underlying region.10-29-2009
20090267189PHOTO-PATTERNED CARBON ELECTRONICS - A system is provided for the manufacture of carbon based electrical components including, an ultraviolet light source; a substrate receiving unit whereby a substrate bearing a first layer of carbon based semiconductor is received and disposed beneath the ultraviolet light source; a mask disposed between the ultraviolet light source and the carbon based semiconductor layer; a doping agent precursor source; and environmental chemical controls, configured such that light from the ultraviolet light source irradiates a doping agent precursor and the first carbon layer.10-29-2009
20110204483Electroluminescent device for the production of ultra-violet light - The invention provides a method of producing an opto-electronic device wherein a layer of lattice matched material is grown on a substrate, the lattice matched material being a cubic zincblend material and the substrate being a cubic diamond or zincblend material, to form a coated substrate.08-25-2011
20080277763Abrupt Metal-Insulator Transition Wafer, and Heat Treatment Apparatus and Method For the Wafer - Provided are a wafer with the characteristics of abrupt metal-insulator transition (MIT), and a heat treatment apparatus and method that make it possible to mass-produce a large-diameter wafer without directly attaching the wafer to a heater or a substrate holder. The heat treatment apparatus includes a heater applying heat to a wafer having the characteristics of abrupt MIT and one surface covered with a thermally opaque film, and a plurality of fixing units formed along an edge portion of a top surface of the heater to fix the wafer to the heater.11-13-2008
20080290467SEMICONDUCTOR MEMORY STRUCTURES - A semiconductor structure includes a first conductive layer coupled to a transistor. A first dielectric layer is over the first conductive layer. A second conductive layer is within the first dielectric layer, contacting a portion of a top surface of the first conductive layer. The second conductive layer includes a cap portion extending above a top surface of the first dielectric layer. A first dielectric spacer is between the first dielectric layer and the second conductive layer. A phase change material layer is above a top surface of the second conductive layer. A third conductive layer is over the phase change material layer. A second dielectric layer is over the first dielectric layer. A second dielectric spacer is on a sidewall of the cap portion, wherein a thermal conductivity of the second dielectric spacer is less than that of the first dielectric layer or that of the second dielectric layer.11-27-2008
20090140389NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode.06-04-2009
20090212395Identifying New Semiconductor Detector Materials by D.C. Ionization Conductivity - Herein is described a method for identifying semiconductor radiation detector materials based on the mobility of internally generated electrons and holes. It was designed for the early stages of exploration, when samples are not available as single crystals, but as crystalline powders. Samples are confined under pressure in an electric field and the increase in current resulting from exposure to a high-intensity source of ionization current (e.g., 08-27-2009
20090321881EPITAXIAL LIFT OFF STACK HAVING A PRE-CURVED HANDLE AND METHODS THEREOF - Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming an ELO thin film is provided which includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a flattened, pre-curved support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process includes bending the pre-curved support handle to have substantial curvature while peeling the epitaxial material from the substrate and forming an etch crevice therebetween. Compression is maintained within the epitaxial material during the etching process. The flattened, pre-curved support handle may be formed by flattening a pre-curved support material.12-31-2009
20090200644SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer, an electrode connected to the semiconductor layer, a sacrificial metal layer connected to the electrode and made of a metal having higher ionization tendency than the material of the semiconductor layer and the material of the electrode.08-13-2009
20090127661NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Semiconductor devices, in particular nitride semiconductor devices for use in the manufacture of laser diodes, prevent peeling-off of the electrode, and at the same time reduces the complexity of processes and a reduction in yield. A nitride semiconductor device according to the invention includes a P-type nitride semiconductor layer with a ridge on its surface, an SiO05-21-2009
20100264517NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al10-21-2010
20100001374EPITAXIAL LIFT OFF STACK HAVING A MULTI-LAYERED HANDLE AND METHODS THEREOF - Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods for forming such films and devices. In one embodiment, a method for forming an ELO thin film includes depositing an epitaxial material over a sacrificial layer on a substrate, adhering a multi-layered support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process further includes peeling the epitaxial material from the substrate and forming an etch crevice therebetween while maintaining compression in the epitaxial material. The method further provides that the multi-layered support handle contains a stiff support layer adhered to the epitaxial material, a soft support layer adhered to the stiff support layer, and a handle plate adhered to the soft support layer. In one example, the stiff support layer may contain multiple inorganic layers, such as metal layers, dielectric layers, or combinations thereof.01-07-2010
20110127639SEMICONDUCTOR NANOSTRUCTURE - The present disclosure relates to a semiconductor nanostructure. The semiconductor nanostructure includes a substrate and at least one ridge. The substrate includes a first crystal plane and a second crystal plane perpendicular to the first crystal plane. The at least one ridge extends from the first crystal plane along a crystallographic orientation of the second crystal plane. A width of cross section at a position of half the height of the at least one ridge is less than 17 nm. The semiconductor nanostructure is a patterned structure which can lead to generate a quantum confinement effect, such that the impurity scattering phenomenon is reduced.06-02-2011
20120241911METHODS OF SELF-ALIGNED GROWTH OF CHALCOGENIDE MEMORY ACCESS DEVICE - Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.09-27-2012
20120032306Method for Patterning a Semiconductor Surface, and Semiconductor Chip - A method for patterning a semiconductor surface is specified. A photoresist is applied to an outer area of a second semiconductor wafer. A surface of the photoresist that is remote from the second semiconductor wafer is patterned by impressing a patterned surface of the first wafer into the photoresist. A patterning method is applied to the surface of the photoresist, wherein a structure applied on the photoresist is transferred at least in places to the outer area of the second semiconductor wafer.02-09-2012
20100078766NITRIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING THEREOF - A P-type nitride semiconductor and a method for manufacturing the same are provided. A nitride semiconductor includes a P-type nitride layer formed on a active layer, wherein the P-type nitride layer is a P-type nitride layer with the group 4 element doped.04-01-2010
20100019352PROCESS FOR SMOOTHENING III-N SUBSTRATES - A process for preparing smoothened III-N, in particular smoothened III-N substrate or III-N template, wherein III denotes at least one element of group III of the Periodic System, selected from Al, Ga and In, utilizes a smoothening agent comprising cubic boron nitride abrasive particles. The process provides large-sized III-N substrates or III-N templates having diameters of at least 40 mm, at a homogeneity of very low surface roughness over the whole substrate or wafer surface. In a mapping of the wafer surface with a white light interferometer, the standard deviation of the rms-values is 5% or lower, with a very good crystal quality at the surface or in surface-near regions, measurable, e.g., by means of rocking curve mappings and/or micro-Raman mappings.01-28-2010
20120146189QUATERNARY CHALCOGENIDE WAFERS - Disclosed herein are processes for making quaternary chalcogenide wafers. The process comprises milling quaternary chalcogenide crystals to form milled particles, and then compressing the milled particles to form a quaternary chalcogenide wafer. The quaternary chalcogenide wafers are useful for forming solar cells.06-14-2012
20120306053SOLUTION-BASED SYNTHESIS OF CsSnI3 - This invention discloses a solution-based synthesis of cesium tin tri-iodide (CsSnI12-06-2012
20100096727SEMI-CONDUCTOR SUBSTRATE AND METHOD OF MASKING LAYER FOR PRODUCING A FREE-STANDING SEMI-CONDUCTOR SUBSTRATE BY MEANS OF HYDRIDE-GAS PHASE EPITAXY - The invention relates to a free-standing semiconductor substrate as well as a process and a mask layer for the manufacture of a free-standing semiconductor substrate, wherein the semiconductor substrate self-separates from the starting substrate without further process steps.04-22-2010
20120161287METHOD FOR ENHANCING GROWTH OF SEMI-POLAR (Al,In,Ga,B)N VIA METALORGANIC CHEMICAL VAPOR DEPOSITION - A method for growing a semi-polar nitride semiconductor thin film via metalorganic chemical vapor deposition (MOCVD) on a substrate, wherein a nitride nucleation or buffer layer is grown on the substrate prior to the growth of the semi-polar nitride semiconductor thin film.06-28-2012
20120080774SEMICONDUCTOR, N-TYPE SEMICONDUCTOR, P-TYPE SEMICONDUCTOR, SEMICONDUCTOR JUNCTION DEVICE, PN JUNCTION DEVICE AND PHOTOELECTRIC CONVERTER - The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group 13 element of the IUPAC system into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor.04-05-2012
20120280362SIMPLE ROUTE FOR ALKALI METAL INCORPORATION IN SOLUTION-PROCESSED CRYSTALLINE SEMICONDUCTORS - A precursor solution for producing a semiconductor includes at least one of an alkali metal or an alkali metal compound dissolved in a solvent, and a metal chalcogenide dissolved in the solvent. A method of producing a precursor solution for a semiconductor includes preparing a first precursor solution that has at least one of an alkali metal or an alkali metal compound dissolved in a first solvent, preparing a second precursor solution that has a metal chalcogenide dissolved in a second solvent, and combining the first and second precursor solutions to obtain the precursor solution for producing the semiconductor. A method of producing a semiconductor device includes providing a precursor solution for producing a semiconductor layer on a substructure, and forming a layer of the precursor solution on the substructure. The precursor solution includes at least one of an alkali metal or an alkali metal compound dissolved in a solvent, and a metal chalcogenide dissolved in the solvent.11-08-2012
20130168825FABRICATION OF IONIC LIQUID ELECTRODEPOSITED CU-SN-ZN-S-SE THIN FILMS AND METHOD OF MAKING - A semiconductor thin-film and method for producing a semiconductor thin-films comprising a metallic salt, an ionic compound in a non-aqueous solution mixed with a solvent and processing the stacked layer in chalcogen that results in a CZTS/CZTSS thin films that may be deposited on a substrate is disclosed.07-04-2013
20130140679SEMICONDUCTIVE CERAMIC SINTERED COMPACT - There is provided a semiconductive ceramic sintered compact that has a conductivity high enough to attain static electricity removal and antistatic purposes and, at the same time, has excellent mechanical properties or stability over time. The semiconductive ceramic sintered compact includes a main phase and a conductive phase present between the main phases, wherein the main phase is a ceramic sintered phase including Al06-06-2013
20110272787FORMATION OF SELENIDE, SULFIDE OR MIXED SELENIDE-SULFIDE FILMS ON METAL OR METAL COATED SUBSTRATES - A composition for preventing cracking in composite structures comprising a metal coated substrate and a selenide, sulfide or mixed selenidesulfide film. Specifically, cracking is prevented in the coating of molybdenum coated substrates upon which a copper, indium-gallium diselenide (CIGS) film is deposited. Cracking is inhibited by adding a Se passivating amount of oxygen to the Mo and limiting the amount of Se deposited on the Mo coating.11-10-2011
20110309477GROUP IIB/VA SEMICONDUCTORS SUITABLE FOR USE IN PHOTOVOLTAIC DEVICES - The present invention relates to devices, particularly photovoltaic devices, incorporating Group IIB/VA semiconductors such phosphides, arsenides, and/or antimonides of one or more of Zn and/or Cd. In particular, the present invention relates to methodologies, resultant products, and precursors thereof in which electronic performance of the semiconductor material is improved by causing the Group IIB/VA semiconductor material to react with at least one metal-containing species (hereinafter co-reactive species) that is sufficiently co-reactive with at least one Group VA species incorporated into the Group IIB/VA semiconductor as a lattice substituent (recognizing that the same and/or another Group VA species also optionally may be incorporated into the Group IIB/VA semiconductor in other ways, e.g., as a dopant or the like).12-22-2011

Patent applications in class INCLUDING SEMICONDUCTOR MATERIAL OTHER THAN SILICON OR GALLIUM ARSENIDE (GAAS) (E.G., PB X SN 1-X TE)

Patent applications in all subclasses INCLUDING SEMICONDUCTOR MATERIAL OTHER THAN SILICON OR GALLIUM ARSENIDE (GAAS) (E.G., PB X SN 1-X TE)