Entries |
Document | Title | Date |
20080224267 | SEMICONDUCTOR DEVICES INCLUDING HYDROGEN IMPLANTATION LAYERS AND METHODS OF FORMING THE SAME - Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer. | 09-18-2008 |
20080308904 | P-DOPED REGION WITH IMPROVED ABRUPTNESS - A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor substrate to transform the predefined region into an activated doped region. | 12-18-2008 |
20080308905 | SEMI-CONDUCTOR DEVICE, AND METHOD OF MAKING THE SAME - A semiconductor device and a method for manufacturing the device are disclosed. The device, and the method for making the device, includes the steps of forming a gate oxide film on a semiconductor substrate; forming a gate poly silicon layer on the gate oxide film; and implanting deuterium ions over the semiconductor substrate including the gate poly silicon layer. | 12-18-2008 |
20080315363 | METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT, AND A SEMICONDUCTOR COMPONENT - A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa structures remain between adjacent trenches; introducing a first dopant of a first conduction type using the mask into the bottoms of the trenches; carrying out a first thermal step; introducing a second dopant of a second conduction type, which is complementary to the first conduction type, at least into the bottoms of the trenches; and carrying out a second thermal step. | 12-25-2008 |
20090026580 | Semiconductor Device and Manufacturing Method - A semiconductor device and its manufacturing method are disclosed. The semiconductor device includes at least one integrated circuit on a semiconductor substrate having an active side and a back side. The lattice constant of the semiconductor material is increased. The manufacturing method includes stretching the semiconductor lattice in near-surface areas of the back side of the semiconductor substrate. | 01-29-2009 |
20090026581 | FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method includes forming trenches in a semiconductor substrate by etching the semiconductor substrate; and then forming a first ion injection layer in sidewalls of the trenches at an active region of the semiconductor substrate; and then forming a second ion injection layer in a substantially horizontally extending surface of the active region located between the trenches; and then performing a threshold voltage adjusting implant on at least the active region, wherein the first ion injection layer and the second ion injection layer overlap at a portion of the active region to provide the overlapping portion with a higher doping concentration than a non-overlapping portion of the active region; and then forming a gate structure on the active region. Since the ion doping concentration of the surface of an active area between isolation layers is totally uniform, an electric current flows uniformly through the overall surface to prevent leakage current, to improve reliability, and to prolong lifespan of the flash memory device. | 01-29-2009 |
20090102019 | CONTROLLED DOPING OF SEMICONDUCTOR NANOWIRES - A catalyst particle on a substrate is exposed to reactants containing a semiconductor material in a reactor. An intrinsic semiconductor nanowire having constant lateral dimensions is grown at a low enough temperature so that pyrolysis of the reactant is suppressed on the sidewalls of the intrinsic semiconductor nanowire. Once the intrinsic semiconductor nanowire grows to a desired length, the temperature of the reactor is raised to enable pyrolysis on the sidewalls of the semiconductor nanowire, and thereafter dopants are supplied into the reactor with the reactant. A composite semiconductor nanowire having an intrinsic inner semiconductor nanowire and a doped semiconductor shell is formed. The catalyst particle is removed, followed by an anneal that distributes the dopants uniformly within the volume of the composite semiconductor nanowire, forming a semiconductor nanowire having constant lateral dimensions and a substantially uniform doping. | 04-23-2009 |
20090200643 | SEMICONDUCTOR AND METHOD FOR PRODUCING THE SAME - A method for producing a semiconductor by conducting superimposed doping of a plurality of dopants in a semiconductor substrate, which includes evaporating a (2×n) structure by a first dopant and forming its thin line structure on the substrate, then bringing the semiconductor substrate to a temperature capable of epitaxial growth, vapor depositing a second or third or subsequent dopants above the semiconductor substrate where the first dopant has been deposited, then epitaxially growing a semiconductor crystal layer over the semiconductor substrate, subsequently forming a superimposed doping layer composed of the first, second, or the third or subsequent dopants in the semiconductor substrate, and applying an annealing treatment to the superimposed doping layer at a high temperature, thereby activating the plurality of dopants electrically or optically. Superimposed doping of a plurality kinds of elements as dopants can thus be performed to a predetermined depth also in the case of an elemental semiconductor. | 08-13-2009 |
20090283865 | ELECTROCHEMICAL METHOD TO MAKE HIGH QUALITY DOPED CRYSTALLINE COMPOUND SEMICONDUCTORS - A process for fabricating doped crystalline semiconductors is provided using layer by layer deposition of semiconductors and the corresponding dopants. | 11-19-2009 |
20090283866 | Semiconductor Substrate and a Method of Manufacturing the Same - The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×10 | 11-19-2009 |
20100025821 | ION IMPLANTING APPARATUS AND ION IMPLANTING METHOD - When positively charged ions are implanted into a target substrate, charge-up damage may occur on the target substrate. In order to suppress charge-up caused by secondary electrons emitted from the target substrate when positively charged ions are implanted, a conductive member is installed at a position facing the target substrate and electrically grounded with respect to a high frequency. Further, a field intensity generated in the target substrate may be reduced by controlling an RF power applied to the target substrate in pulse mode. | 02-04-2010 |
20100052103 | SILICON WAFER AND METHOD FOR PRODUCING THE SAME - A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×10 | 03-04-2010 |
20100140744 | METHODS OF DEPOSITING ELECTRICALLY ACTIVE DOPED CRYSTALLINE SI-CONTAINING FILMS - Methods of making Si-containing films that contain relatively high levels of Group III or Group V dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain at least about 3×10 | 06-10-2010 |
20100155898 | METHOD FOR ENHANCING TENSILE STRESS AND SOURCE/DRAIN ACTIVIATION USING Si:C - A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using a millisecond anneal process. Subsequent ion implantation steps are used to dope the source/drain region, and the source/drain extension with phosphorus ions, so that the doped regions remain above the strain layer. A second millisecond anneal step activates the source/drain region and the source/drain extension. The strain layer enhances carrier mobility within a channel region of the semiconductor structure, while also preventing diffusion of P within the structure. | 06-24-2010 |
20100200954 | ION IMPLANTED SUBSTRATE HAVING CAPPING LAYER AND METHOD - In an ion implantation method, a substrate is placed in a process zone and ions are implanted into a region of the substrate to form an ion implanted region. A porous capping layer is deposited on the ion implanted region. The substrate is annealed to volatize at least 80% of the porous capping layer overlying the ion implanted region during the annealing process. An intermediate product comprises a substrate, a plurality of ion implantation regions on the substrate, and a porous capping layer covering the ion implantation regions. | 08-12-2010 |
20110018102 | Method for Simultaneous Recrystallization and Doping of Semiconductor Layers and Semiconductor Layer Systems Produced According to this Method - A method for simultaneous recrystallisation and doping of semiconductor layers, in particular for the production of crystalline silicon thin layer solar cells. A substrate base layer | 01-27-2011 |
20110108953 | FAST RECOVERY DIODE - A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*10 | 05-12-2011 |
20110127638 | COMPLEMENTARY DOPING METHODS AND DEVICES FABRICATED THEREFROM - Improved complementary doping methods are described herein. The complementary doping methods generally involve inducing a first and second chemical reaction in at least a first and second portion, respectively, of a dopant source, which has been disposed on a thin film of a semiconductor or semimetal material. The chemical reactions result in the introduction of an n-type dopant, a p-type dopant, or both from the dopant source to each of the first and second portions of the thin film of the semiconductor or semimetal. Ultimately, the methods produce at least one n-type and at least one p-type region in the thin film of the semiconductor or semimetal. | 06-02-2011 |
20110140241 | PROCESSES FOR PRODUCTION OF SILICON INGOT, SILICON WAFER AND EPITAXIAL WAFER , AND SILICON INGOT - A process for production of a silicon ingot, by which a silicon ingot exhibiting a low resistivity even in the top portion can be produced. The process for the production of a silicon ingot comprises includes withdrawing a silicon seed crystal ( | 06-16-2011 |
20110233728 | SEMICONDUCTOR COMPONENT - A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa structures remain between adjacent trenches; introducing a first dopant of a first conduction type using the mask into the bottoms of the trenches; carrying out a first thermal step; introducing a second dopant of a second conduction type, which is complementary to the first conduction type, at least into the bottoms of the trenches; and carrying out a second thermal step. | 09-29-2011 |
20110254133 | PHOTORESISTS AND METHODS FOR USE THEREOF - New photoresist are provided that comprises an Si-containing component and that are particularly useful for ion implant lithography applications. Photoresists of the invention can exhibit good adhesion to underlying inorganic surfaces such as SiON, silicon oxide, silicon nitride and other inorganic surfaces. | 10-20-2011 |
20110260294 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first well and a second well formed in a substrate and having a different impurity doping concentration; a first isolation layer and a second isolation layer formed in the first well and the second well, respectively, and having a different depth; and a third isolation layer formed in a boundary region in which the first well and the second well are in contact with each other, and having a combination type of the first isolation layer and the second isolation layer. | 10-27-2011 |
20120001300 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, forming a film of amorphous Si on a substrate including an insulating upper surface; injecting a first impurity of a first conductivity in a first region and a second region of the film; crystallizing the film by melting and solidifying the film and activating the first impurity by scanning a first laser light in a first direction and radiating the first laser light over the film; injecting a second impurity of a second conductivity at a higher concentration than the first impurity, the second impurity being a lighter element than the first impurity in the first region with masking the second region; and activating the second impurity. | 01-05-2012 |
20120007216 | Multi-Chip Package Module And A Doped Polysilicon Trench For Isolation And Connection - A circuit module comprises a die attach pad with a surface and a plurality of leads surrounding the surface. A nonconductive adhesive is on the surface. A plurality of electronic circuit dies are on the surface of the die attach pad. Each die has a top surface and a bottom surface with the bottom surface on the adhesive. The top surface has a plurality of bonding pads. A first electronic circuit die has at least one routing path of a conductive material connecting a first bonding pad to a second bonding pad. A first bonding wire connects a bonding pad of a second electronic circuit die to the first bonding pad of the first electronic die. A second bonding wire connects the second bonding pad of the first electronic circuit die to a lead. Where one of the dies contains vertical circuit element, where a doped layer forms a terminal along the bottom surface of the layer, a trench filled with doped polysilicon extends from the top surface to the terminal to connect to the terminal. The doped polysilicon filled trench also serves to isolate and separate different circuit elements. | 01-12-2012 |
20120012983 | SILICON WAFER AND METHOD OF MANUFACTURING SAME - This method of manufacturing a silicon wafer has a step of preparing a wafer, in which a surface of the silicon wafer is surface-treated, a step of setting stress, in which the stress S (MPa) subjected on the wafer is set, a step of inspecting, in which a defect on a surface of the wafer is inspected, and a step of determining, in which the wafer is evaluated if the wafer satisfies a criterion. In this method, it is possible to manufacture a wafer with cracking resistance even if it is subjected to a millisecond annealing by the FLA annealing treatment. | 01-19-2012 |
20120032305 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof is disclosed in which the semiconductor device includes a p-type anode layer formed by a transition metal acceptor transition, and the manufacturing process is significantly simplified without the breakdown voltage characteristics deteriorating. An inversion advancement region inverted to a p-type by a transition metal acceptor transition, and in which the acceptor transition is advanced by point defect layers, is formed on the upper surface of an n-type drift layer. The inversion advancement region configures a p-type anode layer of a semiconductor device of the invention. The transition metal is, for example, platinum or gold. An n-type semiconductor substrate with a concentration higher than that of the n-type drift layer is adjacent to the lower surface of the n-type drift layer. | 02-09-2012 |
20120043644 | SILICON WAFER AND MANUFACTURING METHOD - A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process. | 02-23-2012 |
20120074523 | CONTROLLING MICROELECTRONIC SUBSTRATE BOWING - The present disclosure relates to the field of epitaxial structures for microelectronic device formation, particularly to heavily doped, substrates having a compensation component embedded along the dopant to prevent bowing of the substrate during deposition of an epitaxial layer. | 03-29-2012 |
20120098100 | Support Ring For Supporting A Semiconductor Wafer Composed Of Monocrystalline Silicon During A Thermal Treatment, Method For The Thermal Treatment of Such A Semiconductor Wafer, and Thermally Treated Semiconductor Wafer Composed of Monocrystalline Silicon - A support ring for supporting a monocrystalline silicon semiconductor wafer during a thermal treatment of the semiconductor wafer has outer and inner lateral surfaces and a curved surface extending from the outer lateral surface to the inner lateral surface, this curved surface serving for the placement of the semiconductor wafer. The curved surface has a radius of curvature of not less than 6000 mm and not more than 9000 mm for 300 mm diameter wafers, or a radius of curvature of not less than 9000 mm and not more than 14,000 mm for 450 mm diameter wafers. Use of the support ring during thermal treatment reduces slip and improves wafer nanotopography. | 04-26-2012 |
20120112319 | EPITAXIAL SILICON WAFER AND METHOD FOR MANUFACTURING SAME - It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration to execute a baking treatment. After a surface layer of the silicon crystal substrate is then polished up to a predetermined amount, a silicon epitaxial layer is grown by a CVD method. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced. | 05-10-2012 |
20120133026 | Electrically Actuated Device And Method Of Controlling The Formation Of Dopants Therein - An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. The device further includes at least one of dopant initiators or dopants localized at an interface between i) the first electrode and the active region, or ii) the second electrode and the active region, or iii) the active region and each of the first and second electrodes. | 05-31-2012 |
20120187539 | DEVICE AND METHOD FOR BORON DIFFUSION IN SEMICONDUCTORS - A device and method for semiconductor fabrication includes forming a buffer layer on a semiconductor substrate and depositing an amorphous elemental layer on the buffer layer. Elements of the elemental layer are diffused through the buffer layer and into the semiconductor layer. | 07-26-2012 |
20120235281 | SYSTEMS AND METHODS FOR PREPARING FILMS COMPRISING METAL USING SEQUENTIAL ION IMPLANTATION, AND FILMS FORMED USING SAME - Systems and methods for preparing films comprising metal using sequential ion implantation, and films formed using same, are provided herein. A structure prepared using ion implantation may include a substrate; an embedded structure having pre-selected characteristics; and a film within or adjacent to the embedded structure. The film comprises a metal having a perturbed arrangement arising from the presence of the embedded structure. The perturbed arrangement may include metal ions that coalesce into a substantially continuous, electrically conductive metal layer, or that undergo covalent bonding, whereas in the absence of the embedded structure the metal ions instead may be free to diffuse through the substrate. The embedded structure may control the diffusion of the metal through the substrate and/or the reaction of the metal within the substrate. | 09-20-2012 |
20120248576 | Semiconductor Device and Substrate with Chalcogen Doped Region - An undoped semiconductor substrate is doped by applying stress at a side of the undoped semiconductor substrate to release self interstitials in the substrate and implanting chalcogen atoms into the side of the substrate. The substrate is annealed to form a first semiconductor region containing the chalcogen atoms and a second semiconductor region devoid of the chalcogen atoms. The first semiconductor region has a doping concentration higher than the doping concentration of the second semiconductor region. The indiffusion of chalcogen atoms into a semiconductor material in the presence of self interstitials can also be used to form field stop regions in power semiconductor devices. | 10-04-2012 |
20120256295 | MULTILAYER SELECT DEVICES AND METHODS RELATED THERETO - Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e | 10-11-2012 |
20120256296 | SEMICONDUCTOR MATERIALS, APPARATUSES AND METHODS - Various methods and apparatuses involving salt-based compounds and related doping are provided. In accordance with one or more embodiments, a salt-based material is introduced to a semiconductor material, is heated to generate a neutral compound that dopes the semiconductor material. Other embodiments are directed to semiconductor materials with such a neutral compound as an impurity that affects electrical characteristics therein. | 10-11-2012 |
20120292742 | SEMICONDUCTOR DEVICE - A MOSFET includes a silicon carbide substrate, a buffer layer made of silicon carbide formed on the silicon carbide substrate, a drift layer made of silicon carbide of an n conductivity type formed on the buffer layer, a p type body region of a p conductivity type formed in the drift layer to include a main surface of the drift layer opposite to the buffer layer, a source contact electrode formed on the p type body region, and a drain electrode formed on a main surface of the silicon carbide substrate opposite to the buffer layer. A current path region having an impurity concentration higher than that of another region in the drift layer is formed in a region in the drift layer sandwiched between the buffer layer and the body region. | 11-22-2012 |
20120299154 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEBICE - A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal. | 11-29-2012 |
20120306052 | SILICON WAFER AND METHOD OF MANUFACTURING THEREOF, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An object of the present invention is to provide an epitaxial wafer on which dislocation is preventable even when a LSA treatment is performed in device processes. An epitaxial wafer according to the present invention includes a wafer | 12-06-2012 |
20120326277 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A power semiconductor device and a manufacturing method thereof are provided. The method of manufacturing a power semiconductor device includes the steps: (a) forming a cell structure on a first conductivity type semiconductor substrate; (b) implanting second conductivity type ions onto the rear surface of the first conductivity type semiconductor substrate and activating to form an electrode region; and (c) implanting ions creating first conductivity type with a doping concentration higher than that of the semiconductor substrate and activating to form a high-concentration ion implanted region at a position below the cell structure and on the electrode region. Accordingly, it is possible to form a field stop layer regardless of conditions for forming an electrode region (for example, a P-type collector region) and thus to optimize stable breakdown voltage characteristics and device characteristics. | 12-27-2012 |
20130009281 | MULTILAYER SELECT DEVICES AND METHODS RELATED THERETO - Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e | 01-10-2013 |
20130043563 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, there is provided a method of manufacturing a semiconductor device. In the method, a substrate portion and a fin portion on the substrate portion are formed. A first silicon oxide film is formed on each side surface of the fin portion. A polysilazane film having an upper surface lower than the upper surface of the first silicon oxide film is formed on each side surface of the first silicon oxide film. The polysilazane film is converted into a silicon oxynitride film. The first silicon oxide film is etched to make the upper surface of the first silicon oxide film not higher than the upper surface of the silicon oxynitride film. A heavily doped semiconductor layer is formed in the fin portion. | 02-21-2013 |
20130056856 | SEMICONDUCTOR DEVICE CAPABLE OF REDUCING PLASMA INDUCED DAMAGE AND FABRICATION METHOD THEREOF - A method of fabricating a semiconductor device having reduced plasma-induced damage includes providing a p-type semiconductor substrate. The p-type semiconductor substrate has a front surface including the semiconductor device and a back surface. The method further includes doping the back surface with an n-type dopant to form an n-type semiconductor region before forming metal interconnections on the front surface. The n-type semiconductor region and the p-type semiconductor substrate form a pn junction. The method also includes forming an insulation layer on an exposed surface of the n-type semiconductor region. | 03-07-2013 |
20130082354 | Semiconductor Structure and Method for Manufacturing the Same - The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming a dielectric film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin; and forming a retrograde doped well structure on the inner walls of the first semiconductor fin and the second semiconductor fin, wherein the inner walls thereof are opposite to each other. Correspondingly, the present invention further provides a semiconductor structure. In the present invention, a retrograde doped well structure is formed on the sidewalls of the two semiconductor fins that are opposite to each other, so that the width of the source/drain depletion layer may be effectively reduced, and thereby the short channel effect is reduced. | 04-04-2013 |
20130087889 | DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF - A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions. | 04-11-2013 |
20130093058 | P-Type Silicon Single Crystal and Method Of Manufacturing The Same - Silicon wafers having a resistivity >6 Ωcm and axially uniform resistivity are grown by the Czochralski method from a melt containing boron as the main dopant, an n-type first sub-dopant with a segregation coefficient lower than boron, and a p-type second sub-dopant with a segregation coefficient lower than the first sub-dopant. | 04-18-2013 |
20130154059 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes exciting plasma, applying RF power onto a target substrate to generate substrate bias and performing an ion implantation plural times by applying the RF power in the form of pulses. | 06-20-2013 |
20130161793 | Silicon Single Crystal Substrate and Method Of Manufacturing The Same - Silicon single crystal substrates having uniform resistance, few BMDs in a surface layer and a moderate number of BMDs in a center of thickness of the substrate are formed from Czochralski silicon single crystals. The substrates have a resistivity in the center of a first main surface not lower than 50 Ω·cm and a rate of change in resistivity in the first main surface not higher than 3%, an average density of bulk micro defects in a region between the first main surface and a plane at a depth of 50 μm of less than 1×10 | 06-27-2013 |
20130168823 | SYSTEMS AND METHODS FOR BACKSIDE THRESHOLD VOLTAGE ADJUSTMENT - Described herein are semiconductor devices with a threshold voltage (V | 07-04-2013 |
20130168824 | P-DOPED SILICON LAYERS - The invention relates to a process for producing p-doped silicon layers, especially those silicon layers which are produced from liquid silane-containing formulations. The invention further relates to a substrate coated with a p-doped silicon layer. The invention additionally relates to the use of particular dopants based on boron compounds for p-doping of a silicon layer. | 07-04-2013 |
20130187257 | Semiconductor device and method for manufacturing the same - A method is disclosed for manufacturing a semiconductor device. The method includes providing a substrate and forming a well region in the substrate by an ion implantation. The method also includes forming, by rapid thermal oxidation and on the substrate having the well region, an oxide layer for repairing the substrate damaged by the ion implantation. Further, the method includes removing the oxide layer and forming a gate oxide layer on the repaired substrate having the well region. | 07-25-2013 |
20130249058 | SEMICONDUCTOR COMPONENT COMPRISING A DOPANT REGION IN A SEMICONDUCTOR BODY AND A METHOD FOR PRODUCING A DOPANT REGION IN A SEMICONDUCTOR BODY - A semiconductor component includes a semiconductor body having a first side and a second side opposite the first side. In the semiconductor body, a dopant region is formed by a dopant composed of an oxygen complex. The dopant region extends over a section L having a length of at least 10 μm along a direction from the first side to the second side. The dopant region has an oxygen concentration in a range of 1×10 | 09-26-2013 |
20130249059 | COATING LIQUID FOR IMPURITY DIFFUSION - Disclosed is a coating liquid for impurity diffusion comprising: (A) a polyvinyl alcohol resin having a 1,2-diol structural unit represented by the following general formula (1): | 09-26-2013 |
20130264683 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall. | 10-10-2013 |
20130285211 | DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES - Device structures, design structures, and fabrication methods for fin-type field-effect transistor integrated circuit technologies. First and second fins, which constitute electrodes of the device structure, are each comprised of a first semiconductor material. The second fin is formed adjacent to the first fin to define a gap separating the first and second fins. Positioned in the gap is a layer comprised of a second semiconductor material. | 10-31-2013 |
20130292799 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer. | 11-07-2013 |
20130313684 | PROCESS FOR FORMING A PLANAR DIODE USING ONE MASK - A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction. | 11-28-2013 |
20130341761 | METHODS FOR EXTENDING ION SOURCE LIFE AND IMPROVING ION SOURCE PERFORMANCE DURING CARBON IMPLANTATION - A novel method and system for extending ion source life and improving ion source performance during carbon implantation are provided. Particularly, the carbon ion implant process involves utilizing a dopant gas mixture comprising carbon monoxide and one or more fluorine-containing gas with carbon. At least one fluorine containing gases with carbon is contained in the mixture at about 3-12 volume percent (vol %) based on the volume of the dopant gas mixture. Fluoride ions, radicals or combinations thereof are released from the ionized dopant gas mixture and reacts with deposits derived substantially from carbon along at least one of the surfaces of the repeller electrodes, extraction electrodes and the chamber to reduce the overall amount of deposits. In this manner, a single dopant gas mixture is capable of providing carbon ions and removing and eliminating a wide range of problematic deposits typically encountered during carbon implantation. | 12-26-2013 |
20140001602 | DEVICE MANUFACTURING USING HIGH-RESISTIVITY BULK SILICON WAFER | 01-02-2014 |
20140042593 | SEMICONDUCTOR DEVICE INCLUDING A TRENCH IN A SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate. A first trench extends into or through the semiconductor substrate from a first side. A semiconductor layer adjoins the semiconductor substrate at the first side. The semiconductor layer caps the first trench at the first side. The semiconductor device further includes a contact at a second side of the semiconductor substrate opposite to the first side. | 02-13-2014 |
20140061860 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A compound semiconductor device and method of fabricating the same according to the present invention is disclosed. The compound semiconductor device comprises a substrate having at least a first doped region and at least a second doped region, and a semiconductor layer disposed on the substrate, wherein doping conditions of said first doped region and said second doped region may be different from each other. | 03-06-2014 |
20140070369 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n | 03-13-2014 |
20140097517 | SEMICONDUCTOR DEVICE HAVING LOCALIZED CHARGE BALANCE STRUCTURE AND METHOD - In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, UIS performance. | 04-10-2014 |
20140117502 | METHOD FOR PROCESSING A SEMICONDUCTOR CARRIER, A SEMICONDUCTOR CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier. | 05-01-2014 |
20140124896 | FORMULATIONS OF SOLUTIONS AND PROCESSES FOR FORMING A SUBSTRATE INCLUDING AN ARSENIC DOPANT - Formulations of solutions and processes are described to form a substrate including a dopant. In particular implementations, the dopant may include arsenic (As). In an embodiment, a dopant solution is provided that includes a solvent and a dopant. In a particular embodiment, the dopant solution may have a flashpoint that is at least approximately equal to a minimum temperature capable of causing atoms at a surface of the substrate to attach to an arsenic-containing compound of the dopant solution. In one embodiment, a number of silicon atoms at a surface of the substrate are covalently bonded to the arsenic-containing compound. | 05-08-2014 |
20140151853 | Ion Implantation Apparatus, Ion Implantation Method, and Semiconductor Device - In the plasma-based ion implantation for accelerating positive ions of a plasma and implanting the positive ions into a substrate to be processed on a holding stage in a processing chamber where the plasma has been excited, ion implantation is achieved in the following manner: an RF power having a frequency of 4 MHz or greater is applied to the holding stage to cause a self-bias voltage to generate on the surface of the substrate. The RF power is applied a plurality of times in the form of pulses. | 06-05-2014 |
20140231964 | Multiple Layer Substrate - A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration. | 08-21-2014 |
20140252553 | WAFER STRUCTURE AND POWER DEVICE USING THE SAME - In one embodiment, a method of making a super-junction MOS transistor in a wafer can include: (i) forming a first doping layer having a high doping concentration; (ii) forming a second doping layer on the first doping layer, wherein a doping concentration of the second doping layer is less than a doping concentration of the first doping layer; (iii) forming a third doping layer on the second doping layer, wherein the third doping layer comprises an intrinsic layer; (iv) etching through the third doping layer and partially through the second doping layer to form trenches; and (v) filling the trenches to form pillar structures. | 09-11-2014 |
20140252554 | WAFER STRUCTURE AND POWER DEVICE USING THE SAME - In one embodiment, a wafer structure configured for a power device can include: (i) a first doping layer having a high doping concentration; (ii) a second doping layer on the first doping layer, where a doping concentration of the second doping layer is less than the high doping concentration; and (iii) a third doping layer on the second doping layer, where a doping concentration of the third doping layer is greater than the doping concentration of the second doping layer. For example, the power device can be part of a switching voltage regulator. | 09-11-2014 |
20140264754 | METHODS OF FORMING DOPED ELEMENTS AND RELATED SEMICONDUCTOR DEVICE STRUCTURES - Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures. | 09-18-2014 |
20140291809 | Semiconductor Substrate and a Method of Manufacturing the Same - The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×10 | 10-02-2014 |
20140361407 | SILICON MATERIAL SUBSTRATE DOPING METHOD, STRUCTURE AND APPLICATIONS - A method for forming a boron doped region within a silicon material substrate, and the resulting silicon material substrate that includes the boron doped region, each use a boron doped aluminum oxide material layer as a boron dopant source layer. The method provides the boron doped region with a sheet resistance in a range from about 15 to about 300 ohms per square. The method is also applicable, in general, to forming an n doped region, a p doped region or an n and p co-doped region within a silicon material substrate. | 12-11-2014 |
20140361408 | OXYGEN PRECIPITATION IN HEAVILY DOPED SILICON WAFERS SLICED FROM INGOTS GROWN BY THE CZOCHRALSKI METHOD - A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony. | 12-11-2014 |
20150014816 | DOPED SEMICONDUCTOR FILMS AND PROCESSING - A method of forming a semiconductor material incorporating an electrical dopant is disclosed. In one aspect, a method of incorporating dopant in a semiconductor film comprises forming a first semiconductor material incorporating the dopant at a first dopant concentration and preferentially etching a portion of the first semiconductor material, wherein etching leaves a first etched semiconductor material incorporating the dopant at a second dopant concentration higher than the first dopant concentration. | 01-15-2015 |
20150028453 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate. | 01-29-2015 |
20150054134 | SILICON WAFER AND MANUFACTURING METHOD THEREOF - A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process. | 02-26-2015 |
20150076660 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10. | 03-19-2015 |
20150084162 | ELECTRONIC DEVICE INCLUDING A DIODE AND A PROCESS OF FORMING THE SAME - An electronic device can include a substrate, lower and upper semiconductor layers over the substrate, and a doped region at the interface between the lower and upper semiconductor layers. The doped region can have a conductivity type opposite that of a dopant within the lower semiconductor layer. Within the lower semiconductor layer, the dopant can have a dopant concentration profile that has a relatively steeper portion adjacent to the substrate, another relatively steeper portion adjacent to an interface between the first and second semiconductor layers, and a relatively flatter portion between the relative steeper portions. A diode lies at a pn junction where a second dopant concentration profile of the first doped region intersects the relatively flatter portion of the first dopant concentration profile. The electronic device can be formed using different processes described herein. | 03-26-2015 |
20150123247 | SEMICONDUCTOR COMPONENT HAVING A DOPANT REGION FORMED BY A DOPANT COMPOSED OF AN OXYGEN / VACANCY COMPLEX - A semiconductor component includes a semiconductor body having a first side and a second side opposite the first side. In the semiconductor body, a dopant region is formed by a dopant composed of an oxygen complex. The dopant region extends over a section L having a length of at least 10 μm along a direction from the first side to the second side. The dopant region has an oxygen concentration in a range of 1×10 | 05-07-2015 |
20150123248 | SILICON WAFERS WITH SUPPRESSED MINORITY CARRIER LIFETIME DEGRADATION - Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates. | 05-07-2015 |
20150294868 | Method of Manufacturing Semiconductor Devices Containing Chalcogen Atoms - Chalcogen atoms are implanted into a single crystalline semiconductor substrate. At a density of interstitial oxygen of at least 5E16 cm | 10-15-2015 |
20150303071 | EPITAXIAL WAFER AND A METHOD OF MANUFACTURING THEREOF - An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1×10 | 10-22-2015 |
20150348785 | SEMICONDUCTOR DEVICE STRUCTURES WITH DOPED ELEMENTS AND METHODS OF FORMATION - Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures. | 12-03-2015 |
20150380242 | SILICON SUBSTRATES WITH COMPRESSIVE STRESS AND METHODS FOR PRODUCTION OF THE SAME - A heterostructure including: a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate from the first primary surface; and an epitaxial layer disposed on the second primary surface of the substrate is disclosed along with methods for production of the same. | 12-31-2015 |
20150380492 | Semiconductor Device Containing Chalcogen Atoms and Method of Manufacturing - A semiconductor device includes a single crystalline semiconductor body with a first surface and a second surface parallel to the first surface. The semiconductor body contains chalcogen atoms and a background doping of pnictogen and/or hydrogen atoms. A concentration of the chalcogen atoms is at least 1E12 cm | 12-31-2015 |
20150380493 | MANUFACTURING METHOD OF EPITAXIAL SILICON WAFER, AND EPITAXIAL SILICON WAFER - An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 mΩ·cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter. | 12-31-2015 |
20160023892 | RADIO FREQUENCY (RF) MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICES WITH GOLD-DOPED SILICON - The present disclosure relates to radio frequency (RF) microelectromechanical system (MEMS) device packaging, and specifically to reducing harmonic distortion caused by such packaging. In one embodiment, a die is provided that employs a gold-doped silicon substrate, wherein at least one RF MEMS device is disposed on the gold-doped silicon substrate. By employing the gold-doped silicon substrate, the packaging can achieve an exceptionally high resistivity without any additional expensive components, wherein the high resistivity has an associated low carrier lifetime. Notably, the low carrier lifetime corresponds to reduced harmonic distortion generated by the gold-doped silicon substrate, even when operating at high power. Thus, the gold-doped silicon substrate provides a less expensive packaging in which to place RF MEMS devices, wherein the packaging is capable of operating at high power with reduced harmonic distortion. | 01-28-2016 |
20160035572 | DOPING OF A SUBSTRATE VIA A DOPANT CONTAINING POLYMER FILM - Disclosed herein is a method for doping a substrate, comprising disposing a coating of a composition comprising a copolymer, a dopant precursor and a solvent on a substrate; where the copolymer is capable of phase segregating and embedding the dopant precursor while in solution; and annealing the substrate at a temperature of 750 to 1300° C. for 0.1 second to 24 hours to diffuse the dopant into the substrate. Disclosed herein too is a semiconductor substrate comprising embedded dopant domains of diameter 3 to 30 nanometers; where the domains comprise Group 13 or Group 15 atoms, wherein the embedded spherical domains are located within 30 nanometers of the substrate surface. | 02-04-2016 |
20160035842 | Semiconductor Device Including a Trench at Least Partially Filled with a Conductive Material in a Semiconductor Substrate and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a semiconductor substrate and a first trench extending into or through the semiconductor substrate from a first side. The first trench is at least partially filled with a conductive material and electrically connected to the semiconductor substrate via a doped semiconductor layer at a sidewall of the first trench. A semiconductor layer adjoins the semiconductor substrate at the first side, and caps the first trench at the first side. A contact is disposed at a second side of the semiconductor substrate opposite to the first side. A method of manufacturing the semiconductor device is also provided. | 02-04-2016 |
20160141382 | Fabrication of Nanoscale Vacuum Grid and Electrode Structure With High Aspect Ratio Dielectric Spacers Between the Grid and Electrode - Some embodiments of vacuum electronics call for a grid that is fabricated in close proximity to an electrode, where, for example, the grid and electrode are separated by nanometers or microns. Methods and apparatus for fabricating a nanoscale vacuum grid and electrode structure are described herein. | 05-19-2016 |
20160155735 | SEMICONDUCTOR COMPONENT INCLUDING A SHORT-CIRCUIT STRUCTURE | 06-02-2016 |
20160379828 | SILICON DOPING SOURCE FILMS BY ALD DEPOSITION - A conformal thermal ALD film having a combination of elements containing a dopant, such as boron (or phosphorus), and an oxide (or nitride), in intimate contact with a semiconductor substrate said combination having stable ambient and thermal annealing properties providing a shallow (less than ˜100 A) diffused (or recoil implanted) dopant, such as boron (or phosphorus) profile, into the underlying semiconductor substrate. | 12-29-2016 |
20170234960 | SURFACE PHOTOVOLTAGE CALIBRATION STANDARD | 08-17-2017 |