| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257587000 |
With specified electrode means
| 21 |
| 257577000 |
Including additional component in same, non-isolated structure (e.g., transistor with diode, transistor with resistor, etc.)
| 19 |
| 257566000 |
Plural non-isolated transistor structures in same structure
| 16 |
| 257586000 |
With non-planar semiconductor surface (e.g., groove, mesa, bevel, etc.)
| 15 |
| 257578000 |
With enlarged emitter area (e.g., power device)
| 11 |
| 257592000 |
With base region having specified doping concentration profile or specified configuration (e.g., inactive base more heavily doped than active base or base region has constant doping concentration portion (e.g., epitaxial base))
| 9 |
| 257593000 |
With means to increase current gain or operating frequency | 5 |
| 20090206449 | STRESS-MODIFIED DEVICE STRUCTURES, METHODS OF FABRICATING SUCH STRESS-MODIFIED DEVICE STRUCTURES, AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT - Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices. The intervening materials or structures, such as contacts extending through an insulating layer of a local interconnect level between the contact level and the semiconductor devices, provide paths for the transfer of stress from the stress-imparting structures to the stress-modified semiconductor devices. | 08-20-2009 |
| 20100187657 | BIPOLAR TRANSISTOR WITH BASE-COLLECTOR-ISOLATION WITHOUT DIELECTRIC - The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittivity gas. In particular, a multilayer base-collector dielectric film is deposited over the collector region. A base region is formed onto the multilayer dielectric film and is patterned to form one or more base connection regions. The multilayer dielectric film is selectively etched during a plurality of isotropic etch processes to allow for the formation of one or more isolation region between the base connection regions and the collector region, wherein the one or more isolation regions comprise cavities filled with a gas having a low dielectric constant (e.g., air). The resultant bipolar transistor has a reduced base-collector capacitance, thereby allowing for improved frequency properties (e.g., higher maximum frequency operation). | 07-29-2010 |
| 20100013051 | Method Of Forming A Bipolar Transistor And Semiconductor Component Thereof - A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer. | 01-21-2010 |
| 20100219504 | Four-Terminal Gate-Controlled LVBJTs - An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantially encircling the emitter, and a base contact of the first conductivity type over the well region. The base contact is horizontally spaced apart from the emitter by the collector. At least one conductive strip horizontally spaces the emitter, the collector, and the base contact apart from each other. A dielectric layer is directly under, and contacting, the at least one conductive strip. | 09-02-2010 |
| 20120025352 | BIPOLAR JUNCTION TRANSISTOR DEVICES - A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other. | 02-02-2012 |
| 257591000 |
With emitter region having specified doping concentration profile (e.g., high-low concentration step) | 5 |
| 20130082353 | TUNABLE ESD PROTECTION DEVICE - The present disclosure provides an ESD protection device. The device contains a bipolar junction transistor device that includes a collector, a base, and an emitter. The collector includes a first doped element and a more heavily doped second doped element disposed over the first doped element. The first and second doped elements each have a first doping polarity. The base is located adjacent to the collector and includes a third doped element having a second doping polarity different from the first doping polarity. A p-n junction is formed between the third doped element and one of the first and second doped elements. The emitter is formed over the base. The emitter includes a fourth doped element having the first doping polarity and forming a p-n junction with the third doped element. The fourth doped element is more heavily doped than the third doped element. | 04-04-2013 |
| 20090321880 | SEMICONDUCTOR DEVICE - A semicoductor device includes: a collector layer made of a first conductivity type semiconductor; an intrinsic base layer formed on the collector layer and including a second conductivity type monocrystalline silicon germanium layer; a base extraction electrode formed around the intrinsic base layer and including a second conductivity type polycrystalline silicon layer and a second conductivity type polycrystalline silicon germanium layer; and a first conductivity type emitter layer formed in an upper portion of the intrinsic base layer. A silicon layer is formed in the upper portion of the intrinsic base layer and the emitter layer includes an upper emitter region formed in an upper portion of the silicon layer and a lower emitter region formed below and in contact with the upper emitter region. | 12-31-2009 |
| 20110291242 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device in which an IGBT, a control circuit for the IGBT and so on are formed on an SOI substrate divided by trenches, the invention is directed to providing the IGBT with a higher breakdown voltage, an enhanced turn-off characteristic and so on. An N type epitaxial layer is formed on a dummy semiconductor substrate, a trench is formed in the N type epitaxial layer, an N type buffer layer and then a P type embedded collector layer are formed on the sidewall of the trench and the front surface of the N type epitaxial layer, and the bottom of the trench and the P+ type embedded collector layer are covered by an embedded insulation film. The embedded insulation film is covered by a polysilicon film, and a P type semiconductor substrate is attached to the polysilicon film with an insulation film being interposed therebetween. Then the dummy semiconductor substrate is removed, thereby forming an SOI substrate having the embedded insulation film, the P+ type embedded collector layer, the N type buffer layer, the N type drift layer and so on that are exposed being almost flush with each other on the bottom of the trench. An IGBT and so on are formed on this SOI substrate. | 12-01-2011 |
| 20110169137 | HIGH-BETA BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURE - An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes. | 07-14-2011 |
| 20110049678 | LATERAL BIPOLAR TRANSISTOR WITH COMPENSATED WELL REGIONS - Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance. | 03-03-2011 |
| 257589000 |
Avalanche transistor | 1 |
| 20120025351 | SEMICONDUCTOR DEVICE - A bipolar transistor of the invention has a second base region | 02-02-2012 |
| Entries |
| Document | Title | Date |
|---|
| 20090160025 | LATERAL BIPOLAR TRANSISTOR - A P+ base drawing diffusion region is formed on a substrate having an SOI structure. N+ emitter diffusion regions are formed on both sides of the P+ base drawing diffusion region through isolation insulating films interposed therebetween. A P type SOI layer, which serves as a base diffusion region, is formed so as to surround the N+ emitter diffusion regions, and conductive layers are formed thereon. Further, an N+ collector diffusion region is formed so as to surround the conductive layers. | 06-25-2009 |
| 20120235280 | INTEGRATED CIRCUIT INCLUDING A BIPOLAR TRANSISTOR AND METHODS OF MAKING THE SAME - An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer. | 09-20-2012 |
| 20100019350 | Resonant operating mode for a transistor - The PN junctions of a transistor are biased for operation in the active mode but an initial flow of current reverses the bias of the base-emitter junction causing the transistor to conduct a resonant current with a voltage less than the forward junction voltage of said base-emitter. | 01-28-2010 |
| 20110140239 | High Voltage Bipolar Transistor with Pseudo Buried Layers - A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process. | 06-16-2011 |
| 20120098096 | BIPOLAR TRANSISTOR - A bipolar transistor comprises at least first and second connected emitter-base (EB) junctions having, respectively, different first and second EB junction depths, and a buried layer (BL) collector having a greater third depth. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region overlies the second EB junction location thereby providing its shallower EB junction depth. The BL collector does not underlie the first EB junction and is laterally spaced therefrom by a variable amount to facilitate adjusting the transistor's properties. In other embodiments, the BL collector can underlie at least a portion of the second EB junction. Regions of opposite conductivity type over-lie and under-lie the BL collector, which is relatively lightly doped, thereby preserving the breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements. | 04-26-2012 |
| 20120098095 | BIPOLAR TRANSISTOR WITH IMPROVED STABILITY - Instability and drift sometimes observed in bipolar transistors, having a portion of the base extending to the transistor surface between the emitter and base contact, can be reduced or eliminated by providing a further doped region of the same conductivity type as the emitter at the transistor surface between the emitter and the base contact. The further region is desirably more heavily doped than the base region at the surface and less heavily doped than the adjacent emitter. In another embodiment, a still or yet further region of the same conductivity type as the emitter is provided either between the further region and the emitter or laterally within the emitter. The still or yet further region is desirably more heavily doped than the further region. Such further regions shield the near surface base region from trapped charge that may be present in dielectric layers or interfaces overlying the transistor surface. | 04-26-2012 |
| 20110198727 | ESD PROTECTION DEVICE - An ESD protection device is described, which includes a P-body region, a P-type doped region, an N-type doped region and an N-sinker region. The P-body region is configured in a substrate. The P-type doped region is configured in the middle of the P-body region. The N-type doped region is configured in the P-body region and surrounds the P-type doped region. The N-sinker region is configured in the substrate and surrounds the P-body region. | 08-18-2011 |
| 20080290464 | NPN DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconductor device, wherein the BiCMOS-like process and the CMOS process provides the semiconductor device. | 11-27-2008 |
| 20080290463 | LATERAL BIPOLAR TRANSISTOR AND METHOD OF PRODUCTION - Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact with electrically conductive material that is introduced into trenches at the surface of the semiconductor body. | 11-27-2008 |
| 20080308903 | POLYCRYSTALLINE THIN FILM BIPOLAR TRANSISTORS - A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide. | 12-18-2008 |
| 20090174034 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE - The invention relates to a semiconductor device ( | 07-09-2009 |
| 20090212393 | METHOD OF MANUFACTURING AN ELECTRONIC DEVICE INCLUDING A PNP BIPOLAR TRANSISTOR - A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer. | 08-27-2009 |
| 20120104553 | Semiconductor device - A semiconductor device in which only the trigger voltage can be controlled without change in the hold voltage. In the semiconductor device, a protection device includes a lower doped collector layer, a sinker layer, a highly-doped collector layer, an emitter layer, a highly-doped base layer, a base layer, a first conductivity type layer, and a second conductivity type layer. The second conductivity type layer is formed in the lower doped collector layer and located between the base layer and first conductivity type layer. The second conductivity type layer has a higher impurity concentration than the lower doped collector layer. | 05-03-2012 |
| 20090085162 | SEMICONDUCTOR DEVICE AND INTEGRATED SEMICONDUCTOR CIRCUIT DEVICE - The present invention provides a semiconductor device that includes a plurality of transistor cells and makes it possible to achieve higher degree of integration and lower cost of an integrated semiconductor circuit device as the first object, and provide an integrated semiconductor circuit device of high density integration and compact construction at a low cost. | 04-02-2009 |
| 20090250789 | METHODS OF COUNTER-DOPING COLLECTOR REGIONS IN BIPOLAR TRANSISTORS - The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a first dopant profile in the silicon layer. The method also includes performing a second implant process to implant additional dopant of the second type in the silicon layer. The additional implanted dopant has a second dopant profile in the silicon layer different than the first dopant profile. The method further includes growing an insulating layer formed over the silicon layer by consuming a portion of the silicon layer and the first type of dopant. | 10-08-2009 |
| 20090315145 | ADJUSTABLE BIPOLAR TRANSISTORS FORMED USING A CMOS PROCESS - By providing a novel bipolar device design implementation, a standard CMOS process ( | 12-24-2009 |
| 20100148308 | Dopant Profile Control for Ultrashallow Arsenic Dopant Profiles - A method of manufacturing a semiconductor device comprises growing or depositing an implantation oxide layer, implanting a dopant, activating the dopant, and removing the implantation oxide layer after the step of activating the dopant. | 06-17-2010 |
| 20100155894 | Fabricating Bipolar Junction Select Transistors For Semiconductor Memories - A bipolar junction transistor may act as a select device for a semiconductor memory. The bipolar junction transistor may be formed of a stack of base and collector layers. Sets of parallel trenches are formed in a first direction down to the base and in a second direction down to the collector. The trenches may be used to form local enhancement implants into the exposed portion of the base and collector in each trench. As a result of the local enhancement implants, in some embodiments, leakage current may be reduced, active current capability may be higher, gain may be higher, base resistance may be reduced, breakdown voltage may be increased, and parasitic effects with adjacent junctions may be reduced. | 06-24-2010 |
| 20110233727 | VERTICAL SOI BIPOLAR JUNCTION TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost. | 09-29-2011 |
| 20090243042 | LATERAL SEMICONDUCTOR DEVICE - A semiconductor device has a first main electrode and a second main electrode that are provided on a semiconductor layer. The semiconductor layer has: an n type first semiconductor region in contact with the first main electrode; a p type second semiconductor region in contact with the second main electrode; and an n type third semiconductor region provided between the first and second semiconductor regions. The third semiconductor region has a first layer and a second layer. The impurity concentration in the first layer is uniform. The second layer has a higher impurity concentration than the first layer that increases in a gradient from the first semiconductor region to the second semiconductor region. | 10-01-2009 |
| 20100295157 | ESD PROTECTION DEVICE - An ESD protection device is described, which includes a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region and an isolation structure. The first P-type doped region is configured in a substrate. The second P-type doped region is configured in the first P-type doped region. The first N-type doped region is configured in the first P-type doped region and surrounds the second P-type doped region. The second N-type doped region is configured in the substrate and surrounds the first P-type doped region. The isolation structure is disposed between the first P-type doped region and the second N-type doped region, wherein a spacing is deployed between an outward edge of the first N-type doped region and the isolation structure. | 11-25-2010 |
| 20090127659 | Bipolar junction transistor with a low collector resistance and method of forming the bipolar junction transistor in a CMOS process flow - The collector resistance of a bipolar junction transistor that is formed in a CMOS process is substantially reduced by forming a heavily-doped collector extension region that extends from a heavily-doped collector contact region down to a deep well of the same conductivity type to a point that lies close to the base of the transistor. | 05-21-2009 |
| 20090200641 | Semiconductor device and method of manufacturing the same - The invention relates to a semiconductor device ( | 08-13-2009 |
| 20110095398 | BIPOLAR SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME - A bipolar semiconductor device includes a collector region that is an n-type low-resistance layer formed in one surface of a semiconductor crystal substrate, an n-type first high-resistance region on the collector region, a p-type base region on the first high-resistance region, an n-type low-resistance emitter region that is formed in another surface of the semiconductor crystal substrate, an n-type second high-resistance region between the emitter region and the base region so as to contact the emitter region, an n-type recombination suppressing region around the second high-resistance region so as to adjoin the second high-resistance region, and a p-type low-resistance base contact region which is provided so as to adjoin the recombination suppressing region, and which contacts the base region. Each of doping concentrations of the second high-resistance region and the recombination suppressing region is equal to or lower than 1×10 | 04-28-2011 |
| 20110260292 | Bipolar Junction Transistor Having a Carrier Trapping Layer - A bipolar junction transistor having a carrier trapping layer, comprises a semi-conductor substrate including a well with a first type ions formed thereon; two impurity regions with a second type ions formed opposite with each other over the well; an insulation layer over the well, and edges extend over the second two impurity regions; and a carrier trapping layer formed over the insulation layer. | 10-27-2011 |
| 20110147892 | Bipolar Transistor with Pseudo Buried Layers - A structure and fabrication method for a bipolar transistor with shallow trench isolation (STI) comprises a collector formed by implanting first electric type impurity in active area; pseudo buried layers at the bottom of STI at both sides of active area by implanting heavy dose of first electric type impurity; deep contacts through field oxide to connect to pseudo buried layers and to pick up the collector; a base, a thin film deposited on the collector and doped with second electric type impurity; an emitter, a polysilicon film doped by heavy dose implant of first electric type impurity. This transistor has smaller device area, less parasitic effect, less photo layers and lower process cost. | 06-23-2011 |
| 20110186965 | REVERSE-CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR - Reverse-conducting insulated gate bipolar transistor in which IGBT region and FWD region are integrated into a single body in a semiconductor substrate with a common active region is disclosed. MOS gate structure is on a first major surface side. Rear surface side structure is in a second major surface side of the semiconductor substrate and includes a plurality of recessed parts vertical to the second major surface, which are repeated periodically along the second major surface. A plurality of protruding parts are interposed between the recessed parts. Rear surface side structure includes p type collector region on a bottom surface of the recessed part, n type first field stop region at a position deeper than the collector region, n type cathode region on the top surface of the protruding part, and n type second field stop region in the protruding part at a position deeper than the cathode region. | 08-04-2011 |
| 20100320571 | BIPOLAR TRANSISTOR STRUCTURE AND METHOD INCLUDING EMITTER-BASE INTERFACE IMPURITY - A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure. | 12-23-2010 |
| 20110304019 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES OBTAINED THEREBY - Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer ( | 12-15-2011 |
| 20110156210 | SEMICONDUCTOR DEVICE - A semiconductor device according to embodiments of the invention includes an n | 06-30-2011 |
| 20120056305 | SPACER STRUCTURE FOR TRANSISTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width. | 03-08-2012 |
| 20120112318 | TRANSISTOR AND PROCESS OF PRODUCING THE SAME, LIGHT-EMITTING DEVICE, AND DISPLAY - A transistor capable of modulating, at low voltages, a large current flowing between an emitter electrode and a collector electrode. A process of producing the transistor, a light-emitting device comprising the transistor, and a display comprising the transistor. The transistor comprises an emitter electrode and a collector electrode. Between the emitter electrode and the collector electrode are situated a semiconductor layer and a sheet base electrode. It is preferred that the semiconductor layer be situated between the emitter electrode and the base electrode and also between the collector electrode and the base electrode to constitute a second semiconductor layer and a first semiconductor layer, respectively. It is also preferred that the thickness of the base electrode be 80 nm or less. Furthermore, a dark current suppressor layer is situated at least between the emitter electrode and the base electrode, or between the collector electrode and the base electrode. | 05-10-2012 |
| 20120018845 | Polysilicon Plug Bipolar Transistor For Phase Change Memory - Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base. | 01-26-2012 |
| 20120068309 | Transistor and Method of Manufacturing a Transistor - In accordance with an embodiment of the present invention a transistor is disclosed. The transistor comprises a collector, a base and an emitter, wherein a first end width of the base is larger than a middle width of the base, wherein a first end width of the collector is larger than a middle width of the collector, or wherein a first end width of the emitter is larger than a middle width of the emitter. | 03-22-2012 |
| 20110089535 | Electrostatic Discharge Protection Device - The invention provides an electrostatic discharge (ESD) protection device having an ESD path between a first circuit and a second circuit. The electrostatic discharge protection device includes a first doped region having a first conductive type. A first well has a second conductive type opposite to the first conductive type. A second doped region and a third doped region are in the first well, respectively having the first and second conductive types. The first doped region is coupled to a power supply terminal or a ground terminal of the first circuit, and the second and third doped regions are both coupled to a power supply terminal or a ground terminal of the second circuit, respectively. | 04-21-2011 |
| 20120168908 | SPACER FORMATION IN THE FABRICATION OF PLANAR BIPOLAR TRANSISTORS - A bipolar transistor is fabricated having a collector ( | 07-05-2012 |
| 20120168909 | RADIATION HARDENED BIPOLAR INJUNCTION TRANSISTOR - A method for integrating a bipolar injunction transistor in a semiconductor chip includes the steps of forming an intrinsic base region of a second type of conductivity extending in the collector region from a main surface through an intrinsic base window of the sacrificial insulating layer, forming an emitter region of the first type of conductivity extending in the intrinsic base region from the main surface through an emitter window of the sacrificial insulating layer, removing the sacrificial insulating layer, forming an intermediate insulating layer on the main surface, and forming an extrinsic base region of the second type of conductivity extending in the intrinsic base region from the main surface through an extrinsic base window of the intermediate insulating layer | 07-05-2012 |
| 20120168907 | FLAT RESPONSE DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS - Bipolar transistors with tailored response curves, as well as fabrication methods for bipolar transistors and design structures for BiCMOS integrated circuits. The bipolar transistor includes a first section of a collector region implanted with a first dopant concentration and a second section of the collector region implanted with a second dopant concentration that is higher than the first dopant concentration. A first emitter is formed in vertical alignment with the first section of the collector region. A second emitter is formed in vertical alignment with the second section of the collector region. | 07-05-2012 |
| 20090020851 | BICMOS DEVICES WITH A SELF-ALIGNED EMITTER AND METHODS OF FABRICATING SUCH BICMOS DEVICES - A method of fabricating an heterojunction bipolar transistor (HBT) structure in a bipolar complementary metal-oxide-semiconductor (BiCMOS) process selectively thickens an oxide layer overlying a base region in areas that are not covered by a temporary emitter and spacers such that the temporary emitter can be removed and the base-emitter junction can be exposed without also completely removing the oxide overlying the areas of the base region that are not covered by the temporary emitter or spacers. As a result, a photomask is not required to remove the temporary emitter and to expose the base-emitter junction. | 01-22-2009 |
| 20130009280 | BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES - Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together. | 01-10-2013 |
| 20120248573 | TUNABLE SEMICONDUCTOR DEVICE - Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern. | 10-04-2012 |
| 20130093057 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductive type semiconductor layer formed on a substrate; a first conductive type embedded layer formed between the substrate and the semiconductor layer; a second conductive type well formed on the semiconductor layer; a first conductive type first contact layer that is positioned on the semiconductor layer, separate from the well; a second conductive type second contact layer formed on the well; a first conductive type third contact layer formed on the well between the first and second contact layers; and a first conductive type deep layer formed between the embedded layer and the first contact layer and in contact with the first contact layer. A minimum point in the effective impurity concentration profile along a straight line that extends in a vertical direction and passes through the embedded layer and the second part exists between the embedded layer and the first part. | 04-18-2013 |
| 20130119516 | PNP BIPOLAR JUNCTION TRANSISTOR FABRICATION USING SELECTIVE EPITAXY - Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base. | 05-16-2013 |
