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Including capacitor component

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257499000 - INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS

257528000 - Passive components in ICs

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
257534000 With means to increase surface area (e.g., grooves, ridges, etc.) 41
257535000 Both terminals of capacitor isolated from substrate 11
257533000 Combined with resistor to form RC filter structure 8
Entries
DocumentTitleDate
20090102018LOCALIZED MASKING FOR SEMICONDUCTOR STRUCTURE DEVELOPMENT - Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical planarization (CMP), thus eliminating CMP-induced defects and variations. The methods utilize localized masking of holes for protection of the inside of the holes during non-mechanical removal of exposed surface layers. The localized masking is accomplished through differential exposure of a resist layer to electromagnetic or thermal energy. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.04-23-2009
20130069201Yttrium and Titanium High-K Dielectric Films - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.03-21-2013
20090085158Package with improved connection of a decoupling capacitor - A package (04-02-2009
20130043559TRENCH FORMATION IN SUBSTRATE - A method includes removing an exposed portion of a first portion of a substrate to define a first trench portion partially defined by the first portion of the substrate and expose a second portion of the substrate, the first portion of the substrate disposed on the second portion of the substrate, the second portion of the substrate including an N+ doped silicon material, and removing a portion the exposed second portion of the substrate with an isotropic etching process to define a second trench portion.02-21-2013
20130043562Compressive Polycrystalline Silicon Film and Method of Manufacture Thereof - In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.02-21-2013
20130026602SEMICONDUCTOR DEVICE - A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 01-31-2013
20130026603SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.01-31-2013
20110204477Semiconductor integrated circuit device - A capacitance cell includes a substrate structure layer having pair diffusion regions, and an interconnect layer having pair of power supply lines. The capacitance cell also includes a capacitance composed of a first electrode, a dielectric member and a second electrode stacked together, and is formed in a frame shape and disposed in a space between the substrate structure layer and the interconnect layer so as to extend along an outer rim of the frame shape of a standard cell region in which a standard cell is arranged. The capacitance cell also includes a first substrate contact that electrically connects one of the pair of power supply lines to one of the diffusion regions externally of the standard cell region. The capacitance cell also includes a second substrate contact that electrically connects the other power supply line to the other diffusion region, externally of the standard cell region. The capacitance cell further includes a first capacitance contact electrically connecting the first electrode to the other diffusion region internally of the standard cell region, and a second capacitance contact electrically connecting the second electrode to the one power supply line internally of the standard cell region.08-25-2011
20090194844SUBSTRATE CONTACT FOR ADVANCED SOI DEVICES BASED ON A DEEP TRENCH CAPACITOR CONFIGURATION - By forming a first portion of a substrate contact in an SOI device on the basis of a trench capacitor process, the overall manufacturing process for patterning contact elements may be enhanced since the contacts may only have to extend down to the level of the semiconductor layer. Since the lower portion of the substrate contact may be formed concurrently with the fabrication of trench capacitors, complex patterning steps may be avoided which may otherwise have to be introduced when the substrate contacts are to be formed separately from contact elements connecting to the device level.08-06-2009
20100052097CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a capacitor of a semiconductor device includes f forming a cylindrical storage node over a semiconductor substrate; depositing a first dielectric layer over the cylindrical storage node; and etching the first dielectric layer to reduce a thickness of a portion of the first dielectric layer on a protruded end of the cylindrical storage node. The method further includes depositing a second dielectric layer over the etched first dielectric layer, wherein the second dielectric layer supplements a thickness of a portion of the first dielectric layer on a bottom corner of the cylindrical storage node. Finally, a cell plate is formed over the second dielectric layer.03-04-2010
20130134555CAPACITIVE ELEMENT - A capacitive element includes: an upper electrode; a lower electrode; and a dielectric layer that is disposed between the upper electrode and the lower electrode, and includes a first film, a second film and a third film which are made of any one of silicon nitride and aluminum oxide and laminated from a side of the lower electrode in order, a composition ratio of any one of silicon and aluminum in each of the first film and the third film being larger than a corresponding composition ratio in the second film.05-30-2013
20130043560Metal-Insulator-Metal Capacitor and Method of Fabricating - Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.02-21-2013
20110193194THIN FILM MIM CAPACITORS AND MANUFACTURING METHOD THEREFOR - Proposed are thin film MIM capacitors with which deterioration of insulating properties and leakage current properties can be sufficiently inhibited. Also proposed is a manufacturing method for the thin film MIM capacitors. For the thin film MIM capacitor (08-11-2011
20110193193STRUCTURE AND METHOD FOR FORMING ISOLATION AND BURIED PLATE FOR TRENCH CAPACITOR - A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.08-11-2011
20100164064Capacitor and Method for Manufacturing the Same - A capacitor and methods for manufacturing the capacitor are disclosed. The method may include forming a first electrode on a substrate, forming a dielectric layer on the first electrode, the dielectric layer having a first silicon oxide (SiO07-01-2010
20100164061SEMICONDUCTOR CHIP, SEMICONDUCTOR MOUNTING MODULE, MOBILE COMMUNICATION DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR CHIP - A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor.07-01-2010
20130037913Inexpensive electrode materials to facilitate rutile phase titanium oxide - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO02-14-2013
20130037912METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) WITH SIMULTANEOUS FORMATION OF SIDEWALL FERROELECTRIC CAPACITORS - Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.02-14-2013
20130037911CHIP-COMPONENT STRUCTURE AND METHOD OF PRODUCING SAME - In a chip-component structure, a monolithic ceramic capacitor is a structure including a predetermined number of substantially flat internal electrodes stacked on each other. An interposer includes a substrate larger than the outer shape of the monolithic ceramic capacitor. The substrate includes a first major surface on which first front electrodes for use in mounting the monolithic ceramic capacitor are disposed and a second major surface on which first back electrodes for use in connecting to an external circuit board are disposed. The interposer includes a depression in its side surface. The depression includes a wall surface on which a connection conductor is disposed. The front surface of the substrate is overlaid with resist films extending along its edges.02-14-2013
20130037910Decoupling MIM Capacitor Designs for Interposers and Methods of Manufacture Thereof - Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device.02-14-2013
20130037909Semiconductor Structure with Galvanic Isolation - Galvanic isolation between a high-voltage die and a low-voltage die in a multi-die chip is provided by a galvanic isolation die that physically supports the high-voltage die and the low-voltage die, and provides capacitive structures with high breakdown voltages that allow the high-voltage die to capacitively communicate with the low-voltage die.02-14-2013
20130087887STACK PACKAGE - A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.04-11-2013
20120175733SEMICONDUCTOR DEVICE HAVING CONDUCTORS WITH DIFFERENT DIMENSIONS AND METHOD FOR FORMING - A device structure includes an inter-level dielectric, a via, a first conductive trench, and a second conductive trench. The inter-level dielectric has a top surface and a bottom surface. The via extends from the top surface to the bottom surface. The first conductive trench extends from the top surface to a first depth below the top surface. The second conductive trench extends from the top surface to a second depth below the top surface, wherein the second depth is above the bottom surface and below the first depth.07-12-2012
20100117192SEMICONDUCTOR INTEGRATED CIRCUIT CHIP, MULTILAYER CHIP CAPACITOR AND SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGE - Disclosed are a semiconductor integrated circuit chip, a multilayer chip capacitor, and a semiconductor integrated circuit chip package. The semiconductor integrated circuit chip includes a semiconductor integrated circuit chip body, an input/output terminal disposed on the outside of the semiconductor integrated circuit chip body, and a decoupling capacitor disposed at a side face of the semiconductor integrated circuit chip body and electrically connected to the input/output terminal. The semiconductor integrated circuit chip cab be obtained, which can maintain an impedance of a power distribution network below a target impedance in a wide frequency range, particularly at a high frequency, by minimizing an inductance between a decoupling capacitor and a semiconductor integrated circuit chip.05-13-2010
20130032925SEMICONDUCTOR DEVICE - A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.02-07-2013
20130032924SEMICONDUCTOR DEVICE HAVING CYLINDRICAL LOWER ELECTRODE OF CAPACITOR AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.02-07-2013
20130075862EMBEDDED CAPACITOR AND METHOD OF FABRICATING THE SAME - Methods are provided for forming a capacitor. In one embodiment, a method comprises providing an insulator material layer over a substrate, etching at least one via in the insulator material layer and depositing a contact material fill in the at least one via to form a first set of contacts. The method further comprises etching the insulator material layer adjacent at least one contact of the first set of contacts to form at least one void, depositing a dielectric material layer over the at least one void and over the first set of contacts and depositing a contact material fill in the at least void to form a second set of contacts.03-28-2013
20130043561SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a capacitor dielectric film formed on a lower electrode and made of a ferroelectric material, and an upper electrode formed on a capacitor dielectric film, wherein the lower electrode includes a lowest conductive layer and an upper conductive layer, the lowest conductive layer being made of a noble metal other than iridium, and the upper conductive layer being formed on the lowest conductive layer and made of a conductive material, which is different from a material for the lowest conductive layer, and which is other than platinum.02-21-2013
20100032801CAPACITOR FORMED IN INTERLEVEL DIELECTRIC LAYER - An capacitor is formed in an interlevel dielectric (ILD) layer of the integrated circuit (IC) by etching vertical trenches through the ILD and depositing conformal layers of a bottom electrode metal, a capacitor dielectric and a top electrode metal. The capacitor can attain a capacitance density of 20 nanofarads/mm02-11-2010
20100044832STRUCTURE OF TRENCH CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - A structure of trench capacitor and method for manufacturing the trench capacitor is provided. The collar oxide layer of the trench capacitor is formed by a thermal oxidation process. Moreover, a protective layer such as silicon nitride covers the collar oxide layer. A failure analysis of the collar oxide layer can be operated by detecting the protective layer. If the protective layer is detected, the collar oxide layer is therefore at a suitable thickness. Furthermore, a mask layer rather than the collar oxide layer is used as a mask during the trench formation.02-25-2010
20100044831MULTI-LAYER FILM CAPACITOR WITH TAPERED FILM SIDEWALLS - A multi-layer capacitor of staggered construction is formed of one or more layers having tapered sidewall(s). The edge(s) of the capacitor film(s) can be etched to have a gentle slope, which can improve adhesion of the overlying layers and provide more uniform film thickness. The multi-layer capacitor can be used in various applications such as filtering and decoupling.02-25-2010
20090160023Semiconductor device and manufacturing method thereof - An insulation film (06-25-2009
20090160021Corona prevention in high power MMICs - The present invention is drawn to an MMIC capacitor comprising a dielectric material interposed between a metal top plate and a metal bottom plate; and a passivation layer having the composition of the dielectric material and applied to the capacitor components such that thickness of the layer eliminates a corona effect. The invention also includes a method for passivating a layer of SiNi material onto a top plate having a thickness sufficient to reduce a corona effect dependent on an applied voltage.06-25-2009
20090160020Moisture Barrier Capacitors in Semiconductor Components - Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.06-25-2009
20090160019SEMICONDUCTOR CAPACITOR - A capacitor structure is provided. The capacitor structure includes a plurality of first conductive lines paralleled disposed in a conductive layer on a substrate, wherein the first conductive lines are isolated to each other in the conductive layer and are grouped into a first electrode group and a second electrode group, an insulating layer formed on the first conductive lines and in the space between the first conductive lines, a second conductive line formed on the insulating layer electrically connected to the first conductive lines of the first electrode group, and a third conductive line formed on the insulating layer electrically connected to the first conductive lines of the second electrode group.06-25-2009
20100109124METHOD OF FORMING A METAL-INSULATOR-METAL CAPACITOR - A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer.05-06-2010
20130082352STACK PACKAGE - A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.04-04-2013
20130082351Method for Fabricating a MIM Capacitor Having a Local Interconnect Metal Electrode and Related Structure - According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.04-04-2013
20100025818INTEGRATED CIRCUIT PACKAGE - An integrated circuit package is described that includes an integrated circuit die, a plurality of lower contact leads, and an insulating substrate positioned over the die and lower contact leads. The insulating substrate includes a plurality of electrically conducting upper routing traces formed on the bottom surface of the substrate. The traces on the bottom surface of the substrate electrically couple each lower contact lead with an associated I/O pad.02-04-2010
20090230511METHOD FOR FORMING CAPACITOR IN A SEMICONDUCTOR DEVICE - A method for forming a capacitor of a semiconductor device ensures charging capacity and improves leakage current characteristic. In the capacitor forming method, a semiconductor substrate formed with a storage node contact is prepared first. Next, a storage electrode is formed such that the storage electrode is connected to the storage node contact. Also, a dielectric film comprised of a composite dielectric of a SrTiO3 film and an anti-crystallization film is formed on the storage electrode. Finally, a plate electrode is formed on the dielectric film.09-17-2009
20130087885Metal-Oxide-Metal Capacitor Apparatus - A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A via-hole region is employed to enclose the metal-oxide-metal capacitor so as to remove the moisture stored in the low k dielectric material.04-11-2013
20130087888SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a method for manufacturing a semiconductor device, including, forming a first insulating film on a semiconductor substrate, forming a capacitor on the first insulating film, forming a second insulating film covering the capacitor, forming a metal wiring on the second insulating film, forming a first capacitor protective insulating film covering the metal wiring and the second insulating film, forming an insulating sidewall on a side of the metal wiring, forming a third insulating film on the insulating sidewall, forming a hole by etching the third insulating film under a condition that an etching rate of the insulating sidewall would be lower than that of the third insulating film, and forming a conductive plug inside the hole.04-11-2013
20130087886MOM Capacitor Having Local Interconnect Metal Plates and Related Method - According to one exemplary embodiment, a metal-oxide-metal (MOM) capacitor in a semiconductor die comprises a first plurality of capacitor plates and a second plurality of capacitor plates sharing a plane parallel to and below a plane of a first metallization layer of the semiconductor die. The MOM capacitor further comprises a local interlayer dielectric between the first plurality of capacitor plates and the second plurality of capacitor plates. The first and second plurality of capacitor plates are made from a local interconnect metal for connecting devices formed in a device layer of the semiconductor die situated below the first metallization layer.04-11-2013
20120181662LANTHANIDE DIELECTRIC WITH CONTROLLED INTERFACES - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.07-19-2012
20120181661METHOD FOR TUNING THE TRHESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE - A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.07-19-2012
20120181660SEMICONDUCTOR DEVICE - A semiconductor device comprises a capacitor, the capacitor including a lower electrode, a dielectric film containing crystalline zirconium oxide formed on the lower electrode, and an upper electrode containing a titanium nitride film contacting to the dielectric film, wherein the dielectric film comprises an amorphous film on an interface with the titanium nitride film, thereby preventing the reduction of the thickness of the titanium nitride film formed on the dielectric electrode with a low leakage current and a high dielectric constant.07-19-2012
20120181659SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A ferroelectric capacitor formed above a semiconductor substrate includes a lower electrode, a dielectric film (ferroelectric film) having ferroelectric characteristics, and an upper electrode. The upper electrode includes a conductive oxide film made of a ferroelectric material to which conductivity is provided by adding a conductive material such as Ir, and the conductive oxide film is in contact with the dielectric film.07-19-2012
20120181658HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape.07-19-2012
20090045485CAPACITOR, METHOD OF MANUFACTURING CAPACITOR, CAPACITOR MANUFACTURING APPARATUS, AND SEMICONDUCTOR MEMORY DEVICE - The present invention provides a capacitor including: an under electrode; an upper electrode; and a dielectric film which is provided between the under electrode and the upper electrode, wherein at least a portion of the dielectric film is composed of an aluminum oxide film deposited by an atomic layer deposition method and a titanium oxide film deposited by the atomic layer deposition method. An aluminum composition ratio x and a titanium composition ratio y in the dielectric film preferably comply with 7≦[x/(x+y)]×100≦35.02-19-2009
20100038752MODULAR & SCALABLE INTRA-METAL CAPACITORS - An intra-metal capacitor unit cell comprises a first electrode and a second electrode formed in the same device layer. A dielectric layer separates the electrodes. The first electrode is substantially surrounded by the second electrode. Misalignment between the first and second electrodes does not substantively alter the capacitance of the unit cell.02-18-2010
20090302422Capacitor-cell, integrated circuit, and designing and manufacturing methods - A capacitor-cell is in an integrated circuit that is configured by disposing a plurality of cells on a site that is on a chip and that is provided between a power line and a grounding line in a direction of the power line and grounding line. The capacitor cell is disposed in a remaining region on the site, after the plurality of cells are disposed on the site. The capacitor-cell includes a gate poly for accumulating capacitance extending up to at least one of positions of the power line and the grounding line in a planar quadrangular cell-frame that is set for disposing the plurality of cells on the site.12-10-2009
20090302421Method and apparatus for creating a deep trench capacitor to improve device performance - A deep trench capacitor includes a trench having walls and a floor. The deep trench capacitor also includes a layer of gate oxide on the walls and floor. Gate polysilicon is deposited over the gate oxide.12-10-2009
20120217616SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE - A semiconductor device includes a plurality of functional element chips, an electric connection member joined to two of the functional element chips, a first wire and a resin configured to cover the functional element chips, the electric connection member and the first wire. One of the two functional element chips may be a first semiconductor chip having first and second major surface electrodes facing toward the same direction and a first rear surface electrode facing in a direction opposite to a direction in which the first major surface electrode faces. The electric connection member may be joined to the first major surface electrode. The first wire may be joined to the second major surface electrode. The first wire may include a portion overlapping with the electric connection member in a thickness direction of the first semiconductor chip.08-30-2012
20120217615GRAIN BOUNDARY-INSULATED SEMICONDUCTOR CERAMIC, SEMICONDUCTOR CERAMIC CAPACITOR, AND METHOD FOR PRODUCING SEMICONDUCTOR CERAMIC CAPACITOR - A grain boundary-insulated semiconductor ceramic contains a SrTiO08-30-2012
20110006393Multilayer electronic devices for imbedded capacitor - Disclosed herein are multilayer electronic devices comprising a high dielectric constant polymer composite layer that contains conductive components for embedded capacitor applications01-13-2011
20130069198Semiconductor structure and method for making same - An embodiment may be a semiconductor structure, comprising; a workpiece having a front side and a back side; and a capacitor disposed in the workpiece, the capacitor including a bottom electrode electrically coupled to a back side of said workpiece. In an embodiment, the bottom electrode may form a conductive pathway to the front side of the workpiece. In an embodiment, the capacitor may be a trench capacitor.03-21-2013
20130069200METHOD OF FORMING A ROBUST, MODULAR MIM CAPACITOR WITH IMPROVED CAPACITANCE DENSITY - A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilsicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack an don exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.03-21-2013
20130069202Electrode Treatments for Enhanced DRAM Performance - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO03-21-2013
20130069199METAL INSULATOR METAL (MIM) CAPACITOR STRUCTURE - A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.03-21-2013
20130056852Methods For Depositing High-K Dielectrics - Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.03-07-2013
20130056851Molybdenum Oxide Top Electrode for DRAM Capacitors - A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO03-07-2013
20130056850SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.03-07-2013
20120112316SEMICONDUCTOR DEVICE AND FABRICATING METHOD OF THE SAME - Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 μm.05-10-2012
20120112315METHOD AND SYSTEM FOR MANUFACTURING COPPER-BASED CAPACITOR - Embodiments of the present invention provide a method and system for manufacturing copper-based capacitor on an integrated circuit. For example, the integrated circuit is associated with a channel length of less than 0.13 um. It is to be appreciated that, depending upon application, the present invention provides a more improved method for manufacturing capacitors and thus allow MIM capacitors to be manufactured at smaller dimensions. The method includes a step for providing a substrate. The method also includes a step for providing a layer of inter-metal dielectric overlaying the substrate. The method additionally includes a step for providing a bottom layer. The bottom layer includes a first portion and a second portion. The first portion can be characterized as electrically conductive. In addition, the method includes a step for providing a first insulating layer overlaying the bottom layer.05-10-2012
20120187533Capacitors and Methods of Forming Capacitors - Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of upwardly-extending sidewalls. Individual sidewalls may have a narrower segment over a wider segment. Capacitor dielectric material and capacitor electrode material may be along the narrower and wider segments of the sidewalls. Some embodiments include methods of forming capacitors in which an initial container-shaped storage node structure is formed to have a pair of upwardly-extending sidewalls along a cross-section, with the sidewalls being of thickness that is substantially constant or increasing from a base to a top of the initial structure. The initial structure is then converted into a modified storage node structure by reducing thicknesses of upper segments of the sidewalls while leaving thicknesses of lower segments of the sidewalls substantially unchanged. Capacitor dielectric material and capacitor electrode material are formed along the modified storage node structure.07-26-2012
20130113080NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device contains a memory cell region, a first electrode, and a second electrode. The memory cell region is formed on a substrate and comprises multiple memory cells stacked on the substrate as part of memory strings. Multiple first conductive layers are laminated on the substrate. The first electrode functions as an electrode at one side of a capacitive component and comprises multiple conductive layers stacked on the substrate and separated horizontally from stacked conductive layers of the second electrode which is disposed at a side of the capacitive component opposite the first electrode.05-09-2013
20090283857METHOD OF MANUFACTURING CAPACITOR OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes sequentially forming an insulating layer and a metal layer over a semiconductor substrate, forming a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a reflowed photoresist pattern surrounding the metal line pattern, forming a metal-insulator-metal (MIM) layer over the semiconductor substrate provided with the reflowed photoresist pattern, and removing the MIM layer arranged over the photoresist pattern and the photoresist pattern.11-19-2009
201301130723D Capacitor and Method of Manufacturing Same - A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.05-09-2013
20100084738CAPACITANCE ELEMENT, PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR CIRCUIT - A capacitive element that can efficiently reduce high-frequency noise generated in a circuit is provided. A capacitive element 04-08-2010
20100084739Semiconductor device and method of manufacturing the same - A semiconductor device includes a MIM capacitor that includes an insulating film and a first electrode and a second electrode which are formed in the same layer in the insulating film and are facing to each other with the insulating film interposed therebetween. The first electrode and the second electrode respectively include a first high aspect via and a second high aspect via which extend as long as a length, in a stacked direction of the substrate, of a via and an interconnect provided on the via so as to be connected to the via formed in another region. A first potential and a second potential are respectively supplied to the first electrode and the second electrode.04-08-2010
20090267185METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.10-29-2009
20090267183Through-substrate power-conducting via with embedded capacitance - When integrated circuits are mounted on a substrate, little space is often available for the required large number of bypass capacitors. A novel substrate structure therefore includes many closely spaced through-holes that extend from a first surface of the substrate to a second surface of the substrate. Each through-hole includes a first conducting layer, a dielectric layer, and a second conducting layer. The first and second conducting layers and the intervening dielectric layer constitute a via having a substantial capacitance (one picofarad). Some of the many vias provide bypass capacitance directly under the integrated circuits. A first set of vias supplies power from a power bus bar on one side of the substrate to the integrated circuits on the other side. A second set of vias sinks current from the integrated circuits on the other side, through the substrate, and to a ground bus bar on the one side.10-29-2009
20130062733Integrated Circuit with Integrated Decoupling Capacitors - Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.03-14-2013
20130062732INTERCONNECT STRUCTURES WITH FUNCTIONAL COMPONENTS AND METHODS FOR FABRICATION - An electronic device includes an interlevel dielectric layer formed over a substrate and has a first set of openings and a second set of openings formed through the interlevel dielectric layer. The substrate includes conductive areas. A conductive contact structure is formed in the first set of openings in the interlevel dielectric layer to make electrical contact with the conductive areas of the substrate. A functional component is formed in the second set of openings in the interlevel dielectric layer and occupies a same level as the conductive contact structure.03-14-2013
20120223414METHODS FOR INCREASING BOTTOM ELECTRODE PERFORMANCE IN CARBON-BASED MEMORY DEVICES - In some aspects, a method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including: forming a first conducting layer comprising a titanium nitride material having between about 50% Ti and about 95% Ti, forming a carbon nano-tube (CNT) material above the first conducting layer, forming a second conducting layer above the CNT material, and etching the first conducting layer, CNT material and second conducting layer to form the MIM stack. Numerous other aspects are provided.09-06-2012
20120223413SEMICONDUCTOR STRUCTURE HAVING A CAPACITOR AND METAL WIRING INTEGRATED IN A SAME DIELECTRIC LAYER - Semiconductor structures having capacitors and metal wiring integrated in a same dielectric layer are described. For example, a semiconductor structure includes a plurality of semiconductor devices disposed in or above a substrate. One or more dielectric layers are disposed above the plurality of semiconductor devices. Metal wiring is disposed in each of the dielectric layers. The metal wiring is electrically coupled to one or more of the semiconductor devices. A metal-insulator-metal (MIM) capacitor is disposed in one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers. The MIM capacitor is electrically coupled to one or more of the semiconductor devices.09-06-2012
20120223412Semiconductor Device Comprising a Capacitor Formed in the Metallization System Based on Dummy Metal Features - When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.09-06-2012
20110012230SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An insulation film (01-20-2011
20110012229SEMICONDUCTOR DEVICE WITH CAPACITOR AND METHOD OF FABRICATING THE SAME - A capacitor, comprising a substrate, a first electrode and a second electrode is provided. The first electrode is located over a substrate. The second electrode is located over the first electrode and overlapping with a portion of the first electrode. The dielectric layer is located between the first electrode and the second electrode and a portion of the first electrode, a portion of the dielectric layer and a portion of the second electrode, which overlap each other, are together form the capacitor. The first electrode is electrically connected to a first metal interconnects, the second electrode is electrically connected to a second metal interconnects underneath the second electrode and no via for being electrically connected to the second electrode is located over the second electrode.01-20-2011
20090236691DEEP TRENCH (DT) METAL-INSULATOR-METAL (MIM) CAPACITOR - A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subsequent structures to be placed over the deep trench.09-24-2009
20090008743CAPACITOR WITH PILLAR TYPE STORAGE NODE AND METHOD FOR FABRICATING THE SAME - A capacitor includes a pillar-type storage node, a supporter filling an inner empty crevice of the storage node, a dielectric layer over the storage node, and a plate node over the dielectric layer.01-08-2009
20130161789Method for Fabricating a DRAM Capacitor - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal. A dielectric layer is formed over the first electrode. The dielectric layer is subjected to a milliseconds anneal process that serves to crystallize the dielectric material and decrease the concentration of oxygen vacancies.06-27-2013
20120235279SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.09-20-2012
20120235278SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM USING THE SAME - Adhesive strength between a rewiring and a solder bump is improved in a semiconductor integrated circuit device in which a bump electrode is connected to a land section of the rewiring. The land section 09-20-2012
20120235277MULTIPLE ENERGIZATION ELEMENTS IN STACKED INTEGRATED COMPONENT DEVICES - This invention discloses a device comprising multiple functional layers with multiple energization elements formed on substrates, wherein at least one functional layer comprises an electrical energy source. In some embodiments, the present invention includes a component for incorporation into ophthalmic lenses that has been formed by the stacking of multiple functionalized layers.09-20-2012
20120235276ELECTRODE TREATMENTS FOR ENHANCED DRAM PERFORMANCE - A method for fabricating a dynamic random access memory capacitor is disclosed. The method may comprise depositing a first titanium nitride (TiN) electrode; creating a first layer of titanium dioxide (TiO09-20-2012
20130161787SEMICONDUCTOR DEVICE HAVING CAPACITORS - A semiconductor device including at least one first capacitor and at least one second capacitor. The at least one first capacitor includes a first storage node having a cylindrical shape. The at least one second capacitor includes a lower second storage node having a hollow pillar shape including a hollow portion, and an upper second storage node having a cylindrical shape and extending upward from the lower second storage node.06-27-2013
20130161788Semiconductor Package Including Stacked Semiconductor Chips and a Redistribution Layer - Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second semiconductor chip that are stacked sequentially on a board. The semiconductor packages may also include a wiring layer on the memory chips and the wiring layer may include redistribution patterns and redistribution pads. Each of the memory chips may include a data pad. The data pads of the first semiconductor chips may be electrically connected to the board via the second semiconductor chip, some of redistribution patterns, and some of redistribution pads.06-27-2013
20130161790METHOD OF MANUFACTURING A FeRAM DEVICE - A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a Pt film is formed as a cap layer on the upper electrode film. Then, a hard mask (a TiN film and an SiO06-27-2013
201301617913D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY - The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.06-27-2013
20110018099COMPONENT-INCORPORATING WIRING BOARD - An objective is to provide a component-incorporated wiring substrate capable of solving a problem caused by an increase in length of wiring lines that connect a component and a capacitor. A component-incorporated wiring substrate 01-27-2011
20110018098Semiconductor Constructions - Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.01-27-2011
20120267758Isolated Capacitors Within Shallow Trench Isolation - A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer (10-25-2012
20110024874SEMICONDUCTOR DEVICE HAVING A 3D CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a three-dimensional capacitor and a method for manufacturing the same is presented. The semiconductor device may have lower electrodes, a buffer layer, a dielectric layer, and an upper electrode. The lower electrodes are formed over a semiconductor substrate. The buffer layer is formed on sidewalls of the lower electrodes. The dielectric layer and an upper electrode are formed over semiconductor substrate including over the lower electrodes and the buffer layer. Accordingly, sufficient space between the lower electrodes can be secured. Furthermore, the lower electrodes can be each formed of a ruthenium layer and a titanium nitride layer and configured to have a pillar form. The dielectric layer may be composed of titanium dioxide.02-03-2011
20110031586High Breakdown Voltage Embedded MIM Capacitor Structure - Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material.02-10-2011
20110108950VERTICAL METAL INSULATOR METAL CAPACITOR - A capacitor includes a first electrode. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The capacitor includes a second electrode. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures. The capacitor includes an insulating structure between the first electrode and the second electrode. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other thereby providing higher capacitance density.05-12-2011
20100230786PRODUCTION OF INTEGRATED CIRCUITS COMPRISING SEMICONDUCTOR INCOMPATIBLE MATERIALS - It is described a procedure for the integration of semiconductor incompatible materials in a process family created for the production of passive electric components and active electric components formed within integrated circuits. The procedure is applicable in known techniques like bipolar, MOS or BIMOS processes for semiconductor production. The modular concept of the described procedure may combine diodes, resistors and capacitors, which components are made from different materials. The provision of an encapsulation material for a semiconductor incompatible material enables the manufacturing of integrated circuits even within a sensitive environment with respect to contaminations originating from the semiconductor incompatible material. The encapsulation is provided early within the manufacturing process such that the risk for a contamination may be reduced to a minimum. Further, it is described an integrated circuit element and an integrated circuit comprising an encapsulated semiconductor incompatible material. The semiconductor incompatible material may be a lead containing ceramics, in particular Lead Lanthanum Zirconium Titanate (PLZT), which is used for ferroelectric capacitors and which represents a highly contaminating substance in particular for ‘heavy metal sensitive’ environments.09-16-2010
20100283122SYSTEMS AND METHODS FOR PROVIDING HIGH-DENSITY CAPACITORS - The present invention describes systems and methods for providing high-density capacitors. An exemplary embodiment of the present invention provides a high-density capacitor system comprising a substrate and a porous conductive layer formed on the substrate, wherein the porous conductive layer is formed in accordance with a predetermined pattern. Furthermore, the high-density capacitor system includes a dielectric material formed on the porous conductive layer and a second conductive layer formed on the dielectric material. Additionally, the high-density capacitor system includes a plurality of conductive pads configured in communication with the second conductive layer.11-11-2010
20110278699THREE-TERMINAL METAL-OXIDE-METAL CAPACITOR - A capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one dielectric layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.11-17-2011
20110278698Integrated Circuit Capacitors Having Composite Dielectric Layers Therein Containing Crystallization Inhibiting Regions and Methods of Forming Same - Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.11-17-2011
20110278697METAL-INSULATOR-METAL CAPACITOR AND METHOD FOR FABRICATING METAL-INSULATOR-METAL CAPACITOR STRUCTURES - A Metal-Insulator-Metal Capacitor and Method for Fabricating Metal-Insulator-Metal Capacitor Structures. The MIM (Metal insulator Metal) capacitor structure comprising a Capacitor Top Metal (CTM); a dielectric; and a Capacitor Bottom Metal (CBM); said CTM comprising an etch stop portion; a conductivity portion having a lower resistivity compared to the etch stop portion; and an interface portion of a different material from the conductivity portion; wherein the conductivity portion is sandwiched between the etch stop portion and the interface portion; and the interface portion interfaces the CTM with the dielectric.11-17-2011
20090189250Semiconductor Device and a Method of Manufacturing the Same - A capacitor has an MIM (Metal Insulator Metal) structure comprising a lower electrode formed in the interior of an electrode trench which is formed in an interlayer insulating film, a dielectric film formed over the lower electrode, and an upper electrode formed over the dielectric film. The upper electrode and the dielectric film are each formed with an area larger than the area of the lower electrode so that the whole of the lower electrode is positioned inside the upper electrode and the dielectric film. The reliability and production yield of the capacitor are improved.07-30-2009
20100270646THIN-FILM CAPACITOR STRUCTURES EMBEDDED IN SEMICONDUCTOR PACKAGES AND METHODS OF MAKING - Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.10-28-2010
20100276783SELECTIVE PLASMA ETCH OF TOP ELECTRODES FOR METAL-INSULATOR-METAL (MIM) CAPACITORS - A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ≦100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.11-04-2010
20090096062STACK CAPACITOR IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A stack capacitor in a semiconductor device includes a first capacitor formed on and/or over a semiconductor substrate and a second capacitor formed on and/or over the first capacitor. The first and second capacitors each have a multi-layer laminated structure which includes a lower electrode, a capacitor dielectric layer and an upper electrode. At least two of the lower electrodes and the upper electrodes are arranged vertically with respect to each other to have the same width and/or surface area.04-16-2009
20130161786CAPACITOR ARRAY AND METHOD OF FABRICATING THE SAME - A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.06-27-2013
20080203528METAL-INSULATOR-METAL CAPACITOR AND METHOD FOR FABRICATING THE SAME - A metal-insulator-metal (MIM) capacitor that includes a silicon nitride (SiN) dielectric film is disclosed. The MIM capacitor includes a bottom electrode, a top electrode and a dielectric layer positioned between the bottom electrode and the top electrode. The dielectric layer includes a silicon nitride film that has a plurality of silicon-hydrogen bonds and a plurality of nitride-hydrogen bonds. A ratio of silicon-hydrogen bonds to nitride-hydrogen bonds is equal to or smaller than 0.5. Accordingly, the nitrogen-rich and compressive silicon nitride film can improve the breakdown voltage of the MIM capacitor.08-28-2008
20110272785IC PACKAGE WITH CAPACITORS DISPOSED ON AN INTERPOSAL LAYER - An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.11-10-2011
20110147887STACK CAPACITOR OF MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.06-23-2011
20090309187Semiconductor Device and Method of Fabricating the Same - Provided is a semiconductor device including a multi-layer dielectric structure and a method of fabricating the semiconductor device. According to one example embodiment, the semiconductor device includes a capacitor comprising: first and second electrodes facing each other; at least one first dielectric layer that is disposed between the first and second electrodes, the at least one first dielectric layer comprising a first high-k dielectric layer doped with silicon; and at least one second dielectric layer that is disposed between the at least one first dielectric layer and any of the first and second electrodes, the at least one second dielectric layer having a higher crystallization temperature than that of the first dielectric layer.12-17-2009
20110298090Capacitors, Systems, and Methods - Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.12-08-2011
20110284990Process for making an alignment structure in the fabrication of a semiconductor device - A process for making an alignment structure in manufacturing a semiconductor device, comprising copper interconnect (Cu-interconnect) fabrication involving chemical-mechanical planarization (CMP) is disclosed. The process comprises tailoring said CMP process to produce a sufficiently high dishing on a designated alignment key area during bulk removal of Cu. The additional dishing step would have sufficient step height for optical pickup to produce alignment signal. Subsequent photolithographic processes specifically for making conventional alignment structure may thus be omitted. Preferably, the additional dishing is achieved by control over any one or combination of pressuring, vacuuming and/or venting of a CMP head's membrane, inner tube and retaining ring chambers, and selection of any one or combination of pads, slurry, pad conditioner and recipe, and may only need to achieve a removal of up to 100 {dot over (A)}. Our process may be adapted for fabricating a MIM top and MIM bottom layers via 2 masking processes, wherein the additional dishing is created as a narrow metal line. It may also be adapted for fabricating an MIM capacitor wherein the underlying Cu layer is used as the bottom plate of the MIM. The additional dishing does not appear to affect electrical properties of the underlying Cu layer.11-24-2011
20100038750Structure, Design Structure and Method of Manufacturing a Structure Having VIAS and High Density Capacitors - A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.02-18-2010
20100224960EMBEDDED CAPACITOR DEVICE AND METHODS OF FABRICATION - Embodiments of the present invention describe a semiconductor device having an embedded capacitor device and methods of fabricating the capacitor device. The capacitor device is formed between the passivation layers above the backend interconnect stack of a substrate. Fabricating the capacitor device between the passivation layers above the backend interconnect stack minimizes any adverse effects the capacitor device might cause to the backend interconnect stack.09-09-2010
20110284991SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.11-24-2011
20120104548Semiconductor Capacitor with Large Area Plates and a Small Footprint that is Formed with Shadow Masks and Only Two Lithography Steps - A semiconductor capacitor with large area plates and a small footprint is formed on a semiconductor wafer by forming an opening in the wafer, depositing a first metal atoms through a first shadow mask that lies spaced apart from the wafer to form a first metal layer in the opening, a dielectric layer on the first metal layer, and a second metal atoms through a second shadow mask that lies spaced apart from the wafer to form a second metal layer on the dielectric layer.05-03-2012
20110298091SEMICONDUCTOR DEVICE HAVING CAPACITORS - A capacitor is formed over a semiconductor substrate. The capacitor includes a lower electrode, a capacitor dielectric film and an upper electrode in this order recited, and has an area S equal to or larger than 1000 μm12-08-2011
20110298089TRENCH CAPACITOR AND METHOD OF FABRICATION - An improved trench capacitor and method of fabrication are disclosed. The trench capacitor utilizes a rare-earth oxide layer to reduce depletion effects, thereby improving performance of the trench capacitor.12-08-2011
20080277761ON-CHIP ISOLATION CAPACITORS, CIRCUITS THEREFROM, AND METHODS FOR FORMING THE SAME - An integrated circuit includes a substrate having a semiconducting surface, and at least one isolation capacitor on the surface. The capacitor includes a bottom electrically conductive plate in or on the surface, a multi-layer dielectric comprising stack over the bottom plate, and a top electrically conductive plate formed over the dielectric stack. The dielectric stack comprises at least one layer of silicon dioxide and at least one layer of silicon nitride, wherein the layer of silicon nitride is located immediately below or immediately above the top plate.11-13-2008
20110291239SEMICONDUCTOR DEVICE - A semiconductor device includes: a first interlayer insulating film; a first conductive member provided lower than the first interlayer insulating film; a contact plug that penetrates through the first interlayer insulating film, and is electrically connected to the first conductive member, the contact plug including a small-diameter part, and a large-diameter part arranged on the small-diameter part, an outer diameter of the large-diameter part being larger than an outer diameter of the small-diameter part, and the outer diameter of the large-diameter part being larger than an outer diameter of a connection face between the second conductive member and the large-diameter part; and a second conductive member that is provided on the first interlayer insulating film, and is electrically connected to the contact plug.12-01-2011
20120012981SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides technology directed to a semiconductor device and a method of manufacturing the same. According to the present invention, metal contact plugs are formed to come into contact with both sidewalls of a capacitor, including lower electrodes, dielectric layers, and an upper electrode. Accordingly, contact resistance can be reduced because the contact area of the upper electrode and the metal contact plugs forming the capacitor, can be increased. Furthermore, the number of chips per wafer can be increased because the area in which the metal contact plugs and the capacitor are formed can be reduced. In addition, the generation of noise can be reduced because the contact area of the capacitor and the metal contact plugs is increased and thus voltage at the upper electrode is stabilized.01-19-2012
20110291238BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CIRCUIT DEVICE STRUCTURES - A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques12-01-2011
20110291236SEMICONDUCTOR MODULE WITH ELECTRICAL SWITCHING ELEMENTS - A semiconductor module is provided which is capable of lowering surges caused when switching elements are switched on and off. The module has a plurality of lead frames, switching elements, electronic components, and a sealing member. The switching elements are electrically connected to the lead fames respectively. Part of the lead frames, the switching elements, and the electronic components are sealed by the sealing member. The electronic components are mounted on primary surfaces of the lead frames respectively.12-01-2011
20110291235COPPER INTERCONNECTION STRUCTURE WITH MIM CAPACITOR AND A MANUFACTURING METHOD THEREOF - The present invention discloses a copper interconnection structure with MIM capacitor and a manufacturing method thereof. The method firstly makes a copper conductive pattern in a copper interconnection structure and a copper through hole bolt connected with the copper conductive pattern; etch away an insulation layer around the copper through hole bolt and deposit a etch stop layer, so as to expose the top and side surface of the copper through hole bolt and part of the top surface of the copper conductive pattern; deposit a dielectric layer on the obtained structure and fill a protection material in the recession area of the obtained structure; etch a trench for receiving other copper conductive patterns; remove the protection material; plate copper in the recession area, and plate copper in the trench, so as to obtain a copper interconnection structure with MIM capacitor.12-01-2011
20110291234SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD OF MAKING THE SAME - A semiconductor circuit structure includes an interconnect region, and a material transfer region. The semiconductor circuit structure includes a conductive bonding region which couples the material transfer region to the interconnect region through a bonding interface. The conductive bonding region includes a barrier layer between a conductive layer and bonding layer. The bonding layer is positioned towards the material transfer region, and the conductive layer is positioned towards the interconnect region.12-01-2011
20100213574HIGH DIELECTRIC CONSTANT TRANSITION METAL OXIDE MATERIALS - A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.08-26-2010
20100213573Semiconductor device - A semiconductor device including a plurality of decoupling capacitors formed on a semiconductor substrate, and a plurality of decoupling capacitor contact plugs disposed between the semiconductor substrate and the plurality of decoupling capacitors, the plurality of decoupling capacitor contact plugs being electrically connected to the plurality of decoupling capacitors and including an array of first decoupling capacitor contact plugs and second decoupling capacitor contact plugs.08-26-2010
20100213572Dual-Dielectric MIM Capacitors for System-on-Chip Applications - An integrated circuit structure includes a chip having a first region and a second region. A first metal-insulator-metal (MIM) capacitor is formed in the first region. The first MIM capacitor has a first bottom electrode; a first top electrode over the first bottom electrode; and a first capacitor insulator between and adjoining the first bottom electrode and the first top electrode. A second MIM capacitor is in the second region and is substantially level with the first MIM capacitor. The second MIM capacitor includes a second bottom electrode; a second top electrode over the second bottom electrode; and a second capacitor insulator between and adjoining the second bottom electrode and the second top electrode. The second capacitor insulator is different from the first capacitor insulator. The first top electrode and the first bottom electrode may be formed simultaneously with the second top electrode and the second bottom electrode, respectively.08-26-2010
20100213571EDRAM INCLUDING METAL PLATES - A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode.08-26-2010
20120098094METAL CAPACITOR AND METHOD OF MAKING THE SAME - A metal capacitor structure is disclosed. The metal capacitor structure includes: a dielectric layer having a first region and a second region, a dielectric constant of the dielectric layer in the second region being higher than a dielectric constant of the dielectric layer in the first region; a dual damascene metal interconnection positioned in the first region; and a damascene capacitor electrode positioned in the second region.04-26-2012
20120098093Capacitors and Methods of Forming Capacitors - A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive TiO04-26-2012
20120098092SEMICONDUCTOR DEVICE CAPACITORS INCLUDING MULTILAYERED LOWER ELECTRODES - A capacitor of a semiconductor device may include a lower electrode on a semiconductor substrate. A dielectric film can cover a surface of the lower electrode and an upper electrode can cover the dielectric film. The lower electrode can be a first conductive pattern that includes a bottom portion and a sidewall portion that defines a groove region. A core support pattern can be in the groove region of the first conductive pattern and a second conductive pattern can electrically connect to the first conductive pattern on the core support pattern.04-26-2012
20120098091SEMICONDUCTOR DEVICE SUBSTRATE AND SEMICONDUCTOR DEVICE - There is provided a semiconductor device substrate including: a multi-layer wiring layer; a first capacitor pad which is provided on an uppermost layer of the multi-layer wiring layer, and which includes a first power supply pad connected to a power supply layer of the multi-layer wiring layer through a first via and a first ground pad connected to a ground layer of the multi-layer wiring layer through a second via; and a second capacitor pad which is provided on the uppermost layer of the multi-layer wiring layer, and which includes a second power supply pad connected to the first power supply pad through a first wire and a second ground pad connected to the first ground pad through a second wire.04-26-2012
20080203530SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor device includes a silicon substrate; a first interlayer insulating film provided on the silicon substrate; and a capacitor that is provided on the first interlayer insulating film and that includes a lower electrode, a capacitor dielectric film made of a ferroelectric substance, and an upper electrode, wherein the capacitor dielectric film does not contain a non-oriented component under the upper electrode.08-28-2008
20090194845SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR IN THE METALLIZATION SYSTEM AND A METHOD OF FORMING THE CAPACITOR - By forming metal capacitors in the metallization structures of semiconductor devices, complex manufacturing sequences in the device level may be avoided. The process of manufacturing the metal capacitors may be performed on the basis of well-established patterning regimes of modern metallization systems by using appropriately selected etch stop materials, which may enable a high degree of compatibility for forming via openings in a metallization layer while providing a capacitor dielectric of a desired high dielectric constant in the capacitor.08-06-2009
20090230508SOI PROTECTION FOR BURIED PLATE IMPLANT AND DT BOTTLE ETCH - An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band of oxide on an inner periphery of the SOI layer to protect it during a subsequent RIE step for forming a deep trench. The initial trench may stop on BOX underlying the SOI. The band of oxide may also protect the SOI during buried plate implant or gas phase doping.09-17-2009
20120032301SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame including an island, a power supply lead, and a GND lead; a sheet-like solid electrolytic capacitor that is mounted on the island; a semiconductor chip that is mounted on the solid electrolytic capacitor, a plane area of the semiconductor chip being smaller than that of the solid electrolytic capacitor; a bonding wire that connects the semiconductor chip and the solid electrolytic capacitor, and a bonding wire that connects the solid electrolytic capacitor and the power supply lead or the GND lead, in which at least the connection part between the anode plate and the anode part of the solid electrolytic capacitor and the connection part between the anode plate and the bonding wire do not overlap when being vertically projected.02-09-2012
20090121317SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a three dimensional type capacitor is provided. The method includes forming a first insulation layer including first contact layers over a substrate, forming a second insulation layer over the first insulation layer, forming second contact layers by using a material having an etch selectivity different from the first contact layers such that the second contact layers are connected with the first contact layers within the second insulation layer, forming an etch stop layer over the second insulation layer and the second contact layers, forming a third insulation layer over the etch stop layer, etching the third insulation layer and the etch stop layer to form first contact holes exposing the second contact layers, etching the exposed second contact layers to form second contact holes exposing the first contact holes, and forming bottom electrodes over the inner surface of the second contact holes.05-14-2009
20090152678CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A capacitor includes a first lower metal layer and an insulating layer on a lower interlayer dielectric layer of a semiconductor substrate; a first upper metal layer aligned on the insulating layer to partially expose it; a first capping layer and an upper interlayer dielectric layer on the insulating layer including the first upper metal layer; a second lower metal layer connected to the first upper metal layer through the upper interlayer dielectric layer and the first capping layer; a second capping layer aligned on the upper interlayer dielectric layer including the second lower metal layer and formed with a hole for partially exposing the second lower metal layer; a pad aligned on the second capping layer and connected to the second lower metal layer; a protective layer on the second capping layer; and a second upper metal layer aligned on the second capping layer.06-18-2009
20090152677Semiconductor device and method for manufacturing semiconductor device - A semiconductor device including: a conducting plug provided in an interlayer insulating film over a semiconductor substrate; and a capacitor including a lower electrode provided over the conducting plug, the lower electrode being connected to the conducting plug, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film. The lower electrode includes a conducting pillar and a conducting outer layer provided over at least a circumferential side surface of the conducting pillar. The dielectric film covers at least a circumferential side surface of the lower electrode, and is contact with the conducting outer layer.06-18-2009
20080237793Semiconductor device having projection on lower electrode and method for forming the same - A method of forming a semiconductor device, includes forming a lower electrode including a metal and a nitrogen on a semiconductor substrate, irradiating a reducing gas to a surface of the lower electrode, and irradiating a gas containing silicon to the surface of the lower electrode to form a projection containing silicide by reacting the metal with the silicon in an island shape on the surface of the lower electrode. Then, a capacitor film is formed on the lower electrode and the projection, and an upper electrode is formed on the capacitor film.10-02-2008
20080237792SEMICONDUCTOR CAPACITOR STRUCTURE AND LAYOUT PATTERN THEREOF - The present invention provides a metal-oxide-metal (MOM) capacitor structure having a plurality of symmetrical ring type sections. The MOM capacitor structure of the present invention does not need photomasks above standard CMOS process, and thus the process cost is cheaper. In addition, due to the semiconductor process improvement, a significantly large number of metal layers can be stacked in the MOM capacitor structure, and since the distance between the metal layers becomes smaller, the unit capacitance will be increased.10-02-2008
20090146255Capacitor for Semiconductor Device and Method for Manufacturing the Same - Disclosed is a capacitor of a semiconductor device, capable of varying a capacitance according to a design of the semiconductor device. The capacitor can include a first electrode area and a second electrode area with a dielectric therebetween. The first electrode area can have a metal electrode spanning the entire first electrode area. The second electrode area can include a plurality of metal electrodes connected to each other through thin bridge patterns. Internal pads can be arranged around the electrode areas and are connected to certain ones of the plurality of metal electrodes of the second electrode area in order to provide a voltage capable of melting or breaking certain ones of the thin bridge patterns. The capacitance of the capacitor arranged according to embodiments can be adjusted to a desirable level using the internal pads. Therefore, a designer can easily design the capacitor or change the design of the capacitor.06-11-2009
20080296731ENHANCED ON-CHIP DECOUPLING CAPACITORS AND METHOD OF MAKING SAME - An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.12-04-2008
20100038753Variable capacitor employing MEMS technology - When a positive voltage of V02-18-2010
20100123213METAL-INSULATOR-METAL CAPACITORS - Metal-insulator-metal capacitors are provided that are formed in integrated circuit dielectric stacks. A line-plate-line capacitor is provided that alternates layers that contain metal plates with layers that contain straight or angled parallel lines of alternating polarity. A segmented-plate capacitor is provided that has metal plates that alternate in polarity both within a layer and between layers. The line-plate-line and segmented-plate capacitors may exhibit a reduced parasitic inductive coupling. The capacitances of the line-plate-line capacitor and the metal-insulator-metal capacitor may have an enhanced contribution from an interlayer capacitance component with a vertical electric field than a horizontal intralayer capacitance component with a horizontal electric field.05-20-2010
20110156207MIM CAPACITOR WITH PLATE HAVING HIGH MELTING POINT - A method for producing an integrated device including an MIM capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate; the first plate has a first melting temperature. The method further includes depositing a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate; the layer of insulating material is deposited at a process temperature being lower than the first melting temperature. The method further includes forming a second conductive layer including a second plate of the capacitor on a portion of the layer of insulating material corresponding to the dielectric layer. In the solution according to an embodiment of the invention, the first melting temperature is higher than 500° C.06-30-2011
20090085156METAL SURFACE TREATMENTS FOR UNIFORMLY GROWING DIELECTRIC LAYERS - A fabrication process for a MIM capacitor comprises providing a substrate, depositing a first metal layer on a dielectric layer of the substrate, forming an interfacial layer on the first metal layer, wherein the interfacial layer has a hydroxyl terminated surface, depositing a capacitor dielectric layer on the interfacial layer using an ALD process, and depositing a second metal layer on the capacitor dielectric layer. The interfacial layer may be formed by depositing a thin layer of a metal oxide, by oxidizing a surface of the first metal layer with an oxygen plasma, or by evaporating a thin metal oxide onto the surface of the first metal layer.04-02-2009
20090309188SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a substrate and a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode. The upper electrode includes a first layer formed of an oxide whose stoichiometric composition is expressed as AOx12-17-2009
20090309186SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.12-17-2009
20110140238SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to an embodiment, there is provided a method for manufacturing a semiconductor device having a ferroelectric capacitor including a lower electrode, an upper electrode, and a dielectric film provided between the lower electrode and the upper electrode. The method includes firstly forming a conductive film on the lower electrode. Next, it includes forming an SRO film on the conductive film. Then, it includes performing a first thermal treatment crystallizing the SRO film. Then, it includes forming a first PZT film on the SRO film by the sputtering method and performing a second thermal treatment crystallizing the first PZT film. Then, it includes forming the second PZT film on the first PZT film by the CVD method.06-16-2011
20110147890MIM CAPACITOR STRUCTURE HAVING PENETRATING VIAS - The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction.06-23-2011
20100084740CAPACITOR WITH ZIRCONIUM OXIDE AND METHOD FOR FABRICATING THE SAME - A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO04-08-2010
20110062552SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to a first electrode upwardly extending, and a second electrode upwardly extending along the first electrode. The first electrode includes a lower portion and an upper portion. The second electrode covers a bottom surface and an outer side surface of the lower portion of the first electrode. The upper portion of the first electrode is positioned higher than the second electrode.03-17-2011
20110062551MULTILAYER OXIDE ON NITRIDE ON OXIDE STRUCTURE AND METHOD FOR THE MANUFACTURE OF SEMICONDUCTOR DEVICES - An integrated circuit device having a capacitor structure and methods of manufacture are disclosed. The device has a substrate, e.g., silicon wafer, silicon on insulator, epitaxial wafer. The device has a dielectric layer overlying the substrate and a polysilicon layer overlying the dielectric layer. The device has a tungsten silicide layer overlying the polysilicon layer and a first oxide layer overlying the tungsten silicide layer. A nitride layer overlies the oxide layer. A second oxide layer is overlying the nitride layer to form a sandwiched oxide on nitride on oxide structure to form a capacitor dielectric. The device also has an upper capacitor plate formed overlying the second oxide layer.03-17-2011
20110062550HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS - An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.03-17-2011
20100090308METAL-OXIDE-METAL CAPACITORS WITH BAR VIAS - Metal-oxide-metal capacitors with bar vias are provided for integrated circuits. The capacitors may be formed in the interconnect layers of integrated circuits. Stacked bar vias and metal lines in the interconnect layers may be connected to form conductive vertical plates that span multiple interconnect layers. The capacitors with bar vias may be formed by placing multiple vertical plates formed from stacked bar vias and metal lines parallel to each other, alternating the polarity of adjacent vertical parallel plates to form multiple parallel plate capacitors. The parallel plates may be interconnected to form first and second terminals in a capacitor.04-15-2010
20100006979METHOD OF MANUFACTURING A TRENCH CAPACITOR FOR HIGH VOLTAGE PROCESSES - The present invention provides embodiments of a capacitor and a method of forming the capacitor. The capacitor includes one or more trenches formed in a semiconductor layer above a substrate. The trench includes dielectric material deposited on the trench walls and a conductive fill material formed within the trench and above the dielectric material. The capacitor also includes one or more first doped regions formed adjacent the trench(es) in the semiconductor layer. The first doped region is doped with a first type of dopant. The capacitor further includes one or more second doped regions formed adjacent the first doped region(s) in the semiconductor layer. The second doped regions are doped with a second type of dopant that is opposite to the first type of dopant.01-14-2010
20100006980SEMICONDUCTOR DEVICE - A problem of an increased manufacturing cost is caused in conventional semiconductor devices. A semiconductor device 01-14-2010
20090206448SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.08-20-2009
20090090999HIGH PERMITTIVITY LOW LEAKAGE CAPACITOR AND ENERGY STORING DEVICE AND METHOD FOR FORMING THE SAME - A method is provided for making a high permittivity dielectric material for use in capacitors. Several high permittivity materials in an organic nonconductive media with enhanced properties and methods for making the same are disclosed. A general method for the formation of thin films of some particular dielectric material is disclosed, wherein the use of organic polymers, shellac, silicone oil, and/or zein formulations are utilized to produce low conductivity dielectric coatings. Additionally, a method whereby the formation of certain transition metal salts as salt or oxide matrices is demonstrated at low temperatures utilizing mild reducing agents. Further, a circuit structure and associated method of operation for the recovery and regeneration of the leakage current from the long-term storage capacitors is provided in order to enhance the manufacturing yield and utility performance of such devices.04-09-2009
20090090996SEMICONDUCTOR DEVICE WITH CONTACT STABILIZATION BETWEEN CONTACT PLUGS AND BIT LINES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate divided into a cell array region, a core region, and a peripheral region. Bit lines are formed in the respective regions. Storage node contact plugs are formed in the cell array region, and blocking patterns are simultaneously formed around the bit lines of the core region and the peripheral region. Capacitors are formed in the cell array region to come into contact with the storage node contact plugs, and metal contact plugs are formed to come into contact with the capacitors of the cell array region and the bit lines of the core region and the peripheral region. In the semiconductor device, even if the metal contact plugs are not aligned with the bit lines, the blocking pattern works to stabilize the contact between the metal contact plugs and the bit lines.04-09-2009
20090273058ELECTRICAL COMPONENTS FOR MICROELECTRONIC DEVICES AND METHODS OF FORMING THE SAME - Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.11-05-2009
20090090997SOLID ELECTROLYTIC CAPACITOR ELEMENT AND PRODUCTION METHOD THEREOF - The present invention relates to a production method of solid electrolytic capacitor element, comprising a step of forming a semiconductor layer on a surface of a conductor having a dielectric oxide film thereon and having an anode lead connected thereto by conducting electrolytic oxidation-polymerization using pyrrole dimer at around room temperature, a solid electrolytic capacitor element produced by the method, solid electrolytic capacitor using the element and uses thereof. According to the invention, low-temperature polymerizability of pyrrole, which is inexpensive, can be suppressed, whereby the invention enables production of solid electrolytic capacitor elements having a semiconductor layer formed in industrially advantageous manner.04-09-2009
20090090998SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first and second structures formed in a first insulating layer, a lower metal interconnection formed in the second structure, a metal-insulator-metal (MIM) capacitor formed in the first structure, and first, second and third electrodes formed in the first structure and electrically connected to the MIM capacitor. The first electrode is a chip bottom metal (CBM) layer, the second electrode is a first chip top metal (CTM) layer and the third electrode is a second chip top metal (CTM) layer.04-09-2009
20080277762Semiconductor device including capacitor including upper electrode covered with high density insulation film and production method thereof - A semiconductor device includes a lower electrode provided on a semiconductor substrate, an upper electrode provided on the lower electrode to overlap a part of the lower electrode, a first insulating film provided between the lower electrode and the upper electrode, and a second insulating film provided in contact with an upper part of the upper electrode and on the upper part of the lower electrode, and having a density higher than that of the first insulating film, the second insulating film covering a side surface and a top surface of the upper electrode.11-13-2008
20090189249SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first and second structures formed in a first insulating layer, a lower metal interconnection formed in the second structure, a metal-insulator-metal (MIM) capacitor formed in the first structure, and first, second and third electrodes formed in the first structure and electrically connected to the MIM capacitor. The first electrode is a chip bottom metal (CBM) layer, the second electrode is a first chip top metal (CTM) layer and the third electrode is a second chip top metal (CTM) layer.07-30-2009
20090283859Integrated Circuit Arrangements With ESD-Resistant Capacitor and Corresponding Method of Production - A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.11-19-2009
20100123215Capacitor Die Design for Small Form Factors - A semiconductor package has a capacitor die and a packaging substrate. The capacitor die is coupled to circuitry on a front or back side of a die coupled to the packaging substrate for providing decoupling capacitance. In one example, the capacitor die is coupled to a land side of the packaging substrate in an area depopulated of a packaging array and adjacent to the packaging array. In another example, the capacitor die may be stacked on the die and coupled through wire bonds to circuitry on the die. The capacitor die reduces impedance of the integrated circuit allowing operation at higher frequencies.05-20-2010
20090289327CAPACITOR INSULATING FILM AND METHOD FOR FORMING THE SAME, AND CAPACITOR AND SEMICONDUCTOR DEVICE - A capacitor insulating film includes a laminated structure in which aluminum oxide films and titanium dioxide films are alternately laminated, wherein the titanium dioxide films each have a rutile crystal structure, and the ratio of the total thickness of the aluminum oxide films to the total thickness of the laminated structure ranges from 3 to 8%.11-26-2009
20090289328INSULATION FILM FOR CAPACITOR ELEMENT, CAPACITOR ELEMENT AND SEMICONDUCTOR DEVICE - An insulation film includes niobium, oxygen and a metal element, and the insulation film has a band gap width of larger than 4.2 eV, and at least a portion of the insulation film includes an amorphous structure.11-26-2009
20110198725GENERATING AND EXPLOITING AN ASYMMETRIC CAPACITANCE HYSTERESIS OF FERROELECTRIC MIM CAPACITORS - The present invention relates to an electric component comprising at least one first MIM capacitor having a ferroelectric insulator with a dielectric constant of at least 100 between a first capacitor electrode of a first electrode material and a second capacitor electrode of a second electrode material. The first and second electrode materials are selected such that the first MIM capacitor exhibits, as a function of a DC voltage applicable between the first and second electrodes, an asymmetric capacity hysteresis that lets the first MIM capacitor, in absence of the DC voltage, assume one of at least two possible distinct capacitance values, in dependence on a polarity of a switching voltage last applied to the capacitor, the switching voltage having an amount larger than a threshold-voltage amount. The invention is applicable for ESD sensors, memories and high-frequency devices.08-18-2011
20110198724METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.08-18-2011
20110198723METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA - A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.08-18-2011
20090294906SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME, AND LIGHT MODULATION DEVICE AND FABRICATION METHOD FOR THE SAME - A light modulation device, which uses the ITO used as a transparent electrode as an etching mask of the PLZT, performing the self-aligned formation, and a fabrication method for the light modulation device is provided. A light modulation device includes a substrate; and a ferroelectric capacitor placed on the substrate and includes a lower electrode, a ferroelectric film placed on the lower electrode, and an upper electrode placed on the ferroelectric film, and the upper electrode includes a conducting film by which self-alignment patterning is performed to the ferroelectric film as an etching mask of the ferroelectric film, and the ferroelectric capacitor is provided so as to laminate on the substrate, and the ferroelectric capacitor is functioned as a Fabry-Perot type resonator from which a refractive index of the ferroelectric film changes according to an electric field applied between the lower electrode and the upper electrode.12-03-2009
20090278231Semiconductor device and method for fabricating the same - The semiconductor device comprises a first insulation film 11-12-2009
20090278230SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a substrate, an insulating interlayer, an interconnect as one example of an electro-conductive pattern, a through-electrode, and a bump as one example of a connection terminal, wherein the insulating interlayer is positioned up above the surface of the substrate, the interconnect is positioned on the surface of the insulating interlayer, the through-electrode extends through the substrate and the insulating interlayer, from the back surface of the former to the surface of the latter, one end of which is connected to the interconnect, and the bump is provided on the back surface side of the substrate, and connected to the other end of the through-electrode.11-12-2009
20090267184METAL-INSULATOR-METAL (MIM) CAPACITOR STRUCTURE AND METHODS OF FABRICATING SAME - A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode. Furthermore, a multi-rate etching process may be used to etch the top electrode and insulator layer of an MIM structure, using a first, higher rate to perform an anisotropic etch up to a point proximate an interface between the conductive and dielectric materials respectively defining the top electrode and insulator layer of the MIM structure, and then using a second, lower rate to perform an anisotropic etch to a point proximate an etch stop layer defined on the bottom electrode of the MIM structure.10-29-2009
20090283858Scalable Integrated Circuit High Density Capacitors - The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.11-19-2009
20090289326Semiconductor device and method of fabricating the same - A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting a top surface of the second storage node contact plug; and a second interlayer insulation layer formed over the first interlayer insulation layer, wherein the second interlayer insulation layer surrounds an outer sidewall at a bottom region of the first storage node, and the second storage node contact plug, and wherein the first storage node contact plug protruding above the first interlayer insulation layer and the second storage node contact plug.11-26-2009
20090294905Semiconductor device - A substrate is provided with a first wiring layer 12-03-2009
20090294904INTEGRATED CIRCUIT SYSTEM EMPLOYING BACK END OF LINE VIA TECHNIQUES - An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first metallization layer over the substrate and electrically connected to the substrate; forming a viabar or a via group over the first metallization layer; and forming a second metallization layer over the first metallization layer and electrically connected to the first metallization layer through either the viabar or the via group.12-03-2009
20090256238Capacitor of Semiconductor Device and Method of Fabricating the Same - Disclosed are a capacitor of a semiconductor device and a method of fabricating the same. The capacitor includes a capacitor top electrode, a capacitor bottom electrode aligned with a bottom surface and three lateral sides of the capacitor top electrode, and a capacitor insulating layer between the capacitor top electrode and the capacitor bottom electrode.10-15-2009
201102044803D INTEGRATION OF A MIM CAPACITOR AND A RESISTOR - The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (08-25-2011
20110204475ENHANCED WORK FUNCTION LAYER SUPPORTING GROWTH OF RUTILE PHASE TITANIUM OXIDE - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO08-25-2011
20110204474MEMORY CELL WITH SILICON-CONTAINING CARBON SWITCHING LAYER AND METHODS FOR FORMING THE SAME - In a first aspect, a method of forming a memory cell is provided that includes (1) forming a metal-insulator-metal (MIM) stack, the MIM stack including (a) a first conductive carbon layer; (b) a low-hydrogen, silicon-containing carbon layer above the first conductive carbon layer; and (c) a second conductive carbon layer above the low-hydrogen, silicon-containing carbon layer; and (2) forming a steering element coupled to the MIM stack. Numerous other aspects are provided.08-25-2011
20090261454CAPACITOR IN SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A capacitor includes a bottom electrode, a dielectric layer and a top electrode over a substrate. A Ru10-22-2009
20090008744SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes: a first interlayer insulating film; a first conductive member provided lower than the first interlayer insulating film; a contact plug that penetrates through the first interlayer insulating film, and is electrically connected to the first conductive member, the contact plug including a small-diameter part, and a large-diameter part arranged on the small-diameter part, an outer diameter of the large-diameter part being larger than an outer diameter of the small-diameter part, and the outer diameter of the large-diameter part being larger than an outer diameter of a connection face between the second conductive member and the large-diameter part; and a second conductive member that is provided on the first interlayer insulating film, and is electrically connected to the contact plug.01-08-2009
20120193758SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - A semiconductor apparatus includes a first capacitor formed in a normal cell area and including a lower electrode coupled to one end of a cell transistor, and a second capacitor formed in a dummy cell area and including a lower electrode coupled to a power terminal.08-02-2012
20100283124SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which impedances of power-supply wiring/GND wiring are matched with each other inside the semiconductor device to reduce a noise current without depending on a mounting layout of a circuit board. In a semiconductor device according to a typical embodiment of the present invention including: a package board; a semiconductor chip; a power-supply wiring; and a GND wiring, the semiconductor device includes a conductive plate, and further includes a first impedance adjusting element and a second impedance adjusting element. Parasitic capacitances of the power-supply wiring and the GND wiring are determined by the conductive plate, and the impedances of the power-supply wiring and the GND wiring are adjusted by the first impedance adjusting element and the second impedance adjusting element.11-11-2010
20100102417VAPOR DEPOSITION METHOD FOR TERNARY COMPOUNDS - Embodiments provide a method for depositing or forming titanium aluminum nitride materials during a vapor deposition process, such as atomic layer deposition (ALD) or plasma-enhanced ALD (PE-ALD). In some embodiments, a titanium aluminum nitride material is formed by sequentially exposing a substrate to a titanium precursor and a nitrogen plasma to form a titanium nitride layer, exposing the titanium nitride layer to a plasma treatment process, and exposing the titanium nitride layer to an aluminum precursor while depositing an aluminum layer thereon. The process may be repeated multiple times to deposit a plurality of titanium nitride and aluminum layers. Subsequently, the substrate may be annealed to form the titanium aluminum nitride material from the plurality of layers. In other embodiments, the titanium aluminum nitride material may be formed by sequentially exposing the substrate to the nitrogen plasma and a deposition gas which contains the titanium and aluminum precursors.04-29-2010
20100127347SHIELDING FOR INTEGRATED CAPACITORS - A capacitor in an integrated circuit (“IC”) includes a core capacitor portion having first conductive elements electrically connected to and forming a part of a first node of the capacitor formed in a first layer and second conductive elements electrically connected to and forming a part of a second node of the capacitor formed in the first layer. The first and second conductive elements alternate in the first conductive layer. Third conductive elements electrically connected to and forming a part of the first node are formed in a second layer adjacent to the first layer. The capacitor also includes a shield capacitor portion having fourth conductive elements formed in at least first, second, third, and fourth layers. The shield capacitor portion is electrically connected to and forms a part of the second node of the capacitor and surrounds the first and third conductive elements.05-27-2010
20090065896CAPACITOR HAVING Ru ELECTRODE AND TiO2 DIELECTRIC LAYER FOR SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a capacitor of a semiconductor device using a TiO03-12-2009
20090166805Metal Insulator Metal Capacitor and Method of Manufacturing the Same - Disclosed are a metal insulator metal (MIM) capacitor and a method of manufacturing a MIM capacitor. The MIM capacitor includes a lower metal interconnection layer, a dielectric layer pattern formed on the lower metal interconnection layer, and a third metal layer pattern formed on the dielectric layer pattern. The dielectric layer pattern has a concave surface that can be formed by performing an isotropic etching process. Accordingly, the third metal layer pattern fills the concave surface, resulting in a larger surface contact area between the dielectric material and the metal material of the MIM capacitor.07-02-2009
20080277760INTEGRATED CIRCUIT DEVICE HAVING OPENINGS IN A LAYERED STRUCTURE - An integrated circuit device includes a substrate with a first layer situated on the substrate. The first layer defines a first opening with a cover layer deposited on the first layer and coating a sidewall portion of the first opening. A second layer is situated on the cover layer. The second layer defines a second opening extending through the second layer and through the cover layer to connect the first and second openings.11-13-2008
20110204476Electronic Package with Fluid Flow Barriers - The present invention is directed to a method and electronic computer package that is formed by placing an integrated circuit, having a plurality of bonding pads with solder bumps deposited thereon, in contact with the substrate so that one of the plurality of solder bumps is in superimposition with respect to one of the contacts and one of the plurality of bonding pads, with a volume being defined between region of the substrate in superimposition with the integrated circuit. A portion of the volume is filled with a quantity of underfill. A fluid flow bather is formed on the substrate and defines a perimeter of the volume, defining a flow restricted region. The fluid flow barrier has dimensions sufficient to control the quantity of underfill egressing from the flow restricted region.08-25-2011
20080265370Semiconductor device - In the semiconductor device according to the present invention, a lower electrode and an upper electrode are relatively positionally deviated from each other through a capacitance film in a direction perpendicular to the laminating direction thereof. Thus, the upper electrode and the lower electrode each have portions opposed to each other through the capacitance film in the laminating direction and portions not opposed to each other. An upper electrode plug is connected to the portion of the upper electrode not opposed to the lower electrode through an upper electrode contact hole passing through an insulating film formed on the upper electrode. Further, a lower electrode plug is connected to the portion of the lower electrode not opposed to the upper electrode through a lower electrode contact hole passing through the insulating film.10-30-2008
20080290459MIM Capacitors - A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.11-27-2008
20080283965SEMICONDUCTOR DEVICE - A semiconductor device includes, in one semiconductor substrate: a plurality of switching elements connected between a terminal of an input voltage and an inductor; a driver circuit connected to a gate electrode of the switching element and driving the switching element; a reference voltage line connected to a source electrode of the switching element; a power supply line of the driver circuit; and a capacitor connected between the power supply line and the reference voltage line.11-20-2008
20100127350SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a lower electrode on a semiconductor substrate, applying a photoresist on the lower electrode, forming an opening in the photoresist spaced from the periphery of the lower electrode, forming a high-dielectric constant film of a high-k material having a dielectric constant of 10 or more, performing liftoff so that the high-dielectric-constant film remains on the lower electrode, and forming an upper electrode on the high-dielectric-constant film remaining after the liftoff.05-27-2010
20100127349INTEGRATED CAPACITOR WITH ARRAY OF CROSSES - A capacitor in an integrated circuit (“IC”) has a first plurality of conductive crosses formed in a layer of the IC electrically connected to and forming a portion of a first node of the capacitor and a second plurality of conductive crosses formed in the metal layer of the IC. The conductive crosses in the second plurality of conductive crosses are electrically connected to and form a portion of a second node of the capacitor and capacitively couple to the first node.05-27-2010
20090014831Electronic device comprising an integrated circuit and a capacitance element - An electronic device (ICD) comprises an integrated circuit (AIC) and a capacitance element (PIC). The integrated circuit (AIC) is provided with a plurality of circuit contact pairs (CI). The capacitance element (PIC) is provided with a plurality of capacitance contact pairs (CC). A capacitance is present between each of at least part of the capacitance contact pairs (CC). The plurality of capacitance contact pairs (CC) faces the plurality of circuit contact pairs (CI). At least a part of the capacitance contact pairs (CC) is electrically coupled in a pair-by-pair manner to at least a part of the circuit contact pairs (CI).01-15-2009
20080308902SEMICONDUCTOR DEVICE - This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided in the interlayer dielectric film and electrically connected to the lower electrode; a diffusion layer connecting between the contact plug and the switching transistor; a trench formed around the ferroelectric capacitor; and a barrier film filling in the trench and provided on a side surface of the ferroelectric capacitor and on an upper surface of the interlayer dielectric film, the barrier film suppressing percolation of hydrogen, wherein a thickness of the barrier film on the side surface of the ferroelectric capacitor is larger than a thickness of the barrier film on the upper surface of the interlayer dielectric film.12-18-2008
20080265369Semiconductor Capacitor Structure - The present invention discloses a capacitor in an integrated circuit which comprises a first and second conductive lines substantially parallel to each other and having a thickness equals substantially to a sum of a via thickness and an interconnect thickness, the first and second conductive lines, the via and the interconnect being formed by a single deposition step, and at least one dielectric material in a space horizontally across the first and second conductive lines, wherein the first and second conductive lines serve as two conductive plates of the capacitor, respectively, and the dielectric material serves as an insulator of the capacitor.10-30-2008
20090085160Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System - Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.04-02-2009
20080272459Semiconductor Device and Manufacturing Method of Semiconductor Device - A semiconductor device and method of manufacturing the same are provided. According to certain embodiments, a device layer structure can be formed above a metal wiring line by using a stepped portion of the wiring line as an alignment key. The stepped portion can be provided by a height difference between a first insulating layer and the metal wiring line formed in a trench of the first insulating layer. In one embodiment, the stepped portion can be formed by removing a thickness from a top surface of the first insulating layer after forming the metal wiring line in the trench.11-06-2008
20130119512Top Electrode Templating for DRAM Capacitor - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.05-16-2013
20130119513Adsorption Site Blocking Method for Co-Doping ALD Films - A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.05-16-2013
20080265371Capacitor Unit and Method of Forming the Same - A capacitor unit includes a first capacitor and a second capacitor. The first capacitor includes a first lower electrode, a first dielectric layer pattern and a first upper electrode sequentially stacked. The first capacitor includes a first control layer pattern for controlling a voltage coefficient of capacitance (VCC) of the first capacitor between the first lower electrode and the first dielectric layer pattern. The second capacitor includes a second lower electrode, a second dielectric layer pattern and a second upper electrode sequentially stacked. The second lower electrode is electrically connected to the first upper electrode, and the second upper electrode is electrically connected to the second lower electrode. The second capacitor includes a second control layer pattern for controlling a VCC of the second capacitor between the second lower electrode and the second dielectric layer pattern.10-30-2008
20080265368Integrated Stacked Capacitor and Method of Fabricating Same - An integrated stacked capacitor comprises a first capacitor film (10-30-2008
20110006394CONNECT AND CAPACITOR SUBSTRATES IN A MULTILAYERED SUBSTRATE STRUCTURE COUPLED BY SURFACE COULOMB FORCES - A multi layered substrate structure can be formed where the substrates are coupled together using surface Coulomb forces. Connect substrates electrically connects signals and DC voltages between the substrates. The connect substrates bypass output/input buffers between two communicating substrates. The capacitor substrates provide a fully charged capacitor that provides additional energy to a levitated substrate if the capacitor substrate is connected to the levitated substrate. VLSI systems can also be build on each of the substrates.01-13-2011
20110204479SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a first ferroelectric film on a first conductive film by a film-forming method including at least a step of forming a film by a sol-gel method; forming a second ferroelectric film on the first ferroelectric film by a sputtering method; forming a second conductive film on the second ferroelectric film; and forming a capacitor provided with a lower electrode, a capacitor dielectric film and an upper electrode by patterning the first conductive film, the first and second ferroelectric films and the second conductive film.08-25-2011
20110204478INSULATOR LAYER BASED MEMS DEVICES - The present invention relates to using an insulator layer between two metal layers of a semiconductor die to provide a micro-electromechanical systems (MEMS) device, such as an ohmic MEMS switch or a capacitive MEMS switch. In an ohmic MEMS switch, the insulator layer may be used to reduce metal undercutting during fabrication, to prevent electrical shorting of a MEMS actuator to a MEMS cantilever, or both. In a capacitive MEMS switch, the insulator layer may be used as a capacitive dielectric between capacitive plates, which are provided by the two metal layers. A fixed capacitive element may be provided by the insulator layer between the two metal layers. In one embodiment of the present invention, an ohmic MEMS switch, a capacitive MEMS switch, a fixed capacitive element, or any combination thereof may be integrated into a single semiconductor die.08-25-2011
20080258260SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed over the dielectric film, an insulation film formed over the semiconductor substrate and the capacitor, and an electrode pad formed over the insulation film and including an alloy film of aluminum and magnesium.10-23-2008
20080258259SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor chip and a semiconductor device mounting the semiconductor chip capable of increasing a capacitance of a capacitor without reducing the number of signal bumps or power bumps of a package and the number of C10-23-2008
20080258258SEMICONDUCTOR DEVICE - The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors.10-23-2008
20080258257Electronic Device and Use Thereof - The integrated capacitor structure comprises a first branch with a first capacitor (10-23-2008
20100140742Semiconductor Device and Method of Forming Thin Film Capacitor - A semiconductor device has a first coil structure formed over the substrate. A second coil structure is formed over the substrate adjacent to the first coil structure. A third coil structure is formed over the substrate adjacent to the second coil structure. The first and second coil structures are coupled by mutual inductance, and the second and third coil structures are coupled by mutual inductance. The first, second, and third coil structures each have a height greater than a skin current depth of the coil structure defined as a depth which current reduces to 1/(complex permittivity) of a surface current value. A thin film capacitor is formed within the semiconductor device by a first metal plate, dielectric layer over the first metal plate, and second and third electrically isolated metal plates opposite the first metal plate. The terminals are located on the same side of the capacitor.06-10-2010
20100140743SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.06-10-2010
20090127657Semiconductor device and method of manufacturing the same - There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.05-21-2009
20090127655CAPACITOR FOR SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A capacitor for the semiconductor device may include a bottom electrode formed over a semiconductor substrate, a dielectric film pattern formed over the bottom electrode, an insulating member formed over a peripheral portion of the top surface of the dielectric film pattern, and a top electrode formed over the insulating member and dielectric film pattern. Capacitor properties are improved and capacitor values are maintained as constant by reducing a parasitic capacitance generated from edges of a capacitor electrode. Therefore, embodiments make it possible to improve semiconductor device properties and yields.05-21-2009
20100200950Semiconductor device having dielectric layer with improved electrical characteristics and associated methods - A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.08-12-2010
20100200949METHOD FOR TUNING THE THRESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE - A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.08-12-2010
20090283856METHOD FOR FABRICATING A SEMICONDUCTOR CAPACITPR DEVICE - A method for fabricating a semiconductor capacitor includes a substrate having thereon a carbon electrode. A transitional barrier layer is then deposited on the carbon electrode layer. Thereafter, a metal oxide layer is deposited on the transitional barrier layer, which reacts with the underlying transitional barrier layer to form a metal oxy-nitride layer acting as a capacitor dielectric layer of the capacitor device. A top electrode layer is then formed on the metal oxy-nitride layer.11-19-2009
20090174030LINEARITY CAPACITOR STRUCTURE AND METHOD07-09-2009
20090184394High performance system-on-chip inductor using post passivation process - A system and method for forming post passivation passive components, such as resistors and capacitors, is described. High quality electrical components, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.07-23-2009
20090184393MEMORY CAPACITOR AND MANUFACTURING METHOD THEREOF - The structure strength of a memory capacitor is reduced as the height of the memory capacitor is increased, which results in collapse and a short circuit. This invention provides a capacitor with a special reinforced structure outside, wherein the reinforced structure extends upward from the bottom of the lower electrode of the capacitor to a height, thus reducing the deformation caused by the process loading and supplying sufficient capacitance. In addition, the height of the reinforced structure is adaptable to requirement. Thereby, even when the capacitors are connected with one another because the capacitors collapse, the capacitors are prevented from malfunction. Moreover, the reinforced structures can be connected to one another or not, and thus the structure strength of the capacitor arrays is increased. Besides, the process is simplified and the cost is also reduced.07-23-2009
20090184392METHOD AND STRUCTURE FOR FORMING TRENCH DRAM WITH ASYMMETRIC STRAP - A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node dielectric covers said first side portion and said second side portion; depositing a first conductive layer over said node dielectric; performing an ion implantation or ion bombardment at an angle into a portion of said node dielectric, thereby removing said portion of said node dielectric from said first side portion of said deep trench; and depositing a second conductive layer over said first conductive layer, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. A trench device structure having a single-side buried strap is also provided. The device structure includes a semiconductor substrate having a deep trench therein; and a first conductive layer and a second conductive layer sequentially disposed on said deep trench, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate.07-23-2009
20090140386SEMICONDUCTOR DEVICE HAVING CAPACITOR ELEMENT - Provided is a semiconductor device which includes a capacitor element having a flat-plate-type lower electrode provided over a semiconductor substrate, a flat-plate-type TiN film provided over the lower electrode in parallel therewith, and a capacitor film provided between the lower electrode and the TiN film; and a first Cu plug brought into contact with the bottom surface of the lower electrode, and is composed of a metal material, wherein the capacitor film has a film which contains an organic molecule as a constituent.06-04-2009
20090140385Capacitor with nanotubes and method for fabricating the same - A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.06-04-2009
20120068306SEMICONDUCTOR PACKAGE INCLUDING DECOUPLING SEMICONDUCTOR CAPACITOR - A semiconductor package includes a packaging substrate including a first bond finger and a second bond finger, a first semiconductor chip mounted on the packaging substrate, and including a first chip pad and a second chip pad, the first bond finger being electrically connected to the first chip pad by a first bonding wire, and the second bond finger being electrically connected to the second chip pad by a second bonding wire, and a first decoupling semiconductor capacitor mounted on the first semiconductor chip, and including a first capacitor pad, the first capacitor pad being electrically connected to the second chip pad.03-22-2012
20120068305LATERAL CAPACITOR AND METHOD OF MAKING - An active device region is formed in and on a semiconductor substrate. An interconnect layer is formed over the active device region, wherein the interconnect layer comprises a first dielectric material having a first dielectric constant, a first metal interconnect in the first dielectric material, and a second metal interconnect in the first dielectric material and laterally spaced apart from the first metal interconnect. A portion of the first dielectric material is removed such that a remaining portion of the first dielectric material remains within the interconnect layer, wherein the removed portion is removed from a location between the first and second metal interconnects. The location between the first and second metal interconnects from which the portion of the first dielectric material was removed is filled with a second dielectric material having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant.03-22-2012
20120068304SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a semiconductor substrate; forming an opening within the substrate; forming a conductive layer within the opening; and forming a semiconductor layer over the conductive layer.03-22-2012
20090212392Capacitor Pairs with Improved Mismatch Performance - A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.08-27-2009
20100270648SEMICONDUCTOR INTEGRATED CIRCUIT, D-A CONVERTER DEVICE, AND A-D CONVERTER DEVICE - A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.10-28-2010
20110221036SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 09-15-2011
20110140237SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip and a passive element. The semiconductor chip has a semiconductor chip s body which possesses a first surface and a second surface facing away from the first surface, and a circuit section is formed in the semiconductor chip body. The passive element includes passive element bodies which are disposed in through-electrodes passing through the semiconductor chip body and connection members to which are disposed on at least one of the first surface and the second surface of the semiconductor chip body and which electrically connect to at least one of the passive element bodies.06-16-2011
20090051007SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.02-26-2009
20120104549MEMORY DEVICE AND FABRICATION THEREOF - The invention is related to a memory device, including a substrate, a capacitor which is substantially C-shaped in a cross section parallel to the substrate surface and a word line coupling the capacitor. In an embodiment, the C-shaped capacitor is a stack capacitor. Both inner edge and outer edge of the C-shaped capacitor can be used for providing capacitance.05-03-2012
20120104547LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE - Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure.05-03-2012
20090072349Semiconductor device and method of manufacturing the same - Example embodiments provide a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may include a lower electrode including a first lower electrode and a second lower electrode, and the second lower electrode may be formed on at least a part of the first lower electrode using a material different from the first lower electrode. A dielectric film may be formed on at least a part of the second lower electrode and a first upper electrode may be formed on the dielectric film.03-19-2009
20090102017SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE - A semiconductor device and a method of fabricating a semiconductor device provide high quality cylindrical capacitors. The semiconductor device includes a substrate defining a cell region and a peripheral circuit region, a plurality of capacitors in the cell region, and supports for supporting lower electrodes of the capacitors. The lower electrodes are disposed in a plurality of rows each extending in a first direction. A dielectric layer is disposed on the lower electrodes, and an upper electrode is disposed on the dielectric layer. The supports are in the form of stripes extending longitudinally in the first direction and spaced from each other along a second direction. Each of the supports engages the lower electrodes of a respective plurality of adjacent rows of the lower electrodes. Each one of the supports is also disposed at a different level in the device from the support that is adjacent thereto in the second direction.04-23-2009
20090014832Semiconductor Device with Reduced Capacitance Tolerance Value - A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.01-15-2009
20110227195Flexible Processing Method for Metal-Insulator-Metal Capacitor Formation - A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.09-22-2011
20080237795SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a semiconductor device which includes a base insulating film formed on a semiconductor substrate, a capacitor formed on the base insulating film, an interlayer insulating film covering the capacitor, a first layer metal wiring formed on the interlayer insulating film, a single-layer first insulating film which covers the interlayer insulating film and the first layer metal wiring and has a first film thickness above the first layer metal wiring, a first capacitor protective insulating film formed on the first insulating film, a first cover insulating film which is formed on the first capacitor protective insulating film and has a second film thickness thicker than the first film thickness, above the first layer metal wiring, a third hole formed in the insulating films on the first layer metal wiring, and a fifth conductive plug formed in the third hole.10-02-2008
20080237794Thin film capacitor - Disclosed is a thin film capacitor which can improve the uniformity of the capacitance while keeping a high capacitance. The thin film capacitor has a lower electrode serving as a trench forming layer where a trench pattern is to be formed, a dielectric film so provided as to cover the lower electrode, and an upper electrode laminated in order on the entire top surface of a substrate. The trench pattern is configured to have a first pattern and a second pattern separate from the first pattern. The first pattern has a plurality of protrusions provided upright at predetermined intervals, and the second pattern has a plurality of recesses provided at predetermined intervals. Trenches are each defined by the outer wall of each protrusion and the inner wall of each recess.10-02-2008
20110221034SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises a peripheral circuit region including a wiring layer having wiring patterns, a cavity formed in a non-wiring region between the wiring patterns of the wiring layer, and an insulating film forming at least a part of a wall defining the cavity, and a memory cell region.09-15-2011
20120193759CAPACITOR AND SEMICONDUCTOR DEVICE - A capacitor that has an electrode of an n-type semiconductor that is provided in contact with one surface of a dielectric, has a work function of 5.0 eV or higher, preferably 5.5 eV or higher, and includes nitrogen and at least one of indium, tin, and zinc. Since the electrode has a high work function, the dielectric can have a high potential barrier, and thus even when the dielectric is as thin as 10 nm or less, a sufficient insulating property can be maintained. In particular, a striking effect can be obtained when the dielectric is formed of a high-k material.08-02-2012
20090200639PACKAGE SUBSTRATE WITH BUILT-IN CAPACITOR AND MANUFACTURING METHOD THEREOF - When a package substrate with a built-in capacitor includes a first thin-film small electrode 08-13-2009
20090200637METHODS AND DEVICES FOR A HIGH-K STACKED CAPACITOR - An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.08-13-2009
20090200638MIM CAPACITOR INTEGRATION - An integrated metal-insulator-metal capacitor is formed so that there is an extension portion of its top plate that does not face any portion of the bottom plate, and an extension portion of its bottom plate that does not face any portion of the top plate. Vias connecting the MIM capacitor plates to conductors in an overlying metallization layer are formed so as to contact the extension portions of the top and bottom plates. Etching of the via holes is simplified because it is permissible for the via holes to punch through the extension portions of the capacitor plates. The bottom plate of the MIM capacitor is inlaid. The top plate of the MIM capacitor may be inlaid.08-13-2009
20090108402Method for Manufacturing Capacitor of Semiconductor Device - A method for manufacturing a capacitor of a semiconductor device may include: forming an interlayer insulating film including a contact plug over a semiconductor substrate; forming a first stack film comprising a capacitor oxide film and a nitride film over the interlayer insulating film; etching the first stack film to form a first stack pattern and a contact hole that exposes the contact plug; forming a lower electrode in the contact hole; forming a capping oxide film continuously over the first stack pattern so as to form a bridge between neighboring the first stack patterns; forming an etching barrier film including cavities over the capping oxide film; performing a blanket etching process onto the etching barrier film including cavities until the capacitor oxide film is exposed to form a nitride film pattern; and removing the exposed capacitor oxide film.04-30-2009
20090243037SEMICONDUCTOR DEVICE HAVING CAPACITORS FIXED TO SUPPORT PATTERNS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device containing a cylindrical shaped capacitor and a method for manufacturing the same is presented. The semiconductor device includes a plurality of storage nodes and a support pattern. The plurality of storage nodes is formed over a semiconductor substrate. The support pattern is fixed to adjacent storage nodes in which the support pattern has a flowable insulation layer buried within the support pattern. The buried flowable insulation layer direct contacts adjacent storage nodes.10-01-2009
20090230507MIM Capacitors in Semiconductor Components - Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.09-17-2009
20090256237SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DATA PROCESSING SYSTEM - A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.10-15-2009
20090243039MIM Capacitor And Method For Manufacturing the Same - Disclosed are an MIM (Metal-Insulator-Metal) capacitor and a method of manufacturing the same. The MIM capacitor includes: a lower metal layer and a lower metal interconnection on a substrate; a barrier metal layer on the lower metal layer; an insulating layer on the barrier metal layer; an upper metal layer on the insulating layer; an interlayer dielectric layer having a via hole on the lower metal interconnection; and a plug in the via hole.10-01-2009
20090243038METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening.10-01-2009
20090250787SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor storage device includes: a first conductive adhesive layer selectively formed over a semiconductor substrate; an insulating film formed on the semiconductor substrate to cover the first conductive adhesive layer and having an opening exposing a central part of the first conductive adhesive layer; and a capacitive element including a bottom electrode formed along a bottom surface and a wall surface of the opening, a capacitive insulating film formed on the bottom electrode, and a top electrode formed on the capacitive insulating film. The first conductive adhesive layer is in contact with the bottom electrode only at a bottom surface part of the opening which includes a corner where the bottom surface of the opening meets the wall surface thereof.10-08-2009
20090146254SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.06-11-2009
20090250788SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction, a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.10-08-2009
20090243036Semiconductor Devices and Methods of Manufacture Thereof - Capacitor plates, capacitors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes at least one via and at least one conductive member coupled to the at least one via. The at least one conductive member comprises an enlarged region proximate the at least one via.10-01-2009
20120193760SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.08-02-2012
20120193757CAPACITOR STRUCTURE AND FABRICATION METHOD THEREOF - A DRAM capacitor structure is disposed on the interior surface of a vertical hollow cylinder of a support structure overlying a semiconductor substrate. The support structure further includes a horizontal supporting layer that is integrally connected with the vertical hollow cylinder. A fabrication method for forming the DRAM capacitor structure is also provided.08-02-2012
20120193756DIODES WITH NATIVE OXIDE REGIONS FOR USE IN MEMORY ARRAYS AND METHODS OF FORMING THE SAME - In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.08-02-2012
20120193761Highly Integrated Semiconductor Devices Including Capacitors - A capacitor of semiconductor device is provided including a lower electrode on a semiconductor substrate; a dielectric film covering a surface of the lower electrode; and an upper electrode covering the dielectric film. The lower electrode includes a first conductive pattern having a groove region defined by a bottom portion and a sidewall portion; and a first core support pattern disposed in the groove region of the first conductive pattern and exposing a portion of inner sidewall of the first conductive pattern. Related methods are also provided herein.08-02-2012
20100032802Assembling of Electronic Members on IC Chip - The objective of this invention is to provide an assembling method for electronic members characterized by the fact that electronic members can be joined reliably and easily without using solder paste. The semiconductor device of the present invention has the following parts: silicon substrate 02-11-2010
20100155891SEMICONDUCTOR DEVICE HAVING CYLINDRICAL LOWER ELECTRODE OF CAPACITOR AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.06-24-2010
20100013047INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME - An integrated circuit on a substrate comprises a buffer capacitor in a buffer region. The buffer capacitor comprises a buffer electrode arranged at least partially in a recess, and a dielectric layer disposed between the buffer electrode and the substrate.01-21-2010
20090315144SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - An upper electrode of a ferroelectric capacitor has a first layer formed of a first oxide expressed by a chemical formula AO12-24-2009
20100148305Semiconductor Device and Fabricating Method Thereof - A semiconductor device and fabricating method thereof are disclosed. The present invention includes an insulating layer on a semiconductor substrate, a contact plug in and protruding from the insulating layer, and a capacitor on the insulating layer and the exposed contact plug, having a dome shape.06-17-2010
20100148307SEMICONDUCTOR DEVICE INCLUDING METAL-INSULATOR-METAL CAPACITOR ARRANGEMENT - A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.06-17-2010
20100148306Capacitor and Method of Manufacturing the Same - Disclosed are a capacitor and a method of manufacturing the same. The capacitor includes a plurality of polysilicon electrodes spaced apart from each other at a predetermined distance on a substrate, a dielectric layer between the polysilicon electrodes and having an air layer or void therein, a silicide on each polysilicon electrode, and a conductive contact electrically connected to the silicide.06-17-2010
20100148304INTEGRATED CIRCUIT DECOUPLING CAPACITORS - Power supply decoupling capacitors are provided for integrated circuits. The decoupling capacitors may be distributed in clusters amongst powered circuit components. Each cluster may contain a number of individual capacitor cells that are connected in parallel. Each capacitor cell may contain a capacitor and a resistor connected in series with the capacitor. The capacitors may be metal-insulator-metal (MIM) capacitors. The resistor in each cell may limit the current through an individual capacitor in the event of a short in the capacitor due to a dielectric defect.06-17-2010
20100155892Semiconductor Constructions - Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second material is formed over the first material. The second material may be one or both of polycrystalline and amorphous silicon. A third material is formed over the second material. A pattern is transferred through the first material, second material, third material, and oxide to form openings. Capacitors may be formed within the openings. Some embodiments include semiconductor constructions in which an oxide is over a substrate, a first material is over the oxide, and a second material containing one or both of polycrystalline and amorphous silicon is over the first material. Third, fourth and fifth materials are over the second material. An opening may extend through the oxide; and through the first, second, third, fourth and fifth materials.06-24-2010
20090121315METHOD FOR PRODUCING AN INTEGRATED CIRCUIT AND ARRANGEMENT COMPRISING A SUBSTRATE - Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided.05-14-2009
20100155890MIM CAPACITOR OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a MIM capacitor of a semiconductor device and a MIM capacitor. A MIM structure and a metal layer may be formed using a single process. A method of manufacturing a MIM capacitor may include forming a hole on and/or over a lower metal wire region. A method of manufacturing a MIM capacitor may include forming a lower metal layer, an inter-metal dielectric and/or an upper metal layer on and/or over a hole to form a MIM structure. Patterns to form a MIM structure and a metal layer may be formed at substantially the same time. If etching is performed with a photoresist pattern as a mask, a MIM structure and a metal layer structure may be formed at substantially the same time using a single mask.06-24-2010
20100155888SILICON INTERPOSER TESTING FOR THREE DIMENSIONAL CHIP STACK - A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer. The method thus provides same-sided probe testing of the interposer. The method also provides for loading or power application to the conductive glass handler and testing of circuits and interconnects on the test side of the silicon interposer.06-24-2010
20100155887Common plate capacitor array connections, and processes of making same - A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.06-24-2010
20100164062METHOD OF MANUFACTURING THROUGH-SILICON-VIA AND THROUGH-SILICON-VIA STRUCTURE - A method of manufacturing through-silicon-via (TSV) and a TSV structure are provided. The TSV structure includes a silicon substrate, an annular capacitor, a conductive through-via, a layer of low-k material, and a bump. The annular capacitor is within the silicon substrate and constituted of a first conductive layer, a capacitor dielectric layer, and a second conductive layer from the inside to the outside. The conductive through-via is disposed in the silicon substrate surrounded by the annular capacitor, and the layer of low-k material is between the annular capacitor and the conductive through-via. The bump is in touch with the conductive through-via for bonding other chip.07-01-2010
20100258903STRONTIUM RUTHENIUM OXIDE INTERFACE - Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.10-14-2010
20100176485 STORAGE CAPACITOR HAVING AN INCREASED APERTURE RATIO AND METHOD OF MANUFACTURING THE SAME - Disclosed is a method of manufacturing a storage capacitor having increased aperture ratio: providing a substrate having a metal layer disposed thereon, and said metal layer is covered correspondingly with a first dielectric layer and a second dielectric layer in sequence; forming a photoresist layer with a uniform thickness to cover said second dielectric layer; performing a process of exposure-to-light and development to a portion of said photoresist layer that is correspondingly disposed over said metal layer sequentially, so that its thickness is less than its original thickness; removing said photoresist layer and etching said portion of said second dielectric layer, so that a thickness of said portion of said second dielectric layer is less than its original thickness, and the etching depth of said portion is greater than that of the other remaining portions of said second dielectric layer; and forming an electrode layer on said second dielectric layer.07-15-2010
20090079030Forming SOI Trench Memory with Single-Sided Buried Strap - A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.03-26-2009
20090079029CAPACITOR STRUCTURE AND FABRICATING METHOD THEREOF - A capacitor structure including a substrate, a butting conductive layer, a second dielectric layer, a plurality of openings, a bottom electrode layer, a capacitor dielectric layer, a top electrode layer, and a second metal interconnect layer is provided. The substrate has a first dielectric layer and a first metal interconnect layer located in the first dielectric layer in a non-capacitor region. The butting conductive layer is disposed over the first dielectric layer in a capacitor region. The second dielectric layer is disposed over the first dielectric layer and covers the butting conductive layer. The openings include a first opening exposing a portion of the butting conductive layer and a second opening exposing the first metal interconnect layer. The bottom electrode layer, the capacitor dielectric layer, and the top electrode layer are conformally stacked in the first opening sequentially. The second metal interconnect layer is disposed in the openings.03-26-2009
20120032300METHOD OF MANUFACTURING A FERROELECTRIC CAPACITOR AND A FERROELECTRIC CAPACITOR - A lower electrode film is formed above a substrate. A ferroelectric film is formed above the lower electrode film. An amorphous intermediate film of a perovskite-type conductive oxide is formed above the ferroelectric film. A first upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the intermediate film. The intermediate film is crystallized by carrying out a first heat treatment in an atmosphere containing an oxidizing gas after the formation of the first upper electrode film. After the first heat treatment, a second upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the first upper electrode film, at a temperature lower than the growth temperature for the first upper electrode film.02-09-2012
20100187654Semiconductor device having capacitor and method of fabricating the same - A semiconductor device having a capacitor and a method of fabricating the same may be provided. A method of fabricating a semiconductor device may include forming an etch stop layer and a mold layer sequentially on a substrate, patterning the mold layer to form a mold electrode hole exposing a portion of the etch stop layer, etching selectively the exposed etch stop layer by an isotropic dry etching process to form a contact electrode hole through the etch stop layer to expose a portion of the substrate, forming a conductive layer on the substrate and removing the conductive layer on the mold layer on the mold layer to form a cylindrical bottom electrode in the mold and contact electrode holes. The isotropic dry etching process may utilize a process gas including main etching gas and selectivity adjusting gas. The selectivity adjusting gas may increase an etch rate of the etch stop layer by more than an etch rate of the mold layer by the isotropic wet etching process.07-29-2010
20100258904BOTTLE-SHAPED TRENCH CAPACITOR WITH ENHANCED CAPACITANCE - In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.10-14-2010
20100258906CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the conductive pattern. The buffer insulating pattern defines a region wider than a storage node region. An etch stop film is formed over the conductive pattern and the buffer insulating pattern. An interlayer insulating film is formed over the etch stop film. The interlayer insulating film is etched using the storage node mask to expose the etch stop film. The exposed etch stop film is etched to form the storage node region exposing conductive pattern. A lower storage node is formed over the storage node region.10-14-2010
20100258905SEMICONDUCTOR PACKAGE TO REMOVE POWER NOISE USING GROUND IMPEDANCE - A semiconductor package removes power noise by using a ground impedance. The semiconductor package includes an analog circuit block, a digital circuit block, an analog ground impedance structure, a digital ground impedance structure, and an integrated ground. The integrated ground and the analog circuit block are electrically connected via the analog ground impedance structure, and the integrated ground and the digital circuit block are electrically connected via the digital ground impedance structure, and an inductance of the analog ground impedance structure is greater than an inductance of the digital ground impedance structure.10-14-2010
20100207242Capacitive element, designing method of the same and integrated circuit device including the same - Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings.08-19-2010
20120228739HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS - An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.09-13-2012
20100176487ELECTRONIC COMPONENT WITH REACTIVE BARRIER AND HERMETIC PASSIVATION LAYER - An electronic component is provided on a substrate. A thin-film capacitor is attached to the substrate, the thin-film capacitor includes a pyrochlore or perovskite dielectric layer between a plurality of electrode layers, the electrode layers being formed from a conductive thin-film material. A reactive barrier layer is deposited over the thin-film capacitor. The reactive barrier layer includes an oxide having an element with more than one valence state, wherein the element with more than one valence state has a molar ratio of the molar amount of the element that is in its highest valence state to its total molar amount in the barrier of 50% to 100%. Optionally layers of other materials may intervene between the capacitor and reactive barrier layer. The reactive barrier layer may be paraelectric and the electronic component may be a tunable capacitor.07-15-2010
20100176486Semiconductor device and method of manufacturing the same - A semiconductor device includes a memory cell region and a peripheral circuit region. The memory cell region includes a first region and a second region surrounding the first region. The first region includes a plurality of first electrodes, a plurality of first support portions, and a second support portion. The plurality of first electrodes upwardly extends. The plurality of first support portions upwardly extends along the plurality of first electrodes. Each of the plurality of first support portions mechanically supports corresponding one of the plurality of first electrodes. The second support portion contacts with the plurality of the first support portions. The second support portion connects between each of the plurality of first electrodes.07-15-2010
20100193906Integrated Circuit Package for Magnetic Capacitor - An integrated circuit package for magnetic capacitor including a substrate, an integrated circuit and a magnetic capacitor unit is disclosed. The substrate has a first surface and an opposite second surface. The integrated circuit is connected to the second surface of the substrate. The magnetic capacitor unit has a positive terminal and a negative terminal connected to the substrate.08-05-2010
20100001371SEMICONDUCTOR DEVICE HAVING CAPACITOR INCLUDING A HIGH DIELECTRIC FILM AND MANUFACTURE METHOD OF THE SAME - A semiconductor device includes a substrate, a plurality of lower electrodes arranged on the substrate, a high dielectric film disposed continuously on the plurality of lower electrodes, and an upper electrode disposed on the high dielectric film.01-07-2010
20110001216Semiconductor device and manufacturing method thereof - A manufacturing method of a semiconductor device includes: forming a wiring in a first interlayer insulating layer in a first region; etching an surface portion of the first interlayer insulating layer in a second region;01-06-2011
20100207244Semiconductor apparatus with decoupling capacitor - A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.08-19-2010
20100237463Selective Fabrication of High-Capacitance Insulator for a Metal-Oxide-Metal Capacitor - Methods and devices of a capacitor in a semiconductor device having an increased capacitance are disclosed. In a particular embodiment, a method of forming a capacitor is disclosed. A section of a first insulating material between a first metal contact element and a second metal contact element is removed to form a channel. A second insulating material is deposited in the channel between the first metal contact element and the second metal contact element.09-23-2010
20100001373CORRESPONDING CAPACITOR ARRANGEMENT AND METHOD FOR MAKING THE SAME - The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.01-07-2010
20100001372SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Stable contact hole forming is attained even when an aluminum oxide film is present between layers provided with contact holes. The process comprises the steps of forming a first element layer on a semiconductor substrate; forming a first interlayer insulating film on the first element layer; forming a second element layer on the first interlayer insulating film; forming a second interlayer insulating film on the second element layer; forming a hole resist pattern on the second interlayer insulating film; conducting a first etching for forming of holes by etching the second interlayer insulating film; and conducting a second etching for extending of holes to the first element layer by etching the first interlayer insulating film.01-07-2010
20100224959Semiconductor Chip, Transponder and Method of Manufacturing a Transponder - A semiconductor chip (09-09-2010
20100237466SEMICONDUCTOR DEVICES - A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.09-23-2010
20100237465CAPACITOR AND A METHOD OF MANUFACTURING A CAPACITOR - A device comprises a substrate (09-23-2010
20100140740Semiconductor device - A semiconductor device includes: a first capacitor including an upper electrode, a lower electrode, an intermediate electrode arranged between the upper electrode and the lower electrode, and a shield line arranged in the same layer as the intermediate electrode; and a second capacitor, including an upper electrode, a lower electrode, and an intermediate electrode arranged between the upper electrode and the lower electrode, and arranged adjoining to the first capacitor. In the first capacitor and the second capacitor, the upper electrode, the lower electrode and the shield line are electrically connected to a ground electrode. The shield line lies between the first capacitor and the second capacitor. Accordingly, a MIM capacitor with excellent layout efficiency is provided while noise effects are reduced.06-10-2010
20100207246METHOD OF MAKING AN MIM CAPACITOR AND MIM CAPACITOR STRUCTURE FORMED THEREBY - A method of forming an MIM capacitor having interdigitated capacitor plates. Metal and dielectric layers are alternately deposited in an opening in a layer of insulator material. After each deposition of the metal layer, the metal layer is removed at an angle from the side to form the capacitor plate. The side from which the metal layer is removed is alternated with every metal layer that is deposited. When all the capacitor plates have been formed, the remaining opening in the layer of insulator material is filled with dielectric material then planarized, followed by the formation of contacts with the capacitor plates. There is also an MIM capacitor structure having interdigitated capacitor plates.08-19-2010
20100252911SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor.10-07-2010
20100252909Three-Dimensional Memory Devices - An integrated circuit memory device may include a semiconductor substrate and a plurality of word-line layers wherein adjacent word-line layers are separated by respective word-line insulating layers. A plurality of active pillars may extend from a surface of the semiconductor substrate through the plurality of word-line layers and insulating layers. Dielectric information storage layers may be provided between the active pillars and the respective word-line layers. Related methods of operation and fabrication are also discussed.10-07-2010
20100140741STRUCTURE OF CAPACITOR SET - A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.06-10-2010
20110057293METAL-OXIDE-METAL CAPACITOR HAVING LOW PARASITIC CAPACITOR - A metal-oxide-metal capacitor including a first metal layer of negative electric charge, a second metal layer of the negative electric charge, and at least a third metal layer formed between the first metal layer and the second metal layer, each of the at least a third metal layer including a plurality of first stripes of the negative electric charge and a plurality of second stripes of positive electric charge, wherein one of the plurality of first stripes is at a side of the third metal layer.03-10-2011
20110057292CAPACITORS AND INTERCONNECTS INCLUDING AT LEAST TWO PORTIONS OF A METAL NITRIDE MATERIAL, METHODS OF FORMING SUCH STRUCTURES, AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES - Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects.03-10-2011
20100127348INTEGRATED CAPICITOR WITH CABLED PLATES - A capacitor in an integrated circuit (“IC”) has a distribution grid formed in a first patterned metal layer of the integrated circuit and a first vertical conductive filament connected to and extending away from the distribution grid along a first direction. A second vertical conductive filament is connected to the distribution grid and extends in the opposite direction. First and second grid plates are formed in the metal layers above and below the first patterned metal layer. The grid plates surround the first and second vertical conductive filaments. The distribution grid, first vertical conductive filament and second vertical conductive filament are connected to and form a portion of a first node of the capacitor and the first grid plate and the second grid plate are connected to and form a portion of a second node of the capacitor.05-27-2010
20130127011Passive Devices For 3D Non-Volatile Memory - Passive devices such as resistors and capacitors are provided for a 3D non-volatile memory device. In a peripheral area of a substrate, a passive device includes alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are provided above the stack. Contact structures extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel, for a capacitor, or serially, for a resistor, by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers.05-23-2013
20090014833SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - An exemplary semiconductor device includes a semiconductor substrate on which lower electrodes are formed. The lower electrodes are arranged in an array including a rows extending substantially parallel to one another along a first direction. A stripe-shaped capacitor support pad is interposed between a pair of adjacent ones of the rows and is connected to lower electrodes in the pair of adjacent ones of the rows. The semiconductor device may include plurality of capacitors each including a one of the lower electrodes, a dielectric film, and an upper electrode. An upper end of the capacitor support pad is below the upper ends of the lower electrodes. A portion of the stripe-shaped capacitor support pad is interposed between adjacent ones of lower electrodes included within at least one of the rows and is connected to the adjacent ones of lower electrodes included within the at least one of the rows.01-15-2009
20090273057METHOD, APPARATUS, AND SYSTEM FOR LOW TEMPERATURE DEPOSITION AND IRRADIATION ANNEALING OF THIN FILM CAPACITOR - Some embodiments of the invention include thin film capacitors formed in a package substrate of an integrated circuit package. At least one of the thin film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.11-05-2009
20080315357INTEGRATED CIRCUIT AND METHOD INCLUDING STRUCTURING A MATERIAL - A method of making an integrated circuit including structuring a material. The method includes providing an arrangement of three-dimensional bodies. The material is arranged between the bodies and structured directed radiation. The projection pattern of the three-dimensional bodies is transferred into the material. The structured material connects at least two of the three-dimensional bodies.12-25-2008
20100193907CAPACITOR STRUCTURE IN A SEMICONDUCTOR DEVICE - A semiconductor device comprises an integrated circuit formed on a substrate with a signal interface and at least one isolator capacitor. The integrated circuit comprises a plurality of interleaved inter-metal dielectric layers and interlayer dielectrics formed on the substrate, a thick passivation layer formed on the plurality of the interleaved inter-metal dielectric layers and interlayer dielectrics, and a thick metal layer formed on the thick passivation layer. The thick passivation layer has a thickness selected to be greater than the isolation thickness whereby testing for defects is eliminated. The one or more isolator capacitors comprise the thick metal layer and a metal layer in the plurality of interleaved inter-metal dielectric layers and interlayer dielectrics separated by the thick passivation layer as an insulator.08-05-2010
20110115051SEMICONDUCTOR DEVICES INCLUDING 3-D STRUCTURES WITH SUPPORT PAD STRUCTURES AND RELATED METHODS AND SYSTEMS - A semiconductor device may include a semiconductor substrate and a plurality of three-dimensional capacitors on the semiconductor substrate. Each of the plurality of three-dimensional capacitors may include a first three-dimensional electrode, a capacitor dielectric layer, and a second three-dimensional electrode with the first three-dimensional electrode between the capacitor dielectric layer and the semiconductor substrate and with the capacitor dielectric layer between the first and second three-dimensional electrodes. A plurality of capacitor support pads may be provided with each capacitor support pad being arranged between adjacent first three-dimensional electrodes of adjacent three-dimensional capacitors with portions of the capacitor dielectric layers between the capacitor support pads and the semiconductor substrate. Related methods and apparatuses are also discussed.05-19-2011
20090146256METHOD OF FORMING SEMICONDUCTOR DEVICE INCLUDING CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING CAPACITOR - A method of forming a semiconductor device may include, but is not limited to, the following processes. A second insulating film may be formed over a first insulating film. At least one through-hole may be formed, which penetrates the first and second insulating films. At least one first electrode may be formed, which extends at least along the side wall of the at least one through-hole. The first inter-layer insulator may be removed, while using the second insulating film as a temporary supporter that supports the at least one first electrode. At least one permanent supporter may be formed, which supports the at least one first electrode. The second insulating film as the temporary supporter may be removed, while leaving the at least one permanent supporter to support the at least one first electrode.06-11-2009
20090039466SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Effective area of a capacitor is to be increased while suppressing increase in number of manufacturing steps. In a semiconductor device, a silicon substrate includes a plurality of first recessed portions having a first depth from the main surface thereof, a second recessed portion provided in a region other than the first recessed portion and having a second depth from the main surface, and a third recessed portion provided in at least one of the plurality of first recessed portions and having a third depth from the bottom portion of the first recessed portion. The second recessed portion and the third recessed portion have the same depth, and a decoupling condenser is provided so as to fill the at least one of the first recessed portion and the third recessed portion provided therein, and an isolation insulating layer is provided so as to fill the remaining first recessed portions, and the second recessed portion is filled with a gate electrode.02-12-2009
20090039465ON-CHIP DECOUPLING CAPACITOR STRUCTURES - The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.02-12-2009
20090115023CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A capacitor of a semiconductor device and a method for manufacturing the same. In one example embodiment, a capacitor of a semiconductor device includes a first electrode, first dielectric layer, second electrode, second dielectric layer, and third electrode sequentially formed on a semiconductor substrate. The capacitor also includes a first contact coupled to the first electrode and to the third electrode. The capacitor further includes a second contact coupled to the second electrode.05-07-2009
20080296730Semiconductor device - A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a main component and formed on the insulating film to be electrically connected to the copper wire via a via hole formed to penetrate through the insulating film; and a surface protective film formed on the aluminum wire; and the surface protective film formed with a pad opening exposing a portion of the aluminum wire as an electrode pad for electrical connection with an external portion.12-04-2008
20100219503CHIP CAPACITIVE COUPLING - A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.09-02-2010
20090072350SEMICONDUCTOR DEVICES HAVING A CONTACT PLUG AND FABRICATION METHODS THEREOF - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.03-19-2009
20100219502MIM Decoupling Capacitors under a Contact Pad - An integrated circuit structure includes one or more external contact pads with decoupling capacitors, such as metal-insulator-metal (MIM) capacitors, formed directly thereunder. In an embodiment, the decoupling capacitors are formed below the first metallization layer, and in another embodiment, the decoupling capacitors are formed in the uppermost inter-metal dielectric layer. A bottom plate of the decoupling capacitors is electrically coupled to one of V09-02-2010
20090108404SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction.04-30-2009
20090108403SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a capacitor embedded in a dielectric material below the surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed.04-30-2009
20090108405SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A conductive film embedded in a predetermined region on an upper surface of an insulation film and metallic wirings embedded so as to penetrate through the conductive film and protrudes into the insulation film constitute a lower electrode of an MIM capacitor.04-30-2009
20100295154Capacitor Structure - One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.11-25-2010
20100295155TECHNIQUES FOR CAPACITIVELY COUPLING SIGNALS WITH AN INTEGRATED CIRCUIT - System and apparatus for capacitively coupling signals with an integrated circuit (IC) are described. Capacitive elements disposed with a transmitting IC effectively function as AC coupling capacitors for a PCIe, DisplayPort™ or other interconnect linking the transmitting IC with a receiver disposed remote there from. Integrating the coupling capacitors allows for a smaller and more economical design for the circuits that utilize the interconnect.11-25-2010
20100295152Precision high-frequency capacitor formed on semiconductor substrate - A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.11-25-2010
20100295153INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.11-25-2010
20100301451Semiconductor device, lower layer wiring designing device, method of designing lower layer wiring and computer program - A semiconductor device includes a lower layer wiring layer, an MIM capacitors and an upper layer wiring layer. The lower layer wiring layer includes a plurality of lower layer wirings. The MIM capacitor is formed above the lower layer wiring layer. The MIM capacitor includes a lower electrode, a capacity dielectric film and an upper electrode which are layered from underneath in this order. A planar form of the upper electrode is smaller than that of the lower electrode. The upper layer wiring layer includes a plurality of upper layer wirings which are connected to the lower electrode and the upper electrode through via plugs. A plane of the upper electrode is made rectangular. The lower layer wirings are not arranged right below one or more than one edge of the plane of the upper electrode.12-02-2010
20130134553INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES - Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.05-30-2013
20130134554VERTICAL CAPACITORS AND METHODS OF FORMING THE SAME - Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate.05-30-2013
20100314715SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a memory cell area; and a peripheral circuit area separated by a groove from the memory cell area. The peripheral circuit area is positioned outside the memory cell area. The memory cell area includes a plurality of electrodes that stand; and a first insulating film that support the plurality of electrodes standing. The first insulating film has a plurality of holes through which the plurality of electrodes penetrates. The first insulating film is in contact with at least a part of an outside surface of the electrode. The first insulating film has at least a first opening which is connected to part of the plurality of holes. The first insulating film has at least a second opening which is closer to the groove than any holes of the plurality of holes. The second opening is separated from the plurality of holes.12-16-2010
20110006395HYBRID BUMP CAPACITOR - A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.01-13-2011
20100237464Chip Inductor With Frequency Dependent Inductance - A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.09-23-2010
20100327407INTERCONNECTION WIRING STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; forming storage node contact lines which fill the second damascene trenches.12-30-2010
20100133655SEMICONDUCTOR DEVICE HAVING A CAPACITANCE ELEMENT AND METHOD OF MANUFACTURING THE SAME - A dielectric film is formed by depositing an amorphous strontium oxide film to a thickness of one to several atomic layers on a first electrode layer, then depositing an amorphous titanium oxide film to a thickness of one to several atomic layers on the amorphous strontium oxide film, and then heat-treating a laminated film of the amorphous strontium oxide film and the amorphous titanium oxide film at a temperature close to a crystallization start temperature, thereby converting the laminated film to a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein. The laminated film may have a plurality of amorphous strontium oxide films and a plurality of amorphous titanium oxide films that are alternately laminated. A semiconductor device includes a capacitor having as its dielectric film a single-layer amorphous strontium titanate film containing a plurality of crystal grains therein.06-03-2010
20100133654METHOD FOR MANUFACTURING CAPACITOR OF SEMICONDUCTOR - The present invention relates to a method of producing a semiconductor capacitor, and more particularly, to a method of producing a semiconductor capacitor, in which an electroless plating is performed during the production of a lower electrode to form a lower electrode.06-03-2010
20110241170MONOLITHIC SEMICONDUCTOR SWITCHES AND METHOD FOR MANUFACTURING - One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.10-06-2011
20110018100CAPACITOR, SEMICONDUCTOR DEVICE COMPRISING THE SAME, METHOD FOR MANUFACTURING THE CAPACITOR, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - Provided is a capacitor that realizes a capacitance insulation film having a large relative permittivity and has sufficient capacitance even if an occupied space is small with a reduced amount of leakage current. A capacitor includes: a capacitance insulation film; and an upper electrode and lower electrode each formed on both sides of the capacitance insulation film. The capacitance insulation film is a complex oxide whose main ingredients are Zr, Al and O with the composition ratio of Zr to Al being set at (1−x): x (0.01≦x≦0.15) and is composed of a dielectric substance having a crystal structure. The lower electrode is composed of a conductor whose surface contiguous to at least the dielectric film has an amorphous structure.01-27-2011
20110018095THREE DIMENSIONAL INTEGRATED DEEP TRENCH DECOUPLING CAPACITORS - A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.01-27-2011
20110108951SEMICONDUCTOR DEVICE WITH MIM CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a lower electrode formed on a substrate, a dielectric layer including an etched dielectric region and an as-grown dielectric region formed on the lower electrode, an upper electrode formed on the as-grown dielectric region, a hardmask formed on the upper electrode, a spacer formed at a side surface of the hardmask and the upper electrode and over a surface of the etched dielectric region, and a buffer insulation layer formed on the hardmask and the spacer.05-12-2011
20110108949METAL CAPACITOR DESIGN FOR IMPROVED RELIABILITY AND GOOD ELECTRICAL CONNECTION - A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias. The design enables the spacing between metal lines to be maintained, the spacing between via to metal to be increased, and via connection to be maintained for both nets, thereby improving the conductivity and reliability of the capacitor and maintaining capacitance density.05-12-2011
20110024875METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND SUBSTRATE PROCESSING APPARATUS - A high-k capacitor insulating film stable at a higher temperature is formed. There is provided a method of manufacturing a semiconductor device. The method comprises: forming an amorphous first insulating film comprising a first element on a substrate; adding a second element different from the first element to the first insulating film so as to form an amorphous second insulating film on the substrate; and annealing the second insulating film at a predetermined annealing temperature so as to form a third insulating film by changing a phase of the second insulating film. The concentration of the second element added to the first insulating film is controlled according to the annealing temperature.02-03-2011
20110031585Method for fabricating a MIM capacitor using gate metal for electrode and related structure - According to one exemplary embodiment, a method for fabricating a MIM capacitor in a semiconductor die includes forming a dielectric one segment over a substrate and a metal one segment over the dielectric one segment, where the metal one segment forms a lower electrode of the MIM capacitor. The method further includes forming a dielectric two segment over the dielectric one segment and a metal two segment over the dielectric two segment, where a portion of the metal two segment forms an upper electrode of the MIM capacitor. The metal one segment comprises a first gate metal. The metal two segment can comprise a second gate metal.02-10-2011
20110042785SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes an insulation layer formed over a semiconductor substrate; a capacitance element including a conduction layer containing Cu and formed in the insulation layer, a lower electrode including a first barrier film of a conductive material formed over the conduction layer and the insulation layer, the first dielectric film formed over the lower electrode, and an upper electrode formed over the first dielectric film; an interconnection containing Cu formed in the insulation layer; and the second barrier film of a conductive material formed over the interconnection and the insulation layer.02-24-2011
20110042784Mechanical Barrier Element for Improved Thermal Reliability of Electronic Components - Embodiments of the invention are generally related to packaging of integrated circuit devices, and more specifically to the placement of thermal paste for cooling an integrated circuit device during operation. A barrier element may be placed along at least one side of an integrated circuit chip. The barrier element may contain thermal paste pumped out during expansion and contraction of the package components to areas near the chip. The barrier element may also form a reservoir to replenish thermal paste that is lost during thermal pumping of the paste.02-24-2011
20110115052SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a capacitor having a lower electrode in which the lower electrode includes a first cylindrical lower electrode connected to a contact electrically connected to a semiconductor substrate; and a second cylindrical lower electrode in contact with an inner wall of at least an upper end of the first cylindrical lower electrode and extending upwards from a top of the first cylindrical lower electrode.05-19-2011
20110115050Semiconductor Device and Method of Forming IPD on Molded Substrate - A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.05-19-2011
20110018097INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR - Disclosed is an integrated circuit (IC) comprising a substrate (01-27-2011
20090085157Manufacturing method for an integrated circuit, corresponding intermediate integrated circuit structure and corresponding integrated circuit - The present invention provides a method of manufacturing integrated circuit including a plurality of pillars, comprising the steps of: forming a plurality of first trenches in a first layer comprising a first material, thereby leaving a plurality of fins of the first material between said trenches; forming an infill comprising a second material in said first trenches; forming a plurality of second trenches in said first layer and said infill, the second trenches having sidewalls, walls, wherein first portions of said sidewalls expose the first material, and second portions of said sidewalls expose the second material; and removing either the first or the second material selectively to the respective other material, thereby leaving said pillars of the remaining material. The invention also provides a corresponding intermediate integrated circuit structure.04-02-2009
20090315143Methods of Forming Integrated Circuit Devices Including Insulating Support Layers and Related Structures - An integrated circuit device may include a substrate, a plurality of storage electrode landing pads on the substrate, and a plurality of storage electrodes. Each of the plurality of storage electrodes may be on a portion of a respective one of the plurality of storage electrode landing pads. In addition, an insulating support layer may be on the substrate, on portions of the storage electrode landing pads that are free of the storage electrodes, and on portions of sidewalls of storage electrodes. Moreover, portions of sidewalls of the storage electrodes may be free of the insulating support layer. Related methods and structures are also discussed.12-24-2009
20090032905Electronic Devices Including Electrode Walls with Insulating Layers Thereon - An electronic device may include a substrate and a plurality of conductive electrodes on the substrate. Each of the conductive electrodes may have a respective electrode wall extending away from the substrate, and an electrode wall of at least one of the conductive electrodes may include a recessed portion. In addition, an insulating layer may be provided on the electrode wall, and portions of the electrode wall may be free of the insulating layer between the substrate and the insulating layer.02-05-2009
20100164066INTEGRATED CAPACITOR HAVING A NON-UNIFORM THICKNESS - An embodiment of an electronic device integrated in a chip of semiconductor material and an embodiment of a corresponding production method are proposed. The electronic device includes a capacitor having a first conductive plate, a second conductive plate, and an insulating layer for insulating the first plate from the second plate. In an embodiment of the invention, at least a selected one between the first plate and the second plate has a non-uniform thickness.07-01-2010
20100164067CAPACITOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor device includes a capacitor element including a first comb-shaped interconnection formed over a substrate and including a first comb tooth, a second comb-shaped interconnection formed over the substrate and including a second comb tooth opposed to the first comb tooth, and a first electrode and a second electrode opposed to each other with opposed surfaces of the first electrode and the second electrode intersecting a longitudinal direction of the first comb tooth and the second comb tooth, a first dielectric layer formed between the first electrode and the second electrode, the first electrode being connected to the first comb tooth, and the second electrode being connected to the second comb tooth.07-01-2010
20100164065CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A capacitor of a semiconductor device and a method for manufacturing the same includes a lower metal layer on and/or over a semiconductor substrate; an insulating layer formed on and/or over the lower metal layer with step difference; and an upper electrode on and/or over the insulating layer pattern, wherein a top corner of the upper electrode is rounded so that a curvature pattern is formed on the top corner of the upper electrode.07-01-2010
20100164063MIM CAPACITOR AND METHOD FOR FABRICATING THE SAME - A MIM capacitor may include a plurality of lower electrodes over a semiconductor substrate. A plurality of insulators may be formed over the lower electrodes, with each insulator having a thickness which is different from the thickness of at least one other insulator among the plurality of insulators. Upper electrodes may be formed over the plurality of insulators. This arrangement permits a plurality of MIM capacitors having differing capacitance values to be formed on a semiconductor substrate, enabling the MIM capacitors to be applied to devices or chips which have various characteristics.07-01-2010
20110241169METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A capacitor having a cylindrical shape is increased in capacitance, and a high-resistance region is prevented from being formed in a lower electrode. A semiconductor device includes a capacitor formed to have a cylindrical shape. The semiconductor device includes an insulating film formed over a substrate, a lower electrode formed to have a cylindrical shape, and including a first metal film which is not formed at a bottom portion in a depressed portion provided in the insulating film, but is selectively formed at a sidewall therein and a second metal film which is formed over the bottom portion in the depressed portion and over the first metal film at the sidewall therein, a capacitive film formed over the lower electrode, and an upper electrode formed over the capacitive film.10-06-2011
20110241166Semiconductor Device Comprising a Capacitor Formed in the Contact Level - A contact level in a semiconductor device may be used for providing a capacitor that may be directly connected to a transistor, thereby providing a very space-efficient capacitor/transistor configuration. For example, superior dynamic RAM arrays may be formed on the basis of the capacitor/transistor configuration disclosed herein.10-06-2011
20100025814STRUCTURE FOR DUAL CONTACT TRENCH CAPACITOR AND STRUCTURE THEREOF - A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.02-04-2010
20110241168PACKAGE ON PACKAGE STRUCTURE - A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate.10-06-2011
20110210424SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Ferroelectric capacitors (09-01-2011
20110210423INTEGRATED CIRCUIT DEVICES HAVING A STRONTIUM RUTHENIUM OXIDE INTERFACE - Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.09-01-2011
20110210421TRENCH-TYPE CAPACITOR, SEMICONDUCTOR DEVICE HAVING THE SAME, AND SEMICONDUCTOR MODULE HAVING THE SEMICONDUCTOR DEVICE - Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.09-01-2011
20090085159SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes cylinder type bottom electrodes connected to a contact plug formed over a semiconductor substrate, and a supporting pattern formed between the cylinder type bottom electrodes, wherein a portion of sidewalls of the bottom electrodes is higher than the supporting pattern and the other portion of the sidewalls of the bottom electrode is lower than the supporting pattern.04-02-2009
20110241167Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime - Capacitors may be formed in the metallization system of semiconductor devices without requiring a modification of the hard mask patterning process for forming vias and trenches in the dielectric material of the metallization layer under consideration. To this end, a capacitor opening is formed prior to actually forming the hard mask for patterning the trench and via openings, wherein the hard mask material may thus preserve integrity of the capacitor opening and may remain as a portion of the electrode material after filling in the conductive material for the metal lines, vias and the capacitor electrode.10-06-2011
20100187655Integrated Circuit Capacitors Having Composite Dielectric Layers Therein Containing Crystallization Inhibiting Regions and Methods of Forming Same - Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.07-29-2010
20100032799Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips - A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.02-11-2010
20090321877SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a ferroelectric capacitor formed over a semiconductor substrate, wherein the ferroelectric capacitor including a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film, and the upper electrode including a first conductive film formed of a first conductive noble metal oxide, and a second conductive film formed of a metal nitride compound formed on the first conductive film.12-31-2009
20100013049SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A first multilayer body is formed by alternately layering dielectric films and electrode films on a substrate. Then, an end portion of the first multilayer body is processed into a staircase shape, and a first interlayer dielectric film is formed around the first multilayer body. Next, a plurality of contact holes having a diameter decreasing downward are formed in the first interlayer dielectric film so that the contact holes reach respective end portions of the electrode films. Then, a sacrificial material is buried in the contact holes. Next, a second multilayer body is formed immediately above the first multilayer body, and a second interlayer dielectric film is formed around the second multilayer body. Thereafter, a plurality of contact holes having a diameter decreasing downward are formed in the second interlayer dielectric film to communicate with the respective contact holes formed in the first interlayer dielectric film. Then, the sacrificial material is removed and a contact is buried inside the contact holes. The contact has a step difference.01-21-2010
20100013048INTERCONNECT LINE SELECTIVELY ISOLATED FROM AN UNDERLYING CONTACT PLUG - A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration, and in subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.01-21-2010
20100032800Capacitor Structure - One or more embodiments relate to a semiconductor device, comprising: a substrate; and a plurality of first conductive vias, the first conductive vias electrically coupled together, each of the first conductive vias passing through the substrate; and a plurality of second conductive vias, the second conductive vias electrically coupled together, each of the second conductive vias passing through the substrate, the second conductive vias spacedly disposed from the first conductive vias.02-11-2010
20100038751STRUCTURE AND METHOD FOR MANUFACTURING TRENCH CAPACITANCE - A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.02-18-2010
20110175196SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p07-21-2011
20120146182HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.06-14-2012
20120241907FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER - An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.09-27-2012
20100065944SEMICONDUCTOR DEVICE WITH DECOUPLING CAPACITOR DESIGN - An integrated circuit includes a circuit module having a plurality of active components coupled between a pair of supply nodes, and a capacitive decoupling module coupled to the circuit module. The capacitive decoupling module includes a plurality of metal-insulator-metal (MiM) capacitors coupled in series between the pair of supply nodes, wherein a voltage between the supply nodes is divided across the plurality of MiM capacitors, thereby reducing voltage stress on the capacitors.03-18-2010
20110084360EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE - Trench capacitors and methods of manufacturing the trench capacitors are provided. The trench capacitors are very dense series capacitor structures with independent electrode contacts. In the method, a series of capacitors are formed by forming a plurality of insulator layers and a plurality of electrodes in a trench structure, where each electrode is formed in an alternating manner with each insulator layer. The method further includes planarizing the electrodes to form contact regions for a plurality of capacitors.04-14-2011
20100127346POWER DISTRIBUTION FOR CMOS CIRCUITS USING IN-SUBSTRATE DECOUPLING CAPACITORS AND BACK SIDE METAL LAYERS - A semiconductor device and method for fabricating the same is provided. The semiconductor device includes a substrate, at least one capacitor, an active circuit and a power plane. The substrate has a first cavity formed through a first surface to a first depth and a second cavity formed through a second surface to a second depth. The first and second cavities forming a via hole through the substrate. The at least one capacitor includes a first conductive material layer deposited in the via hole, a first isolation material layer deposited over the first conductive material layer, and a second conductive material layer deposited over the first isolation material layer. The active circuit adjacent the first surface and electrically coupled to the at least one capacitor, and the power plane adjacent the second surface and electrically coupled to the at least one capacitor to provide power conditioning to the active circuit.05-27-2010
20120267761CAPACITOR - A capacitor is provided. The capacitor includes first and second electrode layers facing each other, a first conductive pattern disposed between the first and second electrode layers, the first conductive pattern forming a closed loop in plan view, a second conductive pattern disposed within an inner space surrounded by the closed loop of the first conductive pattern, the second conductive pattern being spaced from the first conductive pattern, and a first contact plug passing through the second conductive pattern to contact the first and second electrode layers.10-25-2012
20120267760CAPACITOR AND MANUFACTURING METHOD THEREOF - A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.10-25-2012
20100123214METAL-OXIDE-METAL STRUCTURE WITH IMPROVED CAPACITIVE COUPLING AREA - A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.05-20-2010
20100123216Semiconductor integrated circuit including a power supply, semiconductor system including a semiconductor integrated circuit, and method of forming a semiconductor integrated circuit - Provided are a semiconductor integrated circuit including a power supply, a semiconductor system including the semiconductor integrated circuit, and a method of forming the semiconductor integrated circuit. The semiconductor integrated circuit includes: a semiconductor substrate on a surface of which a plurality of electrical circuits and a plurality of power pads are mounted; an insulation layer stacked on the semiconductor substrate; a first conductive layer connected to a first power pad by a first via and stacked on the insulation layer; a second conductive layer connected to a second power pad by a second via, stacked on the insulation layer, and separated from the first insulation layer; and a power generation layer stacked on the first conductive layer and the second conductive layer and that generates voltage.05-20-2010
20110073991REDOX CAPACITOR AND MANUFACTURING METHOD THEREOF - To provide a redox capacitor that can be used at room temperature and a manufacturing method thereof. Amorphous semiconductor including hydrogen is used as an electrolyte of a redox capacitor. As a typical example of the amorphous semiconductor including hydrogen, an amorphous semiconductor including a semiconductor element such as amorphous silicon, amorphous silicon germanium, or amorphous germanium can be used. As another example of the amorphous semiconductor including hydrogen, oxide semiconductor including hydrogen can be used. As typical examples of the oxide semiconductor including hydrogen, an amorphous semiconductor including a single-component oxide semiconductor such as zinc oxide, titanium oxide, nickel oxide, vanadium oxide, and indium oxide can be given. As another example of oxide semiconductor including hydrogen, a multi-component oxide semiconductor such as InMO03-31-2011
20110073993Laminated thin-film device, manufacturing method thereof, and circuit - The present invention provides a novel capacitor element, laminated thin-film device, and circuit wherein the capacitance dependency on voltage can be appropriately adjusted, and a technology for manufacturing such a capacitor element and laminated thin-film device. In the capacitor element that comprises a pair of electrode layers and a dielectric layer disposed between the electrode layers, a well region where an ion is implanted is disposed in the dielectric layer, and the C-V curve between the electrode layers is shifted or shifted and expanded in at least one direction of the plus direction and minus direction with respect to the voltage axis.03-31-2011
20110073992MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A first interlayer dielectric is formed over a substrate, and an electric conductor pillar is formed in the first interlayer dielectric. A damascene wiring part insulating film is formed over an upper surface of the first interlayer dielectric. The damascene wiring part insulating film above the electric conductor pillar is removed to form an opening part for capacitance, and an insulating film for capacitive element is formed over the upper surface of the first interlayer dielectric. The insulating film for capacitive element and the first interlayer dielectric above the electric conductor pillar are removed to form a trench for wiring. Metal bodies are embedded in the opening part for capacitance and the trench for wiring. The metal body in the opening part for capacitance is to be an upper electrode of the capacitive element, and the metal body in the trench for wiring is to be a logic wiring.03-31-2011
20120199945METHOD OF FORMING DEEP TRENCH CAPACITOR - Aspects of the invention provide for methods of forming a deep trench capacitor structure. In one embodiment, aspects of the invention include a method of forming a deep trench capacitor structure, including: forming a deep trench within a semiconductor substrate; depositing a first liner within the deep trench; filling a lower portion of the deep trench with a filler material; depositing a second liner within an upper portion of the deep trench; removing the filler material, such that the lower portion of the deep trench includes only the first liner and the upper portion of the deep trench includes the first liner and the second liner; forming a high doped region around the lower portion of the deep trench; and removing the first liner within the lower portion of the deep trench and the second liner within the upper portion of the deep trench.08-09-2012
20120119329Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) - A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.05-17-2012
20120119328Dielectric Thin Film Element and Method for Producing the Same - A dielectric thin film element that includes a substrate, a close-adhesion layer formed on one principal surface of the substrate, a capacitance section having a lower electrode layer formed on the close-adhesion layer, a dielectric layer formed on the lower electrode layer, and an upper electrode layer formed on the dielectric layer, and a protective layer formed to cover the capacitance section, wherein the end of the close-adhesion layer is exposed from the protective layer.05-17-2012
20110018094BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CIRCUIT DEVICE STRUCTURES - A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques01-27-2011
20110254125SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to the present invention is equipped with a plurality of analog macros having comb capacitors (10-20-2011
20110031587SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a lower electrode on a semiconductor substrate, applying a photoresist on the lower electrode, forming an opening in the photoresist spaced from the periphery of the lower electrode, forming a high-dielectric constant film of a high-k material having a dielectric constant of 10 or more, performing liftoff so that the high-dielectric-constant film remains on the lower electrode, and forming an upper electrode on the high-dielectric-constant film remaining after the liftoff.02-10-2011
20100301452Integrated nano-farad capacitors and method of formation - A high value capacitance per unit area capacitor is fabricated on a substrate 12-02-2010
20090001515SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes a capacitor 01-01-2009
20090001513Semiconductor structure - The present invention discloses a structure of a buried word line, which comprises a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer in the U-shape trench, a polysilicon layer on the U-shape gate dielectric layer, a conducting layer on the polysilicon layer, and a cover dielectric layer on the conducting layer. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect.01-01-2009
20090001514METAL INSULATOR METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME - A metal-insulator-metal (MIM) capacitor may include a lower metal layer including a lower metal layer including a first lower metal layer and a second lower metal layer formed on a semiconductor substrate, an upper metal layer including a first upper metal layer and a second upper metal layer formed on the lower metal layer, a capacitor dielectric layer formed between the lower metal layer and the upper metal layer, a first bonding metal layer formed on the upper metal layer and a second bonding metal layer formed on the lower metal layer, a first connection wiring formed between the upper metal layer and the first bonding metal layer for directly connect the upper metal layer to the first bonding metal layer, and a second connection wiring formed between the lower metal layer and the second bonding metal layer for directly connecting the lower metal layer to the second bonding metal layer.01-01-2009
20110037146Capacitors and Methods of Manufacture Thereof - Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device.02-17-2011
20110037145WAFER LEVEL PACKAGE HAVING CYLINDRICAL CAPACITOR AND METHOD OF FABRICATING THE SAME - Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided.02-17-2011
20110037144Method for fabricating a decoupling composite capacitor in a wafer and related structure - According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode.02-17-2011
20110037143Semiconductor Device Using An Aluminum Interconnect To Form Through-Silicon Vias - An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TV to other BEOL interconnects.02-17-2011
20090230510SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A rutile phase can be formed even in the case of a thin film by adding nickel or cobalt to titanium dioxide in the range of 0.5 to 10 atm %, and the use of this element-added titanium dioxide film in a capacitor dielectric film results in an increase in capacitance per unit area of a DRAM memory cell and enables a high-integration DRAM to be realized at low cost.09-17-2009
20120199947METHOD FOR MANUFACTURING AND REOXIDIZING A TIN/TA2O5/TIN CAPACITOR - A method for manufacturing a TiN/Ta2O5/TiN capacitor, including the steps of forming a Ta08-09-2012
20120199948SEMICONDUCTOR CHIP COMPRISING PROTECTION MEANS AGAINST A PHYSICAL ATTACK - A semiconductor chip includes a semiconductor substrate, an integrated circuit region having an integrated circuit, and conductive lines extending above the integrated circuit region. To protect the semiconductor chip against a physical attack, the semiconductor chip includes an array of protection capacitors extending above the conductive lines, at least first and second interconnection conductive lines, arranged to interconnect the protection capacitors in parallel, and a cprotection circuit configured to prevent at least some data from circulating on at least some conductive lines, when a short occurs in at least one protection capacitor.08-09-2012
20120199946SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.08-09-2012
20120199944CAPACITORS INCLUDING A RUTILE TITANIUM DIOXIDE MATERIAL, SEMICONDUCTOR DEVICES INCORPORATING SAME AND RELATED METHODS - Methods of forming a capacitor including forming at least one aperture in a support material, forming a titanium nitride material within the at least one aperture, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The support material may then be removed and the titanium nitride material may be oxidized to form a titanium dioxide material. A second conductive material may then be formed over an outer surface of the titanium dioxide material. Capacitors, semiconductor devices and methods of forming a semiconductor device including the capacitors are also disclosed.08-09-2012
20090160022METHOD OF FABRICATING MIM STRUCTURE CAPACITOR - The present invention relates to a method of fabricating a MIM structure capacitor. The method includes sequentially depositing a nitride film, a Ti film, and a TiN film over a lower electrode metal layer, the nitride film being an insulating layer, and a combination of the Ti/TiN layers being a upper metal electrode, for the MIM structure capacitor. The method further includes coating a photoresist layer on the upper electrode metal layer and patterning the photoresist layer, then selectively etching the upper metal electrode layer, and the nitride film by using the patterned photoresist layer as an etch mask, and finally removing nitride remaining on sidewalls of the MIM structure capacitor through a wet cleaning process.06-25-2009
20090102016DESIGN STRUCTURE INCORPORATING VERTICAL PARALLEL PLATE CAPACITOR STRUCTURES - Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a vertical parallel plate capacitor structure with a first plurality of conductive plates and a second plurality of conductive plates having an overlying relationship with the first plurality of conductive plates. The first plurality of conductive plates are spaced apart by a first distance. The second plurality of conductive plates are spaced apart by a second distance different than the first distance04-23-2009
20080296729SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.12-04-2008
20100244193System-in-Package Having Integrated Passive Devices and Method Therefor - A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.09-30-2010
20100244192DIELECTRIC FILM AND SEMICONDUCTOR DEVICE USING DIELECTRIC FILM - The present invention provides a dielectric film having a high permittivity and a high heat resistance. An embodiment of the present invention is a dielectric film (09-30-2010
20100308435Through Silicon Via With Embedded Decoupling Capacitor - A semiconductor die, having a substrate, includes a through silicon via. The through silicon via includes a decoupling capacitor having a first co-axial conductor, a second co-axial conductor, and a co-axial dielectric separating the first co-axial conductor from the second co-axial conductor. The decoupling capacitor is configured to provide local charge storage for components on the semiconductor die.12-09-2010
20130168811CAPACITOR HAVING MULTI-LAYERED ELECTRODES - The instant disclosure relates to a capacitor having multi-layered electrodes. The capacitor includes a dielectric layer having a first surface and a second surface oppositely arranged, a first electrode formed on the first surface, and a second electrode formed on the second surface. At least one of the first and second electrodes having a low band gap material layer formed on the dielectric layer and a conducting layer formed on the low band gap material layer. The band gap of the low band gap material layer is lower than the band gap of the conducting layer.07-04-2013
20100244191SEMICONDUCTOR DEVICE - A semiconductor device includes an insulation interlayer and an etch stop layer sequentially stacked on a substrate wherein a lower structure including a first contact pad is formed. A second contact pad penetrates the insulation interlayer and the etch stop layer and is connected to the first contact pad. The second contact pad protrudes from the etch stop layer. A pad spacer is provided between the second contact pad and the insulation interlayer. A lower electrode is provided on the etch stop layer and is connected to the second contact pad. A dielectric layer and an upper electrode are sequentially provided on the lower electrode.09-30-2010
20100244190SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device, include a capacitor of a MIM (Metal-Insulator-Metal) structure; and at least one pair of shield parts which sandwich said MIM structure capacitor sandwiched by an insulating film.09-30-2010
20100244189INTEGRATION SUBSTRATE WITH A ULTRA-HIGH-DENSITY CAPACITOR AND A THROUGH-SUBSTRATE VIA - An integration substrate for a system in package comprises a through-substrate via and a trench capacitor wherein with a trench filling that includes at least four electrically conductive capacitor-electrode layers in an alternating arrangement with dielectric layers. —The capacitor-electrode layers are alternatingly connected to a respective one of two capacitor terminals provided on the first or second substrate side. The trench capacitor and the through-substrate via are formed in respective trench openings and via openings in the semiconductor substrate, which have an equal lateral extension exceeding 10 micrometer. This structure allows, among other advantages, a particularly cost-effective fabrication of the integration substrate because the via openings and the trench openings in the substrate can be fabricated simultaneously.09-30-2010
20110254127METHOD AND DEVICE FOR A DRAM CAPACITOR HAVING LOW DEPLETION RATIO - A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.10-20-2011
20080251888Method and Apparatus for Self-Contained Automatic Decoupling Capacitor Switch-Out in Integrated Circuits - An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained. Because of the self-contained nature of the decoupling capacitor circuit, an integrated circuit may contain an array of decoupling capacitor circuits without expenditure of substantial chip real estate for respective decoupling capacitor control lines.10-16-2008
20120032299SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an insulating film over a semiconductor substrate, forming a capacitor including a lower electrode, a capacitor dielectric film including a ferroelectric material, and an upper electrode over the insulating film, forming a first protective insulating film over a side surface and upper surface of the capacitor by a sputtering method, and forming a second protective insulating film over the first protective insulating film by an atomic layer deposition method.02-09-2012
20120146183SEMICONDUCTOR DEVICE - A technology is a semiconductor device and a method of manufacturing the same, capable of preventing characteristics of a storage node from degrading to improve operation characteristics of a device, by connecting an upper electrode of a peripheral circuit area to an active region of the peripheral circuit area and thus making charges generated in a plasma environment to be transferred to the active regions of the peripheral circuit area. The method includes forming a landing contact plug on a semiconductor substrate in a cell area, forming a storage node contact plug connected to the landing contact plug and a dummy contact plug on the semiconductor substrate in a peripheral circuit area, forming a lower electrode connected to the storage node contact plug, and forming an upper electrode on the lower electrode and the dummy contact plug.06-14-2012
20080203529SEMICONDUCTOR DEVICE COMPRISING MULTILAYER DIELECTRIC FILM AND RELATED METHOD - A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film.08-28-2008
20110254128ELECTRODE FOR ENERGY STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - An electrode for an energy storage device with less deterioration due to charge and discharge, and a method for manufacturing thereof are provided. Further, an energy storage device having large capacity and high endurance can be provided. In an electrode of an energy storage device in which an active material is formed over a current collector, the surface of the active material is formed of a crystalline semiconductor film having a {10-20-2011
20100320568SEMICONDUCTOR DEVICE, RF-IC AND MANUFACTURING METHOD OF THE SAME - Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.12-23-2010
20100320566Semiconductor constructions - The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.12-23-2010
20100320567INTEGRATED CIRCUIT COMPRISING A CAPACITOR WITH METAL ELECTRODES AND PROCESS FOR FABRCATING SUCH A CAPACITOR - An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (12-23-2010
20110163415SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises depositing an absorption barrier layer of a dielectric film on a semiconductor substrate including a bottom electrode contact plug so as to separate the dielectric films between capacitors without having any influence of a bias of the adjacent capacitor, thereby improving a refresh characteristic of cells.07-07-2011
20110163416METHODS FOR FORMING SMALL-SCALE CAPACITOR STRUCTURES - The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.07-07-2011
20110254130SEMICONDUCTOR DEVICE INCLUDING METAL-INSULATOR-METAL CAPACITOR ARRANGEMENT - A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.10-20-2011
20100283125Semiconductor device and method of manufacturing the same - The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.11-11-2010
20110108948INTEGRATED DECOUPLING CAPACITOR EMPLOYING CONDUCTIVE THROUGH-SUBSTRATE VIAS - A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.05-12-2011
20110133311SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provided between the plurality of interconnection layers and electrically interconnecting the plurality of the electrode patterns between the interconnection layers adjacent to each other, and an insulating films formed between the plurality of interconnection layers and the plurality of via parts. Each of the plurality of via parts is laid out, offset from a center of the electrode pattern in a second direction intersecting the first direction, and the plurality of electrode patterns has a larger line width at parts where the via parts are connected to, and a distance between the electrode patterns and the adjacent electrode patterns is reduced at the parts.06-09-2011
20100252910SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a conventional semiconductor device, part of a dielectric film of a capacitive element is removed when photoresist is peeled off, and this causes problems of variation in capacitance value of the capacitive element and deterioration of breakdown voltage characteristics. In a semiconductor device according to the present invention, a silicon nitride film serving as a dielectric film is formed on the top face of a lower electrode of a capacitive element, and an upper electrode is formed on the top face of the silicon nitride film. The upper electrode is formed of a laminated structure having a silicon film and a polysilicon film protecting the silicon nitride film. This structure prevents part of the silicon nitride film from being removed when, for example, photoresist is peeled off, thereby preventing variation in capacitance value of the capacitive element and deterioration of the breakdown voltage characteristics.10-07-2010
20100181646SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present invention relates to a semiconductor and manufacturing method thereof, in which a nano tube structure is vertically grown to form a lower electrode of a cell region and a via contact of peripheral circuit region. Therefore, capacitance of the lower electrode is secured without an etching process for high aspect ratio. Also, the via contact can be formed for corresponding to the height of the lower electrode.07-22-2010
20100181644IC PACKAGE WITH CAPACITORS DISPOSED ON AN INTERPOSAL LAYER - An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.07-22-2010
20100181645SEMICONDUCTOR ARRANGEMENT WITH TRENCH CAPACITOR AND METHOD FOR ITS MANUFACTURE - The invention relates to a semiconductor arrangement and method for production thereof, wherein the semiconductor arrangement is provided with an integrated circuit arranged on a substrate. The integrated circuit is structured on the front face of the substrate and at least one capacitor is connected to the integrated circuit, wherein the at least one capacitor is designed as a monolithic deep structure in trenches. The trenches are arranged in at least one first group and at least one second group, the trenches of a group running essentially parallel to each other and the first and second group are at an angle to each other, essentially at right angles to each other.07-22-2010
20100181647SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.07-22-2010
20110254129ELECTRICAL COMPONENTS FOR MICROELECTRONIC DEVICES AND METHODS OF FORMING THE SAME - Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.10-20-2011
20110018096SEMICONDUCTOR DEVICE - A semiconductor device including: multiple layer wirings which are formed above a semiconductor substrate; multiple first electrode type contact plugs which have a granular shape in plane view, extend in a lower direction from the layer wirings to be connected to the layer wirings on an upper side, and serve as a first electrode; multiple second electrode type contact plugs which have a granular shape in plane view, extend in the lower direction from the layer wirings to be connected to the layer wirings on an upper side, and serve as a second electrode different from the first electrode; and a capacitative element section that fauns a capacity between adjacent ones of the first electrode type contact plugs and second electrode type contact plugs. The layer wirings serving as emergence portions of capacity electrodes of the first and second electrode type contact plugs are formed by different layer wirings.01-27-2011
20110133310 INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT - Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).06-09-2011
20110169134CAPACITOR WITH PILLAR TYPE STORAGE NODE AND METHOD FOR FABRICATING THE SAME - A capacitor includes a pillar-type storage node, a supporter disposed entirely within an inner empty crevice of the storage node, a conductive capping layer over the supporter and contacting the storage node so as to seal an entrance to the inner empty crevice, a dielectric layer over the storage node, and a plate node over the dielectric layer.07-14-2011
20110169135SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR STORAGE DEVICE - A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing apart that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.07-14-2011
20110169131DEEP TRENCH DECOUPLING CAPACITOR - Solutions for forming a silicided deep trench decoupling capacitor are disclosed. In one aspect, a semiconductor structure includes a trench capacitor within a silicon substrate, the trench capacitor including: an outer trench extending into the silicon substrate; a dielectric liner layer in contact with the outer trench; a doped polysilicon layer over the dielectric liner layer, the doped polysilicon layer forming an inner trench within the outer trench; and a silicide layer over a portion of the doped polysilicon layer, the silicide layer separating at least a portion of the contact from at least a portion of the doped polysilicon layer; and a contact having a lower surface abutting the trench capacitor, a portion of the lower surface not abutting the silicide layer.07-14-2011
20110169132Semiconductor device and manufacturing method of semiconductor device - A semiconductor device has a capacitor element in which a capacitance dielectric film is disposed between an upper electrode film (upper electrode film, an upper electrode film) and a lower electrode film, and the lower electrode film has polycrystalline titanium nitride at least to a portion in contact with the capacitance dielectric film.07-14-2011
20110169133WIRING SUBSTRATE, METHOD FOR MANUFACTURING WIRING SUBSTRATE, AND SEMICONDUCTOR PACKAGE INCLUDING WIRING SUBSTRATE - A wiring substrate includes a ceramic substrate including plural ceramic layers, an inner wiring, and an electrode electrically connected to the inner wiring, the electrode exposed on a first surface of the ceramic substrate, and a silicon substrate body having a front surface and a back surface situated on an opposite side of the front surface and including a wiring pattern formed on the front surface and a via filling material having one end electrically connected to the wiring pattern and another end exposed at the back surface. The back surface is bonded to the first surface of the ceramic substrate via a polymer layer. The via filling material penetrates through the polymer layer and is directly bonded to the electrode.07-14-2011
20100117197SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided. The method includes: forming a contact plug passing through an inter-layer insulation layer; sequentially forming a lower electrode layer, a dielectric layer and an upper electrode layer on the inter-layer insulation layer; patterning the upper electrode layer; patterning the dielectric layer and the lower electrode layer, thereby obtaining a capacitor including an upper electrode, a patterned dielectric layer and a lower electrode; and sequentially forming a first metal interconnection line connected with the contact plug and second metal interconnection lines connected with the capacitor.05-13-2010
20100117196Support For Vertically-Oriented Capacitors During The Formation of a Semiconductor Device - A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during wafer processing. The structure is particularly useful for supporting the bottom plates during removal of a base dielectric layer to expose the outside of the bottom plates to form a double-sided capacitor. The support structure further supports the bottom plates during formation of a cell dielectric layer, a capacitor top plate, and final supporting dielectric. An inventive structure is also described.05-13-2010
20100117194METAL-INSULATOR-METAL CAPACITORS WITH A CHEMICAL BARRIER LAYER IN A LOWER ELECTRODE - A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.05-13-2010
20100117193SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of capacitor cells having respective lower electrodes to which signals are applied and respective upper electrodes arranged to face the respective lower electrodes, wherein each interconnect connected to a corresponding one of the lower electrodes includes a shield interconnect section enclosing a corresponding one of the upper electrodes.05-13-2010
20110073994TRENCH CAPACITOR AND METHOD FOR PRODUCING THE SAME - A method of fabricating a trench capacitor, and a trench capacitor fabricated thereby, are disclosed. The method involves the use of a vacuum impregnation process for a sol-gel film, to facilitate effective deposition of high-permittivity materials within a trench in a semiconductor substrate, to provide a trench capacitor having a high capacitance whilst being efficient in utilisation of semiconductor real estate.03-31-2011
20110073990Capacitor and Method for Making Same - One or more embodiments relate to a method for making a capacitor such as a trench capacitor. The method includes: providing a substrate; forming an opening within the substrate; forming a sidewall spacer over a sidewall surface of the opening; forming a first conductive layer within the opening after forming the sidewall spacer; removing the sidewall spacer; forming a dielectric layer over the first conductive layer within the opening; and forming a second conductive layer over the dielectric layer within the opening.03-31-2011
20110073989OPTICAL MODULATOR UTILIZING WAFER BONDING TECHNOLOGY - Optical modulator utilizing wafer bonding technology. An embodiment of a method includes etching a silicon on insulator (SOI) wafer to produce a first part of a silicon waveguide structure on a first surface of the SOI wafer, and preparing a second wafer, the second wafer including a layer of crystalline silicon, the second wafer including a first surface of crystalline silicon. The method further includes bonding the first surface of the second wafer with a thin oxide to the first surface of the SOI wafer using a wafer bonding technique, wherein a second part of the silicon waveguide structure is etched in the layer of crystalline silicon.03-31-2011
20110079878FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER - An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.04-07-2011
20110095397Semiconductor Structures Including Dielectric Layers and Capacitors Including Semiconductor Structures - Semiconductor structures including a first conductive layer; a dielectric layer on the first conductive layer; a second conductive layer on the dielectric layer; and a crystallized seed layer in at least one of a first portion between the first conductive layer and the dielectric layer and a second portion between the dielectric layer and the second conductive layer. Related capacitors and methods are also provided herein.04-28-2011
20110095396METHOD AND STRUCTURE FOR SILICON NANOCRYSTAL CAPACITOR DEVICES FOR INTEGRATED CIRCUITS - An improved semiconductor device, including a capacitor structure. The device has a first electrode member, which has a first length and a first width. The device also has a second electrode member, which has a second length and a second width. Additionally, the device includes a capacitor dielectric material provided between the first electrode member and the second electrode member according to a specific embodiment. Depending upon the embodiment, the capacitor dielectric material is made of a suitable material or materials such as Al04-28-2011
20100078762SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film.04-01-2010
20100283123BIPOLAR JUNCTION TRANSISTOR INTEGRATED WITH PIP CAPACITOR AND METHOD FOR MAKING THE SAME - A bipolar junction transistor (BJT) integrated with a PIP capacitor includes a substrate including a bipolarjunction transistor region and a PIP capacitor region, a bipolar junction transistor disposed in the bipolar junction transistor region and extending an isolation layer to the PIP capacitor region and a base poly layer disposed on the isolation layer, and a PIP capacitor disposed in the PIP capacitor region and including a lower poly layer, the isolation layer and the base poly layer to selectively form a PIP capacitor.11-11-2010
20090230509FINGER CAPACITOR STRUCTURES - A capacitive structure formed in an Integrated Circuit (IC) includes a plurality of capacitor node conductor pairs, each including a first node conductor having a base portion and a plurality of finger portions and a second node conductor having a base portion and a plurality of finger portions that are inter digitized with the plurality of finger portions of the first node conductor. Dielectric is horizontally disposed between the first node conductor and the second node conductor. At least one dielectric layer vertically separates adjacent metal layers, each dielectric layer including dielectric disposed between the adjacent metal layers, a plurality of first node vias vertically connecting finger portions of first node conductors of the adjacent metal layers, and a plurality of second node vias vertically connecting finger portions of the second node conductors of the adjacent metal layers. The plurality of first node vias and plurality of second node vias have staggered spacing to preclude laterally adjacent first node vias and second node vias.09-17-2009
20080217737SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.09-11-2008
20110186964METHODS OF FORMING INTEGRATED CIRCUIT DEVICES - The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions.08-04-2011
20110260289Semiconductor device and bypass capacitor module - A semiconductor device includes an Si substrate having a first surface provided with semiconductor elements, such as a CMOS transistor and a diode, and a second surface opposite to the first surface. On one of the first and the second surfaces, a bypass capacitor is formed. The bypass capacitor includes a Vcc power supply layer and a GND layer which serve to supply a power supply voltage to the semiconductor element, and a high dielectric constant layer sandwiched between the Vcc power supply layer and the GND layer.10-27-2011
20110260288SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a method for manufacturing a semiconductor device comprising: a process of forming a first trench 10-27-2011
20110147891CAPACITOR AND A METHOD OF MANUFACTURING THE SAME - A capacitor (06-23-2011
20110147889SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating film over a silicon substrate, the insulating film having an opening and a contact plug in the opening, the contact plug having a first top that is lower than an upper face of the insulating film.06-23-2011
20100025817METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.02-04-2010
20100025816Semiconductor device - A width of a region where each of the N wells is in contact with the buried P well is not more than 2 μm. A ground voltage and a power supply voltage are applied to the P well and the N well, respectively. A decoupling capacitor is formed between the N well and the buried P well.02-04-2010
20100025815SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a metallic compound Hf02-04-2010
20100025813STRUCTURE FOR DUAL CONTACT TRENCH CAPACITOR AND STRUCTURE THEROF - A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.02-04-2010
20100019349METHOD FOR FABRICATING CONDUCTING PLATES FOR A HIGH-Q MIM CAPACITOR - A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process.01-28-2010
20100019348SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.01-28-2010
20090065895MIM capacitor high-k dielectric for increased capacitance density - According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlN03-12-2009
20080315358Capacitive element, method of manufacture of the same, and semiconductor device - A capacitive element is characterized by including: a base (12-25-2008
20120146184TWO TERMINAL MEMCAPACITOR DEVICE - A memcapacitor device includes a memcapacitive matrix interposed between a first electrode and a second electrode. The memcapacitive matrix includes deep level dopants having a first decay time constant and shallow level dopants having a second decay time constant. The second decay time constant is substantially shorter than the first decay time constant. The capacitance of the memcapacitor device depends upon an initial voltage applied across the memcapacitive matrix and a time dependent change in capacitance of the memcapacitor device depends upon the first decay time constant. A method for forming a memcapacitive device is also provided.06-14-2012
20090121316Electronic Component with Reactive Barrier and Hermetic Passivation Layer - An electronic component is provided on a substrate. A thin-film capacitor is attached to the substrate, the thin-film capacitor includes a pyrochlore or perovskite dielectric layer between a plurality of electrode layers, the electrode layers being formed from a conductive thin-film material. A reactive barrier layer is deposited over the thin-film capacitor. The reactive barrier layer includes an oxide having an element with more than one valence state, wherein the element with more than one valence state has a molar ratio of the molar amount of the element that is in its highest valence state to its total molar amount in the barrier of 50% to 100%. Optionally layers of other materials may intervene between the capacitor and reactive barrier layer. The reactive barrier layer may be paraelectric and the electronic component may be a tunable capacitor.05-14-2009
20090108401SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a semiconductor chip. The semiconductor chip includes a first electrode of a capacitor. An insulating layer is arranged on top of the first electrode. A second electrode of the capacitor is applied over the insulating layer, wherein the second electrode is made of a conductive layer arranged over the semiconductor chip.04-30-2009
20090174031DRAM HAVING DEEP TRENCH CAPACITORS WITH LIGHTLY DOPED BURIED PLATES - By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.07-09-2009
20090032904ORIENTATION-INDEPENDENT MULTI-LAYER BEOL CAPACITOR - A plurality of interdigitized conductive fingers are arranged to form a substantially square configuration in each of a plurality of layers separated by a high dielectric constant material, wherein each of the plurality of interdigitized conductive fingers includes at least one bend of substantially ninety degrees. The plurality of interdigitized conductive fingers includes a first set of fingers that are connected to an anode terminal, and a second set of fingers that are connected to a cathode terminal. The plurality of layers includes a bottommost layer that is in closest proximity to a substrate relative to other layers of the plurality of layers. The bottommost layer does not include any fingers connected to the anode terminal.02-05-2009
20090001512Providing a moat capacitance - In one embodiment, the present invention includes an apparatus having core logic formed on a die, input/output (IO) buffers surrounding the core logic, and a moat capacitance surrounding the IO buffers and extending to an edge of the die. Other embodiments are described and claimed.01-01-2009
20100155889CAPACITOR AND METHOD FOR FABRICATING THE SAME - A capacitor includes a lower electrode; a dielectric layer formed on a predetermined portion of the lower electrode; an upper electrode formed on the dielectric layer; a hard mask pattern formed on the upper electrode; and an isolation layer having a shape of a spacer, formed on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer.06-24-2010
20090278232RUTHENIUM SILICIDE DIFFUSION BARRIER LAYERS AND METHODS OF FORMING SAME - A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSi11-12-2009
20120098090HIGH-EFFICIENCY POWER CONVERTERS WITH INTEGRATED CAPACITORS - A power converter device comprises a substrate, a power die mounted on the substrate, and a capacitor die mounted over the power die in a stacked configuration. The capacitor die is electrically coupled to the power die. A packaging material encapsulates the power die and the capacitor die. An integrated circuit die can also be mounted to the substrate and electrically coupled to the power die to receive power signals from the power die, with the packaging material also encapsulating the integrated circuit die.04-26-2012
20120146185SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.06-14-2012
20120205779SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METAL CONTACTS, AND METHODS OF FABRICATING THE SAME - Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. Related devices are also provided.08-16-2012
20120306051SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTORING THE SAME - In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.12-06-2012
20120306050METHOD FOR IMPROVING PROMPT DOSE RADIATION RESPONSE OF MIXED-SIGNAL INTEGRATED CIRCUITS - A system and method for improving the prompt dose radiation response of mixed-signal integrated circuits is disclosed. An internal analog circuit inside a mixed-signal integrated circuit generates an internal analog reference voltage that has been used for various purposes in the integrated circuit. At least one external capacitor is added either internal or external to a device package of the integrated circuit. The external capacitor reduces any change in the internal reference voltage due to prompt dose radiation by stabilizing the internal reference voltage and thus improves prompt dose radiation response of mixed-signal integrated circuits. A much greater value of capacitance may be provided without increase in dielectric rupture suceptability or decrease in manufacturing yield which may be associated with added on-chip capacitance. This increased capacitance primarily reduce the amount of disturbance caused to the internal node during a prompt dose radiation event.12-06-2012
20120306049METAL TRENCH CAPACITOR AND IMPROVED ISOLATION AND METHODS OF MANUFACTURE - A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.12-06-2012
20100001370INTEGRATED CIRCUIT SYSTEM EMPLOYING ALTERNATING CONDUCTIVE LAYERS - An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.01-07-2010
20110316119SEMICONDUCTOR PACKAGE HAVING DE-COUPLING CAPACITOR - Provided is a semiconductor package including a de-coupling capacitor. The semiconductor package includes a substrate, on an upper surface of which a semiconductor chip is mounted; a plurality of first conductive bumps that are disposed on a lower surface of the substrate and that electrically connect the substrate to an external device; and a de-coupling capacitor that is disposed on the lower surface of the substrate and includes an electrode portion and at least one dielectric layer, wherein the electrode portion of the de-coupling capacitor includes second conductive bumps that electrically connect the substrate to an external device.12-29-2011
20120043642Semiconductor device - A semiconductor device includes a first signal wiring, a first dummy wiring, and a second dummy wiring. The first signal wiring is configured to be supplied with a first signal potential. The first dummy wiring is insulated from the first wiring. The first dummy wiring is configured to be supplied with a fixed potential. The second dummy wiring is disposed between the first signal wiring and the first dummy wiring. The second dummy wiring is insulated from the first dummy wiring. The second dummy wiring is configured to be supplied with substantially the same potential as the first signal potential.02-23-2012
20110101499SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating a semiconductor device are provided. The method for fabricating a semiconductor device includes forming an isolation layer over a semiconductor substrate defining first and second regions, etching the isolation layer at an edge of the first region to form a guard ring pattern, forming a buried guard ring filling the guard ring pattern, selectively etching the isolation layer of the first region to form a plurality of patterns, forming a plurality of conductive patterns in the respective patterns, and completely removing the isolation layer of the first region through a dip-out process.05-05-2011
20120104550HIGH ASPECT RATIO CONTACTS - A contact formed in accordance with a process for etching a insulating material to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating material to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening having an aspect ratio of less than 15:1. Secondly, the insulating material is exposed to a first plasma of a first gaseous etchant having at least fifty percent helium (He) to etch the opening having an aspect ratio of at least 15:1, thereby increasing the aspect ratio to greater than 15:1,05-03-2012
20120001299Semiconductor Constructions - Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.01-05-2012
20110156206SEMICONDUCTOR DEVICE EMPLOYING NITRIDE FLOATING CAPACITOR (NFC) - A semiconductor device includes: a substrate configured to include cell regions and a peripheral region around the cell regions; storage nodes arranged in each of the cell regions; a first support pattern configured in each cell region to support the storage nodes; and a second support pattern configured in the peripheral region to couple first support patterns to each other.06-30-2011
20110156208SEMICONDUCTOR DEVICE - The present invention provides a technology capable of providing a semiconductor device having an MIM structure capacitor with improved reliability. The capacitor has a lower electrode, a capacitor insulating film, and an upper electrode. The lower electrode is comprised of a metal film embedded in an electrode groove formed in an insulating film over the main surface of a semiconductor substrate; and the upper electrode is comprised of a film stack of a TiN film (lower metal film) and a Ti film (cap metal film) formed over the TiN film (lower metal film).06-30-2011
20120056302SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.03-08-2012
20120056301STACK CAPACITOR OF MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.03-08-2012
20120056298Semiconductor Device - A semiconductor device includes a first power supply terminal, a second power supply terminal, and first and second capacitors. The first power supply terminal is configured to be supplied with a first electrical potential. The second power supply terminal is configured to be supplied with a second electrical potential. The second electrical potential is different from the first electrical potential. The first and second capacitors are coupled in series between the first and second power supply terminals.03-08-2012
20120056300SEMICONDUCTOR DEVICE AND FABRICATING METHOD OF THE SAME - Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 μm.03-08-2012
20120007215ON-CHIP CAPACITOR STRUCTURE - At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.01-12-2012
20120007214INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.01-12-2012
20100065943METHOD FOR INCLUDING DECOUPLING CAPACITORS INTO SEMICONDUCTOR CIRCUIT HAVING LOGIC CIRCUIT THEREIN AND SEMICONDUCTOR CIRCUIT THEREOF - A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor.03-18-2010
20120012980SEMICONDUCTOR CAPACITOR - A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor.01-19-2012
20120012979SEMICONDUCTOR CAPACITOR - An improved semiconductor capacitor and method of fabrication is disclosed. A nitride stack, comprising alternating sublayers of slow-etch and fast-etch nitride is deposited on a substrate. The nitride stack is etched via an anisotropic etch technique such as reactive ion etch. A wet etch then etches the nitride stack, forming a corrugated shape. The corrugated shape increases surface area, and hence increases the capacitance of the capacitor.01-19-2012
20110049675METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device includes a capacitor provided above a substrate including electrodes and a ferroelectric film provided therebetween, a pad electrode electrically connected to one of the electrodes of the capacitor, the pad electrode being formed above the substrate, the pad electrode having a recess on a surface of the substrate, a protective film covering a part of the pad electrode other than the recess on the exposed surface, and a hydrogen absorbing film on the protective film and the recess of the pad electrode.03-03-2011
20110049674INTERDIGITATED VERTICAL PARALLEL CAPACITOR - An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.03-03-2011
20110049673Nanopillar Decoupling Capacitor - Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.03-03-2011
20090102015Integrated Circuit, Memory Cell Array, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit includes a plurality of resistivity changing memory cells, each memory cell including a top electrode, a bottom electrode and resistivity changing material being disposed between the top electrode and the bottom electrode. The top electrodes together form a continuous common first electrode. Alternatively, a first continuous common electrode which is electrically connected to all top electrodes is disposed above the top electrodes. A second electrode connectable to a fixed potential is disposed above the first electrode such that the first electrode and the second electrode together form a capacitor.04-23-2009
20120112314Low Cost Metal-Insulator-Metal Capacitors - A device includes a top metal layer over a substrate; a copper-containing metal feature in the top metal layer; a passivation layer over the top metal layer; and a capacitor. The capacitor includes a bottom electrode including at least a portion in the first passivation layer, wherein the bottom electrode includes aluminum; an insulator over the bottom electrode; and a top electrode over the insulator.05-10-2012
20120153435ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED GROUND OR POWER DISTRIBUTION - A microelectronic assembly includes a dielectric element having at least one aperture and electrically conductive elements thereon including terminals exposed at the second surface of the dielectric element; a first microelectronic element having a rear surface and a front surface facing the dielectric element, the first microelectronic element having a plurality of contacts exposed at the front surface thereof; a second microelectronic element having a rear surface and a front surface facing the rear surface of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at the front surface and projecting beyond an edge of the first microelectronic element; and an electrically conductive plane attached to the dielectric element and at least partially positioned between the first and second apertures, the electrically conductive plane being electrically connected with one or more of the contacts of at least one of the first or second microelectronic elements.06-21-2012
20120153434METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY - Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.06-21-2012
20120153436SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM USING THE SAME - Capacitance blocks (first block and second block) respectively formed on two different adjacent common pad electrodes are electrically connected in series through an upper electrode. A distance between two adjacent capacitance blocks connected in series through an upper electrode film for the upper electrode corresponds to a distance between opposing lower electrodes disposed in an outermost perimeter of each capacitance block, and is two or less times than a total film thickness of the upper electrode film embedded between the two adjacent capacitance blocks.06-21-2012
20120025348SEMICONDUCTOR DEVICE COMPRISING A PASSIVE COMPONENT OF CAPACITORS AND PROCESS FOR FABRICATION - A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.02-02-2012
20120061800CAPACITOR ELEMENT, MANUFACTURING METHOD THEREOF AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first capacitive insulating film, a first electrode, and a first barrier film. The first electrode has a first surface containing nitrogen. The first barrier film is between the first capacitive insulating film and the first electrode. The first barrier film faces the first surface of the first electrode. The first barrier film includes zinc oxide. The first barrier film is conductive.03-15-2012
20120061799Yttrium and Titanium High-K Dielectric Films - This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.03-15-2012
20100117195CAPACITOR INTEGRATION AT TOP-METAL LEVEL WITH A PROTECTIVE CLADDING FOR COPPER SURFACE PROTECTION - An on-chip decoupling capacitor (05-13-2010
20100096726METAL CAPACITOR AND METHOD OF MAKING THE SAME - A method of making a metal capacitor includes the following steps. A dielectric layer having a metal interconnection and a capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the metal interconnection and the dielectric layer can be prevented.04-22-2010
20110079879Semiconductor Devices Including Capacitor Support Pads - A semiconductor device may include a semiconductor substrate and a plurality of first capacitor electrodes arranged in a plurality of parallel lines on the semiconductor substrate with each of the first capacitor electrodes extending away from the semiconductor substrate. A plurality of capacitor support pads may be provided with each capacitor support pad being connected to first capacitor electrodes of at least two adjacent parallel lines of the first capacitor electrodes and with adjacent capacitor support pads being spaced apart. A dielectric layer may be provided on each of the first capacitor electrodes, and a second capacitor electrode may be provided on the dielectric layer so that the dielectric layer is between the second capacitor electrode and each of the first capacitor electrodes. Related methods are also discussed.04-07-2011
20110079877MOUNTING CIRCUIT SUBSTRATE - A semiconductor package containing a field effect transistor (FET) used in a high frequency band includes a mounting circuit substrate on which the semiconductor device is mounted. The mounting circuit substrate has a gate wiring conductor, a drain wiring conductor, and a source wiring conductor, which are connected to the gate electrode, the drain electrode, and the source electrode, respectively, of the semiconductor device. The gate wiring conductor and the drain wiring conductor extend toward each other so that their adjacent or facing ends are in close proximity to each other, thereby increasing the capacitance between the gate wiring conductor and the drain wiring conductor.04-07-2011
20120112317INTEGRATED CIRCUIT CAPACITORS HAVING SIDEWALL SUPPORTS - In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.05-10-2012
20090134493Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a MIM capacitor, and having excellent waterproof property and antioxidant property even when being formed between wiring layers. The semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first wiring layer embedded in the first insulating film, a wiring cap film for covering the first wiring layer, the MIM capacitor formed on the wiring cap film, a hydrogen barrier film for covering the MIM capacitor, a second insulating film formed on the hydrogen barrier film, conductive plugs passing through the second insulating film and the hydrogen barrier film, one of which being connected to an upper electrode of the MIM capacitor and the other of which being connected to a lower electrode of the MIM capacitor, and a second wiring layer connected to the conductive plugs, and the upper and lower electrodes of the MIM capacitor.05-28-2009
20090134492METHODS AND DEVICES FOR FABRICATING TRI-LAYER BEAMS - Methods and devices for fabricating tri-layer beams are provided. In particular, disclosed are methods and structures that can be used for fabricating multilayer structures through the deposition and patterning of at least an insulation layer, a first metal layer, a beam oxide layer, a second metal layer, and an insulation balance layer.05-28-2009
20090134491Semiconductor Constructions, Methods of Forming Capacitors, And Methods of Forming DRAM Arrays - Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.05-28-2009
20120119326CAPACITOR AND SEMICONDUCTOR DEVICE - A capacitor includes first electrode patterns and second electrode patterns disposed alternately on a plane, each of the first electrode patterns having a linear shape and extending in a first direction from a first end to a third end with a first length, each of the second electrodes having a linear shape and extending in said first direction from a second end to a fourth end with a second length shorter than the first length, a first wiring pattern supplying a first voltage to the first electrode patterns by first via-plugs, and a second wiring pattern supplying a second voltage to the second electrode patterns by second via-plugs, wherein the first end of the first electrode pattern extends beyond the second end of the second electrode pattern and the third end of the first electrode pattern extends beyond the fourth end of said the electrode.05-17-2012
20110089531Interposer Based Monolithic Microwave Integrate Circuit (iMMIC) - A system is disclosed for IC fabrication, including seating an integrated circuit (“IC”) having at least one contact into a recess of a silicon interposer substrate, applying an insulator in liquid form to fill portions of the recess not otherwise occupied by the IC and to cover a top surface of the IC and the silicon interposer substrate, introducing the insulator to a ramped environmental temperature, holding the environmental temperature at a reflow temperature to reflow the insulator and ramping down the environmental temperature to cure the insulator.04-21-2011
20120161281METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING PEELING OF LOWER ELECTRODE OF CAPACITOR - A method of manufacturing a semiconductor device includes: forming a core insulating film that includes first openings, on a semiconductor substrate; forming cylindrical lower electrodes that cover sides of the first openings with a conductive film; forming a support film that covers at least an upper surface of the core insulating film between the lower electrodes; forming a mask film in which an outside of a region where at least the lower electrodes are formed is removed, by using the support film; and performing isotropic etching on the core insulating film so as to leave the core insulating film at a part of an area between the lower electrodes, after the mask film is formed.06-28-2012
20120161282Method for Forming a Ruthenium Film - Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.06-28-2012
20120211868ULTRA-LOW VOLTAGE COEFFICIENT CAPACITORS - A capacitor has first and second conducting plates and a dielectric region between the plates, wherein the dielectric region comprises two dielectric materials for each of which the variation of capacitance with voltage can be approximated by a polynomial having a linear coefficient and a quadratic coefficient, and wherein the quadratic coefficients of the two dielectric materials are of opposite sign. The capacitor comprises for example a first capacitor (08-23-2012
20120211867SIDE-MOUNTED CONTROLLER AND METHODS FOR MAKING THE SAME - A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a vertical surface of the stack, as opposed to a top surface or adjacent of the stack to reduce the volume of the NVM package.08-23-2012
20120211866METAL-INSULATOR-METAL CAPACITOR AND A METHOD OF FABRICATING THE SAME - A metal-insulator-metal (MIM) capacitor and a method of fabricating the same. The MIM capacitor is in a memory area of a wafer and comprises a top electrode formed from the same metal layer as a point contact to a via in the logic area of the wafer. The method of fabricating the MIM capacitor in a memory area of a wafer comprises forming a point contact to a via in a logic area of the wafer from the same metal layer as a top electrode of the MIM capacitor.08-23-2012
20120211865DEEP TRENCH CAPACITOR WITH CONFORMALLY-DEPOSITED CONDUCTIVE LAYERS HAVING COMPRESSIVE STRESS - A high density deep trench MIM capacitor structure is provided wherein conductive-compressive-conformally applied layers of a semiconductor material, such as a Poly-Si08-23-2012
20120313218FERROELECTRIC CAPACITOR - A ferroelectric capacitor includes a ferroelectric film, a lower electrode in contact with one surface of the ferroelectric film, and an upper electrode in contact with the other surface of the ferroelectric film. At least one of the upper electrode and the lower electrode has a stacked electrode structure in which one or more oxide conductive layers and one or more metal layers are stacked alternately, and the stacked electrode structure includes at least one of two or more oxide conductive layers and two or more metal layers.12-13-2012
20100289119INTEGRATED CAPACITOR - According to the preferred embodiment, an integrated capacitor having a key-shaped structure is provided. The integrated capacitor comprises a first pair of key-shaped metal patterns and a second pair of key-shaped metal patterns. The first pair of key-shaped metal patterns engages with the second pair of key-shaped metal patterns, and a dielectric layer is situated therebetween.11-18-2010
20120126369Semiconductor Device and Method of Forming Passive Devices - A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump.05-24-2012
20100224961PASSIVATION OF INTEGRATED CIRCUITS CONTAINING FERROELECTRIC CAPACITORS AND HYDROGEN BARRIERS - An integrated circuit that includes a logic region, a buffer region, and a ferroelectric capacitor region that contains ferroelectric capacitors. The integrated circuit also includes a hydrogen diffusion barrier film that overlies ferroelectric capacitors and also overlies a buffer region located between a ferroelectric capacitor region and a logic region. However, the hydrogen diffusion barrier film is removed from a portion of the logic region. Moreover, a method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.09-09-2010
20110001217ULTRA HIGH DENSITY CAPACITY COMPRISING PILLAR-SHAPED CAPACITORS FORMED ON BOTH SIDES OF A SUBSTRATE - The present invention describes an ultra High-Density Capacitor design, integrated in a semiconductor substrate, preferably a Si substrate, by using both wafer sides. The capacitors are pillar-shaped and comprise electrodes (01-06-2011
20120161283SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having a 6F06-28-2012
20100207240SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked therein, the stacked body including a staircase structure having the plurality of conductive layers processed into a staircase shape; an interlayer dielectric layer covering the staircase structure; and a contact electrode provided inside a contact hole penetrating through the interlayer dielectric layer, the contact hole penetrating through one of the staircase-shaped conductive layers, the contact electrode being in contact with a sidewall portion of the one of the staircase-shaped conductive layers exposed into the contact hole.08-19-2010
20100207247Semiconductor Integrated Circuit Device and Method of Fabricating the Same - A semiconductor integrated circuit device includes a lower electrode formed on a substrate, a first dielectric layer formed of a metal nitride layer, a metal oxynitride layer, or a combination thereof, on the lower electrode, a second dielectric layer formed on the first dielectric layer that includes a zirconium oxide layer, and an upper electrode formed on the second dielectric layer.08-19-2010
20100207245HIGHLY SCALABLE TRENCH CAPACITOR - An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.08-19-2010
20120133022METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE - Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.05-31-2012
20120133021SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA, AND FABRICATION METHOD - A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.05-31-2012
20120133020SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR AND AN ELECTRICAL CONNECTION VIA AND FABRICATION METHOD - A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.05-31-2012
20120313217SEAL RING STRUCTURE WITH CAPACITOR - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate of a conductivity type having a chip region enclosed by a seal ring region. An insulating layer is on the semiconductor substrate. A seal ring structure is embedded in the insulating layer corresponding to the seal ring region. A capacitor is disposed under the seal ring structure and is electrically connected thereto, wherein the capacitor includes a body of the semiconductor substrate.12-13-2012
20120313219CHIP PACKAGE STRUCTURE AND METHOD OF MAKING THE SAME - Methods and structures related to packaging a chip are disclosed. In one embodiment, a chip package structure includes: (i) a chip having a plurality of first and second contact pads thereon; (ii) a lead frame having a plurality of pins for external connection to the package structure, where the chip is disposed on the lead frame; (iii) a plurality of first bonding wires for connecting the first contact pads to the lead frame; and (iv) a plurality of second bonding wires for connecting the second contact pads to the plurality of pins on the lead frame.12-13-2012
20110180899SEMICONDUCTOR DEVICE - A semiconductor device has a package structure provided with leads that are external connection terminals. A base substance is an island, and at least the surface thereof is formed of a conductive material. A semiconductor substrate is mounted on the surface of the base substance, and a ground potential is supplied from the surface of the base substance. A shunt capacitor is provided with an electrode pair of a first electrode and a second electrode formed in parallel, and mounted with the first electrode being electrically connected to the surface of the base substance. An internal bonding wire connects a pad provided on the semiconductor substrate for external connection, to the second electrode of the shunt capacitor. The lead is the external connection terminal of the semiconductor device. An external bonding wire connects the lead to the second electrode of the shunt capacitor.07-28-2011
20110180898SEMICONDUCTOR DEVICE - According to the embodiments, a core block is formed on a semiconductor chip, and is constructed of an integrated circuit that can operate independently. A power-supply switch is formed on the semiconductor chip, and connects or disconnects the core block to or from a power line. A capacitor is formed on the semiconductor chip, and is connected to the power line in parallel to the core block. A selection switch is formed on the semiconductor chip, and connects or disconnects the capacitor to or from the power line.07-28-2011
20120133023THREE DIMENSIONAL INTEGRATED DEEP TRENCH DECOUPLING CAPACITORS - A method of forming an integrated circuit device includes forming a plurality of deep trench decoupling capacitors on a first substrate; forming a plurality of active circuit devices on a second substrate; bonding the second substrate to the first substrate; and forming electrical connections between the deep trench capacitors and the second substrate.05-31-2012
20120161280CAPACITOR WITH RECESSED PLATE PORTION FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND METHOD TO FORM THE SAME - A capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the first metal plate. A portion of the first metal plate directly adjacent to the second dielectric layer is recessed relative to the sidewalls of the second dielectric layer. A second metal plate is disposed on and conformal with the second dielectric layer. A portion of the second metal plate directly adjacent to the second dielectric layer is recessed relative to the sidewalls of the second dielectric layer. A third dielectric layer is disposed above the first metal plate, the second dielectric layer, and the second metal plate, and disposed between the first metal plate and the second dielectric layer and between the second metal plate and the second dielectric layer.06-28-2012
20090014834Contact plug structure - A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep trench capacitor arranged in an S-shape manner with respect to the contact plug structure via a doped region isolated by a shallow trench isolation structure. Preferably, the body portion and the two leg portions can be made of the same conductive material selected from the group consisting of polysilicon, doped polysilicon, tungsten, copper and aluminum, while the dielectric block can be made of material selected from the group consisting of borophosphosilicate glass. Particularly, the contact plug can be prepared by dual-damascene technique. Since the overlapped area between the contact plug structure and a word line can be dramatically decreased, the bit line coupling (BLC) can be effectively reduced.01-15-2009
20090057829SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING THE SAME - A semiconductor device includes a first wiring layer, a second wiring layer and an insulating layer provided between the first wiring layer and the second wiring layer. A capacitor has a first electrode formed on the first wiring layer and a second electrode formed on the second wiring layer in such a manner that the second electrode overlaps with the first electrode. To the first electrode, two connection wirings are connected and, to the second electrode, two connection wirings are connected. The two connection wirings are connected to each other with low DC impedance substantially only through the first electrode. Similarly, the two connection wirings are connected to each other with low DC impedance substantially only through the second electrode.03-05-2009
20090057828METAL-INSULATOR-METAL CAPACITOR AND METHOD FOR MANUFACTURING THE SAME - A metal-insulator-metal (MIM) capacitor having fast frequency characteristics and a method for manufacturing the same are disclosed. The disclosed MIM capacitor may include a first intermetal insulating film, a lower metal layer formed over the first intermetal insulating film, a second intermetal insulating film formed around the lower metal layer, and a third intermetal insulating film formed over the lower metal layer. A first-capacitor lower metal layer, a first-capacitor insulating film, a first-capacitor upper metal layer, and a first capping layer may be sequentially formed over a portion of the third intermetal insulating film. A first interlayer insulating film, a fourth intermetal insulating film, and a second interlayer insulating film may be sequentially formed over the third intermetal insulating film including the first capping layer. A second-capacitor lower metal layer may extend through the second interlayer insulating film and the first capping layer such that the second-capacitor lower metal layer is connected to the first-capacitor upper metal layer. A first passivation film may be formed over the second-capacitor lower metal layer. A second-capacitor upper metal layer may be formed over a portion of the first passivation film and extending through the first passivation film in a region where the second-capacitor lower metal layer is arranged such that the second-capacitor upper metal layer is connected to the second-capacitor lower metal layer. Second to fourth passivation films may be sequentially formed over the first passivation film including the second-capacitor upper metal layer.03-05-2009
20090057827CAPACITOR EMBEDDED IN INTERPOSER, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING CAPACITOR EMBEDDED IN INTERPOSER - As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).03-05-2009
20090057826Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a capacitor plate includes a first propeller-shaped portion and a second propeller-shaped portion. A via portion is disposed between the first propeller-shaped portion and the second propeller-shaped portion.03-05-2009
20120168903Semiconductor Constructions Containing Tubular Capacitor Storage Nodes, And Retaining Structures Along Portions Of The Tubular Capacitor Storage Nodes - The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.07-05-2012
20120168904Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System - Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.07-05-2012
20120168902METHOD FOR FABRICATING A CAPACITOR AND CAPACITOR STRUCTURE THEREOF - A method for fabricating a capacitor includes providing a substrate having a first surface and a second surface, and forming a plurality of openings in the substrate, the openings are separated from each other by a shape of the substrate, each opening having sidewalls and a bottom. The method further includes submitting the substrate including the openings to an oxidation process to form an oxide layer covering the sidewalls and the bottom of the openings, and a portion of a surface of the substrate, wherein a shape of the substrate disposed between a pair of two adjacent openings is completely oxidized to form an insulation layer between the pair of two adjacent openings; and depositing a conductive material layer over the oxide layer in the openings such that the conductive material layer is electrically continuous and such that the pair of adjacent openings form a capacitor.07-05-2012
20100059858Integrated capacitors in package-level structures, processes of making same, and systems containing same - An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.03-11-2010
20100052098Semiconductor device having storage electrode and manufacturing method thereof - A semiconductor device includes a first storage electrode, a second storage electrode, a first landing pad, a capacitive insulating film, and a plate electrode. The second storage electrode is arranged above the first storage electrode. The first landing pad is arranged between a top surface of the first storage electrode and a bottom surface of the second storage electrode. The first landing pad connects the first storage electrode and the second storage electrode. The first landing pad has a first landing surface larger than the bottom surface of the second storage electrode. The second storage electrode is placed on the first landing surface. The capacitive insulating film is laminated on the first and second storage electrodes and on an outer circumferential surface of the first landing pad. The plate electrode contacts the capacitive insulating film.03-04-2010
20100019347Under Bump Metallization for On-Die Capacitor - Various on-chip capacitors and methods of making the same are disclosed. In one aspect, a method of manufacturing a capacitor is provided that includes forming a first conductor structure on a semiconductor chip and forming a passivation structure on the first conductor structure. An under bump metallization structure is formed on the passivation structure. The under bump metallization structure overlaps at least a portion of the first conductor structure to provide a capacitor.01-28-2010
20120119327CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR - A capacitor in a semiconductor memory device comprises a lower electrode on a substrate that is formed of a conductive metal oxide having a rutile crystalline structure, a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and includes impurities for reducing a leakage current, and an upper electrode on the titanium oxide dielectric layer. A method of forming a capacitor in a semiconductor device comprise steps of forming a lower electrode on a substrate that includes a conductive metal oxide having a rutile crystalline structure, forming a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and impurities for reducing a leakage current, and forming an upper electrode on the titanium oxide dielectric layer.05-17-2012
20090065897SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A M-I-M capacitor semiconductor device capable of enhancing the reliability and capacitance of a capacitor and maximizing the integration density of the device, and a method of fabricating the same are disclosed. The semiconductor device includes a semiconductor substrate, a capacitor lower metal layer formed over the semiconductor substrate, a SiN capacitor dielectric layer having a thickness of approximately 30 nm or less formed over the capacitor lower metal layer, and a capacitor upper metal layer formed over a portion of the capacitor dielectric layer and overlapping with the capacitor lower metal layer.03-12-2009
20090127656Dielectric relaxation memory - A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.05-21-2009
20090051006N CELL HEIGHT DECOUPLING CIRCUIT - A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.02-26-2009
20120175736SEMICONDUCTOR DEVICE - A substrate is provided with a first wiring layer 07-12-2012
20120175735Semiconductor Device and Method of Forming IPD on Molded Substrate - A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.07-12-2012
20090096063Semiconductor apparatus with decoupling capacitor - A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.04-16-2009
20120175734SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics. The semiconductor device includes a first storage node contact plug and a second storage node contact plug formed over a semiconductor substrate, wherein the second storage node contact plug is arranged at a height different from that of the first storage node contact plug, and a lower electrode formed over the first storage node contact plug and the second storage node contact plug.07-12-2012
20100270647METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING CAPACITOR - Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.10-28-2010
20100270645THIN-FILM CAPACITOR STRUCTURES EMBEDDED IN SEMICONDUCTOR PACKAGES AND METHODS OF MAKING - Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.10-28-2010
20100270644METHODS OF EMBEDDING THIN-FILM CAPACITORS INTO SEMICONDUCTOR PACKAGES USING TEMPORARY CARRIER LAYERS - Disclosed are methods of making a semiconductor package comprising at least one thin-film capacitor embedded into at least one build-up layer of said semiconductor package. A thin-film capacitor is provided wherein the thin-film capacitor has a first electrode and a second electrode separated by a dielectric. A temporary carrier layer is applied to the first electrode and the second electrode is patterned. A PWB core and a build-up material are provided, and the build-up material is placed between the PWB core and the patterned second electrode of said thin-film capacitor. The patterned electrode side of the thin-film capacitor is laminated to the PWB core by way of the build-up material, the temporary carrier layer is removed, and the first electrode is patterned.10-28-2010
20100270643Semiconductor device and layout method therefor - Provided is a semiconductor device including: an MIM capacitor that includes a lower electrode, an upper electrode, and a capacitor insulating film formed between the lower electrode and the upper electrode; a first via hole that connects to the lower electrode and extends in a normal upward direction of a principal surface of the lower electrode; a second via hole that connects to the upper electrode and extends in a normal upward direction of a principal surface of the upper electrode; and a plurality of lower wiring lines that are formed under the lower electrode, in which formation areas of the first and second via holes overlap formation areas of the plurality of lower wiring lines when viewed in the normal direction of the principal surface of the upper electrode.10-28-2010
20120074521METHOD OF MANUFACTURING CAPACITOR, AND CAPACITOR, CIRCUIT SUBSTRATE AND SEMICONDUCTOR APPARATUS - A method of manufacturing a capacitor includes forming a first ceramic film on a first base made of a metal, forming a second ceramic film on a second base made of a metal, forming a first copper electrode pattern and a first copper via-plug on a surface of one of the first and second ceramic films, the electrode pattern and the via-plug being separate from each other, bonding the first and second ceramic films together with the first electrode pattern and the via-plug therebetween, by applying a pulsed voltage between the first base and the second base while the first base and the second base are pressed so that the first ceramic film and the second ceramic film are pressed on each other, and removing the second base.03-29-2012
20120181657Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer - A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.07-19-2012
20120181656Semiconductor Device and Method of Manufacturing Thereof - A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.07-19-2012
20120256294Nanopillar Decoupling Capacitor - Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.10-11-2012
20120187535SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.07-26-2012
20120187537SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.07-26-2012
20120187536COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHOD OF MANUFACTURE - A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.07-26-2012
20120187534PULSE METHOD OF OXIDIZING SIDEWALL DIELECTRICS FOR HIGH CAPACITANCE APPLICATIONS - The present invention provides systems, methods and apparatus for manufacturing a memory cell. The invention includes forming a feature having sidewalls in a first dielectric material; forming a first conductive material on the sidewalls of the feature; depositing a layer of a second dielectric material on the conductive material; and exposing the second dielectric material to oxidizing species and ultraviolet light to oxidize the second dielectric material. Numerous additional aspects are disclosed.07-26-2012
20090020850SEMICONDUCTOR DESIGN APPARATUS, SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DESIGN METHOD - According to an aspect of the present invention, there is provided a semiconductor design apparatus including: a determination section that determines a connection position of a capacitor to suppress a noise on a layout data in which a layout of circuit cells are completed; a calculation section that calculates a capacitance value required to suppress the noise; a generation section that generates the capacitor satisfying the capacitance value; and a wiring section that wires the capacitor to a power wiring and a ground wiring at the connection position.01-22-2009
20090020849ELECTRONIC DEVICE INCLUDING A CAPACITOR AND A PROCESS OF FORMING THE SAME - An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode. The second electrode can include an opening, wherein from a top view, a defect lies within the opening. In another aspect, a process of forming an electronic device can include forming a first capacitor electrode layer over a substrate, forming a dielectric layer over the first capacitor electrode layer, and forming a second capacitor electrode layer over the dielectric layer. The process can also include detecting a defect and removing a first portion of the second capacitor electrode layer corresponding to the defect, wherein a second portion of the second capacitor electrode layer remains over the dielectric layer.01-22-2009
20120261797LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE - Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer comprising a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.10-18-2012
20120228737SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor.09-13-2012
20120228736TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE - A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.09-13-2012
20120228738PROTECTING ELEMENT - With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n09-13-2012
20110121427THROUGH-SUBSTRATE VIAS WITH POLYMER FILL AND METHOD OF FABRICATING SAME - An through-substrate via fabrication method requires forming a through-substrate via hole in a semiconductor substrate, depositing an electrically insulating, continuous and substantially conformal isolation material onto the substrate and interior walls of the via using ALD, depositing a conductive material into the via and over the isolation material using ALD such that it is electrically continuous across the length of the via hole, and depositing a polymer material over the conductive material such that any continuous top-to-bottom openings present in the via holes are filled by the polymer material. The basic fabrication method may be extended to provide vias with multiple conductive layers, such as coaxial and triaxial vias.05-26-2011
20100327409SEMICONDUCTOR DEVICE COMPRISING CAPACITIVE ELEMENT - A capacitive element formed within a semiconductor device comprises an upper electrode, a capacitive insulating film containing an oxide and/or silicate of a transition metal element, and a lower electrode having a polycrystalline conductive film composed of a material having higher oxidation resistance than the transition metal element and an amorphous or microcrystalline conductive film formed below the polycrystalline conductive film.12-30-2010
20100327408CARBON/EPOXY RESIN COMPOSITION, AND CARBON-EPOXY DIELECTRIC FILM PRODUCED BY USING THE SAME - A carbon/epoxy composition includes a bisphenol-based epoxy, an amine-based curing agent, an imidazole-based curing catalyst, and carbon black. A carbon-epoxy dielectric layer is fabricated using a reaction product of the carbon/epoxy composition.12-30-2010
20120261798SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a wiring configured to be formed in a surface portion of a first interlayer insulating layer in a first region, a common upper electrode configured to be formed in a surface portion of the first interlayer insulating layer in a second region, a plurality of capacitance portions configured to have the common upper electrode as an upper electrode and be extended below, wherein an upper surface of the first interlayer insulating layer and an upper surface of the common upper electrode approximately lie in the same plane.10-18-2012
20120299153STACK CAPACITOR STRUCTURE AND FORMING METHOD - The present invention discloses a stack capacitor structure and method of making the same. The top plate of the stack capacitor structure is connected to each other through a connecting node. The method of forming the stack capacitor structure includes providing an insulating substrate with a doped insulating material layer disposed therein. Then, the insulating substrate is patterned to form a trench, wherein an inner sidewall of the trench has a first region and a second region and the doped insulating material layer within the second region is entirely removed to form a hole. Later, a top plate is formed to surround the inner sidewall of the trench, and the top plate fills in the hole. Next, a capacitor dielectric layer is formed to surround the top plate. Finally, a storage node is formed to fill up the trench.11-29-2012
20120299152DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE - A resistor and capacitor are provided in respective shallow trench isolation structures. The method includes forming a first and second trench in a substrate and forming a first insulator layer within the first and second trench. The method includes forming a first electrode material within the first and second trench, on the first insulator layer, and forming a second insulator layer within the first and second trench and on the first electrode material. The method includes forming a second electrode material within the first and second trench, on the second insulator layer. The second electrode material pinches off the second trench. The method includes removing a portion of the second electrode material and the second insulator layer at a bottom portion of the first trench, and filling in the first trench with additional second electrode material. The additional second electrode material is in electrical contact with the first electrode material.11-29-2012
20120267762Capacitor Structure - One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.10-25-2012
20120267759DECOUPLING CAPACITORS RECESSED IN SHALLOW TRENCH ISOLATION - A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.10-25-2012
20120267757CAPACITOR STRUCTURE WITH METAL BILAYER AND METHOD FOR USING THE SAME - A method for using a metal bilayer is disclosed. First, a bottom electrode is provided. Second, a dielectric layer which is disposed on and is in direct contact with the lower electrode is provided. Then, a metal bilayer which serves as a top electrode in a capacitor is provided. The metal bilayer is disposed on and is in direct contact with the dielectric layer. The metal bilayer consists of a noble metal in direct contact with the dielectric layer and a metal nitride in direct contact with the noble metal.10-25-2012
20120319239SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME - A semiconductor structure includes a through-substrate-via (TSV) structure disposed in a substrate. A first etch stop layer is disposed over the TSV structure. A first dielectric layer is disposed in contact with the first etch stop layer. A first conductive structure is disposed through the first etch stop layer and the first dielectric layer. The first conductive structure is electrically coupled with the TSV structure. The TSV structure is substantially wider than the first conductive structure. A second etch stop layer is disposed in contact with the first dielectric layer. A metal-insulator-metal (MIM) capacitor structure is disposed in contact with the second etch stop layer.12-20-2012
20120319238Large Dimension Device and Method of Manufacturing Same in Gate Last Process - An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode.12-20-2012
20110227194METHOD FOR FORMING A THREE-DIMENSIONAL STRUCTURE OF METAL-INSULATOR-METAL TYPE - A method for forming a capacitive structure in a metal level of an interconnection stack including a succession of metal levels and of via levels, including the steps of: forming, in the metal level, at least one conductive track in which a trench is defined; conformally forming an insulating layer on the structure; forming, in the trench, a conductive material; and planarizing the structure.09-22-2011
20110227193CAPACITOR AND SEMICONDUCTOR DEVICE - A capacitor includes a lower electrode formed over a semiconductor substrate; a first insulating film formed over the lower electrode; a second insulating film formed over the first insulating film; a third insulating film formed over the second insulating film; and an upper electrode formed over the third insulating film, the density of the first insulating film being greater than that of the second insulating film, and the density of the third insulating film being greater than that of the second insulating film.09-22-2011
20120273921SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a dielectric layer, where the dielectric layer includes a metal oxide layer, a metal nitride carbide layer including hydrogen therein, and a reduction prevention layer inserted between the metal nitride carbide layer and the dielectric layer.11-01-2012
20120080772SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor.04-05-2012
201200807713D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY - The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.04-05-2012
20100230787ELECTRIC DEVICE COMPRISING AN IMPROVED ELECTRODE - The invention relates to an electric device including an electric element, the electric element comprising a first electrode (09-16-2010
20120280358INTEGRATED CIRCUITS INCLUDING METAL-INSULATOR-METAL CAPACITORS AND METHODS OF FORMING THE SAME - An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer.11-08-2012
20120326273METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.12-27-2012
20120326272THIN-FILM CAPACITOR, MULTILAYER WIRING BOARD AND SEMICONDUCTOR DEVICE - A thin-film capacitor with first capacitative elements each having an electrode layer with a first polarity on an upper surface of a dielectric layer and an electrode layer with a second polarity on a lower surface of the dielectric layer; second capacitative elements each having an electrode layer with the second polarity on the upper surface and an electrode layer with the first polarity on the lower surface and arranged around a specific position alternately with the first capacitative elements; a single common connection hole at the specific position connecting all electrode layers with the first polarity of the first and second capacitative elements; and individual connection holes around the common connection hole connecting each electrode layer with the second polarity of the adjacent and second capacitative elements.12-27-2012
20120326271SECONDARY DEVICE INTEGRATION INTO CORELESS MICROELECTRONIC DEVICE PACKAGES - The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.12-27-2012
20120326270INTERDIGITATED VERTICAL NATIVE CAPACITOR - A metal capacitor structure includes a plurality of line level structures vertically interconnected with via level structures. Each first line level structure and each second line level structure includes a set of parallel metal lines that is physically joined at an end to a rectangular tab structure having a rectangular horizontal cross-sectional area. A first set of parallel metal lines within a first line level structure and a second set of parallel metal lines within a second line level structure are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure. Because the rectangular tab structures do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures, sub-resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure.12-27-2012
20120091561MEMS DEVICES - A method of manufacturing a MEMS device comprises forming a MEMS device element (04-19-2012
20120091560MIM Capacitors in Semiconductor Components - Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.04-19-2012
20120091559Capacitor and Method for Making Same - A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.04-19-2012
20120286392SUPPRESSION OF DIFFUSION IN EPITAXIAL BURIED PLATE FOR DEEP TRENCHES - Dopants of a first conductivity type are implanted into a top portion of a semiconductor substrate having a doping of the first conductivity type to increase the dopant concentration in the top portion, which is a first-conductivity-type semiconductor layer. A semiconductor material layer having a doping of the second conductivity type, a buried insulator layer, and a top semiconductor layer are formed thereupon. Deep trenches having a narrow width have a bottom surface within the second-conductivity-type semiconductor layer, which functions as a buried plate. Deep trenches having a wider width are etched into the first-conductivity-type layer underneath, and can be used to form an isolation structure. The additional dopants in the first-conductivity-type semiconductor layer provide a counterdoping against downward diffusion of dopants of the second conductivity type to enhance electrical isolation.11-15-2012
20120286393FINGER METAL OXIDE METAL CAPACITOR STRUCTURES - A finger metal oxide metal (MOM) capacitor includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit. First and second side portions include a plurality of first and second finger sections extending in the plurality of metal layers and first and second hole vias connecting the first and second finger sections, respectively. A middle portion connects the first and second side portions. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. A plurality of “T”-shaped sections are defined in the plurality of metal layers and third hole vias connecting the plurality of “T”-shaped sections. Middle portions of the plurality of “T”-shaped sections extend towards the middle portion and between the first side portion and the second side portion of the outer conducting structure.11-15-2012
20120286394METAL OXIDE METAL CAPACITOR STRUCTURES - A metal oxide metal (MOM) capacitor includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit including first opposing side walls, second opposing side walls, a cavity with first and second openings, and openings in the first opposing side walls. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. The inner conducting structure is arranged in the cavity of the outer conducting structure and includes a body, and conducting extensions that extend from the body through the openings in the first opposing side walls. Oxide is arranged between the outer conducting structure and the inner conducting structure.11-15-2012
20120286395EMBEDDED CAPACITOR DEVICE AND METHODS OF FABRICATION - Embodiments of the present invention describe a semiconductor device having an embedded capacitor device and methods of fabricating the capacitor device. The capacitor device is formed between the passivation layers above the backend interconnect stack of a substrate. Fabricating the capacitor device between the passivation layers above the backend interconnect stack minimizes any adverse effects the capacitor device might cause to the backend interconnect stack.11-15-2012
20100207243Semiconductor device and method of fabricating the same - A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer.08-19-2010
20120139083POWER DISTRIBUTION NETWORK - In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.06-07-2012
20130015557SEMICONDUCTOR PACKAGE INCLUDING AN EXTERNAL CIRCUIT ELEMENTAANM Yang; ZhipingAACI CupertinoAAST CAAACO USAAGP Yang; Zhiping Cupertino CA USAANM Xue; JieAACI San RamonAAST CAAACO USAAGP Xue; Jie San Ramon CA USAANM Savic; JovicaAACI Downers GroveAAST ILAACO USAAGP Savic; Jovica Downers Grove IL USAANM Li; LiAACI San RamonAAST CAAACO USAAGP Li; Li San Ramon CA US - Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening.01-17-2013
20130015558SEMICONDUCTOR DEVICEAANM NISHIZAKI; MamoruAACI TokyoAACO JPAAGP NISHIZAKI; Mamoru Tokyo JPAANM OTA; KenAACI TokyoAACO JPAAGP OTA; Ken Tokyo JP - A semiconductor device has at least a first capacitor and a second capacitor. First electrodes of the first and second capacitors are connected in common, a first voltage (½ VPERI) is applied to the first electrodes, a second voltage (for example, VPERI) that is different from the first voltage is applied to either one of the second electrodes, and the first voltage is applied to the other second electrode. A capacitor which constitutes a dummy capacitance is provided by applying one of the second electrodes of the first and second capacitors with the same voltage as the voltage applied to their first electrodes, whereby making it possible to increase the area of the compensation capacitance in the semiconductor device without changing a specified capacitance value.01-17-2013
20130015556SUSPENDED BEAM FOR USE IN MEMS DEVICEAANM YANG; Chin-ShengAACI Hsinchu CityAACO TWAAGP YANG; Chin-Sheng Hsinchu City TW - A suspended beam includes a substrate, a main body and a first metal line structure. A first end of the main body is fixed onto the substrate. A second end of the main body is suspended. The first metal line structure is embedded in the main body. The width of the first metal line structure is smaller than the width of the main body.01-17-2013
20130015559SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAMEAANM LEE; Sung-HoAACI Hwaseong-siAACO KRAAGP LEE; Sung-Ho Hwaseong-si KRAANM Choi; JinAACI Yongin-siAACO KRAAGP Choi; Jin Yongin-si KRAANM Yoo; Yong-HoAACI Yongin-siAACO KRAAGP Yoo; Yong-Ho Yongin-si KRAANM Kang; Jong-HyukAACI SeoulAACO KRAAGP Kang; Jong-Hyuk Seoul KRAANM Cha; Hyun-JooAACI SeoulAACO KRAAGP Cha; Hyun-Joo Seoul KRAANM Park; Hee-DongAACI Yongin-siAACO KRAAGP Park; Hee-Dong Yongin-si KRAANM Park; Tae-JungAACI BusanAACO KRAAGP Park; Tae-Jung Busan KR - A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.01-17-2013
20110147888METHODS TO FORM MEMORY DEVICES HAVING A CAPACITOR WITH A RECESSED ELECTRODE - Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes.06-23-2011
20130020678Semiconductor Devices with Orientation-Free Decoupling Capacitors and Methods of Manufacture Thereof - Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.01-24-2013
20130020677EMBEDDED CAPACITOR STRUCTURE AND THE FORMING METHOD THEREOF - A method for forming an embedded capacitor structure is provided. Firstly, a first dielectric layer having a trench therein on a substrate is provided. A capacitor structure is formed on the bottom surface of the trench. The capacitor structure includes a first metal layer, a capacitance-insulating layer and a second metal layer and the portion surface of the first metal layer on the bottom surface of the trench is exposed. A cap layer is formed on the top surface and the inner surface of the trench and on the capacitor structure. A second dielectric layer is formed on the cap layer. The portion of second dielectric layer and the portion of the cap layer are removed to form a plurality of contact windows therein, and the portion surface of the first metal layer and the portion surface of the second metal layer are exposed by the plurality of contact windows.01-24-2013
20130020679SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF - When producing ferroelectric memory devices on a wafer, a memory cell expected to provide the severest degradation of fatigue characteristics is selected from a chip region of the wafer in which the fatigue characteristics are expected to be the poorest, based on the knowledge acquired in advance with regard to the in-plane distribution of the fatigue characteristics on a wafer. The predetermined number of times of rewriting data is guaranteed by conducting fatigue test in the memory cell thus selected for all of the wafers such that, when the result of the fatigue test is good, the entire devices on the wafer are rendered good with regard to the fatigue characteristics.01-24-2013
20120241908SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.09-27-2012
20120241906CAPACITOR-INCORPORATED SUBSTRATE AND COMPONENT-INCORPORATED WIRING SUBSTRATE - An object of the present invention is to provide a capacitor-incorporated wiring substrate in which connection reliability can be improved through ensuring of a path for supply of electric potential even upon occurrence of a faulty connection in a via-conductor group. In a capacitor-incorporated wiring substrate of the present invention, a capacitor 09-27-2012
20120241905SUBSTRATE ISOLATION STRUCTURE - An integrated circuit includes a conductive substrate pick-up region in the substrate that forms a perimeter around a portion of the substrate. Conductive stripes traverse the portion of the substrate within the perimeter and are coupled to a low impedance node along with the substrate pick-up region. A capacitor has a bottom plate formed above the conductive stripes. The pick-up region and the conductive stripes absorb injected current caused by parasitic capacitance between the bottom plate of the capacitor and the substrate region thereby reducing cross-talk caused by the injected current.09-27-2012
20080251889SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The first metal layer comprises a body-centered cubic lattice metal, and overlies the substrate. The dielectric layer overlies the first metal layer. The second metal layer overlies the dielectric layer.10-16-2008
20100090309Capacitors, Dielectric Structures, And Methods Of Forming Dielectric Structures - Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.04-15-2010
20080230871SEMICONDUCTOR DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.09-25-2008
20130168812MEMORY CAPACITOR HAVING A ROBUST MOAT AND MANUFACTURING METHOD THEREOF - A manufacturing method for memory capacitor having a robust moat, comprising the steps of: providing a substrate; forming a patterned sacrificial layer on the substrate having a moat to separate a cell area and a peripheral area; forming a supporting layer on the sacrificial layer and filling the moat to form a annular member, wherein the supporting layer and the sacrificial layer arranged in alignment to form a stack structure; forming a plurality row of capacitor trenches on the substrate, wherein the capacitor trenches are formed at intervals in the stack structure; and forming a conducting layer on the supporting layer and covering the substrate and the inner surface of the stack structure defining the capacitor trenches.07-04-2013
20130168813SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.07-04-2013
20130168814SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device and a method for manufacturing the same, a mesh shaped lower electrode of a peripheral region is used as a reservoir capacitor to increase the size of a region contacting a dielectric film, such that Cs deterioration is minimized. An exemplary semiconductor device may include a line-type storage node contact plug formed over a semiconductor substrate, a mesh shaped lower electrode formed over the storage node contact plug, and a dielectric film and an upper electrode formed over the lower electrode.07-04-2013
20130140677CAPACITOR STRUCTURES FOR SEMICONDUCTOR DEVICE - A semiconductor device comprising a semiconductor substrate and a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises a capacitor stack comprising a lower and an upper capacitor, respectively comprising first and second dielectric materials, wherein the first and second dielectric materials are different materials and/or have different thicknesses from each other. This can minimize the voltage dependence of the capacitance of the composite capacitor structure. It is also possible to provide a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises at least a first and a second capacitor stack, each comprising a lower and an upper capacitor. The capacitors can be MIM capacitors.06-06-2013
20130140673MONOLITHIC SEMICONDUCTOR SWITCHES AND METHOD FOR MANUFACTURING - A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.06-06-2013
20130140674SEMICONDUCTOR DEVICE - A semiconductor device according to this invention includes a first power line that supplies power to a first circuit, a second power line that supplies power to a second circuit, and a capacitive element that is provided between the first power line and the second power line.06-06-2013
20130140675Method for ALD Deposition Rate Enhancement - A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO06-06-2013
20130140676SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a substrate and a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode. The upper electrode includes a first layer formed of an oxide whose stoichiometric composition is expressed as AOx06-06-2013
20080224263Semiconductor device and method of manufacturing the same - A semiconductor device including a capacitor which includes a first electrode, a second electrode, and a dielectric layer disposed between the first electrode and the second electrode, the dielectric layer including: a first paraelectric film formed of a material containing a first metal element and at least one kind of second metal element; a second paraelectric film disposed between the first electrode and the first paraelectric film; and a third paraelectric film disposed between the second electrode and the first paraelectric film, wherein the second paraelectric film is formed of a material containing the first metal element but substantially not containing the second metal element, and the third paraelectric film is formed of a material containing the first metal element but substantially not containing the second metal element.09-18-2008
20080237791Zirconium oxide based capacitor and process to manufacture the same - A capacitor structure comprises a first and a second electrode of conducting material. Between the first and second electrodes, an atomic layer deposited dielectric film is disposed, which comprises zirconium oxide and a dopant oxide. Herein, the dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, while the dielectric film comprises a dopant content of 10 atomic percent or less of the dielectric film material excluding oxygen. A process for fabricating a capacitor comprises a step of forming a bottom electrode of the capacitor. On the bottom electrode, a dielectric film comprising zirconium oxide is deposited, and a step for introducing a dopant oxide into the dielectric film performed. On the dielectric structure, a top electrode is formed. The dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, whereas the dielectric structure deposited comprises a dopant content of 10 atomic percent or less of the deposited material excluding oxygen.10-02-2008
20130181325Through-Assembly Via Modules and Methods for Forming the Same - A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.07-18-2013
20080217738SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An upper electrode film includes a first conductive oxidation layer made of an oxide expressed by a chemical formula M09-11-2008
20120248572SEMICONDUCTOR DEVICE HAVING CAPACITOR CAPABLE OF REDUCING ADDITIONAL PROCESSES AND ITS MANUFACTURE METHOD - A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film.10-04-2012
20120248571METAL-INSULATION-METAL DEVICE AND MANUFACTURE METHOD THEREOF - A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer. A manufacture method of an MIM device is also provided.10-04-2012
20130093051Asymmetric MIM Capacitor for DRAM Devices - A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO04-18-2013
20130093049High Productivity Combinatorial Dual Shadow Mask Design - Dual shadow mask design can overcome the size and resolution limitations of shadow masks to provide capacitor structures with small effective areas. The capacitor structures have bottom and top electrode layers patterned using shadow masks, sandwiching a dielectric layer. The effective areas of the capacitors are the overlapping areas of the top and bottom electrodes, thus allowing small area sizes without subjected to the size limitation of the electrodes. The dual shadow mask design can be used in conjunction with high productivity combinatorial processes for screening and optimizing dielectric materials and fabrication processes.04-18-2013
20130093050Integrated Circuitry, Methods Of Forming Capacitors, And Methods Of Forming Integrated Circuitry Comprising An Array Of Capacitors And Circuitry Peripheral To The Array - A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.04-18-2013
20130093048Deposited Material and Method of Formation - A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.04-18-2013
20130093047Metal-Oxide-Metal Capacitor Structure - A metal-oxide-metal capacitor comprises a first electrode, a second electrode, a plurality of first fingers and a plurality of second fingers. Each first finger and its corresponding second finger are in parallel and separated by a low k dielectric material. A guard ring is employed to enclose the metal-oxide-metal capacitor so as to prevent moisture from penetrating into the low k dielectric material.04-18-2013
20130093046LOW IMPEDANCE GATE CONTROL METHOD AND APPARATUS - According to one embodiment of a module, the module includes a plurality of gate driver chips coupled in parallel and having a common gate input, a common supply voltage and a common output. The chips are spaced apart from one another and have a combined width extending between an edge of a first outer one of the chips and an opposing edge of a second outer one of the chips. The module further includes a plurality of capacitors coupled in parallel between ground and the common supply voltage, and a transverse electromagnetic (TEM) transmission line medium coupled to the common output of the chips and having a current flow direction perpendicular to the combined width of the chips.04-18-2013
20130113079Blocking Layers for Leakage Current Reduction in DRAM Devices - A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.05-09-2013
20130113075METAL-INSULATOR-METAL CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.05-09-2013
20130113076METAL-SEMICONDUCTOR WAFER BONDING FOR HIGH-Q DEVICES - Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.05-09-2013
20130113078POLYSILICON-INSULATOR-SILICON CAPACITOR IN A SIGE HBT PROCESS AND MANUFACTURING METHOD THEREOF - A PIS capacitor in a SiGe HBT process is disclosed, wherein the PIS capacitor includes: a silicon substrate; a P-well and shallow trench isolations formed in the silicon substrate; a P-type heavily doped region formed in an upper portion of the P-well; an oxide layer and a SiGe epitaxial layer formed above the P-type heavily doped region; spacers formed on sidewalls of the oxide layer and the SiGe epitaxial layer; and contact holes for picking up the P-well and the SiGe epitaxial layer and connecting each of the P-well and the SiGe epitaxial layer to a metal wire. A method of manufacturing the PIS capacitor is also disclosed. The PIS capacitor of the present invention is manufactured by using SiGe HBT process, thus providing one more device option for the SiGe HBT process.05-09-2013
20130113073Integrated Circuit having a MOM Capacitor and Method of Making Same - An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.05-09-2013
20130113074Capacitor system and method for producing a capacitor system - A capacitor system and a method for producing a capacitor system. The capacitor system may be used in a power semiconductor module. In one embodiment, the capacitor system comprises a metal shaped body having a depression; a capacitor arranged at least partly in the depression; a spacer composed of electrically insulating material, the spacer being arranged at least partly between the capacitor and the metal shaped body in the depression; and an electrically insulating potting material provided in the depression, wherein the potting material fixes the capacitor in the depression so that the capacitor does not touch the metal shaped body.05-09-2013
20110272784SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT CYLINDRICAL CAPACITOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.11-10-2011
20110272783SEMICONDUCTOR DEVICE WITH BIPOLAR TRANSISTOR AND CAPACITOR - A semiconductor device with a bipolar transistor and a capacitor that has a down-sized circuit area is presented. During the manufacture of the bipolar transistor, a polysilicon-insulator-polysilicon capacitor, a polysilicon-insulator-metal layer or a metal-insulator-metal capacitor can be formed on the isolating insulator and/or the protective insulator to achieve reduced circuit area, less manufacturing steps and lowered manufacturing cost.11-10-2011
20130113077Metal Finger Capacitor for High-K Metal Gate Processes - Embodiments described herein provide a structure for finger capacitors, and more specifically metal-oxide-metal (“MOM”) finger capacitors and arrays of finger capacitors. A plurality of Shallow Trench Isolation (STI) formations is associated with every other column of capacitor fingers, with poly fill formations covering the STI formations to provide a more robust and efficient structure.05-09-2013
20130099355MEMS Structures and Methods for Forming the Same - A method includes forming a MEMS device, forming a bond layer adjacent the MEMS device, and forming a protection layer over the bond layer. The steps of forming the bond layer and the protection layer include in-situ deposition of the bond layer and the protection layer04-25-2013
20110266654POWER STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a method for manufacturing a power storage device in which a crystalline silicon layer including a whisker-like crystalline silicon region is formed as an active material layer over a current collector by a low-pressure CVD method in which heating is performed using a deposition gas containing silicon. The power storage device includes the current collector, a mixed layer formed over the current collector, and the crystalline silicon layer functioning as the active material layer formed over the mixed layer. The crystalline silicon layer includes a crystalline silicon region and a whisker-like crystalline silicon region including a plurality of protrusions which project over the crystalline silicon region. With the protrusions, the surface area of the crystalline silicon layer functioning as the active material layer can be increased.11-03-2011
20130119515METHOD FOR FABRICATING A DRAM CAPACITOR HAVING INCREASED THERMAL AND CHEMICAL STABILITY - A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode film. The first electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the first electrode film. A high-k dielectric film is formed over the first electrode film. A second electrode film is formed over the dielectric film. The second electrode film comprises a conductive binary metal compound and a dopant. The dopant may have a uniform or non-uniform concentration within the second electrode film. The dopants and their distribution are chosen so that the crystal structure of the surface of the electrode is not degraded if the electrode is to be used as a templating structure for subsequent layer formation. Additionally, the dopants and their distribution are chosen so that the work function of the electrodes is not degraded.05-16-2013
20130119514METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes at least forming a lower electrode comprising titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide as a primary constituent on the lower electrode, forming a first protective film comprising a titanium compound on the dielectric film, and forming an upper electrode comprising titanium nitride on the first protective film. The method can include a step of forming a second protective film on the lower electrode before the step of forming the dielectric film on the lower electrode.05-16-2013
20130127016METAL OXIDE METAL CAPACITOR WITH SLOT VIAS - A capacitor includes a first electrode including a plurality of first conductive lines, at least one first via, and at least one second via. The first conductive lines are parallel and connected to a first periphery conductive line. The first conductor lines in adjacent layers are coupled by the at least one first and second via. The at least one first via has a first length, and the at least one second via has a second length. The capacitor includes a second electrode opposite to the first electrode. The second electrode includes a plurality of second conductive lines and at least one third via. The second conductive lines are parallel and connected to a second periphery conductive line. The second conductor lines in adjacent layers are coupled by the at least one third via. The capacitor includes at least one oxide layer between the first electrode and the second electrode.05-23-2013
20130127013SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device, a support wall is formed between storage nodes to more effectively prevent leaning of a capacitor, and the storage nodes are formed using a damascene process, which may increase a contact area between each storage node and a storage node contact.05-23-2013
20130127015Band Gap Improvement In DRAM Capacitors - A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO05-23-2013
20130127014HERMETIC PACKAGING OF INTEGRATED CIRCUIT COMPONENTS - A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.05-23-2013
20130127012Semiconductor Devices and Methods of Manufacturing the Same - A method of manufacturing a semiconductor device including forming on a substrate an insulating interlayer through which a capacitor contact is interposed; forming on the insulating interlayer a first upper electrode having an opening through which the capacitor contact is exposed; forming a first dielectric layer pattern on a lateral wall of the opening; forming a lower electrode on the first dielectric layer pattern formed in the opening and the capacitor contact; forming a second dielectric layer pattern on the lower electrode formed in the opening and the first dielectric layer pattern; and forming on the second dielectric layer pattern a second upper electrode so as to fill the opening and to contact the first upper electrode. The semiconductor device may prevent a lower electrode of a capacitor from collapsing.05-23-2013
20110272782POWER LAYOUT FOR INTEGRATED CIRCUITS - A power layout of an integrated circuit includes at least one power grid cell. Each power gird cell includes at least one first power layer configured to be coupled to a high power supply voltage and at least one second power layer configured to be coupled to a lower power supply voltage. The at least one first power layer has conductive lines in at least two different directions. The at least one second power layer has conductive lines in at least two different directions.11-10-2011
20100276784ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME - An electronic module including a substrate having at least one structure that reduces stress flow through the substrate, wherein the structure comprises at least one trench in a surface of the substrate.11-04-2010
20130147012CIRCUIT BOARD COMPONENT SHIM STRUCTURE - Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.06-13-2013
20130147013SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal.06-13-2013
20130147014Wafer Level Package Having Cylindrical Capacitor and Method Of Fabrication The Same - Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided.06-13-2013
20110210422SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part.09-01-2011
20130175666SEMICONDUCTOR DEVICE HAVING CAPACITOR INTEGRATED THEREIN - Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes.07-11-2013
20130175667Semiconductor Devices And Methods of Manufacturing The Same - A semiconductor device may include lower electrodes having different heights depending on positions on a substrate. Supporting layer pattern making a contact with the lower electrodes having a relatively large height is provided. The supporting layer pattern is provided between the lower electrodes for supporting the lower electrodes. A dielectric layer is provided on the lower electrodes and the supporting layer pattern. An upper electrode is formed on the dielectric layer and has a planar upper surface. An inter-metal dielectric layer is provided on the upper electrode. A metal contact penetrating through the inter-metal dielectric layer and making a contact with the upper electrode is formed. A bottom portion of the metal contact faces a portion under where the lower electrode having a relatively small height is formed. The device has a higher reliability.07-11-2013
20110221035PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING A METAL-INSULATOR-METAL CAPACITOR AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit is fabricated by producing metallization levels in insulating regions, the insulating region being formed of a first material having a first dielectric constant. At least one metal-insulator-metal capacitor is formed by providing metal electrodes in the metallization level, and locally replacing the first material, which is located between the metal electrodes, with a second material having a second dielectric constant greater than the first dielectric constant.09-15-2011
20130175665THERMALLY STABLE HIGH-K TETRAGONAL HFO2 LAYER WITHIN HIGH ASPECT RATIO DEEP TRENCHES - A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.07-11-2013
20130175668Semiconductor Device and Method of Making Integrated Passive Devices - A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization.07-11-2013
20100295156STRUCTURE FOR SYMMETRICAL CAPACITOR - Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.11-25-2010
20130099356Semiconductor Device and Method of Forming Directional RF Coupler with IPD for Additional RF Signal Processing - A semiconductor device has a substrate and RF coupler formed over the substrate. The RF coupler has a first conductive trace with a first end coupled to a first terminal of the semiconductor device, and a second conductive trace with a first end coupled to a second terminal of the semiconductor device. The first conductive trace is placed in proximity to a first portion of the second conductive trace. An integrated passive device is formed over the substrate. A second portion of the second conductive trace operates as a circuit component of the integrated passive device. The integrated passive device can be a balun or low-pass filter. The RF coupler also has a first capacitor coupled to the first terminal of the semiconductor device, and second capacitor coupled to a third terminal of the semiconductor device for higher directivity. The second conductive trace is wound to exhibit an inductive property.04-25-2013
20120273922SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An amorphous carbon film and an interlayer insulation film are formed in a memory cell region and a peripheral circuit region, respectively. An insulating film is formed on the amorphous carbon film and the interlayer insulation film. A portion of the insulating film that corresponds to capacitors on the amorphous carbon film is removed so that lower electrodes of the capacitors are supported from opposite sides of the lower electrodes. An insulating film pattern continuously extends from the memory cell region to the peripheral circuit region wholly covered with the insulating film pattern. Subsequently, the amorphous carbon film is removed to leave the capacitors supported by the insulating film pattern on both sides of the lower electrodes.11-01-2012
20120273920Devices including composite thermal capacitors - Embodiments of the present disclosure include devices or systems that include a composite thermal capacitor disposed in thermal communication with a hot spot of the device, methods of dissipating thermal energy in a device or system, and the like.11-01-2012
20110233726Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors - A semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.09-29-2011
20110233725SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING THE SAME - A semiconductor device includes a first wiring layer, a second wiring layer and an insulating layer provided between the first wiring layer and the second wiring layer. A capacitor has a first electrode formed on the first wiring layer and a second electrode formed on the second wiring layer in such a manner that the second electrode overlaps with the first electrode. To the first electrode, two connection wirings are connected and, to the second electrode, two connection wirings are connected. The two connection wirings are connected to each other with low DC impedance substantially only through the first electrode. Similarly, the two connection wirings are connected to each other with low DC impedance substantially only through the second electrode.09-29-2011
20110233724SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film.09-29-2011
20110233723DIELECTRIC FILM AND SEMICONDUCTOR DEVICE - Disclosed is a dielectric film having a high dielectric constant and an excellent leakage breakdown. The dielectric film includes a TiO09-29-2011
20110233722CAPACITOR STRUCTURE AND METHOD OF MANUFACTURE - The presented application discloses a capacitor structure and a method for manufacturing the same. The capacitor structure comprises a plurality of sub-capacitors formed on a substrate, each of which comprises a top capacitor plate, a bottom capacitor plate and a dielectric layer sandwiched therebetween; and a first capacitor electrode and a second capacitor electrode connecting the plurality of sub-capacitors in parallel, wherein the plurality of sub-capacitors includes a plurality of first sub-capacitors and a plurality of second sub-capacitors stacked in an alternate manner, each of the first sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying second sub-capacitor, with the overlapping plate being a first electrode layer; and each of the second sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying first sub-capacitor, with the overlapping plate being a second electrode layer, the capacitor structure is characterized in that the first electrode layer and the second electrode layers are made of different conductive materials. The capacitor structure has a small footprint on the chip and a large capacitance value, and can be used as an integrated capacitor in an analogous circuit, an RF circuit, an embedded memory, and the like.09-29-2011
20110254126MEMORY CELL WITH CARBON SWITCHING MATERIAL HAVING A REDUCED CROSS-SECTIONAL AREA AND METHODS FOR FORMING THE SAME - In a first aspect, a method of forming a metal-insulator-metal (“MIM”) stack is provided, the method including: (1) forming a dielectric material having an opening and a first conductive carbon layer within the opening; (2) forming a spacer in the opening; (3) forming a carbon-based switching material on a sidewall of the spacer; and (4) forming a second conductive carbon layer above the carbon-based switching material. A ratio of a cross sectional area of the opening in the dielectric material to a cross sectional area of the carbon-based switching material on the sidewall of the spacer is at least 5. Numerous other aspects are provided.10-20-2011
20130154057Method for Fabricating a DRAM Capacitor - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO06-20-2013
20130154054MICRO-ELECTRO-MECHANICAL STRUCTURE (MEMS) CAPACITOR DEVICES, CAPACITOR TRIMMING THEREOF AND DESIGN STRUCTURES - Micro-electro-mechanical structure (MEMS) capacitor devices, capacitor trimming for MEMS capacitor devices, and design structures are disclosed. The method includes identifying a process variation related to a formation of micro-electro-mechanical structure (MEMS) capacitor devices across a substrate. The method further includes providing design offsets or process offsets in electrode areas of the MEMS capacitor devices across the substrate, based on the identified process variation.06-20-2013
20130154055CAPACITOR AND REGISTER OF SEMICONDUCTOR DEVICE, MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.06-20-2013
20130154056SEMICONDUCTOR DEVICE - In a semiconductor device including a capacitor which has an upper electrode, a polycrystalline silicon layer on the upper electrode, and a metallic member on the polycrystalline silicon layer, the polycrystalline silicon layer includes germanium so that an upper portion of the polycrystalline silicon layer is lower than a lower portion thereof in a concentration of germanium.06-20-2013
20110291237LANTHANIDE DIELECTRIC WITH CONTROLLED INTERFACES - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.12-01-2011
20110304018LOW TEMPERATURE DEPOSITION AND ULTRA FAST ANNEALING OF INTEGRATED CIRCUIT THIN FILM CAPACITOR - Some embodiments of the invention include thin film capacitors formed on a package substrate of an integrated circuit package. At least one of the film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.12-15-2011
20110304017SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.12-15-2011
20110304016WIRING BOARD, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - A wiring board includes a structure in which a plurality of wiring layers are stacked with insulating layers interposed therebetween, a plurality of pads for mounting an electronic component, the pads being formed on an outermost insulating layer on one surface side of the structure and exposed to the surface of the outermost insulating layer, and a recessed portion formed at a place corresponding to a mounting area for the electronic component. The recessed portion is formed in the outermost insulating layer at an area between the pads to which electrode terminals of the electronic component to be mounted are to be connected, respectively.12-15-2011
20110304015SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI).12-15-2011
20110309475THREE-DIMENSIONAL STACKED STRUCTURE SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIA AND SIGNALING METHOD FOR THE SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device including a plurality of stacked layers and a through-silicon via (TSV) electrically connecting the plurality of layers, in which in signal transmission among the plurality of layers, the TSV transmits a signal that swings in a range from an offset voltage that is higher than a ground voltage to a power voltage, thereby minimizing an influence of a metal-oxide-semiconductor (MOS) capacitance of TSV.12-22-2011
20110309474TRENCH CAPACITOR - A trench and method of fabrication is disclosed. The trench shape is cylindrosymmetric, and is created by forming a dopant profile that is monotonically increasing in dopant concentration level as a function of depth into the substrate. A dopant sensitive etch is then performed, resulting in a trench shape providing increased surface area, yet having relatively smooth trench walls.12-22-2011
20120001298Method for manufacturing thin film capacitor and thin film capacitor obtained by the same - A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.01-05-2012
20120018844Solid-State Thin-Film Capacitor - Solid-state thin-film capacitors are provided. Aspects of the solid-state thin-film capacitors include a first electrode layer of a transition metal, a dielectric layer of an oxide of the transition metal, and a second electrode layer of a metal oxide. Also provided are methods of making the solid-state thin-film capacitors, as well as devices that include the same. The capacitor may have one or more cathodic arc produced structures, i.e., structures produced using a cathodic arc deposition process. The structures may be stress-free metallic structures, porous layers and layers displaying crenulations. Aspects of the invention further include methods of producing capacitive structures using chemical vapor deposition and/or by sputter deposition.01-26-2012
20120018843Scalable Integrated Circuit High Density Capacitors - The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.01-26-2012
20130193556SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a capacitor region and a resistor region. A capacitor dielectric material and a capacitor electrode are sequentially stacked on an active region in the capacitor region of the semiconductor substrate. A resistor is provided on the resistor region of the semiconductor substrate. A protection pattern is provided on a top surface of the capacitor electrode. The protection pattern is spaced apart from the capacitor electrode. The protection pattern and the resistor include the same material and have the same thickness in a direction vertical to a surface of the semiconductor substrate.08-01-2013
20130193554Cell Array with Density Features - A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.08-01-2013
20130193555Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a capacitor within a trench in a workpiece, the capacitor comprising a bottom electrode, a dielectric layer disposed over the bottom electrode, and a top electrode disposed over the dielectric layer. A cap layer is formed over the capacitor. Forming the capacitor and forming the cap layer comprise optimizing at least one of: a width of the trench, a thickness of the bottom electrode, a thickness of the dielectric layer, a thickness of the top electrode, and a thickness of the cap layer, so that the cap layer completely covers the top electrode.08-01-2013
20120025349SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.02-02-2012
20120025347Method of forming a MIM capacitor - An embedded memory system includes an array of dynamic random access memory (DRAM) cells, on the same substrate as an array of logic transistors. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The eDRAM system includes fewer metal layers in the logic area than in the memory area02-02-2012
20120056299Integrated Capacitor Comprising an Electrically Insulating Layer Made of an Amorphous Perovskite-Type Material and Manufacturing Process - An integrated capacitor comprises a layer of dielectric material known as functional dielectric material based on crystallized material of perovskite type, between at least one first electrode known as a bottom electrode at the surface of a substrate and at least one second electrode known as a top electrode, said electrodes being electrically insulated by a layer of electrically insulating material in order to allow at least one contact on the top electrode. The electrically insulating material is made of an amorphous dielectric material of perovskite type having a dielectric constant lower than that of the crystallized material of perovskite type. The contact is formed from an etched contacting layer in contact with the electrically insulating dielectric layer level with its surface parallel to the plane of the layers. A process for manufacturing such an integrated capacitor is also provided.03-08-2012
20130200489CAPACITOR ARRAYS FOR MINIMIZING GRADIENT EFFECTS AND METHODS OF FORMING THE SAME - Semiconductor devices having capacitor arrays and methods of forming the same. A semiconductor device is formed including a capacitor array. The capacitor array includes a plurality of operational capacitors formed along a diagonal of the capacitor array. The capacitor array also includes a plurality of dummy capacitors formed substantially symmetrically about the plurality of operational capacitors in the capacitor array. A first operational capacitor is formed at a first edge of the capacitor array. Each one of the plurality of operational capacitors is electrically coupled to a non-adjacent other one of the plurality of operational capacitors.08-08-2013
20130200491METHOD OF MANUFACTURING CAPACITOR, CAPACITOR AND METHOD OF FORMING DIELECTRIC FILM FOR USE IN CAPACITOR - Provided are a method of manufacturing a capacitor capable of achieving a high dielectric constant property and a low leakage current, a capacitor, and a method of forming a dielectric film used in the capacitor. The capacitor is fabricated by forming a lower electrode layer on a substrate; forming a first TiO08-08-2013
20130200490Capacitor Structure and Method of Forming the Same - Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N08-08-2013
20120061798HIGH CAPACITANCE TRENCH CAPACITOR - A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.03-15-2012
20130099354CAPACITOR WITH DEEP TRENCH ION IMPLANTATION - An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.04-25-2013
20120068307SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.03-22-2012
20120086104ATOMIC LAYER DEPOSITION OF CRYSTALLINE PrCaMnO (PCMO) AND RELATED STRUCTURES AND METHODS - Methods of forming a PrCaMnO (PCMO) material by atomic layer deposition. The methods include separately exposing a surface of a substrate to a manganese-containing precursor, an oxygen-containing precursor, a praseodymium-containing precursor and a calcium-containing precursor. The resulting PCMO material is crystalline. A semiconductor device structure including the PCMO material, and related methods, are also disclosed.04-12-2012
20120086103TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE - A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.04-12-2012
20130207231DIELECTRIC FILM WITH NANOPARTICLES - A dielectric film is produced by applying a fluid solvent to a layer of nanoparticles and then polymerizing the solvent between the nanoparticles, or by disposing dielectric nanoparticles in a carrier fluid including a polymerizable substance, applying the resulting fluid to a substrate, and polymerizing a polymerizable substance between the nanoparticles so that the polymerizable substance solidifies to form the dielectric film including the solidified polymerizable substance and the nanoparticles between which the solidified polymerizable substance is disposed. A dielectric film can include nanoparticles and polymer material between at least some of the nanoparticles. The film can have a capacitance change of within 0%-7% over the range 20° C.-125° C. and a dielectric constant between 17.5 and 25 for the range 100 Hz-1 MHz.08-15-2013