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Including programmable passive component (e.g., fuse)

Subclass of:

257 - Active solid-state devices (e.g., transistors, solid-state diodes)

257499000 - INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS

257528000 - Passive components in ICs

Patent class list (only not empty are listed)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
257530000 Anti-fuse 70
Entries
DocumentTitleDate
20130043556SIZE-FILTERED MULTIMETAL STRUCTURES - A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.02-21-2013
20130026601Semiconductor Device and Method for Manufacturing a Semiconductor - A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.01-31-2013
20080258256SEMICONDUCTOR ELECTRICALLY PROGRAMMABLE FUSE ELEMENT WITH AMORPHOUS SILICON LAYER AFTER PROGRAMMING AND METHOD OF PROGRAMMING THE SAME - A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.10-23-2008
20130037908Galvanic Isolation Fuse and Method of Forming the Fuse - The spikes in current and voltage that result from the failure of a galvanic dielectric layer are safely contained by a galvanic isolation fuse that pops and forms and open circuit between a high-voltage die and a low-voltage die in response to the failure of the galvanic dielectric layer.02-14-2013
20130082349SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device capable of preventing, in a SOG etch back planarization process in a multi-layered wiring process, degradation in long-term reliability with respect to the entering of moisture caused by a fuse opening portion. A fuse is shaped so that polycrystalline silicon extends to a lower part of a guard ring provided in a first layer of metal for preventing the entering of moisture from the fuse opening portion. Thus, a metal wiring used for connection to an electrode of the fuse and a metal wiring of the guard ring become equal in height, and hence an SOG layer can be prevented from reaching the inside of an IC.04-04-2013
20090256235Semiconductor device - A semiconductor device (10-15-2009
20100117191SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device that shows excellent manufacturing stability and has lower contact resistance, and a method for manufacturing the semiconductor device.05-13-2010
20130075858SEMICONDUCTOR DEVICE - A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.03-28-2013
20130082350SILICON-ON-INSULATOR CHIP HAVING MULTIPLE CRYSTAL ORIENTATIONS - A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a portion of the insulating layer, and the strained silicon layer is disposed on another portion of the insulating layer and has a crystal orientation different from the first crystal orientation.04-04-2013
20130082348Structure and Method to Form Passive Devices in ETSOI Process Flow - Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon.04-04-2013
20130082347One Time Programmable Structure Using a Gate Last High-K Metal Gate Process - An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.04-04-2013
20090045484METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES - An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.02-19-2009
20100327402FUSE STRUCTURE FOR HIGH INTEGRATED SEMICONDUCTOR DEVICE - The present invention provides a technology capable of improving an operation reliability of a semiconductor device. Particularly, a fuse material which constitutes the copper can be prevented from migrating being locked in the recesses or the grooves after a blowing process. A semiconductor device includes an insulating layer including a concave-convex-shaped upper part; and a fuse formed on the insulating layer.12-30-2010
20110001210FUSE PART IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A fuse part in a semiconductor device includes a conductive pattern formed over a substrate, wherein the conductive pattern includes a blowing part and a pad part, making contact with both sides of the blowing part and having a larger thickness than that of the blowing part, a protection layer formed over the substrate having the conductive pattern, and a fuse box formed in the protection layer located on an upper portion of the blowing part, wherein a portion of the protection layer maintains a certain thickness over the blowing part.01-06-2011
20100133651SEMICONDUCTOR STRUCTURE PROCESSING USING MULTIPLE LATERALLY SPACED LASER BEAM SPOTS WITH JOINT VELOCITY PROFILING - A method is used in processing structures on or within a semiconductor substrate using N series of laser pulses to obtain a throughput benefit, wherein N≧2. The structures are arranged in a plurality of substantially parallel rows extending in a generally lengthwise direction. The N series of laser pulses propagate along N respective beam axes until incident upon selected structures in N respective distinct rows. The method determines a joint velocity profile for simultaneously moving in the lengthwise direction the N laser beam axes substantially in unison relative to the semiconductor substrate so as to process structures in the N rows with the respective N series of laser pulses, whereby the joint velocity profile is such that the throughput benefit is achieved while ensuring that the joint velocity profile represents feasible velocities for each of the N series of laser pulses and for each of the respective N rows of structures processed with the N series of laser pulses. A semiconductor substrate is designed to have a structure layout that takes advantage of the N-fold processing parallelism provided by the N laser beams.06-03-2010
20100133649Contact efuse structure, method of making a contact efuse device containing the same, and method of making a read only memory containing the same - A contact efuse structure includes a silicon layer and a contact contacting the silicon layer with one end. When a voltage is applied to the contact, a void is formed at the end of the contact, and thus the contact is open. Such structure may be utilized in an efuse device or a read only memory. A method of making a contact efuse device and a method of making a read only memory are also disclosed.06-03-2010
20090302418FUSE STRUCTURE OF A SEMICONDUCTOR DEVICE - Provided is a fuse structure of a semiconductor device. The fuse structure may include an insulating layer pattern structure, a fuse and a protecting layer pattern. The insulating layer pattern structure may be formed on a substrate. The insulating layer pattern structure may have an opening. The fuse may be formed in the opening. The protecting layer pattern may be formed in the opening of the insulating layer pattern structure to cover the fuse.12-10-2009
20090302416Programmable Electrical Fuse - The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.12-10-2009
20090302417STRUCTURE AND METHOD TO FORM DUAL SILICIDE E-FUSE - An e-fuse structure and method has anode, a fuse link, and a cathode. The first end of the fuse link is connected to the anode and the second end of the fuse link opposite the first end is connected to the cathode. This structure also includes a first silicide layer on the anode and the fuse link and a second silicide layer, different than the first silicide layer, on the cathode. The difference between the first silicide layer and the second silicide layer causes an enhanced flux divergence region at the second end of the fuse link.12-10-2009
20120217613Programmable Fuse - According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.08-30-2012
20110006391SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of stacked semiconductor chips; and a plurality of through-silicon vias (TSVs) including first TSVs and redundant TSVs and configured to commonly transfer a signal to the plurality of stacked semiconductor chips. At least one of the semiconductor chips includes a plurality of repair fuse units configured to store defect information as to at least one defect of the TSVs; and a plurality of latch units allocated to the respective TSVs and configured to store a plurality of signals indicating at least one TSV defect and outputted from the plurality of repair fuse units.01-13-2011
20130056846SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating film formed above a semiconductor substrate, a fuse formed above the first insulating film, a second insulating film formed above the first insulating film and the fuse and including an opening reaching the fuse, and a third insulating film formed above the second insulating film and in the opening.03-07-2013
20090294900Fuse Device - Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.12-03-2009
20100084737Tunable Semiconductor Component Provided with a Current Barrier - This invention pertains to a color coatings blender apparatus to be used for color composition customization for the application of color coatings on 2D and 3D surfaces. The apparatus is comprised of a main body and interchangeable inserts all with central blender chambers and primary and secondary ports, and interchangeable spindles; the configurations of which are governed by coating technical characteristics. This invention integrates gradient specific programmable computer digital processes to function as internal editors, manipulate information and present the operator with multiple options and production overrides. This invention will make data analysis more interactive by utilizing existing external software applications as editors and expanding the process of visual communications for multiple purposes. While the blender apparatus, complete with external selectable appurtenances, can be used manually, it can also be combined with a programmable computer for producing physical gradient layers.04-08-2010
20090267181SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device with a fuse 10-29-2009
20090267180SEMICONDUCTOR DEVICE HAVING A REDUCED FUSE THICKNESS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device that has a reduced fuse thickness without compromising the bondability of an associated pad and a method for manufacturing the same is described. The semiconductor device includes a pad and a fuse formed on a planar level. The pad and fuse are formed using a metal according to the metal used for the planar level on which the pad and fuse are formed. The pad is formed such that the center portion of the pad is positioned lower than that of the fuse. During the opening of the pad, the thickness of the fuse is reduced without reducing the thickness of the pad. A subsequent repair process can then be easily performed on the fuse having the reduced thickness without degrading the bondability of the pad.10-29-2009
20090267179SYSTEM FOR POWER PERFORMANCE OPTIMIZATION OF MULTICORE PROCESSOR CHIP - A system in one embodiment includes a multiprocessor chip comprising a plurality of cores; a plurality of power circuits, each power circuit being coupled to one of the cores; and an electrically programmable fuse in each power circuit. Each electrically programmable fuse further comprises a first electrode coupled to the associated power circuit; a second electrode coupled to the associated power circuit; a first pad coupled to the first electrode; a second pad coupled to the second electrode; and an electrically conductive material extending between the first and second electrodes and forming part of the associated power circuit, the electrically conductive material being characterized as tending to electromigrate from one of the electrodes to the other electrode under an applied electrical current passing between the electrodes, wherein the electromigration increases an overall resistance of the power circuit.10-29-2009
20090236687Fuse of Semiconductor Device and Method for Forming the Same - A method for forming a fuse of a semiconductor device includes performing an ion-implanting process at sides of a fuse blowing region of a metal fuse, thereby increasing the concentration of impurity ions of a thermal transmission path region. In a subsequent laser blowing process, as a result of the increased resistance of metal fuse the electric and thermal conductivity is reduced, thereby increasing the thermal condensation efficiency of the fuse blowing region and improving the efficiency of the laser blowing process.09-24-2009
20090051002ELECTRICAL FUSE HAVING A THIN FUSELINK - A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.02-26-2009
20100072571EFFECTIVE EFUSE STRUCTURE - An electrically programmable fuse (eFuse) comprises a semiconductor layer, a silicide layer overlying the semiconductor layer, and first and second contact structures electrically coupled to the silicide layer. The first contact structure is configured to function as an anode and the second contact structure is configured to function as a cathode. The eFuse further comprises a back-gate structure disposed underneath the semiconductor layer in a back-gate structure region proximate the second contact structure, the back-gate structure region excluding a region proximate the first contact structure. Responsive to (i) a programming voltage potential supplied between the first and second contact structures and (ii) a voltage potential supplied to the back-gate structure, silicide of the silicide layer operates to migrate, with an enhanced migration, into the semiconductor layer from the cathode to the anode with an absence of silicide residue in at least the back-gate structure region of the semiconductor layer between the first and second contact structures.03-25-2010
20110018091FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE - A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.01-27-2011
20080290455SEMICONDUCTOR DEVICE AND METHOD OF BLOWING FUSE THEREOF - A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region.11-27-2008
20120133018SEMICONDUCTOR DEVICE AND METHOD OF REPAIRING THE SAME - A method of repairing a semiconductor device includes forming a first conductive interconnection and a second conductive interconnection spaced from the first conductive interconnection on a semiconductor substrate, forming a magnetic fuse on the first conductive interconnection and forming a first contact plug on the second conductive interconnection, forming a metal interconnection on the magnetic fuse and the first contact plug, and applying a bias to the first conductive interconnection or to the second conductive interconnection corresponding to a normal cell or a redundancy cell and the metal interconnection. The method can readily prevent the problems caused in a laser cutting method without using a method of physically cutting a fuse by radiation of a laser when a semiconductor device fuse is repaired.05-31-2012
20110278695Semiconductor device - A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.11-17-2011
20110140234FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse of a semiconductor device comprises: a first insulating film formed over a semiconductor substrate; a conductive pattern formed over the first insulating film; a fuse metal formed over the conductive pattern; a contact plug electrically coupling the conductive pattern and the fuse metal; and an energy absorbent pattern formed in the first insulating film and located below an area where the contact plug and the conductive pattern are interconnected. The fuse of the semiconductor device includes a void and a step difference in the lower portion of the contact connected to the fuse pattern. As a result, an energy of a laser applied in the blowing process is absorbed in the void or the step difference, which does not affect peripheral patterns, thereby preventing defects.06-16-2011
20120001295Semiconductor Device Comprising High-K Metal Gate Electrode Structures and Precision eFuses Formed in the Active Semiconductor Material - In a complex semiconductor device, electronic fuses may be formed in the active semiconductor material by using a semiconductor material of reduced heat conductivity selectively in the fuse body, wherein, in some illustrative embodiments, the fuse body may be delineated by a non-silicided semiconductor base material.01-05-2012
20110284988ELECTRICAL FUSE DEVICE - The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.11-24-2011
20090166801FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse blowing process, thereby improving repair efficiency.07-02-2009
20080217735Metal e-Fuse structure design - An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line.09-11-2008
20090090993SINGLE CRYSTAL FUSE ON AIR IN BULK SILICON - An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is removed by selective etching. Whereby a “floating” silicide eFUSE conductor is formed on a silicon beam structure. In its initial state, the eFUSE silicide is highly conductive, exhibiting low electrical resistance (the “unblown state of the eFUSE). When a sufficiently large current is passed through the eFUSE conductor, localized heating occurs. This heating causes electromigration of the silicide into the silicon beam (and into surrounding silicon, thereby diffusing the silicide and greatly increasing its electrical resistance. When the current source is removed, the silicide remains permanently in this diffused state, the “blown” state of the eFUSE.04-09-2009
20110298087ELECTRICAL FUSE DEVICE BASED ON A PHASE-CHANGE MEMORY ELEMENT AND CORRESPONDING PROGRAMMING METHOD - A fuse device has a fuse element provided with a first terminal and a second terminal and an electrically breakable region, which is arranged between the first terminal and the second terminal and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal from the second terminal. The electrically breakable region is of a phase-change material, in particular a chalcogenic material, for example GST.12-08-2011
20110298086Fuse Structures, E-Fuses Comprising Fuse Structures, and Semiconductor Devices Comprising E-Fuses - A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.12-08-2011
20110291230Fuse of a Semiconductor Device - A method for forming a fuse of a semiconductor device includes performing an ion-implanting process at sides of a fuse blowing region of a metal fuse, thereby increasing the concentration of impurity ions of a thermal transmission path region. In a subsequent laser blowing process, as a result of the increased resistance of metal fuse the electric and thermal conductivity is reduced, thereby increasing the thermal condensation efficiency of the fuse blowing region and improving the efficiency of the laser blowing process.12-01-2011
20110291229SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.12-01-2011
20100213569INTEGRATED CIRCUITS HAVING FUSES AND SYSTEMS THEREOF - An integrated circuit includes a fuse over a substrate. The fuse has a first end, a second end, and a central portion between the first end and the second end. A first dummy pattern is disposed adjacent to each side of the central portion of the fuse.08-26-2010
20090014829Semiconductor fuse box and method for fabricating the same - A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.01-15-2009
20080283963Electrical Fuse Circuit for Security Applications - A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.11-20-2008
20090212389SEMICONDUCTOR DEVICE WITH CAPACITOR AND FUSE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device with a capacitor and a fuse, and a method for manufacturing the same are described. The semiconductor device comprises a semiconductor substrate having a capacitor region and a fuse region defined therein, a insulating layer over the semiconductor substrate, a storage node hole formed in the insulating layer, a barrier metal in the storage node hole, a dielectric layer formed on the barrier metal and the insulating layer, a lower metal layer for a plate electrode filling the storage node hole such that it is flush with the dielectric layer, an upper metal layer for the plate electrode on the dielectric layer and lower metal layer for the plate electrode; and a fuse metal layer formed of the same material as that of the upper metal layer for the plate electrode on the dielectric layer in the fuse region.08-27-2009
20090166802SEMICONDUCTOR DEVICE WITH FUSE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor with a fuse includes providing a substrate, forming an insulation layer over the substrate, forming a polysilicon hard mask to form a metal contact over the insulation layer, forming a first mask pattern to form a fuse over the polysilicon hard mask, and removing the polysilicon hard mask exposed by the first hard mask pattern to form a polysilicon fuse connected to a portion of the polysilicon hard mask.07-02-2009
20100032797Electrical fuse and semiconductor device - An electrical fuse comprises: an interconnect to be cut; and a first terminal and a second terminal which are respectively provided at both ends of the interconnect to be cut. The interconnect to be cut comprises: a first orientation film which contains copper as a main component and is oriented in a (111) plane; and a second orientation film which contains copper as a main component and is oriented in a (511) plane. The second orientation film is provided inside the first orientation film over a width direction of the first orientation film, which is perpendicular to a direction from the first terminal toward the second terminal, so as to partition the first orientation film. Accordingly, it becomes possible to securely cut the electrical fuse whose constituent material is copper, and moreover, to maintain a satisfactory cut state of the electrical fuse after the cutting.02-11-2010
20090273055Fuse Structure - An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.11-05-2009
20120187528FINFET FUSE WITH ENHANCED CURRENT CROWDING - A method forms an eFuse structure that has a pair of adjacent semiconducting fins projecting from the planar surface of a substrate (in a direction perpendicular to the planar surface). The fins have planar sidewalls (perpendicular to the planar surface of the substrate) and planar tops (parallel to the planar surface of the substrate). The tops are positioned at distal ends of the fins relative to the substrate. An insulating layer covers the tops and the sidewalls of the fins and covers an intervening substrate portion of the planar surface of the substrate located between the fins. A metal layer covers the insulating layer. A pair of conductive contacts are connected to the metal layer at locations where the metal layer is adjacent the top of the fins.07-26-2012
20100109122METHOD TO REDUCE METAL FUSE THICKNESS WITHOUT EXTRA MASK - Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.05-06-2010
20090146250Semiconductor device - A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.06-11-2009
20110079873SEMICONDUCTOR DEVICE - A semiconductor device includes a base insulating film on which a silicon fuse, silicon wiring patterns, and a silicon guard ring are formed. The silicon guard ring surrounds the silicon fuse and has silicon cutout parts so as not to contact the silicon wiring patterns. A via guard ring, which has via cutout parts located above the silicon cutout parts, is formed in an interlayer insulating film and on the silicon guard ring. A metal wiring guard ring is formed on the via guard ring and the interlayer insulating film. A silicon nitride film is formed on the interlayer insulating film so as to cover the metal wiring guard ring. An interface between the interlayer insulating film and the metal wiring guard ring at the via cutout parts is covered by the silicon nitride film.04-07-2011
20110147886SEMICONDUCTOR DEVICE WITH FUSE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor with a fuse includes providing a substrate, forming an insulation layer over the substrate, forming a polysilicon hard mask to form a metal contact over the insulation layer, forming a first mask pattern to form a fuse over the polysilicon hard mask, and removing the polysilicon hard mask exposed by the first hard mask pattern to form a polysilicon fuse connected to a portion of the polysilicon hard mask.06-23-2011
20090309184STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING - An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.12-17-2009
20090278228DESIGN STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS - A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.11-12-2009
20080211058Semiconductor device and method of manufacturing same - A semiconductor device comprises one or more elements subjected to trimming, formed on a main surface side of a silicon substrate and that is/are to be laser trimmed, and an electrode lead of the element subjected to trimming disposed below the position of the element subjected to trimming. The electrode lead subjected to trimming comprises a diffusion layer formed in an uppermost layer of the silicon substrate. The diffusion layer is covered with a protection film made of doped polysilicon and is directly formed on the silicon substrate.09-04-2008
20080211059ELECTRONIC FUSE HAVING HEAT SPREADING STRUCTURE - A semiconductor device includes a fuse transistor for fuse programming and a fuse block connected to the fuse transistor, wherein the fuse block comprises a fuse line and a heat spreading structure connected to the fuse line. The electrical fuse employs the heat spreading structure connected to the fuse line to prevent a rupture of the electrical fuse such that heat, which is generated in the fuse line during a blowing of the fuse line, is spread throughout the heat spreading structure. Thus, a sensing margin of the electrical fuse can be secured and a deterioration of devices adjacent to the electrical fuse by heat generated in the electrical fuse can be prevented.09-04-2008
20100123212Semiconductor device and method of manufacturing the same - Provided are a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device may include first and second conductive lines separated from each other on a semiconductor substrate; a fuse line on the first and second conductive lines; a first conductive via between the fuse line and the first conductive line and a second conductive via between the fuse line and the second conductive line; and a dummy conductive via disposed between the first and second conductive vias, the dummy conductive via being connected to the fuse line so that a portion of the dummy conductive via is removed together with a portion of the fuse line when the fuse line is cut.05-20-2010
20090273054Non-volatile memory device and method of fabricating the same - A non-volatile memory device and methods of fabricating the device according to example embodiments involve a stacked layer structure. The non-volatile memory device may include at least one first horizontal electrode including a first sidewall and a second sidewall; at least one second horizontal electrode including a third sidewall and a fourth sidewall; wherein the third sidewall may be disposed to face the first sidewall; at least one vertical electrode may be interposed between the first sidewall and the third sidewall, in such a way as to cross or intersect each of the at least one first and second horizontal electrodes, and; at least one data storage layer that may be capable of locally storing a change of electrical resistance may be interposed where the at least one first horizontal electrode and the at least one vertical electrode cross or intersect and where the at least one horizontal electrode and the at least one vertical electrodes cross or intersect.11-05-2009
20110198722SEMICONDUCTOR PACKAGE THROUGH-ELECTRODE SUITABLE FOR A STACKED SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package including a through-electrode for stacked a semiconductor package and a semiconductor package having the same is disclosed. The semiconductor package through-electrode includes a first electrode having a recessed portion formed therein to pass through a semiconductor chip. A second electrode is disposed within the recess of the first electrode. The first electrode of the semiconductor package through-electrode includes a first metal having a first hardness, and a second electrode comprises a second metal having a second hardness lower than the first hardness. The through-electrode passes through the semiconductor chip body and may be formed with the first metal having the first hardness and/or a first melting point and the second metal having the second hardness and/or a second melting point which are lower than the first hardness and/or the first melting point. This through-electrode allows a plurality of semiconductor packages to be easily stacked.08-18-2011
20090278229EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS - A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element.11-12-2009
20090294902SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, an insulating film formed over the substrate, first and second conductive plugs formed in the insulating film, a capacitor element, and a wiring. The capacitor element includes a lower electrode, a dielectric film, and an upper electrode. The lower electrode is connected to an end of the first plug and formed on the insulating film, and includes a first barrier film. The dielectric film is formed on upper and side surfaces of the lower electrode. The upper electrode is formed on the dielectric film, and includes a second barrier metal film being wider than the lower electrode. The wiring is connected to an end of the second plug and formed on the insulating film, and includes a first layer and a second layer formed on the first layer. The first and second layers include the first and second barrier metal films, respectively.12-03-2009
20090261450Electrical Fuse Structure and Method - An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.10-22-2009
20110266653SEMICONDUCTOR DEVICE HAVING A FUSE ELEMENT - A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.11-03-2011
20080246113SEMICONDUCTOR DEVICE INCLUDING REDISTRIBUTION LINE STRUCTURE AND METHOD OF FABRICATING THE SAME - The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.10-09-2008
20100327400FUSE STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor device includes a fuse box including a plurality of fuses and a plurality of common nodes, wherein paired fuses among the plurality of fuses are aligned in a first direction and the plurality of common nodes between fuses of each of the pairs at a different height is aligned in a second direction perpendicular to the first direction.12-30-2010
20090166803SEMICONDUCTOR DEVICE WITH FUSE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor with a fuse includes providing a substrate, forming an insulation layer over the substrate, forming a polysilicon hard mask to form a metal contact over the insulation layer, forming a first mask pattern to form a fuse over the polysilicon hard mask, and removing the polysilicon hard mask exposed by the first hard mask pattern to form a polysilicon fuse connected to a portion of the polysilicon hard mask.07-02-2009
20090001506DUAL STRESS LINER EFUSE - A semiconductor fuse structure comprises an anode connected to a first end of a fuse link, a cathode connected to a second end of the fuse link opposite the first end of the fuse link, a compressive (nitride) liner covering the anode, and a tensile (nitride) liner covering the cathode. The compressive liner and the tensile liner are positioned to cause a net stress gradient between the cathode and the anode, wherein the net stress gradient promotes electromigration from the cathode and the fuse link to the anode.01-01-2009
20080277756ELECTRONIC DEVICE AND METHOD FOR OPERATING A MEMORY CIRCUIT - An electronic device is disclosed having a dielectric layer (11-13-2008
20080296726Fuse Structure for Maintaining Passivation Integrity - A fuse structure (12-04-2008
20080290454SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor integrated circuit device includes a plurality of metal wirings which are separated from one another with respective interlayer insulating films; at least one interlayer conductor for connecting adjacent ones of the metal wirings via the corresponding one of the interlayer insulating films; at least one functional element formed above a semiconductor substrate and between adjacent ones of the interlayer insulating films; and at least one dummy metal portion which is formed above and/or below the functional element via at least one of the interlayer insulating films so as to be located inside the at least one interlayer conductor.11-27-2008
20080308901Integrated circuit having a thin passivation layer that facilitates laser programming, and applications thereof - An integrated circuit having a thin passivation layer that facilitates laser programming, and applications thereof. In an embodiment, the integrated circuit includes a metal layer that has at least one fuse. A passivation layer is deposited over the metal layer. The passivation layer has a thickness that is less than 4,500 angstroms in order to enable laser programming of the at least one fuse without having to etch the passivation layer in the area of the at least one fuse prior to laser programming. In embodiments, the passivation layer has a thickness that is in a range of about 2,000 angstroms to about 4,000 angstroms, and the metal layer includes copper metal conductors that are protected by a barrier metal such as, for example, titanium nitride (TiN) or silicon nitride (SiN).12-18-2008
20080308900ELECTRICAL FUSE WITH SUBLITHOGRAPHIC DIMENSION - A photolithography mask contains at least one sublithographic assist feature (SLAF) such that the image of the fuselink shape on a photoresist contains a constructive interference portion and two neck portions. The width of the constructive interference portion is substantially the same as a critical dimension of the lithography tool and the widths of the two neck portions are sublithographic dimensions. The image on a photoresist is subsequently transferred into an underlying semiconductor layer to form an electrical fuse. The fuselink contains a constructive interference portion having a first width which is substantially the same as the critical dimension of the lithography tool and two neck portions having sublithographic widths. The inventive electrical fuse may be programmed with less voltage bias, current, and energy compared to prior art electrical fuses.12-18-2008
20080315355SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device in accordance with the present invention includes a fuse formed on a substrate; a first insulator film provided so as to cover the fuse; cavity-forming pattern provided in the layer on the first insulator film; and second insulator film provided so as to cover the cavity-forming pattern, wherein the cavity-forming pattern is patterned so that a spatial area is produced therebetween and the second insulator film covers the cavity-forming pattern so that a cavity is produced in the spatial area.12-25-2008
20080237787SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention aims at offering the semiconductor integrated circuit which can perform reliable relief processing using an electric fuse.10-02-2008
20080277757BALLASTED POLYCRYSTALLINE FUSE - A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to form first and second terminal portions of a first width joined along a length of the fuse by a fuse portion of a second width narrower than the first width. First and second contacts are connected to the first and second terminal portions respectively. The silicide material being discontinuous in a terminal region of the second layer along the length of the fuse.11-13-2008
20110006392SEMICONDUCTOR DEVICE - The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered.01-13-2011
20080258255Electromigration Aggravated Electrical Fuse Structure - A fuse structure with aggravated electromigration effect is disclosed, which comprises an anode area overlaying a first plurality of contacts that are coupled to a positively high voltage during a programming of the fuse structure, a cathode area overlaying a second plurality of contacts that are coupled to a complementary low voltage during a programming of the fuse structure, and a fuse link area having a first and second end, wherein the first end contacts the anode area at a predetermined distance to the nearest of the first plurality of contacts, and the second end contacts the cathode area at the predetermined distance to the nearest of the second plurality of contacts, wherein the cathode area is smaller than the anode area for the aggravating electromigration effect.10-23-2008
20100193903THREE DIMENSIONAL SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND ELECTRICAL CUTOFF METHOD FOR USING FUSE PATTERN OF THE SAME - Provided is a three-dimensional semiconductor device. The three-dimensional semiconductor device includes a body in which a plurality of semiconductor chips or packages are stacked, a protective substrate configured to protect an outer layer chip or package of the body and configured to transmit a laser beam, and a fuse pattern portion having a pattern of a fuse function formed to cut off an electrical connection of a defective chip or package by the laser beam penetrating the protective substrate when at least one of the chips or packages is defective.08-05-2010
20090026575SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device which substantially prevents repair failure and a method of manufacturing the same. The semiconductor device includes a plurality of first fuses formed apart from each other on a semiconductor substrate, and on which a protective layer is formed; a first insulating layer filled in between the first fuses and configured to expose the protective layer; a plurality of second fuses formed between the first fuses and on the first insulating layer; and a second insulating layer formed on the first insulating layer, wherein the second insulating layer includes a fuse window configured to fully expose the second fuses and the protective layer formed on the first fuses.01-29-2009
20090184391Semiconductor devices having fuses and methods of forming the same - Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.07-23-2009
20090140382ELECTRIC FUSE DEVICE MADE OF POLYSILICON SILICIDE - A polysilicon silicide electric fuse device, comprising: a substrate; a semiconductor material layer disposed on said substrate, said semiconductor material layer includes lead-out areas of the same doping type at both ends, and an intermediate area of non-doping or having dopant concentration lower than those of said lead-out areas at both ends; and one or more burn-out areas is/are provided in said intermediate area; and a metal silicide layer is provided on said semiconductor material layer. Through the application of said polysilicon silicide electric fuse device, the burning out of said fuse device is thus controlled to within said intermediate area of no doping or light doping, hereby increasing the mean value and reducing distribution area of electrical resistance after burning out of a fuse, and alleviating the overheating of surrounding areas as caused by a current during the burning out of a fuse.06-04-2009
20090001508Semiconductor device including fuse elements and bonding pad - A semiconductor device includes a lower-layer substrate, a fuse above the lower-layer substrate and blown by radiation with light, a silicon oxide film on the fuse and on an exposed portion of the surface of the lower-layer substrate, and a silicon nitride film on the silicon oxide film. The portion of the silicon oxide film on the surface of the lower-layer substrate is thicker than the fuse, and the silicon oxide film has an opening opposite the fuse.01-01-2009
20100276782SEMICONDUCTOR DEVICE MOUNTED WITH FUSE MEMORY - A fuse element utilizing a reaction between two layers by feeding current is manufactured. A fuse element including a first layer formed of an oxide or a nitride and a second layer that becomes high resistant by nitridation or oxidation, in which the first layer and the second layer are in contact with each other, is manufactured. For example, the fuse element is manufactured by using indium tin oxide for the first layer and aluminum for the second layer. By generating joule heat by applying voltage to the first layer and the second layer, oxygen in the indium tin oxide enters the aluminum, which changes the aluminum into aluminum oxide that presents an insulating property. The fuse element can be manufactured by a similar process as that of forming a TFT.11-04-2010
20090206446Electrical Device and Fabrication Method - An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.08-20-2009
20110140235SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device include an insulating interlayer formed over a substrate; an electrical fuse which is composed of a first wiring formed in the insulating interlayer, and has a cutting portion; and a second wiring and a third wiring, formed respectively on both sides of the cutting portion to extend along the cutting portion in the same layer as the first wiring. Air gaps formed to extend along the cutting portion are respectively provided between the cutting portion and the second wiring and between the cutting portion and the third wiring.06-16-2011
20090085152THREE DIMENSIONAL VERTICAL E-FUSE STRUCTURES AND METHODS OF MANUFACTURING THE SAME - Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.04-02-2009
20090051003Methods and Structures Involving Electrically Programmable Fuses - A method for fabricating an eFuse, the method comprising disposing a crystalline silicon eFuse on a substrate having a fuse link portion, a first contact portion, and a second contact portion, wherein the fuse link is oriented parallel to the silicon crystal {02-26-2009
20080315354FUSE FOR SEMICONDUCTOR DEVICE - Embodiments relate to a fuse for a semiconductor device. To maintain a stable blowing characteristic with a minimized applied current, the fuse includes a fuse line having a blowing characteristic dependent on applied current. A first contact pad has a plurality of contacts connected to one side of the fuse line. A second contact pad has a plurality of contacts connected to the other side of the fuse line. The first and second contact pads have an asymmetrical configuration, which may have different ratios of length to width.12-25-2008
20100264514SEMICONDUCTOR DEVICE AND A METHOD OF INCREASING A RESISTANCE VALUE OF AN ELECTRIC FUSE - Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.10-21-2010
20090243033FUSE PART IN SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse part in a semiconductor device has a plurality of fuse lines extended along a first direction with a given width along a second direction. The fuse part includes a first conductive pattern having a space part formed in a fuse line region over a substrate, wherein portions of the first conductive pattern are spaced apart by the space part along the first direction. The fuse part includes a first insulation pattern formed over the space part, the first insulation pattern having a width smaller than a width of the first conductive pattern along the second direction and a thickness greater than a thickness of the first conductive pattern, and a second conductive pattern formed over the first insulation pattern, the second conductive pattern having a width greater than the width of the first insulation pattern along the second direction.10-01-2009
20090243032ELECTRICAL FUSE STRUCTURE - An e-fuse structure includes a cathode block; a plurality of cathode contact plugs on the cathode block; an anode block; a plurality of anode contact plugs on the cathode block; and a fuse link connecting the cathode block with the anode block, wherein a front row of the cathode contact plugs is disposed in close proximity to the fuse link thereby inducing a high thermal gradient at an interface between the cathode block and the fuse link.10-01-2009
20090250786FUSE PART OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A fuse part of a semiconductor device includes an insulation layer over a substrate, and a fuse over the insulation layer, wherein the fuse includes a plurality of blowing pads for irradiating a laser beam and the plurality of blowing pads have laser coordinates different from one another.10-08-2009
20120193755COPPER-BASED METALLIZATION SYSTEM INCLUDING AN ALUMINUM-BASED TERMINAL LAYER - In a copper-based metallization system of a semiconductor device the contact pad, such as a bond pad, is formed on the basis of two lithography steps by depositing the cap metal layer stack directly on any exposed copper surface areas of the last metallization layer. After patterning of the cap layer stack therefore reliable confinement of any exposed metal region is accomplished on the basis of a conductive barrier material, while the actual passivation materials are formed and patterned subsequently, thereby avoiding any negative influence on these materials, as may be the case in some conventional approaches. Moreover, superior mechanical integrity of the contact pad in combination with superior electrical performance of any metal region in the last metallization layer is achieved.08-02-2012
20090121314Manufacturing method for forming an integrated circuit device and corresponding integrated circuit device - The present invention provides a manufacturing method for forming an integrated circuit device and to a corresponding integrated circuit device. The manufacturing method for forming an integrated circuit device comprises the steps of: forming a first level on a substrate; forming a second level above the first level; forming a cap layer on the second level which covers a first region of the level and leaves a second region uncovered; and simultaneously etching a first contact hole in the first region and a second contact hole in the second region such that the etching is selective to the cap layer in the second region and proceeds to a greater depth in the first region.05-14-2009
20100155884MELTING FUSE OF SEMICONDUCTOR AND METHOD FOR FORMING THE SAME - The present invention discloses a fuse of a semiconductor device and manufacturing method thereof. The fuse of a semiconductor device of the present invention includes a first conductive pattern; and a second conductive pattern which is separated from the first conductive pattern with a given gap, wherein the first conductive pattern and the second conductive pattern are melted in a laser irradiation to be connected. Accordingly, the present invention prevents the damage of the adjacent fuse in the repair process, enabling to improve the reliability of device and accomplish the high integration.06-24-2010
20100155885Fuse Corner Pad for an Integrated Circuit - A fuse corner pad is part of an integrated circuit that includes a built-in fuse contact and a plurality of auxiliary pads. The fuse contact is a conductive metallic or metalloid structure that is connected to a fuse element. The fuse contact and fuse element are used inside of the fuse corner pad for programmability (e.g., for security) and/or adjustment (e.g., trimming) of analog and/or digital signals. The fuse contact and fuse element are not required to be bonded to an external electrical connection (such as, a pin or ball). The auxiliary pads provide a variety of functional or non-functional applications, such as testing, probing, programming, and/or circuit adjustment.06-24-2010
20090079028Semiconductor device having fuse with protection capacitor - A semiconductor device has a fuse, an internal circuit and a protection capacitor. The fuse has a first terminal connected to be applied to a fixed voltage and a second terminal. The internal circuit includes a transistor. The transistor has a threshold voltage and a gate. The protection capacitor is connected between the second terminal of the fuse and the gate of the transistor. The protection capacitor supplies the threshold voltage to the transistor where the fuse supplies the fixed voltage to the protection capacitor.03-26-2009
20100187652METHOD AND STRUCTURES OF MONOLITHICALLY INTEGRATED ESD SUPPRESSION DEVICE - This present invention relates in general to protection of integrated circuit chips, and more particularly, to a micromachined suppression device for protecting integrated circuit chips from electrostatic discharges. The proposed ESD suppression device consists of conductive pillars are dispersed in a dielectric material. The gaps between each pillar behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed ESD suppression device is fabricated using micromachining techniques to be on-chip with device ICs.07-29-2010
20100258902METHOD FOR FORMING FUSE IN SEMICONDUCTOR DEVICE - A method for forming a fuse in a semiconductor device is disclosed. The method for forming the fuse in the semiconductor device forms an interlayer insulating layer when forming a fuse, and forms neighboring metal lines having different thicknesses using a zigzag-opened mask, thus preventing a neighboring fuse of a fuse to be blown from being damaged. A method for manufacturing the semiconductor device deposits a first interlayer insulating layer on a semiconductor substrate, patterns the first interlayer insulating layer using a zigzag-opened pad type mask such that the first interlayer insulating layer has different step heights where the same step height is arranged at every second step height location, deposits a second interlayer insulating layer, patterns the second interlayer insulating layer, and buries a metal on an entire surface, and planarizes the metal until the second interlayer insulating layer is exposed, thus forming a metal pattern.10-14-2010
20100013046SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.01-21-2010
20100013045Method of Integrating an Element - The present invention provides a method of integrating a structure, e.g. a fuse, for use in a semiconductor device, the method comprises several steps, the first step is providing a first layer of sacrificial material (01-21-2010
20100193902SEMICONDUCTOR DEVICE INCLUDING FUSE - Provided is a semiconductor device including a fuse, in which a insulating layer surrounding the fuse or metal wiring is prevented from being damaged due to the cut of a fuse, which can occur when a repair process is performed. The semiconductor device includes a conductive line formed on a semiconductor layer, a protective layer formed on the conductive line, one or more fuses that are electrically connected to the conductive line, and a fuse protective layer formed on the one or more fuses, and spaced apart from the protective layer.08-05-2010
20100176483FUSE ELEMENT AND SEMICONDUCTOR INTEGRATED CIRCUIT WITH THE SAME - A fuse element according to the present invention and a semiconductor integrated circuit with the fuse element include interconnects and a via connected to a region for connecting the interconnects. A first angle between a first side surface of the via and the connect region is smaller than a second angle between a second side surface opposite the first side surface and the connect region.07-15-2010
20100237461SEMICONDUCTOR PACKAGE SUBSTRATE INCLUDING FUSES, SEMICONDUCTOR DEVICE PACKAGE, SEMICONDUCTOR MODULE AND ELECTRONIC APPARATUS INCLUDING THE SAME - A semiconductor device package, and a semiconductor module and an electronic apparatus including the semiconductor device package are provided. The semiconductor device package includes a package substrate, first pads and second pads disposed on a first surface of the package substrate and fuses corresponding to the second pads, the fuses being disposed on a second surface of the package substrate. First and second semiconductor chips including a plurality of chip pads are disposed on the first surface of the package substrate and the first pads are electrically connected to both one of the chip pads of the first semiconductor chip and one of the chip pads of the second semiconductor chip, wherein the second pads are selectively electrically connected to one of the chip pads of the first semiconductor chip or one of the chip pads of the second semiconductor chip.09-23-2010
20100224956E-FUSE STRUCTURE OF SEMICONDUCTOR DEVICE - An e-fuse structure includes an anode, a cathode, a fuse part connecting the anode and the cathode to each other, and a dielectric contacting the fuse part. The dielectric is configured to apply a stress to the fuse part, where the stress constructively acting on a migration effect of atoms constituting the fuse part. The migration effect is generated by electromigration and thermomirgration.09-09-2010
20100224955FUSES OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - Devices and methods are disclosed a dielectric interlayer made of materials capable of forming tensile force is formed over a semiconductor substrate, and a fuse metal having stronger tensile force than the first dielectric interlayer is formed over the first dielectric interlayer. Accordingly, formation of fuse residues when blowing a fuse can be prevented. Furthermore, energy and a spot size of a laser applied when blowing a fuse can be reduced. Moreover, damage to neighboring fuses can be prevented, and a fuse made of materials that are difficult to blow the fuse can be cut. Further, since polymer-series materials are used as a dielectric interlayer, the coupling effect between wiring lines can be reduced considerably.09-09-2010
20100237460METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES - An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.09-23-2010
20100252908ELECTRICALLY ALTERABLE CIRCUIT FOR USE IN AN INTEGRATED CIRCUIT DEVICE - An electrically alterable circuit (EAC), suitable for use in an integrated circuit, includes a first interconnect, a link element, and a second interconnect. A first set of interconnect vias provides an electrically conductive connection between the first interconnect and a first end of the link element; A second set of interconnect vias provides an electrically conductive connection between the second interconnect and a second end of the link element. The EAC further includes a third interconnect and a one or more fuse vias that provide an electrical connection between the third interconnect and the link element. A conductance of the one or more fuse vias is less than a conductance of the first set of interconnect vias, a conductance of the second set of interconnect vias, or both.10-07-2010
20110057290FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse of a semiconductor device comprises: a fuse pattern formed on a semiconductor substrate; an insulating film covering one side of the fuse pattern and including a trench; a conductive line disposed on the insulating film including the trench. The fuse of the semiconductor device prevents generation of cracks in a fuse box by thermal and physical stress, thereby improving reliability of the semiconductor device.03-10-2011
20090283853Programmable Devices and Methods of Manufacture Thereof - Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link.11-19-2009
20090236688SEMICONDUCTOR DEVICE HAVING FUSE PATTERN AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.09-24-2009
20090039464SEMICONDUCTOR DEVICE - To protect an internal circuit against ESD breakdown which is caused by exposure of a cut-off portion of a fuse, a separate ESD protection circuit is not provided for each fuse as before, but the internal circuit is efficiently protected by a small number of ESD protection circuits by connecting the ESD protection circuit to a pad arranged for each unit lattice which is set in correspondence with a portion shared by a plurality of fuses, for example, a common wiring connected to the plurality of fuses, and which is set in correspondence with a size of a contact surface of a charged jig, or the like, with a semiconductor chip.02-12-2009
20090039463FUSE BOX AND METHOD FOR FABRICATING THE SAME AND METHOD FOR REPAIRING THE SAME IN SEMICONDUCTOR DEVICE - A fuse box in a semiconductor device having a fuse line formed in a fuse line region to form a conductive pattern; wherein the conductive pattern has an empty space in the center thereof and a phase change material pattern in the empty space, and an insulation pattern formed over the fuse line to expose the phase change material pattern.02-12-2009
20090039462EFUSE DEVICES AND EFUSE ARRAYS THEREOF AND EFUSE BLOWING METHODS - An exemplary embodiment of an efuse device is provided and comprises a plurality of word lines, at least one bit line, a plurality of cells, a plurality of first selection devices, and at least one second selection device. The word lines are interlaced with the bit line. The cells are disposed in an array, and each corresponds to one set of the interlaced word line and bit line. Each first selection device is coupled to one of the word lines, and the second selection device is coupled to the bit line.02-12-2009
20090108396ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE - A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.04-30-2009
20090108398Fuse of Semiconductor Device and Method for Forming the Same - A fuse in a semiconductor device includes: first and second fuse patterns, each being in the shape of a bar, separated from each other in a blowing region; first and second contact plugs respectively coupled to the first and the second fuse patterns; and a third fuse pattern coupled to the first and the second fuse patterns through the first and the second contact plugs.04-30-2009
20090108397THIN FILM DEVICE WITH LAYER ISOLATION STRUCTURE - This invention provides a thin film device with layer isolation structures. Specifically, a plurality of patterned thin film device layers provide a first rail and a second rail. There is at least one overpass between the first rail and the second rail. The overpass is defined by an array of spaced holes disposed transversely through the continuous material of the first rail on either side of the overpass. The holes are in communication with isolation voids adjacent to the second rail adjacent to the overpass.04-30-2009
20100295149Integrated circuit structure with capacitor and resistor and method for forming - An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.11-25-2010
20110121426ELECTRONIC DEVICE WITH FUSE STRUCTURE AND METHOD FOR REPAIRING THE SAME - According to an embodiment of the invention, an electronic device with a fuse structure is provided. The electronic device includes a substrate, at least a conducting layer formed in or on the substrate and having a fuse area, and at least a lens disposed overlying the fuse area of the conducting layer, wherein the lens is substantially aligned with the fuse area and there is no optical device disposed between the lens and the fuse area.05-26-2011
20110108946FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse of a semiconductor device includes a fuse pattern separated by a blowing region formed on an interlayer insulating film, and a recess formed by removing a portion of the upper portion of a plurality of contacts disposed in the lower portion of the blowing region. After the fuse pattern is blown, the fuse pattern moves in the reliable environment, thereby preventing the electric short to improve yield of the semiconductor device.05-12-2011
20100133650Semiconductor device - A semiconductor device includes an electric fuse formed on a substrate. The electric fuse includes: a first interconnect formed on one end side thereof; a second interconnect formed in a layer different from a layer in which the first interconnect is formed; a first via provided in contact with the first interconnect and the second interconnect to connect those interconnects; a third interconnect formed on another end side thereof, the third interconnect being formed in the same layer in which the first interconnect is formed, as being separated from the first interconnect; and a second via provided in contact with the third interconnect and the second interconnect to connect those interconnects, the second via being lower in resistance than the first via. The electric fuse is disconnected by a flowing-out portion to be formed of a conductive material forming the electric fuse which flows outwardly during disconnection.06-03-2010
20110024873SEMICONDUCTOR DEVICE HAVING A FUSE REGION AND METHOD FOR FORMING THE SAME - A semiconductor device having a fuse region, the fuse region includes a conductive pattern and a fuse box formed to partially expose the conductive pattern which have an inclined edge on a bottom surface.02-03-2011
20090085151SEMICONDUCTOR FUSE STRUCTURE AND METHOD - An electrical structure and method of forming. The electrical structure includes a semiconductor substrate, an insulator layer formed over and in contact with the semiconductor substrate, and a semiconductor fuse structure formed over the insulator layer. The fuse structure includes a silicon layer and a continuous metallic silicide layer. The continuous metallic silicide layer includes a first section formed over and in contact with a first horizontal section of a top surface of the silicon layer, a second section formed over and in contact with a second horizontal section of the top surface of the silicon layer, and a third section formed within an opening within the top surface of the silicon layer.04-02-2009
20090102013FUSE BOX AND METHOD OF FORMING THE SAME - A fuse box includes a fuse pattern having a rugged profile and an interlayer insulating film including a fuse blowing window to fill the fuse pattern.04-23-2009
20090218656METHODS OF MAKING SEMICONDUCTOR STRUCTURES INCLUDING VERTICAL DIODE STRUCTURES - Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.09-03-2009
20110241162Semiconductor Device Comprising Metal-Based eFuses of Enhanced Programming Efficiency by Enhancing Heat Generation - In sophisticated semiconductor devices, electronic fuses may be provided in the metallization system, wherein a superior two-dimensional configuration of the metal line, for instance as a helix-like configuration, may provide superior thermal conditions in a central line portion, which in turn may result in a more pronounced electromigration effect for a given programming current. Consequently, the size of the electronic fuse, at least in one lateral direction, and also the width of corresponding transistors connected to the electronic fuse, may be reduced.10-06-2011
20100038747ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD - An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.02-18-2010
20100038748ELECTRIC FUSE CIRCUIT AND ELECTRONIC COMPONENT - An electric fuse circuit is provided which has a capacitor that forms an electric fuse; a write circuit for breaking an insulating film of the capacitor, by applying a voltage to a terminal of the capacitor in response to a write signal; and at least two transistors, including a first transistor and a second transistor, which are connected in series between the capacitor and the write circuit.02-18-2010
20110175192SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern. The conductive polymer layer includes a nano-sized metal powder and a polymer.07-21-2011
20110073986SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a semiconductor integrated circuit device including fuse elements for carrying out laser trimming processing, in which a space width between aluminum interconnects of the first layer to be connected to the adjacent fuse elements is set to less than twice of the thickness of the side wall of the metal interlayer insulating film of the first layer, thereby preventing exposure of the SOG layer having hygroscopic property. In addition, side spacers are provided to side surfaces of the aluminum interconnects of the first layer.03-31-2011
20120199942SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.08-09-2012
20110068432FUSE STRUCTURE FOR HIGH INTEGRATED SEMICONDUCTOR DEVICE - A semiconductor device comprises a fuse having a blowing region at a center part for selectively connecting different two terminals; and a dummy contact positioned under the blowing region for forming empty space by being removed together with the blowing region in a blowing process.03-24-2011
20110248378SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. The semiconductor device includes a first line, a second line spaced apart from the first line, a contact formed over the first line and the second line, a fuse coupled to the contact, and a dummy pattern configured to couple the fuse to the contact.10-13-2011
20080230870INPUT PROTECTION CIRCUIT PREVENTING ELECTROSTATIC DISCHARGE DAMAGE OF SEMICONDUCTOR INTEGRATED CIRCUIT - An input protection circuit comprises a semiconductor chip, an internal circuit disposed on the semiconductor chip, a first input/output terminal which is disposed on the semiconductor chip and connected to the internal circuit, a second input/output terminal which is disposed on the semiconductor chip, connected to the internal circuit and disposed at a position adjacent to the first input/output terminal, and a fusing part which is disposed on the semiconductor chip and connected between the first and second input/output terminals.09-25-2008
20110248379SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having an electrical fuse which is cut in a reliable manner and a method for manufacturing it. The electrical fuse is a multilayer structure which includes a polysilicon film and a metal silicide film such as a tungsten silicide film. By applying an electric current with a density of 40 mA/μm10-13-2011
20080315353EMPTY VIAS FOR ELECTROMIGRATION DURING ELECTRONIC-FUSE RE-PROGRAMMING - The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.12-25-2008
20090230506SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a fuse pattern formed as conductive polymer layer having a low melting point. The fuse pattern is easily cut at low temperature to improve repair efficiency. The semiconductor device includes first and second fuse connecting patterns that are separated from each other by a distance, a fuse pattern including a conductive polymer layer formed between the first and second fuse connection patterns and connecting the first and second fuse connection patterns, and a fuse box structure that exposes the fuse pattern.09-17-2009
20090146251SEMICONDUCTOR DEVICE - The semiconductor device of the present invention comprises a semiconductor substrate; and a conductive element formed on the semiconductor substrate and capable of being opened when a predetermined current flows, wherein the conductive element turns plurality of times.06-11-2009
20090108399APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE INCORPORATING FUSE ELEMENTS - An apparatus and a method for manufacturing semiconductor devices is disclosed for selectively disconnecting a fuse element out of plural fuse elements formed on a semiconductor wafer substrate which is provided with the plural fuse elements and a dielectric layer having at least one opening corresponding to the location for the plural fuse elements. The method includes processing steps implemented onto the wafer substrate, such as (a) forming a layer of etching barrier resin by scanning at least one discharging nozzle for discharging the raw etching barrier resin while suitably discharging droplets of raw etching barrier resin to replenish the opening corresponding to the location of the fuse element not to be disconnected, (b) hardening the raw etching barrier resin to be a layer of etching barrier resin, and (c) the fuse element in the prescribed disconnecting area without overlying portion of the etching barrier resin layer is selectively disconnected by etching using the dielectric layer and the etching barrier resin as a mask.04-30-2009
20080265366SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT FUSE - One aspect of the invention provides an integrated circuit(IC) [40010-30-2008
20080251886Fuse structure, and semiconductor device - A fuse structure includes a reference power layer disposed between first and second resistance-variable material layers. The first and second resistance-variable material layer may at least partially overlap each other in plan view. First and second insulating layers are disposed over and under the first and second resistance-variable material layers. A plurality of first leads is disposed over the first insulating layer. A plurality of second leads is disposed under the second insulating layer. A plurality of first via contacts penetrates the first insulating layer and connects between the first leads and the first resistance-variable material layer. A plurality of second via contacts penetrates the second insulating layer and connects between the second leads and the second resistance-variable material layer. Each of the first leads extends in a second horizontal direction that crosses a first horizontal direction in which the first and second resistance-variable material layer extend.10-16-2008
20080251885Fuse structure, semiconductor device, and method of forming the semiconductor device - There are provided a fuse structure and a semiconductor device having the fuse structure. The fuse structure includes an insulating layer having a hole, a resistance-variable material layer disposed on inner wall of the hole, a reference power layer that covers the resistance-variable material layer, and a plurality of leads in the insulating layer. Each lead has a first portion which reaches the inner wall of the hole and contacts the resistance-variable material layer. Each lead is configured to allow an electrical connection to outside.10-16-2008
20080251884Method and System for Controlling Multiple Electrical Fuses with One Program Device - A fuse circuit comprising one or more one-time programmable electrical fuses; one or more unidirectional conductive devices each coupled to one of the fuses; a programming device coupled to the unidirectional conductive devices; and a selection module coupled to the electrical fuses for selecting a predetermined electrical fuse, wherein upon a selection by the selection module, a programming current is introduced through at least one selected electrical fuse, wherein the selection module is an N-to-one multiplexer selecting one of the N number of electrical fuses to be programmed, and the unidirectional conductive devices not coupled to the selected electrical fuse to prevent the programming current from interfering with the remaining electrical fuses.10-16-2008
20080203525Capacitance trimming circuit of semiconductor device having vertically stacked capacitor layers and operation method thereof - A capacitance trimming circuit of a semiconductor device may include a plurality of capacitor layers and/or a plurality of fuses. The plurality of capacitor layers may be vertically stacked. The plurality of fuses may be arranged to correspond to the plurality of capacitor layers, and/or the plurality of fuses may be configured to select corresponding ones of the plurality of capacitor layers for controlling a capacitance of the plurality of capacitor layers.08-28-2008
20100320563ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.12-23-2010
20100320561Method for forming a one-time programmable metal fuse and related structure - According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.12-23-2010
20100320562SEMICONDUCTOR DEVICE - The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered.12-23-2010
20100320564NANOWIRE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes.12-23-2010
20110133307DAMAGE PROPAGATION BARRIER - A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.06-09-2011
20100308433SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes an etching protection layer to protect a metal layer in a bonding pad area when a metal fuse is etched.12-09-2010
20110169128SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.07-14-2011
20110169127STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS - A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.07-14-2011
20100117190FUSE STRUCTURE FOR INTERGRATED CIRCUIT DEVICES - A fuse structure for an IC device and methods of fabricating the structure are provided. The fuse structure comprises a metal-containing conductive strip formed over a portion of a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate, covering the conductive strip. A first interconnect and a second interconnect are formed in vias extending through the dielectric layer, each physically and electrically connecting to a part of the conductive layer. First and second wiring structures are formed over the dielectric layer in electrical contact with the first and second interconnects respectively. The contact area between one of the interconnects and the strip is chosen so that electromigration will occur when a pre-selected current is applied to the fuse structure.05-13-2010
20100059857METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device. One embodiment provides a metal carrier. A semiconductor chip is provided. A porous layer is produced at a surface of at least one of the carrier and the semiconductor chip. The semiconductor chip is placed on the carrier. The resulting structure is heated until the semiconductor chip is attached to the carrier.03-11-2010
20080217734Multi-level electrical fuse using one programming device - A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.09-11-2008
20080217733ELECTRICAL FUSE STRUCTURE FOR HIGHER POST-PROGRAMMING RESISTANCE - The present invention provides an electrical fuse structure for achieving a post-programming resistance distribution with higher resistance values and to enhance the reliability of electrical fuse programming. A partly doped electrical fuse structure with undoped semiconductor material in the cathode combined with P-doped semiconductor material in the fuselink and anode is disclosed and the data supporting the superior performance of the disclosed electrical fuse is shown.09-11-2008
20110260287STRUCTURE IN A HIGH VOLTAGE PATH OF AN ULTRA-HIGH VOLTAGE DEVICE FOR PROVIDING ESD PROTECTION - An ultra-high voltage device has a high voltage path established from a high voltage N-well through a first metal layer to a second metal layer, and a contact plug electrically connected between the high voltage N-well and the first metal layer. The contact plug has a distributed structure on a horizontal layout to improve the uniformity of the ultra-high voltage device such that the current in the high voltage path will be more uniform distributed so as to avoid the localized heat concentration caused by non-uniform current distribution that would damage the ultra-high voltage device. Multiple fuse apparatus are preferably connected to the first metal layer individually. Each the fuse apparatus includes a poly fuse to be burnt down when an over-load current flows therethrough.10-27-2011
20110186963ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD - An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.08-04-2011
20110186962SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an interlayer dielectric film, a passivation film, made of an insulating material, formed on the interlayer dielectric film, an uppermost wire, made of a material mainly composed of copper, formed between the surface of the interlayer dielectric film and the passivation film, and a wire covering film, made of a material mainly composed of aluminum, interposed between the passivation film and the surface of the uppermost wire for covering the surface of the uppermost wire.08-04-2011
20110186961SEMICONDUCTOR IC HAVING ELECTRICAL FUSE CAPABLE OF PREVENTING THERMAL DIFFUSION - Provided is a semiconductor integrated circuit. The semiconductor integrated circuit comprises: a pair of interconnections; a fuse connecting the pair of interconnections; and one or more heat dissipation patterns connecting the pair of interconnections and are disposed around the fuse.08-04-2011
20100025812PINCHED POLY FUSE - An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased.02-04-2010
20090115020ELECTRICAL FUSE AND METHOD OF MAKING - A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material.05-07-2009
20090057818METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES - An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse.03-05-2009
20100181643EFUSE WITH PARTIAL SIGE LAYER AND DESIGN STRUCTURE THEREFOR - A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.07-22-2010
20090174029Semiconductor device and method of fabricating the same - A semiconductor device is provided including a first fuse link having a copper-containing metal film, a second fuse link having a polysilicon film, a semiconductor substrate, and a field insulating film formed on the semiconductor substrate. The second fuse link is formed on the field insulating film. An interlayer insulating film is provided between the first fuse link and the second fuse link. The first fuse link is electrically connected to the second fuse link via a first plug formed in the interlayer insulating film.07-09-2009
20090174028Fuse in a Semiconductor Device and Method for Forming the Same - A fuse of a semiconductor device, and a method for forming the same, wherein the fuse includes a zigzag-shaped fuse portion on a planar structure, thereby reducing energy when the fuse is cut. The laser irradiation time can be reduced, thereby preventing fuse cutting defects and damages on a neighboring fuse. Also, a laser point where a laser is irradiated is not affected by misalignment, thereby improving characteristics of the fuse.07-09-2009
20120146179ELECTRICAL FUSE WITH A CURRENT SHUNT - Electrical fuses and methods for forming an electrical fuse. The electrical fuse includes a current shunt formed by patterning a first layer comprised of a first conductive material and disposed on a top surface of a dielectric layer. A layer stack is formed on the current shunt and the top surface of the dielectric layer surrounding the current shunt. The layer stack includes a second layer comprised of a second conductive material and a third layer comprised of a third conductive material. The layer stack may be patterned to define a fuse link as a first portion of the layer stack directly contacting the top surface of the dielectric layer and a terminal as a second portion separated from the top surface of the dielectric layer by the current shunt.06-14-2012
20090294901STRUCTURE AND METHOD OF FORMING ELECTRICALLY BLOWN METAL FUSES FOR INTEGRATED CIRCUITS - A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.12-03-2009
20120306048ELECTRICALLY PROGRAMMABLE METAL FUSE - A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.12-06-2012
20080296727Programmable poly fuse - According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.12-04-2008
20110024872FUSE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A fuse of a semiconductor device includes first fuse metals formed over an underlying structure and a second fuse metal formed between the first fuse metals. Accordingly, upon blowing, the fuse metals are not migrated under conditions, such as specific temperature and specific humidity. Thus, reliability of a semiconductor device can be improved.02-03-2011
20100032798Semiconductor device - The semiconductor device includes: a substrate; an electric fuse that includes a lower-layer wiring formed on the substrate, a first via provided on the lower-layer wiring and connected to the lower-layer wiring, and an upper-layer wiring provided on the first via and connected to the first via, a flowing-out portion of a conductive material constituting the electric fuse being formed in a cut-off state of the electric fuse; and a heat diffusion portion that includes a heat diffusion wiring that is formed in the same layer as one of the upper-layer wiring and the lower-layer wiring and is placed on a side of the one of the upper-layer wiring and the lower-layer wiring, the heat diffusion portion being electrically connected to the one of the upper-layer wiring and the lower-layer wiring.02-11-2010
20110101495FUSE BOX FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME - A fuse box for a semiconductor device is disclosed and includes a first fuse group comprising a plurality of first fuses, arranged in a first direction and having a first cutting axis, each first fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first and second portions, a second fuse group comprising a plurality of second fuses, arranged in the first direction and having a second cutting axis, each second fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first portion and the second portion, and a third fuse group comprising a plurality of third fuses, wherein each third fuse has either the first cutting axis or the second cutting axis, comprises a first pattern arranged in the first direction and having a first fuse pitch, and a second pattern arranged in a second direction and having a second fuse pitch smaller than the first fuse pitch, and is arranged to bypass the first fuse or the second fuse.05-05-2011
20110101494SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first bit line contact pattern coupled to a region of a word line conductive layer; a first bit line conductive pattern coupled to the first bit line contact pattern; a first metal interconnection contact pattern coupled to the first bit line conductive pattern; a fuse having a side coupled to the first metal interconnection contact pattern; a second bit line contact pattern coupled to another region of the word line conductive layer; a second bit line conductive pattern coupled to the second bit line contact pattern; a second metal interconnection contact pattern coupled to the second bit line conductive pattern; and a first guard ring metal layer disposed on the same layer as the first and second metal interconnection contact patterns and between the first and second metal interconnection contact patterns and disposed as a layer surrounding the fuse.05-05-2011
20110101493Electrical Fuse Structure and Method of Formation - An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.05-05-2011
20090001507SEMICONDUCTOR DEVICE - A semiconductor device that includes a metal fuse which may be used for redundancy or trimming, allowing for adjustment in the characteristics of a circuit. The fuse includes a disconnecting metal, a plurality of metal-vias that are connected under respective ends of the disconnecting metal, and a plurality of interconnections that connect to the disconnecting metal through respective metal-vias. The disconnecting metal is disconnected by a laser exposure and the metal-vias are located inside of the spot diameter of the laser used for the laser exposure, and are spaced apart from a side surface of the disconnecting metal. The disconnecting metal is formed of a material having a melting point and a boiling point that is lower than the melting point and boiling point of the metal-vias.01-01-2009
20120001294SEMICONDUCTOR DEVICE - A semiconductor device includes a first metal wiring which is formed over substructure; a first contact plug which is coupled to the first metal wiring and passes through a first interlayer insulating film provided over the substructure; a second metal wiring which is provided over the first interlayer insulating film and is coupled to the first contact plug; a second contact plug which is coupled to the second metal wiring and passes through a second interlayer insulating film which is provided over the first interlayer insulating film; and a fuse pattern and a data read fuse pattern which are coupled to the second contact plug and provided over the second interlayer insulating film.01-05-2012
20120056296SEMICONDUCTOR DEVICE AND METHOD OF BLOWING FUSE THEREOF - A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region.03-08-2012
20120007213SEMICONDUCTOR CHIP AND METHOD FOR FABRICATING THE SAME - A semiconductor chip includes: a semiconductor substrate in which a bonding pad is provided on a first surface thereof; a through silicon via (TSV) group including a plurality of TSVs connected to the bonding pad and exposed to a second surface opposite to the first surface of the semiconductor substrate; and a fuse box including a plurality of fuses connected to the plurality of TSVs and formed on the first surface of the semiconductor substrate.01-12-2012
20120012976FUSE STRUCTURE HAVING CRACK STOP VOID, METHOD FOR FORMING AND PROGRAMMING SAME, AND DESIGN STRUCTURE - The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.01-19-2012
20110049670Semiconductor Device Including Fuse Having Form of Capacitor - A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.03-03-2011
20120112311Electrical Fuses Using Junction Breakdown and Semiconductor Integrated Circuits Including the Same - An electrical fuse includes first and second active regions doped with respective first-type and second-type impurities that form a horizontal P/N junction, first and second spaced apart silicide layers on respective portions of the top surfaces of the first and second active regions, and first and second contacts on the respective top surfaces of the first and second silicide layers. When a first reverse voltage that is higher than a threshold voltage is applied to the electrical fuse through the first and second contacts, the P/N junction is broken down by a reverse current flowing between the first and second active regions so that the electrical fuse is rendered conductive in response to a second reverse voltage that is less than the threshold voltage.05-10-2012
20100096724Semiconductor device - A semiconductor device (04-22-2010
20100096723Semiconductor device - A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.04-22-2010
20100096722Fuse in a Semiconductor Device and Method for Fabricating the Same - The present invention relates to a fuse in a semiconductor device and method for fabricating the same. An oxide film is formed on sidewalls of a barrier metal layer in a bottom portion of a fuse pattern, thereby preventing the barrier metal layer from being exposed. As a result, the oxidation of the barrier metal layer is inhibited to improve characteristics of the device.04-22-2010
20110001213FUSE PART FOR SEMICONDUCTOR DEVICE - A fuse part for a semiconductor device includes an insulation layer configured to cover a conductive pattern over a substrate, a dual fuse configured to include a first pattern and a second pattern that are positioned on the same line over the insulation layer and spaced apart from each other by a certain distance, a protective layer configured to cover the dual fuse and include a first fuse box and a second fuse box that partially expose the first pattern and the second pattern, respectively, and a plurality of plugs configured to penetrate the insulation layer and electrically connect the first and second patterns to the conductive pattern. Herein, the plugs are positioned beneath the first and second fuse boxes.01-06-2011
20110001212FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A fuse of a semiconductor device includes a plurality of first conductive patterns, and a plurality of second conductive patterns filling spaces between the first conductive patterns and formed of a material which has a greater specific resistance than the first conductive patterns.01-06-2011
20110001211FUSE FOR IN USE OF A SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - Provided is a fuse of a semiconductor device that includes a Y type fuse and an insulation layer configured to expose the Y type fuse such that an exposed portion of the Y type fuse has a substantially ‘V’ shape. According to the present invention, metal crack is prevented from occurring in a Y type fuse under a high temperature and high humidity condition of a reliability test so that the reliability and competitiveness of semiconductor devices can be improved.01-06-2011
20120161278METHOD AND SYSTEM FOR PROVIDING FUSING AFTER PACKAGING OF SEMICONDUCTOR DEVICES - A method and a system for providing fusing after packaging of semiconductor devices are disclosed. In one embodiment, a semiconductor device is provided comprising a substrate comprising a fuse area, at least one fuse disposed in the fuse area, and at least one layer disposed over the substrate, wherein the at least one layer comprises at least one opening exposing the at least one fuse.06-28-2012
20100207239SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a lower layer interconnection formed on a chip; an upper layer interconnection formed in an upper layer above the lower layer interconnection above the chip; an interconnection via formed to electrically connect the lower layer interconnection and the upper layer interconnection; a via-type electric fuse formed to electrically connect the lower layer interconnection and the upper layer interconnection. The fuse is cut through heat generation, and a sectional area of the fuse is smaller than a sectional area of the upper layer interconnection and a via diameter of the fuse is smaller than that of the interconnection via.08-19-2010
20120248567LAYERED STRUCTURE WITH FUSE - A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.10-04-2012
20090057819ELECTRICAL FUSE DEVICE - The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.03-05-2009
20090096058PINCHED POLY FUSE - An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased.04-16-2009
20090096059FUSE STRUCTURE INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL LAYER AND GAP - A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse.04-16-2009
20100270641Semiconductor Fuse Arrangements - The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of electrically conductive links. Each of the links contacts the electrically conductive plate as a separate region relative to the other links, and the region where a link makes contact to the electrically conductive plate is a fuse. The invention also includes methods of forming semiconductor fuse arrangements.10-28-2010
20120074520ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME - A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.03-29-2012
20100283120FUSE CHAMBERS ON A SUBSTRATE - Embodiments of a system with first means for forming a chamber adjacent to a component formed on a substrate and a single orifice between the chamber and a first surface of the first means that is opposite a second surface of the first means adjacent to the substrate and second means for enclosing the chamber on at least a portion of the first surface that encompasses the single orifice are disclosed.11-11-2010
20120256293ONE-TIME PROGRAMMABLE DEVICES AND METHODS OF FORMING THE SAME - A one-time programmable (OTP) device includes at least one transistor that is electrically coupled with a fuse. The fuse includes a silicon-containing line continuously extending between a first node and a second node of the fuse. A first silicide-containing portion is disposed over the silicon-containing line. A second silicide-containing portion is disposed over the silicon-containing line. The second silicide-containing portion is separated from the first silicide-containing portion by a predetermined distance. The predetermined distance is substantially equal to or less than a length of the silicon-containing line.10-11-2012
20120187529eFUSE AND METHOD OF FABRICATION - An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch.07-26-2012
20090026574ELECTRICAL FUSE HAVING SUBLITHOGRAPHIC CAVITIES THEREUPON - An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current.01-29-2009
20120261794DESIGN STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS - A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.10-18-2012
20120261793ELECTRICAL FUSE AND METHOD OF MAKING THE SAME - An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive feature has a second top surface and a metal cap directly on the second top surface. Each metal cap has a third top surface that is above the first top surface of the dielectric layer. The fuse element is on the third top surface of each metal cap and on the first top surface of the dielectric layer. A method of forming the e-fuse device is also provided.10-18-2012
20120228735FUSE PATTERNS AND METHOD OF MANUFACTURING THE SAME - The present invention provides fuse patterns and a method of manufacturing the same. According to the present invention, an insulating layer and a contact plug are filled between fuse patterns which are formed to have their ends broken and are isolated from each other. In case of a fail cell, the insulating layer is broken owing a difference in an electrical bias (current or voltage) between a metal wire and the fuse patterns, and a short is generated between the fuse patterns. Accordingly, embodiments avoid damage to a semiconductor substrate associated with a conventional fuse repair method employing laser energy, and the area of a fuse box can be reduced.09-13-2012
20100327401FUSE OF SEMICONDUCTOR DEVICE - The present invention relates to a fuse for a semiconductor device, and discloses the technique capable of preventing fuse damage, which might occur during a fuse blowing step, with reducing area of the fuse occupying the semiconductor device. The present invention includes a common source region, wherein a plurality of fuses are radially arranged about the common source region, and a fuse box wall is formed outside the fuses.12-30-2010
20100327399ELECTRICALLY PROGRAMMABLE FUSE USING ANISOMETRIC CONTACTS AND FABRICATION METHOD - An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.12-30-2010
20120319235SEMICONDUCTOR DEVICE WITH A FUSE FORMED BY A DAMASCENE TECHNIQUE AND A METHOD OF MANUFACTURING THE SAME - In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.12-20-2012
20110018092SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a base insulating layer, a silicon fuse, a pair of silicon wires, a silicon guard ring, an insulation coating, a first interlayer insulating layer, a via guard ring, a metal guard ring, a final insulating layer, and a fuse window. The base insulating layer is disposed over the semiconductor substrate. The silicon fuse is disposed on the base insulating layer. The pair of silicon wires is disposed on the base insulating layer. The silicon guard ring is disposed on the base insulating layer. The insulation coating is deposited at least over surfaces of the silicon wires. The first interlayer insulating layer is disposed on the base insulating layer. The final insulating layer is disposed on the interlayer insulating layer. The fuse window is defined above the silicon fuse inside the guard rings.01-27-2011
20120319234E-FUSE STRUCTURES AND METHODS OF OPERATING AND MANUFACTURING THE SAME - An e-fuse structure includes a first doped region and a second doped region formed in a substrate. The first doped region has a first conductivity type and the second doped region has a second conductivity type different from the first conductivity type. The first and second doped regions contact each other. A conductive pattern is disposed on the first and second doped regions and contacts the first and second doped regions. A first contact plug is disposed on the conductive pattern in an area corresponding to the first doped region, and a second contact plug is disposed on the conductive pattern in an area corresponding to the second doped region.12-20-2012
20120267755SEMICONDUCTOR DEVICE WITH ELECTRIC FUSE HAVING A FLOWING-OUT REGION - A method for cutting an electric fuse formed on a semiconductor substrate by applying a predetermined electric voltage between a first interconnect and a second interconnect to flow an electric current in the electric fuse such that the electric conductor is flowed toward outside from the second interconnect to form a void region between the via and the first interconnects or in the via.10-25-2012
20110227192Semiconductor device and method of manufacturing the same - Provided are a semiconductor device including a highly precise resistor formed of a polycrystalline silicon film and a method of manufacturing the same, in which: a portion of a base insulating film below a portion of the polycrystalline silicon film which becomes a resistance region into a convex shape; and the polycrystalline silicon film which becomes the resistor is selectively formed into a thin film, while an electrode lead-out region remains thick so as to obtain the resistor with high precision, high resistivity, and a preferable temperature coefficient while preventing penetration in an opening for contact.09-22-2011
20110127637Nanopillar E-Fuse Structure and Process - Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.06-02-2011
20120126364MITIGATION OF DETRIMENTAL BREAKDOWN OF A HIGH DIELECTRIC CONSTANT METAL-INSULATOR-METAL CAPACITOR IN A CAPACITOR BANK - An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.05-24-2012
20120126363STRUCTURE OF METAL E-FUSE - Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.05-24-2012
20090090994ELECTROMIGRATION FUSE AND METHOD OF FABRICATING SAME - Fuses and methods of forming fuses. The fuse includes: a dielectric layer on a semiconductor substrate; a cathode stack on the dielectric layer, a sidewall of the cathode stack extending from a top surface of the cathode stack to a top surface of the dielectric layer; a continuous polysilicon layer comprising a cathode region, an anode region, a link region between the cathode and anode regions and a transition region between the cathode region and the link region, the transition region proximate to the sidewall of the cathode stack, the cathode region on a top surface of the cathode stack, the link region on a top surface of the dielectric layer, both a first thickness of the cathode region and a second thickness of the link region greater than a third thickness of the transition region; and a metal silicide layer on a top surface of the polysilicon layer.04-09-2009
20120080769ESD DEVICE AND METHOD - A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.04-05-2012
20100230780SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device realizing reliable cutting of a fuse without enlarging layout area of a fuse element and the reduced number of wiring layers of a preventing wall that prevents diffusion of fuse copper atoms. A fuse is formed by using a wire in a metal wiring layer as an upper layer in a plurality of metal wiring layers. Wires are disposed just above and just below a fuse each with a gap of at least two wiring layers. In an upper layer, a power wire that transmits power supply voltage is used as a part covering a preventing wall structure just above the fuse.09-16-2010
20120326269E-FUSE STRUCTURES AND METHODS OF MANUFACTURE - E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.12-27-2012
20120091556VERTICAL SILICIDE E-FUSE - An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.04-19-2012
20120286390ELECTRICAL FUSE STRUCTURE AND METHOD FOR FABRICATING THE SAME - An electrical fuse structure includes a top fuse, a bottom fuse and a via conductive layer positioned between the top fuse and the bottom fuse for providing electric connection. The top fuse includes a top fuse length and the top fuse length is equal to or larger than a predetermined value. The bottom fuse includes a bottom fuse length larger than the top fuse length.11-15-2012
20120133019FUSE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A fuse of a semiconductor device includes first fuse metals formed over an underlying structure and a second fuse metal formed between the first fuse metals. Accordingly, upon blowing, the fuse metals are not migrated under conditions, such as specific temperature and specific humidity. Thus, reliability of a semiconductor device can be improved.05-31-2012
20080237786NON-PLANAR FUSE STRUCTURE INCLUDING ANGULAR BEND AND METHOD FOR FABRICATION THEREOF - A fuse structure includes a non-planar fuse material layer typically located over and replicating a topographic feature within a substrate. The non-planar fuse material layer includes an angular bend that assists in providing a lower severance current within the non-planar fuse material layer.10-02-2008
20130168806ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME - A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved.07-04-2013
20130168807INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS, AND DESIGN STRUCTURE THEREOF - A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.07-04-2013
20130113070Interposers for Semiconductor Devices and Methods of Manufacture Thereof - Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via.05-09-2013
20130187254Semiconductor Chip and Methods for Producing the Same - A fabrication method for thickening pad metal layers comprises: growing a first metal layer on a silicon substrate; etching the first metal layer to obtain a metal wire comprising a metal fuse and a pad; growing a passivation layer on the metal wire; etching the passivation layer to obtain a first window to expose a pad area; growing a second metal layer on the passivation layer having the first window; etching the second metal layer to obtain a metal layer covering the pad area only and expose the passivation layer outside the pad area; and etching the passivation layer outside the pad area to obtain a second window to expose a metal fuse area.07-25-2013
20130119509FORMING BEOL LINE FUSE STRUCTURE - In one embodiment, the invention provides a back-end-of-line (BEOL) line fuse structure. The BEOL line fuse structure includes: a line including a plurality of grains of conductive crystalline material; wherein the plurality of grains in a region between the first end and a second end include an average grain size that is smaller than a nominal grain size of the plurality of grains in a remaining portion of the line.05-16-2013
20110272779EFUSE CONTAINING SIGE STACK - An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.11-10-2011
20110272778Semiconductor device - A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.11-10-2011
20130147008Metal E-Fuse With Intermetallic Compound Programming Mechanism and Methods of Making Same - Disclosed herein is a metal e-fuse device that employs an intermetallic compound programing mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines.06-13-2013
20130147009SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a fuse pattern formed at a first level, a first line pattern formed at a second level lower than the first level, a second line pattern formed at a third level higher than the first level, a first contact plug coupling the fuse pattern to the first line pattern 06-13-2013
20100283121ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS - Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.11-11-2010
20130113071SEMICONDUCTOR DEVICE WITH FUSE - A semiconductor device includes a fuse configured to be programmed in response to a laser, a protective layer formed under the fuse and overlapping with a portion of the fuse, and a heat emission portion coupled with the protective layer.05-09-2013
20130193552INTEGRATED CIRCUIT DEVICES WITH CRACK-RESISTANT FUSE STRUCTURES - A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer.08-01-2013

Patent applications in class Including programmable passive component (e.g., fuse)

Patent applications in all subclasses Including programmable passive component (e.g., fuse)