Entries |
Document | Title | Date |
20080217732 | Carbon memory - An integrated circuit including a memory cell and methods of manufacturing the integrated circuit are described. The memory cell includes a resistive memory element including a top contact, a bottom contact, and a carbon storage layer disposed between the top contact and the bottom contact. The memory cell operates at a voltage in a range of approximately 0.5V to approximately 3V, and at a current in a range of approximately 1 μA to approximately 150 μA. | 09-11-2008 |
20080224259 | METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE - Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing. | 09-18-2008 |
20080308899 | TRIANGULAR SPACE ELEMENT FOR SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16. | 12-18-2008 |
20090065894 | Electronic circuit device having silicon substrate - An electronic circuit device comprises a silicon substrate having front and rear surfaces, a semiconductor element formed on the front surface, and at least one through-hole penetrating through the front surface and the rear surface. At least one passive element is supported by the silicon substrate. At least one connecting element is disposed in the through-hole of the silicon substrate for electrically connecting the semiconductor element to the passive element. | 03-12-2009 |
20090127653 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized. | 05-21-2009 |
20090140381 | Semiconductor Device and Method for Forming Passive Circuit Elements with Through Silicon Vias to Backside Interconnect Structures - A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate. | 06-04-2009 |
20090160017 | Semiconductor device having capacitor, transistor and diffusion resistor and manufacturing method thereof - In manufacturing a semiconductor device including a substrate having a (111)-plane orientation and an off-set angle in a range between 3 degrees and 4 degrees, a capacitor, a transistor and a diffusion resistor are formed in the substrate, each of which are separated by a junction separation layer. A first silicon nitride film is formed by low pressure CVD over a surface of the substrate except a bottom portion of a contact hole and a portion over the junction separation layer, and a silicon oxide film is formed by low pressure CVD over the first silicon nitride film. A second silicon nitride film as a protecting film is formed by plasma CVD so as to cover the semiconductor device finally. Therefore, the semiconductor device having high reliability can be obtained. | 06-25-2009 |
20090218655 | Integrated passive devices - The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line. | 09-03-2009 |
20090236686 | Semiconductor Device and Method of Forming UBM Fixed Relative to Interconnect Structure for Alignment of Semiconductor Die - A semiconductor device is made by forming a first conductive layer over a temporary carrier. A UBM layer is formed over the temporary carrier and fixed in position relative to the first conductive layer. A conductive pillar is formed over the first conductive layer. A semiconductor die is mounted to the UBM layer to align the die relative to the conductive pillar. An encapsulant is deposited over the die and around the conductive pillar. The UBM layer prevents shifting of the semiconductor die while depositing the encapsulant. The temporary carrier is removed. A first interconnect structure is formed over a first surface of the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected through the conductive pillar. The first or second interconnect structure includes an integrated passive device electrically connected to the conductive pillar. | 09-24-2009 |
20090273053 | SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUITRY HAVING A PLURALITY OF DEVICES OF REDUCED MISMATCH - In an analog circuit portion, a systematic mismatch between a plurality of circuit elements may be reduced in view of a technology gradient by appropriately positioning the unit devices of the circuit elements so as to obtain a similar response of the circuit elements with respect to the gradient. For example, the spatial relationship of adjacent unit devices belonging to the same circuit element along an arbitrary lateral direction may be the same as the spatial relationship of adjacent unit devices of another circuit element. | 11-05-2009 |
20090294899 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMBEDDED PASSIVE CIRCUIT ELEMENTS INTERCONNECTED TO THROUGH HOLE VIAS - A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via. | 12-03-2009 |
20090315142 | Semiconductor component and method of manufacture - A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates. | 12-24-2009 |
20100025810 | Method and System for Secure Heat Sink Attachment on Semiconductor Devices with Macroscopic Uneven Surface Features - An integrated circuit package is provided. The integrated circuit package includes a heat sink, a cured silicone thermally conductive adhesive material, and a surface. The adhesive material attaches the heat sink to the surface. The surface is a surface of at least one of a substrate, a surface of an integrated circuit die, or a surface of an encapsulating material of the integrated circuit package. | 02-04-2010 |
20100025811 | INTEGRATED CIRCUIT WITH BUILT-IN HEATING CIRCUITRY TO REVERSE OPERATIONAL DEGENERATION - An integrated circuit device ( | 02-04-2010 |
20100059853 | Semiconductor Device and Method of Forming Shielding Layer over Integrated Passive Device Using Conductive Channels - A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference. | 03-11-2010 |
20100059854 | Semiconductor Device and Method of Forming an IPD over a High-Resistivity Encapsulant Separated from other IPDS and Baseband Circuit - A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant. | 03-11-2010 |
20100059855 | Semiconductor Device and Method of Forming a Fan-Out Structure with Integrated Passive Device and Discrete Component - A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer. | 03-11-2010 |
20100059856 | Method of configuring a semiconductor integrated circuit involving capacitors having a width equal to the length of active resistors - A method of configuring a semiconductor integrated circuit (IC) includes arranging a circuit region in the center of a unit cell. Capacitor/resistor regions are arranged along the left and right edge portions of the unit cell. The capacitor/resistor regions include a plurality of active resistors having the same length and a capacitor having a width equal to the length of the plurality of active resistors. In addition, a first conductive layer is arranged longitudinally in each of the capacitor/resistor regions so as to contact the left and right edge portions of the unit cell. | 03-11-2010 |
20100072570 | Semiconductor Device and Method of Forming Embedded Passive Circuit Elements Interconnected to Through Hole Vias - A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via. | 03-25-2010 |
20100127345 | 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES | 05-27-2010 |
20100140736 | Semiconductor Device and Method of Embedding Integrated Passive Devices into the Package Electrically Interconnected Using Conductive Pillars - A semiconductor device has a first insulation layer formed over a sacrificial substrate. A first conductive layer is formed over the first insulating layer. Conductive pillars are formed over the first conductive layer. A pre-fabricated IPD is disposed between the conductive pillars. An encapsulant is formed around the IPD and conductive pillars. A second insulation layer is formed over the encapsulant. The conductive pillars are electrically connected to the first and second conductive layers. The first and second conductive layers each include an inductor. Semiconductor devices are mounted over the first and second insulating layer and electrically connected to the first and second conductive layers, respectively. An interconnect structure is formed over the first and second insulating layers, respectively, and electrically connected to the first and second conductive layers. The sacrificial substrate is removed. The semiconductor devices can be stacked and electrically interconnected through the conductive pillars. | 06-10-2010 |
20100140737 | Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures - A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate. | 06-10-2010 |
20100140738 | Semiconductor Device and Method of Forming Compact Coils for High Performance Filter - A semiconductor device has a first coil structure formed over the substrate. A second coil structure is formed over the substrate adjacent to the first coil structure. A third coil structure is formed over the substrate adjacent to the second coil structure. The first and second coil structures are coupled by mutual inductance, and the second and third coil structures are coupled by mutual inductance. The first, second, and third coil structures each have a height greater than a skin current depth of the coil structure defined as a depth which current reduces to 1/(complex permittivity) of a surface current value. In the case of copper, the coil structures have a height greater than 5 micrometers. | 06-10-2010 |
20100155883 | INTEGRATED MEMS AND IC SYSTEMS AND RELATED METHODS - An integrated MEMS and IC system (MEMSIC), as well as related methods, are described herein. According to some embodiments, a mechanical resonating structure is coupled to an electrical circuit (e.g., field-effect transistor). For example, the mechanical resonating structure may be coupled to a gate of a transistor. In some cases, the mechanical resonating structure and electrical circuit may be fabricated on the same substrate (e.g., Silicon (Si) and/or Silicon-on-Insulator (SOW and may be proximate to one another. | 06-24-2010 |
20100181642 | WAFER-LEVEL FLIP CHIP PACKAGE WITH RF PASSIVE ELEMENT/ PACKAGE SIGNAL CONNECTION OVERLAY - A packaged integrated circuit includes an integrated circuit having a Radio Frequency (RF) passive element formed therein and a wafer level chip scale flip chip package that contains the integrated circuit. The wafer level chip scale flip chip package includes at least one dielectric layer isolating a top metal layer of the integrated circuit and a package signal connection upon the at least one dielectric layer, wherein the package signal connection partially overlays the RF passive element with respect to a surface of the integrated circuit. The RF passive element may be an inductor, a transformer, a capacitor, a transistor, or another passive element. The package signal connection may be a conductive ball, a conductive bump, a conductive pad, or a conductive spring, for example. A conductive structure may reside upon the at least one dielectric layer to provide shielding to the RF passive element and may include a plurality of conductive elements or a mesh. | 07-22-2010 |
20100187651 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME - Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit. | 07-29-2010 |
20100264512 | Semiconductor Device and Method of Forming High-Frequency Circuit Structure and Method Thereof - A semiconductor device is made by providing an integrated passive device (IPD). Through-silicon vias (TSVs) are formed in the IPD. A capacitor is formed over a surface of the IPD by depositing a first metal layer over the IPD, depositing a resistive layer over the first metal layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the resistive and dielectric layers. The first metal layer and the resistive layer are electrically connected to form a resistor and the first metal layer forms a first inductor. A wafer supporter is mounted over the IPD using an adhesive material and a third metal layer is deposited over the IPD. The third metal layer forms a second inductor that is electrically connected to the capacitor and the resistor by the TSVs of the IPD. An interconnect structure is connected to the IPD. | 10-21-2010 |
20100264513 | INTEGRATED CIRCUIT DEVICES INCLUDING PASSIVE DEVICE SHIELDING STRUCTURES - Integrated circuit devices include a semiconductor substrate and a flux line generating passive electronic element on the semiconductor substrate. A dummy gate structure is arranged on the semiconductor substrate in a region below the passive electronic element. The dummy gate includes a plurality of segments, each segment including a first longitudinally extending part and a second longitudinally extending part. The second longitudinally extending part extends at an angle from an end of the first longitudinally extending part. Ones of the segments extend at a substantially same angle and are arranged displaced from each other in an adjacent nested relationship. | 10-21-2010 |
20100270640 | DEFORMABLE INTEGRATED CIRCUIT DEVICE - An integrated-circuit device is provided, which comprises a rigid substrate island having a main substrate surface with a circuit region circuit elements and at least one fold structure. The fold structure is attached to the substrate island and is unfoldable from a relaxed, folded state to a strained unfolded state. The fold structure contains at least one passive electrical component. The fold structure further has in its folded state at least one surface with an area vector that includes a non-vanishing area-vector component in a direction parallel to the main substrate surface, which area-vector component is diminished or vanishes when deforming the fold structure from the folded into the unfolded state. The fold structure provided by the present invention allows fabricating the integrated-circuit device with small lateral extensions and thus takes up a particularly small amount of chip area, which reduces the cost per device. | 10-28-2010 |
20100301449 | METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHY - The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a double subtractive process. An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a double subtractive process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to rails for forming memory lines and at least one depth corresponds to pillars for forming memory cells. Numerous other aspects are disclosed. | 12-02-2010 |
20110079872 | PASSIVE DEVICE, SEMICONDUCTOR MODULE, ELECTRONIC CIRCUIT BOARD, AND ELECTRONIC SYSTEM HAVING THE PASSIVE DEVICE, AND METHODS OF FABRICATING AND INSPECTING THE SEMICONDUCTOR MODULE - Provided are a passive device of a semiconductor module, a semiconductor module having the passive device, an electronic circuit board and electronic system having the passive device or semiconductor module, and methods of fabricating and inspecting the semiconductor module. The passive device of the semiconductor module includes a main body and at least two real electrodes disposed on one lateral surface of the main body. | 04-07-2011 |
20110089529 | Open Cavity Leadless Surface Mountable Package for High Power RF Applications - An RF semiconductor package includes a substrate having generally planar top and bottom surfaces. The substrate includes a metallic base region and one or more metallic signal terminal regions extending from the top surface to the bottom surface, and an insulative material separating the metallic regions from one another. The bottom surface of an RF semiconductor die is surface-mounted to the base region at the top substrate surface. The RF semiconductor die has a terminal pad disposed at a top surface of the RF semiconductor die. The terminal pad is electrically connected to one of the signal terminal regions at the top substrate surface. A lid is attached to the top substrate surface so that the RF semiconductor die is enclosed by the lid to form an open-cavity around the RF semiconductor die. The base and signal terminal regions are configured for surface-mounting at the bottom substrate surface. | 04-21-2011 |
20110127636 | INTEGRATED PASSIVE DEVICE ASSEMBLY - There is provided an integrated passive device assembly including: a substrate having a wiring pattern disposed therein; a mounting part disposed on an upper surface of the substrate, formed of an insulating material, and having an integrated passive device mounted on an upper surface thereof; a conductive pattern disposed inside the mounting part; and a connecting part disposed on the substrate and electrically connected to the integrated passive device. The connecting part and the conductive pattern are electrically connected to the wiring pattern. | 06-02-2011 |
20110156203 | INTEGRATED PASSIVE DEVICE ASSEMBLY - There is provided an integrated passive device assembly. An integrated passive device assembly according to an aspect of the invention may include: a board having a wiring pattern provided thereon; an integrated passive device mounted on an upper surface of the board and having conductive patterns provided on upper and lower surfaces thereof; a first connection portion electrically connecting the conductive pattern, provided on the upper surface of the integrated passive device, and the wiring pattern to each other; and a second connection portion electrically connecting the conductive pattern, provided on the lower surface of the integrated passive device, and the wiring pattern to each other. | 06-30-2011 |
20110169126 | In-situ passivation methods to improve performance of polysilicon diode - A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated. | 07-14-2011 |
20110180897 | PACKAGED SEMICONDUCTOR PRODUCT AND METHOD FOR MANUFACTURE THEREOF - Packaged semiconductor product ( | 07-28-2011 |
20110204472 | Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame - A semiconductor device is made by mounting a semiconductor component over a carrier. A ferromagnetic inductor core is formed over the carrier. A pillar frame including a plurality of bodies is mounted over the carrier, semiconductor component, and inductor core. An encapsulant is deposited around the semiconductor component, plurality of bodies, and inductor core. A portion of the pillar frame is removed. A first remaining portion of the pillar frame bodies provide inductor pillars around the inductor core and a second remaining portion of the pillar frame bodies provide an interconnect pillar. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors. | 08-25-2011 |
20110241160 | High Voltage Semiconductor Devices and Methods of Forming the Same - High voltage semiconductor devices and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming first trenches in an insulating material. A trap region is formed in the insulating material by introducing an impurity into the first trenches. The first trenches are filled with a conductive material. | 10-06-2011 |
20110241161 | CHIP PACKAGE WITH CHANNEL STIFFENER FRAME - Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate. | 10-06-2011 |
20110266652 | Semiconductor Package with Penetrable Encapsulant Joining Semiconductor Die and Method Thereof - A semiconductor device includes a first substrate. A first semiconductor die is mounted to the first substrate. A bond wire electrically connects the first semiconductor die to the first substrate. A first encapsulant is deposited over the first semiconductor die, bond wire, and first substrate. The first encapsulant includes a penetrable, thermally conductive material. In one embodiment, the first encapsulant includes a viscous gel. A second substrate is mounted over a first surface of the first substrate. A second semiconductor die is mounted to the second substrate. The second semiconductor die is electrically connected to the first substrate. The first substrate is electrically connected to the second substrate. A second encapsulant is deposited over the first semiconductor die and second semiconductor die. An interconnect structure is formed on a second surface of the first substrate, opposite the first surface of the first substrate. | 11-03-2011 |
20110291228 | PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME - A package structure which includes a non-conductive substrate, a conductive element, a passivation, a jointed side, a conductive layer, a solder and a solder mask is disclosed. The conductive element is disposed on a surface of the non-conductive substrate and consists of a passive element and a corresponding circuit. The passivation completely covers the conductive element and the non-conductive substrate so that the conductive element is sandwiched between the passivation and the non-conductive substrate. The conductive layer covers the jointed side which exposes part of the corresponding circuit, extends beyond the jointed side and is electrically connected to the corresponding circuit. The solder mask which completely covers the jointed side and the conductive layer selectively exposes the solder which is disposed outside the jointed side and electrically connected to the conductive layer. | 12-01-2011 |
20110304010 | ELECTROSTATIC DISCHARGE PROTECTION SCHEME FOR SEMICONDUCTOR DEVICE STACKING PROCESS - An electrostatic discharge (ESD) protection scheme for a semiconductor device stacking process is provided, in which an equivalent electrical resistance of a specific path is designed to be less than an equivalent electrical resistance of other paths. Accordingly, when a first active layer and a second active layer in the semiconductor device are stacked, by designing suitable ESD protection cells on such a specific path, electrical charges accumulated on the top layer wafer (or die) select such a specific path over the other paths to be released to the grounded bottom layer wafer (or die), so as to achieve an ESD protection effect. In addition, since such a specific path also serves as a heat dissipation path in a three dimensional integrated circuit (3D IC), an overall heat resistance of the 3D IC may be reduced to improve a heat dissipation effect. | 12-15-2011 |
20120012975 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a semiconductor substrate including a digital circuit area and an analog circuit area that is divided into an active element area disposed away from the digital circuit area and a passive element area disposed adjacent to the digital circuit area; a first well having a first conductivity type that is different from a second conductivity type of the semiconductor substrate and formed in a part of the semiconductor substrate corresponding to the passive element area; a second well having the second conductivity type and formed in the first well; a device isolation film formed on the second well; a digital circuit formed in the digital circuit area; an active element implemented by an analog circuit and formed in the active element area; and a passive element implemented by an analog circuit and formed on the device isolation film in the passive element area. | 01-19-2012 |
20120032296 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR CIRCUIT SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR CIRCUIT SUBSTRATE - A semiconductor circuit substrate includes a transistor-forming substrate and a circuit-forming substrate. The transistor-forming substrate is a GaN substrate and has a Bipolar Junction Transistor (BJT) located in its top surface. The bottom surface of the transistor-forming substrate is flat and has contact regions. The circuit-forming substrate is a material other than a compound semiconductor and has no semiconductor active elements. The circuit-forming substrate has a flat top surface, contact regions buried in and exposed at the top surface, and passive circuits. The transistor-forming substrate and the circuit-forming substrate are directly bonded together without any intervening film, such as an insulating film. | 02-09-2012 |
20120080768 | SHEET-MOLDED CHIP-SCALE PACKAGE - Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described. | 04-05-2012 |
20120104543 | HIGH-SPEED MEMORY SOCKETS AND INTERPOSERS - High-speed memory systems that consume a reduced amount of board space, have a low height or profile, or both. This reduction in board space and height may result in shorter signal paths from a board to a memory device, thereby improving the high-speed performance of the high-speed memory system. One example may provide a space-efficient memory system that consumes a reduced amount of board space. Space efficiency may gained by arraying memory devices on an interposer that mates with a socket attached to a board. Another example may provide a memory system that has a reduced height or profile. This reduced height may be achieved by employing a socket that accepts an interposer in a lateral or rotational direction. | 05-03-2012 |
20120146177 | Semiconductor Device and Method of Forming Recesses in Substrate for Same Size or Different Sized Die with Vertical Integration - A semiconductor device has a substrate with a first and second recess formed in a surface of the substrate using a wet etch process. The second recess can have a size different from a size of the first recess. A plurality of conductive vias are formed in a surface of the first and second recesses using a dry etch process. A first conductive layer is formed over the surface of the substrate, over curved side walls of the first and second recesses, and electrically connected to the plurality of conductive vias. A first and second semiconductor die are mounted into the first and second recesses respectively. The second semiconductor die can have a size different from a size of the first semiconductor die. The first and second semiconductor die are electrically connected to the first conductive layer. An interconnect structure is electrically connected to the plurality of conductive vias. | 06-14-2012 |
20120146178 | OVERMOLDED SEMICONDUCTOR PACKAGE WITH WIREBONDS FOR ELECTROMAGNETIC SHIELDING - According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component. | 06-14-2012 |
20120153432 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a substrate, a control element provided on the substrate, a resin provided on the control element and a memory element provided above the control element. The memory element is in contact with the resin and electrically connected to the control element provided within a region therebeneath in plan view parallel to a surface of the substrate. | 06-21-2012 |
20120299149 | Semicinductor Device with Cross-Talk Isolation Using M-CAP and Method Thereof - A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements. | 11-29-2012 |
20130001740 | HEAT SPREADER FOR THERMALLY ENHANCED FLIP-CHIP BALL GRID ARRAY PACKAGE - A heat spreader is provided for use with a thermally enhanced flip-chip ball grid array package. In the package, a semiconductor die is positioned front-side down on a package substrate, coupled thereto via solder balls. Passive devices can also be coupled to the substrate alongside the die. The heat spreader is positioned over the substrate and die, in thermal contact with the die. A projection in the center of the heat spreader makes contact with the back surface of the die via a thermal interface material, to draw heat from the die for improved cooling. The projection enables close contact with a thinned die while accommodating thicker passive devices positioned around the die on the substrate. | 01-03-2013 |
20130105938 | DEVICE MATCHING LAYOUT AND METHOD FOR IC | 05-02-2013 |
20130105939 | SEMICONDUCTOR DEVICE | 05-02-2013 |
20130161784 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate; first and second pads that are disposed separate from each other on the substrate; and a solder resist that allows a portion of the substrate in a region between the first and second pads and to be exposed while covering a portion of the first and second pads in a region other than the region between the first and second pads. | 06-27-2013 |
20130168805 | Packages with Passive Devices and Methods of Forming the Same - A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM. | 07-04-2013 |
20130214385 | Package-in-Package Using Through-Hole Via Die on Saw Streets - A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die. | 08-22-2013 |
20130214386 | SIP SYSTEM-INTEGRATION IC CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A system-in-package (SiP) system-integration integrated circuit (IC) chip package and a manufacturing method thereof are provided. The package includes a substrate, a passive device and two IC chips are provided on the substrate, an adhesive film is disposed between each of the two IC chips and the substrate, the IC chips are connected to first pads on the substrate through bonding wires, and the substrate is covered by a mold cap. A third IC chip may be further disposed on one of the IC chips, and the third IC chip is connected to the first pad and the IC chip under the third IC chip respectively through a bonding wire. A substrate adopting a surface mount technology (SMT) PAD window-opening manner is used, chip mounting is performed on the substrate, and the substrate undergoes reflow soldering, cleaning, die bonding, plasma cleaning, bonding, marking, cutting, and packing, so that the SiP system-integration IC chip package is manufactured. The package of the present invention integrates devices of different types, has a complete system function, and can be used as a middle stage of further development of system on chip (SoC). | 08-22-2013 |
20130234283 | Semiconductor Packages and Methods of Forming The Same - In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate. | 09-12-2013 |
20130249051 | Packaged Semiconductor Device Having Multilevel Leadframes Configured as Modules - A semiconductor system ( | 09-26-2013 |
20130307113 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first insulating layer; a wiring layer formed on a first surface of the first insulating layer and including a first electrode pad; a semiconductor chip; a second insulating layer including a semiconductor chip accommodating portion; a third insulating layer on the second insulating layer; and a passive element including an electrode and formed of an embedded portion and a protruding portion on a second surface of the first insulating layer, wherein an end surface of the embedded portion is coated by the insulating layer, the electrode of the passive element is electrically connected to the wiring layer through a via wiring formed in the insulating layers, the first electrode pad is electrically connected to another semiconductor device through a joining portion, and a protruding amount of the protruding portion is less than a gap between the second surface and the another semiconductor device. | 11-21-2013 |
20140035095 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure. | 02-06-2014 |
20140035096 | METHOD FOR CONTROLLING ELECTRICAL PROPERTY OF PASSIVE DEVICE DURING FABRICATION OF INTEGRATED COMPONENT AND RELATED INTEGRATED COMPONENT - A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component. | 02-06-2014 |
20140084413 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a top surface and a bottom surface opposing the top surface; an insulating protective layer formed on the top surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and passive components provided on or embedded in the interposer. By integrating the passive components into the package substrate, when a chip is provided on the interposer, the conductive path between the chip and the passive components can be shortened, and the pins of the chip have a stable voltage. Therefore, the overall electrical performance is enhanced. | 03-27-2014 |
20140097512 | HYBRID SEMICONDUCTOR MODULE STRUCTURE - Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights. | 04-10-2014 |
20140097513 | Package-on-Package Type Package Including Integrated Circuit Devices and Associated Passive Components on Different Levels - A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a first substrate, and a second semiconductor package having a second semiconductor device mounted on a second substrate. The first passive element is electrically connected to the second semiconductor device. Related devices are also discussed. | 04-10-2014 |
20140138791 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly. | 05-22-2014 |
20140175599 | INTEGRATED CIRCUIT PACKAGE WITH PRINTED CIRCUIT LAYER - An integrated circuit (IC) package including an IC die and a conductive ink printed circuit layer electrically connected to the IC die. | 06-26-2014 |
20140203394 | Chip With Through Silicon Via Electrode And Method Of Forming The Same - The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening. | 07-24-2014 |
20140203395 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved. | 07-24-2014 |
20140231954 | 3D NAND FLASH MEMORY - A memory device includes an array of NAND strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. The device includes charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and inter-stack semiconductor body elements of a plurality of bit line structures. At least one reference line structure is arranged orthogonally over the stacks, including vertical conductive elements between the stacks in electrical communication with a reference conductor between the bottom plane of conductive strips and a substrate, and linking elements over the stacks connecting the vertical conductive elements. The vertical conductive elements have a higher conductivity than the semiconductor body elements. | 08-21-2014 |
20140239438 | SEMICONDUCTOR DEVICE - A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices. | 08-28-2014 |
20140252537 | PACKAGE ARRANGEMENT AND A METHOD OF MANUFACTURING A PACKAGE ARRANGEMENT - In various embodiments, a package arrangement is provided. The package arrangement may include a first package. The package arrangement may further include a through hole package including at least one contact terminal. The first package may include at least one hole in an encapsulant to receive the at least one contact terminal of the through hole package. The received at least one contact terminal may provide a solder contact. | 09-11-2014 |
20140284760 | INTEGRATED PASSIVE DEVICES FOR FINFET TECHNOLOGIES - Integrated passive devices for silicon on insulator (SOI) FinFET technologies and methods of manufacture are disclosed. The method includes forming a passive device on a substrate on insulator material. The method further includes removing a portion of the insulator material to expose an underside surface of the substrate on insulator material. The method further includes forming material on the underside surface of the substrate on insulator material, thereby locally thickening the substrate on insulator material under the passive device. | 09-25-2014 |
20140291800 | SEMICONDUCTOR DEVICE - When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized. | 10-02-2014 |
20140319649 | Lithium Battery, Method for Manufacturing a Lithium Battery, Integrated Circuit and Method of Manufacturing an Integrated Circuit - A lithium battery includes a cathode, an anode including a component made of silicon, a separator element disposed between the cathode and the anode, an electrolyte, and a substrate. The anode is disposed over the substrate or the anode is integrally formed with the substrate. | 10-30-2014 |
20150035114 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a semiconductor substrate, an active element and a passive element. The active element is made of the semiconductor substrate. The passive element includes a functional element filled in a groove or hole provided in the semiconductor substrate along a thickness direction thereof and is electrically connected to the active element. The functional element has a Si—O bond region obtained by reacting Si particles with an organic Si compound. | 02-05-2015 |
20150084156 | MEMORY CELL WITH INDEPENDENTLY-SIZED ELECTRODE - Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode. | 03-26-2015 |
20150084157 | ELECTRONIC STRUCTURE, A BATTERY STRUCTURE, AND A METHOD FOR MANUFACTURING AN ELECTRONIC STRUCTURE - According to various embodiments, an electronic structure may be provided, the electronic structure may include: a semiconductor carrier, and a battery structure monolithically integrated with the semiconductor carrier, the battery structure including a plurality of thin film batteries. | 03-26-2015 |
20150349254 | BUFFER CAP LAYER TO IMPROVE MIM STRUCTURE PERFORMANCE - The present disclosure relates to method of forming a MIM (metal-insulator-metal) structure having a buffer cap layer that reduces stress induced by an overlying stress-inducing protective layer, and an associated apparatus. The method is performed by forming a lower conductive layer over a semiconductor substrate, forming a dielectric layer over the lower conductive layer, and forming an upper conductive layer over the dielectric layer. A buffer cap layer is formed over the upper conductive layer and a stress-inducing protective layer is formed onto the buffer cap layer. The buffer cap layer reduces a stress induced onto the upper conductive layer by the stress-inducing protective layer, thereby reducing leakage current between the lower and upper conductive layers. | 12-03-2015 |
20160056226 | WAFER LEVEL PACKAGE (WLP) INTEGRATED DEVICE COMPRISING ELECTROMAGNETIC (EM) PASSIVE DEVICE IN REDISTRIBUTION PORTION, AND RADIO FREQUENCY (RF) SHIELD - Some novel features pertain to an integrated device that includes a substrate, several lower level metal layers, several lower level dielectric layers, and a redistribution portion. The redistribution portion includes a first dielectric layer that includes a first dielectric thickness, and an electromagnetic (EM) passive device that includes a first redistribution interconnect. The first redistribution interconnect includes a first redistribution thickness, where the first dielectric thickness is at least about 2 times greater than the first redistribution thickness. In some implementations, the redistribution portion includes a radio frequency (RF) shield. In some implementations, the RF shield is located between a passivation layer and the several lower level dielectric layers. The RF shield is located between the EM passive device and the several lower level dielectric layers. The RF shield is electrically coupled to an interconnect configured to provide an electrical path for a ground signal. | 02-25-2016 |
20160141357 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor device and a method of making the same. The device includes a semiconductor substrate including a body region having a first conductivity type. The device also includes an array of interconnected trenches extending into the body region from a surface of the substrate. The device further includes a plurality of channel stoppers. Each channel stopper includes a doped region of the first conductivity type located at a side of one or more of the trenches at a position intermediate a top of the trench and a bottom of the trench. | 05-19-2016 |