Class / Patent application number | Description | Number of patent applications / Date published |
257491000 | In integrated circuit | 45 |
20080237773 | Integrated High Voltage Power Device Having an Edge Termination of Enhanced Effectiveness - Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub | 10-02-2008 |
20080315344 | SEMICONDUCTOR INTEGRATED CIRCUIT - This invention is directed to improve the electrostatic discharge strength and the latch-up strength of the semiconductor integrated circuit. To achieve the certain level of stable quality of the semiconductor integrated circuit by eliminating the variety in the electrostatic discharge strength and the latch-up strength is also aimed. The first NPN type bipolar transistor | 12-25-2008 |
20090045480 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of circuit cells on a semiconductor chip. The plurality of circuit cells are formed along a first chip side of the semiconductor chip. Each of the plurality of circuit cells has a pad. The semiconductor integrated circuit further includes a high voltage potential interconnect formed over the plurality of circuit cells. The high voltage potential interconnect has a width expanding in a length direction from a center portion to end portions of the high voltage potential interconnect. | 02-19-2009 |
20090166796 | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT AND SEMICONDUCTOR STRUCTURE OF INTEGRATED CIRCUIT - A method for manufacturing an integrated circuit includes: performing ion implantation on a wafer to make a chip in the wafer have an original doping concentration; dividing the chip into a plurality of regions; and controlling at least one region of plurality of the regions to not have further ion implantation performed thereon, thereby making the region only have single ion implantation performed thereon utilize the original doping concentration as a doping concentration of N-wells or P-wells of transistors in the region. Additionally, the region corresponds to signal output circuits of the integrated circuit. | 07-02-2009 |
20100001363 | Semiconductor Device and Method of Providing Electrostatic Discharge Protection for Integrated Passive Devices - A semiconductor device has an integrated passive device (IPD) formed on a substrate. The IPD can be a metal-insulator-metal capacitor or an inductor formed as a coiled conductive layer. A signal interconnect structure is formed on the front side or backside of the substrate. The signal interconnect structure is electrically connected to the IPD. A thin film ZnO layer is formed on the substrate as a part of an electrostatic discharge (ESD) protection structure. The thin film ZnO layer has a non-linear resistance as a function of a voltage applied to the layer. A conductive layer is formed on the substrate. The thin film ZnO layer is electrically connected between the signal interconnect structure and conductive layer to provide an ESD path to protect the IPD from an ESD transient. A ground interconnect structure is formed on the substrate and electrically connects the conductive layer to a ground point. | 01-07-2010 |
20100013043 | CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME - An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate. | 01-21-2010 |
20100078754 | Guard ring structures and method of fabricating thereof - A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first layer. The second layer has a dopant concentration that is higher than the dopant concentration of the first layer. The gates and the guard rings are formed simultaneously using a single mask. | 04-01-2010 |
20100090306 | TWO TERMINAL MULTI-CHANNEL ESD DEVICE AND METHOD THEREFOR - In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes. | 04-15-2010 |
20100264507 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate having a main surface having an element formation region, a guard ring, a guard ring electrode, a channel stopper region, a channel stopper electrode, and a field plate disposed over and insulated from the semiconductor substrate. The field plate includes a first portion located between the main surface of the semiconductor substrate and the guard ring electrode, and a second portion located between the main surface of the semiconductor substrate and the channel stopper electrode. The first portion has a portion overlapping with the guard ring electrode when viewed in a plan view. The second portion has a portion overlapping with the channel stopper electrode when viewed in the plan view. In this way, a semiconductor device allowing for stabilized breakdown voltage can be obtained. | 10-21-2010 |
20110042776 | GUARD RIND STRUCTURES AND METHOD OF FABRICATING THEREOF - A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first layer. The second layer has a dopant concentration that is higher than the dopant concentration of the first layer. The gates and the guard rings are formed simultaneously using a single mask. | 02-24-2011 |
20110049666 | GUARD RING STRUCTURES AND METHOD OF FABRICATING THEREOF - A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first layer. The second layer has a dopant concentration that is higher than the dopant concentration of the first layer. The gates and the guard rings are formed simultaneously using a single mask. | 03-03-2011 |
20110101486 | BIPOLAR TRANSISTOR - A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation. | 05-05-2011 |
20120007207 | APPARATUS AND METHOD FOR ELECTRONIC CIRCUIT PROTECTION - Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a substrate includes an n-well and a p-well adjacent the n-well. An n-type active area and a p-type active area are disposed in the n-well. The p-type active area, the n-well, and the p-well are configured to operate as an emitter, a base, and a collector of an PNP bipolar transistor, respectively, and the p-type active area surrounds at least a portion of the n-type active area so as to aid in recombining carriers injected into the n-well from the p-well before the carriers reach the n-type active area. The n-well and the p-well are configured to operate as a breakdown diode, and a punch-through breakdown voltage between the n-well and the p-well is lower than or equal to about a breakdown voltage between the p-type active area and the n-well. | 01-12-2012 |
20120074515 | Noise Decoupling Structure with Through-Substrate Vias - A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate. | 03-29-2012 |
20120074516 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property. A semiconductor device according to the present invention includes a plurality of semiconductor chips formed on a substrate, and a plate electrode connecting electrodes of the plurality of semiconductor chips. The plate electrode has half-cut portions formed by half-pressing and the raised sides of the half-cut portions are bonded with the electrodes of the semiconductor chips. | 03-29-2012 |
20130234279 | SEMICONDUCTOR DEVICE WITH BURIED WORD LINE STRUCTURES AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with buried word line structures and methods of forming the semiconductor device are provided. The semiconductor device includes a plurality of insulating line patterns extending in a direction in a substrate, a plurality of word lines alternately with ones of the plurality of insulating line patterns, the plurality of word lines extending in the direction and comprising a metal, a plurality of first doped regions on respective ones of the plurality of the word lines and between two adjacent ones of the plurality of insulating line patterns, an interlayer insulating film on the plurality of insulating line patterns and the plurality of first doped regions, the interlayer insulating film including a plurality of openings exposing upper surfaces of ones of the plurality of first doped regions and a plurality of second doped regions contacting respective ones of the plurality of first doped regions within the openings. | 09-12-2013 |
20130249044 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first diode, a second diode, and a third diode. The first diode has an anode connected to a first power supply terminal to which a first power-source voltage is applied and a cathode connected to an input-output terminal at which input-output signals are input and output. The second diode has an anode connected to the input-output terminal and a cathode connected to a second power supply terminal to which a second power-source voltage that is higher than the first power-source voltage is applied. The third diode has an anode connected to the first supply terminal and a cathode connected to the second power supply terminal. The breakdown voltage of at least one of either the first or second diode is higher than the breakdown voltage of the third diode. | 09-26-2013 |
20140299960 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 10-09-2014 |
20150021733 | SEMICONDUCTOR WAFER, SEMICONDUCTOR IC CHIP AND MANUFACTURING METHOD OF THE SAME - A semiconductor wafer includes circuit integration regions each incorporating an integrated circuit and guard rings disposed to surround the circuit integration regions, respectively. A scribe region disposed between every adjacent two of the guard rings. An element and a pad electrically connected to the element are disposed in the scribe region. A groove is disposed along a corresponding guard ring on a front surface of the semiconductor wafer between the pad and the corresponding guard ring. The distance between the groove and the pad is varied along the corresponding guard ring. | 01-22-2015 |
20150035112 | SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF - Disclosed are guard ring structures with an electrically insulated gap in a substrate to reduce or eliminate device coupling of integrated circuit chips, methods of manufacture and design structures. The method includes forming a guard ring structure comprising a plurality of metal layers within dielectric layers. The method further includes forming diffusion regions to electrically insulate a gap in a substrate formed by segmented portions of the guard ring structure. | 02-05-2015 |
20150084154 | Methods and Apparatus for ESD Structures - Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type. | 03-26-2015 |
20150137305 | PROTECTIVE STRUCTURE AND METHOD FOR PRODUCING A PROTECTIVE STRUCTURE - Described herein is a protective structure. The protective structure includes a semiconductor substrate, a first diode disposed at least one of in or on the semiconductor substrate and a diode arrangement disposed at least one of in or on the semiconductor substrate. The diode arrangement includes a stack of a second diode and a transient voltage suppressor (TVS) diode connected in series with the second diode. The diode arrangement is in parallel with the first diode. | 05-21-2015 |
20150145098 | MINIATURE PASSIVE STRUCTURES, HIGH FREQUENCY ELECTROSTATIC DISCHARGE PROTECTION NETWORKS, AND HIGH FREQUENCY ELECTROSTATIC DISCHARGE PROTECTION SCHEMES - According to various embodiments, a miniature passive structure for electrostatic discharge protection and input/output matching for a high frequency integrated circuit may be provided. The structure may include: either a transmission line or an inductor for providing at least one electrostatic discharge path; and a capacitor with a first end connected to the transmission line or inductor and a second end connected to ground. | 05-28-2015 |
20150294985 | DISPLAY PANEL - A display panel is provided. The display panel includes has an active area and a border area surrounding the active area. The display panel includes a plurality of pixels, a plurality of multiplexer portion, a gate driver portion and a source routing portion. The pixels are located in the activate area. The multiplexer portion is located in the border area. The gate driver portion is located in the border area. The source routing portion is located in the border area. In part of the border area, at least part of the multiplexer portion, at least part of the gate driver portion and at least part of the source routing portion are located and sequentially arranged from an internal edge of the border area to an external edge of the border area. | 10-15-2015 |
20150311191 | SEMICONDUCTOR DEVICE COMPRISING ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE - A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further comprises a first isolation layer on the first surface of the semiconductor body, and an electrostatic discharge protection structure on the first isolation layer. The electrostatic discharge protection structure has a first terminal and a second terminal. The semiconductor device further comprises a heat dissipation structure, which has a first end in contact with the electrostatic discharge protection structure and a second end which is in direct contact to an electrically isolating region. | 10-29-2015 |
20150311193 | A SEMICONDUCTOR DEVICE COMPRISING AN ESD PROTECTION DEVICE, AN ESD PROTECTION CIRCUITRY, AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region. | 10-29-2015 |
20150364421 | INTEGRATED CIRCUIT WITH GUARD RING - An integrated circuit includes a circuit and a guard ring. The circuit is over a substrate. The guard ring surrounds the circuit and includes a staggered line. The staggered line comprises a first zigzag line and a second zigzag line. The first zigzag line comprises interconnections formed in at least two GDS layers. The second zigzag line comprises interconnections formed in at least two GDS layers. The first zigzag line and the second zigzag line form a first quadrangle and a second quadrangle. | 12-17-2015 |
20150371984 | ESD PROTECTION DEVICE - The present invention is provided with a Si substrate, an ESD protection circuit formed in the Si substrate, pads formed on the surface of the Si substrate and electrically connected to first and second input/output terminals of the ESD protection circuit, a rewiring layer formed on the surface of the Si substrate for electrically connecting the pads and metal plated films, and an insulating resin film formed on the rear surface of the Si substrate. Thus, provided is an ESD protection device which can suppress the influence of external noise, etc. | 12-24-2015 |
20160005809 | CONFIGURATION AND METHOD TO GENERATE SADDLE JUNCTION ELECTRIC FIELD IN EDGE TERMINATION - This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination. | 01-07-2016 |
20160056230 | GUARD RING STRUCTURE AND METHOD OF FORMING THE SAME - A circuit device includes core circuitry. The circuit device further includes a first set of guard rings having a first dopant type, the first set of guard rings being around a periphery of the core circuitry, the first set of guard rings comprising a first guard ring and a second guard ring. The circuit device further includes a second set of guard rings having a second dopant type, the second dopant type being opposite to the first dopant type, wherein at least one guard ring of the second set of guard rings is around a periphery of at least one guard ring of the first set of guard rings, and the second set of guard rings comprises a third guard ring and a fourth guard ring. | 02-25-2016 |
20160064375 | SEMICONDUCTOR DEVICES HAVING HIGH-RESISTANCE REGION AND METHODS OF FORMING THE SAME - Provided are an electrostatic discharge (ESD) protection device having a high-resistance region and a method of forming the same. The device includes a well on a substrate. A first impurity region is formed on the well and connected to an input/output pad. A second impurity region is formed on the well, spaced apart from the first impurity region, and connected to a ground (Vss). A third impurity region is formed on the well, spaced apart from the first impurity region, and connected to the ground (Vss). An isolation layer is formed between the first impurity region and the second impurity region. A high-resistance region, which directly contacts the first impurity region and the well and has a resistance higher than the first impurity region, is formed between the first impurity region and the isolation layer. The well and the third impurity region include first conductive type impurities. The first impurity region and the second impurity region include second conductive type impurities different from the first conductive type impurities. | 03-03-2016 |
20160093604 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type selectively provided on a surface of the first semiconductor region, an insulating layer provided on the first semiconductor region and on the second semiconductor region, and having a first opening exposing a portion of the second semiconductor region therein, a wiring layer on the insulating layer and electrically connected to the second semiconductor region through the first opening, and a third semiconductor region of the second conductivity type below the insulating layer and contacting the first semiconductor region. | 03-31-2016 |
20160093605 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second semiconductor regions, and a third semiconductor region between the first and second semiconductor regions, wherein the dopant concentration of the third semiconductor region is greater than the dopant concentration of the second semiconductor region. The semiconductor device further includes a fourth semiconductor region selectively provided on an upper surface of the second semiconductor region, wherein a portion of the second semiconductor region is interposed between the third semiconductor region and the fourth semiconductor region, an insulating layer disposed on the second semiconductor region and the fourth semiconductor region and having an opening that exposes a portion of a top surface of the fourth semiconductor region, wherein the ratio of an area of opening to an area of the top surface is from 10% to 90%, and a wiring layer on the insulating layer and connected to the fourth semiconductor region via the opening. | 03-31-2016 |
20160148921 | CIRCUIT CONFIGURATION AND MANUFACTURING PROCESSES FOR VERTICAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) AND EMI FILTER - A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter. | 05-26-2016 |
20160163659 | RADIO FREQUENCY DEVICE PROTECTED AGAINST OVERVOLTAGES - A device includes passive radio frequency components formed of portions of metal layers separated by insulating layers and crossed by vias. The insulating layers are positioned on an upper surface of an insulating substrate. Islands of a semiconductor material extend into the insulating substrate from the upper surface. Active integrated circuit components are formed in the islands. | 06-09-2016 |
20160181236 | TRANSIENT VOLTAGE SUPPRESSOR AND ESD PROTECTION DEVICE AND ARRAY THEREOF | 06-23-2016 |
257492000 | With electric field controlling semiconductor layer having a low enough doping level in relationship to its thickness to be fully depleted prior to avalanche breakdown (e.g., RESURF devices) | 9 |
20080237774 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a major surface of the semiconductor substrate and having lower doping concentration than the semiconductor substrate; a plurality of first semiconductor column regions of the first conductivity type provided on the first semiconductor layer; | 10-02-2008 |
20090057808 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR ELEMENT, AND SUBSTRATE - A semiconductor device, a semiconductor element, and a substrate are provided, which allow the semiconductor element to be provided with a reduced size when combined. The semiconductor device of the invention has a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes a grayscale voltage generating unit for generating a plurality of grayscale voltages by dividing a reference voltage, a plurality of electrodes for the reference voltage formed in the neighborhood of the grayscale voltage generating unit; and an internal wiring for connecting the grayscale voltage generating unit and the reference voltage electrodes. The substrate includes a wiring pattern for the reference voltage for connecting the external input terminal and the reference voltage electrodes. | 03-05-2009 |
20090085146 | SEMICONDUCTOR DEVICE - A semiconductor device | 04-02-2009 |
20100252904 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling. | 10-07-2010 |
20100276779 | Transient Voltage Suppressor Having Symmetrical Breakdown Voltages - A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS. | 11-04-2010 |
20130032922 | INTEGRATED HIGH VOLTAGE DIVIDER - An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider. | 02-07-2013 |
20140110814 | Resurf High Voltage Diode - A trench-isolated RESURF diode structure ( | 04-24-2014 |
20140299961 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region. | 10-09-2014 |
20160079345 | Bipolar Transistor - A semiconductor device comprising a bipolar transistor and a method of making the same. A power amplifier including a bipolar transistor. The bipolar transistor includes a collector including a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a doped region having a conductivity type that is different to that of the collector. The doped region extends laterally beneath the collector to form a junction at a region of contact between the doped region and the collector. The doped region has a non-uniform lateral doping profile. A doping level of the doped region is highest in a part of the doped region closest to a collector-base junction of the bipolar transistor. | 03-17-2016 |