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257 - Active solid-state devices (e.g., transistors, solid-state diodes)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
257488000 Field relief electrode 21
257491000 In integrated circuit 21
257493000 With electric field controlling semiconductor layer having a low enough doping level in relationship to its thickness to be fully depleted prior to avalanche breakdown (e.g., RESURF devices) 14
257496000 With physical configuration of semiconductor surface to reduce electric field (e.g., reverse bevels, double bevels, stepped mesas, etc.) 11
257495000 Floating pn junction guard region 6
257494000 Reverse-biased pn junction guard region 5
20090294892Edge Termination for Semiconductor Devices - A high-voltage termination structure includes a peripheral voltage-spreading network. One or more trench structures are connected at least partly in series between first and second power supply voltages. The trench structures include first and second current-limiting structures connected in series with a semiconductor material, and also includes permanent charge in a trench-wall dielectric. The current-limiting structures in the trench structures are jointly connected in a series-parallel ladder configuration. The current-limiting structures, in combination with the semiconductor material, provide a voltage distribution between the core portion and the edge portion.12-03-2009
20090079022METHOD OF FORMING LOW CAPACITANCE ESD DEVICE AND STRUCTURE THEREFOR - In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.03-26-2009
20100019342SEMICONDUCTOR DEVICE - In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.01-28-2010
20100224953RECTIFIER APPLICABLE IN HIGH TEMPERATURE CONDITION - A rectifier for high temperature application includes a conductive semiconductor layer, a conductive epitaxial layer, and a plurality of conductive doped regions within the conductive epitaxial layer. A fringe conductive doped region is formed surrounding the conductive doped region, and an outer fringe conductive doped region is formed further surrounding the fringe conductive doped region. A first metal layer is formed on the upper surface of the conductive semiconductor substrate covering the entire conductive doped regions, and contacting at least a portion of the fringe conductive doped region. A second metal layer is formed on the lower surface of the conductive semiconductor substrate.09-09-2010
20130175657Surface (Lateral) Voltage-sustaining Region with an Insulator Film Containing Conductive Particles - A method or an auxiliary method to implement Optimum Variation Lateral Electric Displacement uses an insulator film(s) containing conductive particles covering on the semiconductor surface. This film(s) is capable of transmitting electric displacement into or extracting it from the semiconductor surface, or even capable of extracting some electric displacement from a part of the semiconductor surface and then transmitting it to another part of the surface. Optimum Variation Lateral Electric Displacement can be used to fabricate lateral high voltage devices, or as the edge termination for vertical high voltage devices, or to make capacitance. It can be further used to prevent strong field at the boundaries of semiconductor regions of different types of conductivity types.07-11-2013
20090206439Semiconductor device - In order to provide an ESD protection circuit having high immunity to ESD destruction without increasing a chip area of a semiconductor device, a diode-type ESD protection circuit formed of a junction between a first conductivity type diffusion layer and a second conductivity type diffusion layer is formed in an entire peripheral region or a part of the peripheral region outside of internal circuits and bonding pads of the chip, and a diffusion layer formed to fix a substrate potential of the chip and electrically connected to a power source or a ground provided in the peripheral region of the chip is used for any one of the first conductivity type diffusion layer and the second conductivity type diffusion layer, permitting enlargement of the size of the ESD protection circuit without increasing a chip area, and enhancement of immunity to ESD destruction of the semiconductor device.08-20-2009
20120161274SUPERJUNCTION SEMICONDUCTOR DEVICE - A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners. The edge p pillar has an outer region surrounding the active region and an inner region on in the sides of the active region. The active region has active p pillars and active n pillars having vertical stripe shapes. The active p pillars and the active n pillars are alternately arranged horizontally in the active region. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar.06-28-2012
20130075855Manufacturing methods for accurately aligned and self-balanced superjunction devices - A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.03-28-2013
20120181653SEMICONDUCTOR PN JUNCTION STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor PN junction structure and a manufacturing method thereof. From top view, the PN junction includes a staggered comb-teeth structure. The PN junction forms a depletion region with enhanced breakdown voltage, hence broadening the applications of a semiconductor device having such PN junction.07-19-2012
20120112306SEMICONDUCTOR DEVICE WITH SUPERJUNCTION STRUCTURE - A superjunction semiconductor device is disclosed which has, in the active section, a first alternating-conductivity-type layer which makes a current flow in the ON-state of the device and sustains a bias voltage in the OFF-state of the device. There is a second alternating-conductivity-type layer in a edge-termination section surrounding the active section. The width of a region of a second conductivity type in the second alternating-conductivity-type layer becomes narrower at a predetermined rate from the edge on the active section side toward the edge of the edge termination section. The superjunction semiconductor device facilitates manufacturing the edge-termination section which exhibits a high breakdown voltage and a high reliability for breakdown voltage through a process that exhibits a high mass-productivity.05-10-2012
20090236680SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR BODY AND METHOD FOR ITS PRODUCTION - A semiconductor device with a semiconductor body and method for its production is provided. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion.09-24-2009
20100123210ASYMMETRIC BARRIER DIODE - A diode having a reference voltage electrode, a variable voltage electrode, and a diode material between the electrodes. The diode material is formed of at least one high-K dielectric material and has an asymmetric energy barrier between the reference voltage electrode and the variable voltage electrode, with the energy barrier having a relatively maximum energy barrier level proximate the reference voltage electrode and a minimum energy barrier level proximate the variable voltage electrode.05-20-2010
20080290443SEMICONDUCTOR DEVICE WITH A PLURALITY OF ISOLATED CONDUCTIVE FILMS - A semiconductor layer provided on a BOX (buried oxide) layer includes a first P-type region, an N11-27-2008
20090140370SEMICONDUCTOR DEVICE - A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device.06-04-2009
20120068298SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a super junction structure includes: multiple first columns extending in a current flowing direction; and multiple second columns extending in the current flowing direction. The first and second columns are alternately arranged in an alternating direction. Each first column provides a drift layer. The first and second columns have a boundary therebetween, from which a depletion layer expands in case of an off-state. At least one of the first columns and the second columns have an impurity dose, which is inhomogeneous by location with respect to the alternating direction.03-22-2012
20090200634MULTI-ANGLE ROTATION FOR ION IMPLANTATION OF TRENCHES IN SUPERJUNCTION DEVICES - A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.08-13-2009
20110221028SEMICONDUCTOR DEVICE - In a lamination type semiconductor device, in the case where a power source plane is wrapped by a closed area to prevent the needless radiation from being leaked to the outside of the semiconductor package, a planar conductor for shield having an area intersecting with the respective layers is required. However, in a device for manufacturing the lamination type semiconductor device, a process for manufacturing the above-mentioned conductor cannot be realized ordinarily. In order to make the process possible, it is required to modify or replace a manufacturing apparatus of the semiconductor device, and accordingly a manufacturing cost will be considerably increased. In the present invention, a guard ring is arranged in an surrounding area of a power source plane. The guard ring is connected to a GND plane of another layer through a via. Consequently, the RF radiation occurs between the power source plane and the guard ring.09-15-2011
20100155878Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling - This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.06-24-2010
20120228734HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR RECTIFIER - A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor.09-13-2012
20100237457SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.09-23-2010
20110241156SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Methods for manufacturing a semiconductor device with alternating P type and N type semiconductor conductive regions are disclosed. One method includes forming a trench in an N type epitaxial layer; forming carbon-contained silicon layer on sidewalls of the trench; and filling the trench with P type semiconductor layer. In another method, the carbon-contained silicon layer is replaced by a carbon film formed by diffusion process. The carbon-contained silicon layer or the carbon film can effectively inhibit the diffusion of P type impurities into the N type semiconductor layers. Further, a semiconductor device having carbon-contained layer or carbon film formed between P type and N type conductive layers is also disclosed.10-06-2011
20080290442PROCESS FOR HIGH VOLTAGE SUPERJUNCTION TERMINATION - A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.11-27-2008
20100019341BURIED ASYMMETRIC JUNCTION ESD PROTECTION DEVICE - An improved lateral bipolar electrostatic discharge (ESD) protection device (01-28-2010
20120061792BIDIRECTIONAL VOLTAGE-REGULATOR DIODE - In one embodiment, a bidirectional voltage-regulator diode includes first to fifth semiconductor layers formed on an inner surface of a first recess formed in a semiconductor substrate of an N-type in the order. The first semiconductor layer of the N-type has a first impurity concentration lower than an impurity concentration of the semiconductor substrate. The second semiconductor layer of a P-type has a second impurity concentration. The third semiconductor layer of the P-type has a third impurity concentration higher than the second impurity concentration. The fourth semiconductor layer of the P-type has a fourth impurity concentration lower than the third impurity concentration. The fifth semiconductor layer of the N-type has a fifth impurity concentration.03-15-2012
20120248566Configuration and method to generate saddle junction electric field in edge termination - This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.10-04-2012
20100052090SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N− type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.03-04-2010
20100230775TERMINATION FOR A SUPERJUNCTION DEVICE - A superjunction device that includes a termination region having a transition region adjacent the active region thereof, the transition region including a plurality of spaced columns.09-16-2010
20120241899POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of the second conductivity type. The second semiconductor layer is provided on the first semiconductor layer and has a lower concentration of first conductivity type impurity than the first semiconductor layer. The third semiconductor layer is provided on a surface of the second semiconductor layer. The fourth semiconductor layer is selectively provided on a surface of the third semiconductor layer and has a higher concentration of second conductivity type impurity than the third semiconductor layer. The third semiconductor layer includes a carrier lifetime reducing region adjacent to a bottom surface of the fourth semiconductor layer. The carrier lifetime reducing region is spaced from the second semiconductor layer.09-27-2012
20130093038Schottky Diode - An embodiment is a semiconductor structure. The semiconductor structure comprises a p-type region in a substrate; a first n-type well in the p-type region; a first p-type well in the p-type region; and a second p-type well in the first p-type well. A concentration of a p-type impurity in the first p-type well is less than a concentration of a p-type impurity in the second p-type well. Additional embodiments further comprise further n-type and p-type wells in the substrate. A method for forming a semiconductor structure is also disclosed.04-18-2013
20130175655DUAL DNW ISOLATION STRUCTURE FOR REDUCING RF NOISE ON HIGH VOLTAGE SEMICONDUCTOR DEVICES - An isolation structure in a semiconductor device absorbs electronic noise and prevents substrate leakage currents from reaching other devices and signals. The isolation structure provides a duality of deep N-well (“DNW”) isolation structures surrounding an RF device or other source of electronic noise. The DNW isolation structures extend into the substrate at a depth of at least about 2.5 μm and may be coupled to V07-11-2013
20080197441SEMICONDUCTOR COMPONENT WITH VERTICAL STRUCTURES HAVING A HIGH ASPECT RATIO AND METHOD - A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between the drift zone and the drift control zone wherein the drift zone has a varying doping and/or a varying material composition at least in sections proceeding from the dielectric.08-21-2008
20130207223SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE - One embodiment describes a method of manufacturing a semiconductor device. Here, impurities are implanted into a semiconductor body via a first side of the semiconductor body. Thereafter, a drift zone layer on the first side of the semiconductor body is formed. The following is an ablation of the semiconductor body from a second side of the semiconductor body and up to pn junction defined by impurities.08-15-2013
20130207224DIODE FOR ELECTROSTATIC PROTECTION - Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.08-15-2013